STM32H533xx

Arm® Cortex®-M33 32-bit MCU+TrustZone® + FPU, 375 DMIPS

250 MHz, 512-Kbyte flash, 272-Kbyte RAM, cryptography
Datasheet - production data

Features
UFBGA

Includes ST state-of-the-art patented technology

Core LQFP48 (7 x 7 mm)

UFBGA100 (7 x 7 mm)
• Arm® Cortex®-M33 CPU with TrustZone®, LQFP64 (10 x 10 mm)
UFBGA144 (10 x 10 mm)
FPU, frequency up to 250 MHz, MPU, LQFP100 14 x 14 mm)

375 DMIPS (Dhrystone 2.1) LQFP144 (20 x 20 mm)

ART Accelerator
• 8-Kbyte instruction cache allowing
0-wait-state execution from flash and external
memories
UFQFPN48 (7 x 7 mm) WLCSP39 (2.76 x 2.78 mm,
• 4-Kbyte data cache for external memories pitch 0.4mm)

Benchmarks
• 1.5 DMIPS/MHz (Drystone 2.1) Clock management
• 1023 CoreMark® (4.092 CoreMark®/MHz) • Internal oscillators: 64 MHz HSI,
48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
Memories • External oscillators: 4-50 MHz HSE,
• Up to 512 Kbytes of embedded flash memory 32.768 kHz LSE
with ECC, two banks read-while-write
General-purpose inputs/outputs
• Up to 48-Kbyte per bank with high-cycling
capability (100 K cycles) for data flash • Up to 112 fast I/Os with interrupt capability
(most 5 V tolerant)
• 2-Kbyte OTP (one-time programmable)
• Up to ten I/Os with independent supply down to
• 272 Kbytes of SRAM (80-Kbyte SRAM2 with
1.08 V
ECC)
• 2 Kbytes of backup SRAM available in the Low-power consumption
lowest power modes
• Sleep, Stop, and Standby modes
• Flexible external memory controller with up to
16-bit data bus: SRAM, PSRAM, FRAM, • VBAT supply for RTC, 32 backup registers
NOR/NAND memories (32-bit)

• One Octo-SPI memory interface with support Security

for serial PSRAM/NAND/NOR, hyper
RAM/flash frame formats • Arm® TrustZone® with Armv8-M mainline
security extension
• One SD/SDIO/MMC interface
• Up to eight configurable SAU regions
• TrustZone® aware and securable peripherals

April 2024 DS14539 Rev 1 1/231

This is information on a product in full production. www.st.com
 STM32H533xx

• Flexible life cycle scheme with secure debug • Two watchdogs

authentication • Two SysTick timers
• SESIP3 and PSA Level 3 certified assurance
target Up to 34 communication interfaces
• Preconfigured immutable root of trust • Up to three I2Cs Fm+ (SMBus/PMBus®)
(ST-iROT)
• Two I3Cs
• SFI (secure firmware installation)
• Up to six U(S)ARTs (ISO7816 interface, LIN,
• Root of trust thanks to unique boot entry and IrDA, modem control) and one LPUART
secure hide protection area (HDP)
• Up to four SPIs including three muxed
• Secure data storage with hardware unique key full-duplex I2S audio class accuracy via
(HUK) internal audio PLL or external clock, and up to
• Secure firmware upgrade support with TF-M four additional SPIs from four USARTs when
configured in Synchronous mode (one
• Two AES coprocessors including one with DPA
additional SPI with OctoSPI)
resistance
• Two FDCAN controllers
• Public key accelerator, DPA resistant
• One 8- to 14-bit camera interface
• On-the-fly decryption of Octo-SPI external
memories • One 16-bit parallel slave synchronous-
interface
• HASH hardware accelerator
• One HDMI-CEC
• True random number generator, NIST
SP800-90B compliant • One USB 2.0 full-speed host and device
(crystal-less)
• 96-bit unique ID
• One USB Type-C®/ USB Power Delivery r3.1
• Active tampers
Analog
Two DMA controllers to offload the CPU
• Two 12-bit ADCs with up to 5 Msps in 12-bit
• Two dual-port DMAs with FIFO
• One 12-bit DAC with two channels
Reset and supply management • Digital temperature sensor
• 1.71 V to 3.6 V application supply and I/O • Voltage reference buffer
• POR, PDR, PVD, and BOR
Debug
• Embedded regulator with configurable scalable
output to supply the digital circuitry • Authenticated debug and flexible device life
cycle
Up to 16 timers • Serial wire-debug (SWD), JTAG, Embedded
• 10x 16-bit (including two low-power 16-bit Trace Macrocell™ (ETM)
timers available in Stop mode)
ECOPACK2 compliant packages
• Two 32-bit timers with up to four IC/OC/PWM
or pulse counters and quadrature (incremental)
encoder input
Table 1. Device summary
Reference Part numbers

STM32H533xx STM32H533CE, STM32H533HE, STM32H533RE, STM32H533VE, STM32H533ZE

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Arm Cortex-M33 core with TrustZone and FPU . . . . . . . . . . . . . . . . . . . . 18
3.2 ART Accelerator (ICACHE and DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Data cache (DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 FLASH security and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.2 FLASH privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.1 SRAMs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.2 SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 Security overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.1 STM32H533xx boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9.2 Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10.3 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10.4 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10.5 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.11 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.12 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.12.1 RCC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.13 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.14.1 GPIOs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.15 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.16 General purpose direct memory access controller (GPDMA) . . . . . . . . . 33
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 35
3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 35
3.18 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 36
3.19 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.19.1 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.19.2 FMC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.20 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.20.1 OCTOSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.21 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.22 Analog-to-digital converter (ADC1 and ADC2) . . . . . . . . . . . . . . . . . . . . . 38
3.22.1 Analog temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.22.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.22.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.23 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.24 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.25 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.26 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.27 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 41
3.28 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.29 Secure advanced encryption standard hardware accelerator
(SAES) and encryption standard hardware accelerator (AES) . . . . . . . . 42
3.30 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.31 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.32 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.33 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.33.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.33.2 General-purpose timers
(TIM2, TIM3, TIM4, TIM5, TIM12, TIM15) . . . . . . . . . . . . . . . . . . . . . . . 46
3.33.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.33.4 Low-power timers
(LPTIM1, LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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3.33.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.33.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.33.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.34 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 48
3.34.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.34.2 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.35 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.36 Improved inter-integrated circuit (I3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.37 Universal synchronous/asynchronous receiver transmitter
(USART/UART) and low-power universal asynchronous
receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.37.1 Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.37.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 54
3.38 Serial peripheral interface (SPI) / inter-integrated sound interfaces (I2S) 56
3.39 Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 57
3.40 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.41 USB full speed (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.42 USB Type-C / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . . 59
3.43 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.44 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.44.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.44.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4 Pinout, pin description and alternate function . . . . . . . . . . . . . . . . . . . 61

4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.3 Operating conditions at power-up/down . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 104
5.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 129
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 145
5.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.18 Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.3.20 DCMI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.3.21 PSSI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.3.22 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.3.23 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.3.24 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 181
5.3.25 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 182
5.3.26 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.3.27 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5.3.28 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5.3.29 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.3.30 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.3.31 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
5.3.32 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

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6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.2 WLCSP39 package information (B0MM) . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3 LQFP48 package information (5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.4 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.5 UFQFPN48 package information (A0B9) . . . . . . . . . . . . . . . . . . . . . . . . .211
6.6 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.7 UFBGA100 package information (A0C2) . . . . . . . . . . . . . . . . . . . . . . . . 216
6.8 LQFP144 package information (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.9 UFBGA144 package information (A0Y2) . . . . . . . . . . . . . . . . . . . . . . . . 223
6.10 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.10.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

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List of tables STM32H533xx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32H533xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. STM32H533xx boot mode when TrustZone is disabled (TZEN = 0xC3) . . . . . . . . . . . . . . 24
Table 4. STM32H533xx boot mode when TrustZone is enabled (TZEN = 0xB4). . . . . . . . . . . . . . . 24
Table 5. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 6. AES/SAES features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7. Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 8. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 9. I3C peripheral controller/target features versus MIPI v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 10. USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 12. SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 14. STM32H533xx pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 15. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 16. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 17. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 18. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 19. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 21. Maximum allowed clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 22. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 23. Operating conditions at power-up/down (regulator ON) . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 24. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 25. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 26. Internal reference voltage calibration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory, 2-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 107
Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory, 1-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 108
Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from SRAM with cache 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from SRAM with cache 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 31. Typical consumption in Run mode with CoreMark running
from flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 32. Typical consumption in Run mode with SecureMark running from
flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 33. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 111
Table 34. Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 35. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 112
Table 36. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 112
Table 37. Peripheral current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 38. Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 39. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 40. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 41. 4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 42. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

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Table 43. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 44. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 45. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 46. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 47. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 48. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 49. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 50. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 51. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 52. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 53. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 54. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 55. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 56. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 57. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 58. Output voltage characteristics for all I/Os except PC13, PC14, and PC15. . . . . . . . . . . . 133
Table 59. Output voltage characteristics for FT_c I/Os (PB13/PB14). . . . . . . . . . . . . . . . . . . . . . . . 134
Table 60. Output voltage characteristics for PC13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 61. Output voltage characteristics for PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 62. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 63. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 64. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF) . . . . . . . . . . . . . . . . . . . 141
Table 65. Output timing characteristics VDDIO2 1.2 V (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 66. Output timing characteristics for FT_c I/Os (PB13/PB14). . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 67. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 68. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 148
Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 148
Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 149
Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 150
Table 73. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 74. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 151
Table 75. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 76. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 152
Table 77. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 78. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 79. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 80. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 81. Switching characteristics for NAND flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 82. Switching characteristics for NAND flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 83. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 84. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 85. OCTOSPI characteristics in DTR mode (with DQS) / hyperbus . . . . . . . . . . . . . . . . . . . . 163
Table 86. Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 87. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 88. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 89. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 90. 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 91. Minimum sampling time versus RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 92. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 93. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 94. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

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List of tables STM32H533xx

Table 95. Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 96. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 97. Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 98. VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 99. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 100. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 101. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 102. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 103. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 104. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 105. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 106. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 107. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 108. I3C open-drain measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 109. I3C push-pull measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 110. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 111. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 112. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 113. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 114. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 115. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 116. Dynamic characteristics: SD/MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . . 196
Table 117. Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . . . . 197
Table 118. Dynamic JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 119. Dynamic SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 120. WLCSP39 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 121. LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 122. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 123. UFQFPN48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 124. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 125. UFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 126. UFBGA100 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 218
Table 127. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 128. UFBGA144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 129. UFBGA144 - Example of PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . . . 225
Table 130. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 131. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

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List of figures

Figure 1. STM32H533xx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. STM32H533xx power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4. WLCSP39 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 5. LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 6. UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 7. LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 8. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 9. UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 10. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 11. UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 12. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 14. STM32H523xx/H533xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 15. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 16. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 17. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 18. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 20. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 147
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 149
Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 25. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 26. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 28. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 29. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 30. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 31. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 160
Figure 32. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 161
Figure 33. OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 34. OCTOSPI timing diagram - DTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 35. OCTOSPI hyperbus clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 36. OCTOSPI hyperbus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 37. OCTOSPI hyperbus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 38. DCMI timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 39. PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 40. PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 41. ADC conversion timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 42. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 43. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 177
Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 177
Figure 46. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 47. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

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List of figures STM32H533xx

Figure 48. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 49. SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 50. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 51. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 52. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 53. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 54. USB timings - definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 55. SDIO high-speed/eMMC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 56. SD default speed timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 57. DDR mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 58. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 59. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 60. WLCSP39 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 61. WLCSP39 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 62. WLCSP39 - Marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 63. LQFP48 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 64. LQFP48 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 65. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 66. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 67. UFQFPN48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 68. UFQFPN48 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 69. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 70. LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 71. UFBGA100 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 72. UFBGA100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 73. LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 74. LQFP144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 75. UFBGA144 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 76. UFBGA144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

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1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32H533xx microcontrollers.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32H533xx errata sheet.

For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33

Technical Reference Manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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13
Description STM32H533xx

2 Description

The STM32H533xx devices are high-performance microcontrollers of the STM32H5 series,

based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate at a
frequency of up to 250 MHz.
The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports
all the Arm® single-precision data-processing instructions and all the data types.
The Cortex®-M33 core implements a full set of DSP (digital signal processing) instructions
and a memory protection unit (MPU) that enhances the application security.
The devices embed high-speed memories (512 Kbytes of dual bank flash memory and
272 Kbytes of SRAM), a flexible external memory controller (FMC) for devices with
packages of 100 pins and more, one OCTOSPI memory interface (at least one Quad-SPI
available on all packages), and an extensive range of enhanced I/Os and peripherals
connected to three APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix.
The devices offer security foundation compliant with the trusted-based security architecture
(TBSA) requirements from Arm®. Besides these capabilities, the devices incorporate a
secure firmware installation that allows the customer to secure the provisioning of the code
during its production. A flexible life cycle is managed thanks to multiple levels of protection
and secure debug authentication. Firmware hardware isolation is supported thanks to
securable peripherals, memories, and I/Os, and to privilege configuration of peripherals and
memories.
The devices feature several protection mechanisms for embedded flash memory and
SRAM: readout protection, write protection, secure, and hide protection areas.
Dedicated peripherals reinforce security: an HASH hardware accelerator, and a true random
number generator.
The devices offer active tamper detection and protection against transient and
environmental perturbation attacks, thanks to several internal monitoring, generating secret
data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications.
The devices offer two fast 12-bit ADCs, two DAC channels, an internal voltage reference
buffer, a low-power RTC, two 32-bit general-purpose timers, two 16-bit PWM timers
dedicated to motor control, eight 16-bit general-purpose timers, two 16-bit basic timers, and
six 16-bit low-power timers.
The devices also feature standard and advanced communication interfaces, namely: three
I2Cs, two I3Cs, four SPIs with three muxed full-duplex I2S, four USARTs, two UARTs and
one low-power UART, one digital camera interface (DCMI), one SDMMC, two FDCANs, one
USB full-speed, one USB Type-C®/USB power delivery controller.
The devices operate in the -40 to +85 °C/105 °C (+130 °C junction), and to 125 °C at low
dissipation temperature ranges from a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes allow the design of low-power applications.
Independent power supplies are supported: an analog independent supply input for ADC,
DACs, a 3.3 V dedicated supply input for USB, and a dedicated supply input for some
GPIOs and SDMMC. A VBAT input is available to connect a backup battery, to preserve the
RTC functionality, and to backup 32x 32-bit registers and a 2-Kbyte SRAM.

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STM32H533xx Description

The devices offer eight packages, from 39 to 144 pins.

Table 2. STM32H533xx features and peripheral counts

STM32H533HE

STM32H533CE

STM32H533RE

STM32H533VE

STM32H533ZE
Peripherals

Flash memory (Kbytes) 512

System (Kbytes) 272 (128+80+64)
SRAM
Backup (bytes) 2K
Flexible memory controller for
No Yes(1) Yes
external memories (FMC)
OCTOSPI Yes
Advanced
2(16 bits)
control
General purpose 2 (32 bits) 4 (16 bits)
Basic 2 (16 bits)
Timers Low power 2 (16 bits)
SysTick timer 2 (24 bits)
Watchdog timers
(independent, 2
window)
SPI / I2S 3/2 4/3
I2C 2 3
I3C 2
USART 2 3 4
UART 2
LPUART 1
Communication
FDCAN 2
interfaces
USB FS Yes
UCPD No Yes
SDMMC No Yes
Digital camera
interface
No Yes
(DCMI)/
PSSI(2)
HDMI-CEC Yes
Real time clock (RTC) Yes
Tamper pins 4 4 5 8 8

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Description STM32H533xx

Table 2. STM32H533xx features and peripheral counts (continued)

STM32H533HE

STM32H533CE

STM32H533RE

STM32H533VE

STM32H533ZE
Peripherals

Active tampers(3) 3 3 4 7 7
True random number generator Yes
SAES, AES Yes
Public key accelerator (PKA) Yes
HASH (SHA-512) Yes
On-the-fly decryption for OCTOSPI Yes
GPIOs 26 35 49 80 112
Wakeup pins 4 4 6 7 7
Number of I/Os down to 1.08 V N/A 4 10
12-bit ADC 2
ADC Number of
10 16 20
channels
12-bit DAC
1
controller
DAC
Number of
2
channels
Internal voltage reference buffer No Yes
Maximum CPU frequency 250 MHz
Operating voltage 1.71 to 3.6 V
Ambient operating temperature: -40 to 85 °C / -40 to 105 °C
Operating temperature
Junction temperature: -40 to 130 °C
UFQFPN48/ LQFP100/ LQFP144/
Package WLCSP39 LQFP64
LQFP48 UFBGA100 UFBGA144
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 chip select.
2. DCMI and PSSI cannot be used at the same time as they share the same circuitry.
3. Active tampers in output sharing mode (one output shared by all inputs).

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Figure 1. STM32H533xx block diagram

NJTRST, JTDI,
JTCK/SWCLK, JTAG/ SW MPU
JTMS/SWDIO, JTDO CLK, NE[4:1], NL, NBL[1:0],
ETM NVIC A[25:0], D[15:0], NOE, NWE,
Flexible memory controller (FMC):
NWAIT, NCE, INT as AF

(8 Kbytes)
TRACECLK, SRAM, PSRAM, NOR Flash, FRAM, NAND Flash

ICACHE
TRACED[3:0] Arm Cortex-M33
250 MHz IO[7:0], CLK, NCLK, NCS.
C-BUS OCTOSPI1 memory interface DQS as AF
TrustZone FPU

S-BUS

(4 Kbytes)
DCACHE

AHB bus-matrix
Flash memory RNG
(up to 512 Kbytes)
HASH
D[7:0], D[3:1]dir
FIFO

CMD, CMDdir,CK, CKin SDMMC1 SRAM1 (128 Kbytes)

@VDDA
D0dir, D2dir DAC1_OUT1
SRAM2 (80 Kbytes)
ITF DAC1
SRAM3 (64 Kbytes) DAC1_OUT2

DCMI/PSSI D[15:0], CK, CMD as AF

AHB2 250 MHz

GPDMA1
AUDIOCLK as AF
@VDD
VDD Power management
@VDD
GPDMA2
Voltage regulator LDO VDD = 1.71 to 3.6 V
HSI48 3.3 to 1.2 V VSS

HS64 @VDD
Reset Supply supervision
CSI BOR
@VBAT Int
VDDIO, VDDUSB, VDDA,
LSI PVD, PVM VSSA, VDD, VSS, NRST
PA[15:0] GPIO port A BKPSRAM
(2 Kbytes) @VDD
PB[15:0] GPIO port B PLL 1, 2, 3
AHB1 250 MHz

AHB3 250 MHz

XTAL OSC OSC_IN

PC[15:0] GPIO port C
4- 50 MHz OSC_OUT
PD[15:0] GPIO port D
IWDG
RAMCFG
PE[15:0] GPIO port E
Reset and clock control
PF[15:0] GPIO port F GTZC1 Standby
interface WKUPx (x=1 to 8)
PG[15:0] GPIO port G
CRC
FCLK

HCLKx

PCLKx
PH[1:0] GPIO port H TIM2 32b 4 channels, ETR as AF

TIM3 32b 4 channels, ETR as AF

16 AF EXT IT. WKP
TIM4 32b 4 channels, ETR as AF
@VDDA CRS
20xIN ADC1 ITF TIM5 32b 4 channels, ETR as AF
ADC2 EXTI

3 compl. channels smcard

RX, TX, CK, CTS, RTS as AF
(TIM1_CH[1:3]N), AHB/APB2 AHB/APB1 USART2 irDA
TIM1/PWM 16b
6 channels (TIM1_CH[1:4]), smcard
APB1 250 MHz (max)

ETR, BKIN, BKIN2 as AF USART3 irDA RX, TX, CK, CTS, RTS as AF

3 compl. channels UART4 RX, TX, CTS, RTS as AF

(TIM1_CH[1:3]N), TIM8/PWM 16b
6 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF UART5 RX, TX, CTS, RTS as AF

2 channels, TIM15 16b smcard

APB2 250 MHz

1 compl. channel, BKIN as AF USART6 irDA RX, TX, CK, CTS, RTS as AF

MOSI, MISO, SCK, NSS as

smcard SPI2/I2S2
USART1 AF
RX, TX, CK,CTS, RTS as AF irDA
MOSI, MISO, SCK, NSS as
SPI3/I2S3
MOSI, MISO, SCK, NSS as AF
SPI1/I2S1
AF
DTS I2C1/SMBUS SCL, SDA, SMBA as AF
MOSI, MISO, SCK, NSS as SPI4
AF
WWDG I2C2/SMBUS SCL, SDA, SMBA as AF
@VDDUSB
FIFO

IWDG
PHY

DP USB FS FDCAN1 TX, RX as AF

FIFO

DM
FDCAN2 TX, RX as AF
TIM6 16b
PHY

TIM7 16b UCPD1 CC1, DBCC1, CC2, DBCC2,

Temperature FRSCC1, FRSCC2 as AF
monitoring
@VBAT LPTIM2
IN1, IN2, CH1, CH2,
RTC_OUT1, RTC_OUT2, XTAL 32k ETR as AF
AHB/APB3
RTC_REFIN, RTC_TS
RTC TIM12 16b 2 channels, ETR as AF
RTC_OUT[8:1], RTC_IN[8:1] TAMP

@VDDA HDMI-CEC CEC

VREF+
VREF buffer
APB3 250 MHz

I3C1 SCL, SDA

IN1, IN2, CH1, CH2,
LPTIM1
ETR as AF

SCL, SDA, SMBA as AF I2C3/SMBUS

RX, TX, CTS,

LPUART1
RTS_DE as AF

SCL, SDA I3C2

VDD power VDDUSB power VBAT power VDDA power
SBS domain domain domain domain
MSv72393V2

Note: PC[15:13] are in the VBAT domain.

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17
Functional overview STM32H533xx

3 Functional overview

3.1 Arm Cortex-M33 core with TrustZone and FPU

The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor designed for
microcontrollers and deeply embedded applications, especially those requiring efficient
security.
The Cortex-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. It features:
• Arm TrustZone technology, using the Armv8-M main extension supporting secure and
non-secure states
• Memory protection units (MPUs), supporting up to 16 regions for secure and
non-secure applications
• Configurable secure attribute unit (SAU) supporting up to eight memory regions as
secure or non-secure
• Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces:
• System AHB bus:
The system AHB (S-AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
• Code AHB bus:
The code AHB (C-AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32H533xx devices.

3.2 ART Accelerator (ICACHE and DCACHE)

3.2.1 Instruction cache (ICACHE)

The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex-M33 processor
to improve performance when fetching instruction (or data) from both internal and external
memories.
ICACHE offers the following features:
• Multi-bus interface:
– slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
– master1 port performing refill requests to internal memories (flash memory and
SRAMs)
– master2 port performing refill requests to external memories (external flash
memory and RAMs through Octo-SPI and FMC interfaces)
– a second slave port dedicated to ICACHE registers access

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• Close to 0 wait-states instructions/data access performance:

– 0 wait-states on cache hit
– hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
– critical-word-first refill policy, minimizing processor stalls on cache miss
– hit ratio improved by two-way set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– dual master ports allowing to decouple internal and external memory traffic,
respectively, on fast and slow buses, minimizing impact on interrupt latency
– optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– performance monitoring by means of a hit counter and a miss counter
• Extension of cacheable region beyond the code memory space, by means of address
remapping logic that allows four cacheable external regions to be defined
• Power consumption reduced intrinsically (more accesses to cache memory rather to
bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default two-way set-associative mode)
• TrustZone security support
• Maintenance operation for software management of cache coherency
• Error management: detection of unexpected cacheable write access, with optional
interrupt raising

3.2.2 Data cache (DCACHE)

The data cache (DCACHE) is introduced on S-AHB system bus of Cortex-M33 processor to
improve the performance of data traffic to/from external memories.
DCACHE offers the following features:
• Multi-bus interface:
– slave port receiving the memory requests from the Cortex-M33 S-AHB system
port
– master port performing refill requests to external memories (external flash memory
and RAMs through Octo-SPI and FMC interfaces)
– a second slave port dedicated to DCACHE registers access
• Close to zero wait-states external data access performance:
– zero wait-states on cache hit
– hit-under-miss capability, allowing to serve new processor requests to cached
data, while a line refill (due to a previous cache miss) is still ongoing
– critical-word-first refill policy for read transactions, minimizing processor stalls on
cache miss
– hit ratio improved by two-way set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– performance monitoring by means of two hit counters (for read and write) and two
miss counters (for read and write)

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60
Functional overview STM32H533xx

• Supported cache accesses:

– supports both write-back and write-through policies (selectable with AHB
bufferable attribute)
– read and write-back always allocated
– write-through always non-allocated (write-around)
– supports byte, half-word and word writes
• TrustZone security support
• Maintenance operations for software management of cache coherency:
– full cache invalidation (non interruptible)
– address range clean and/or invalidate operations (background task, interruptible)
• Error management: detection of error for master port request initiated by DCACHE (line
eviction or clean operation), with optional interrupt raising

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by other
active tasks. This memory area is organized into up to 20 protected areas (12 secure and 8
non-secure). The MPU regions and registers are banked across secure and non-secure
states.
The MPU is especially helpful for applications where critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by an RTOS
(real-time operating system).
If a program accesses a memory location prohibited by the MPU, the RTOS can detect it
and take action. In an RTOS environment, the kernel can dynamically update the MPU area
setting based on the process to be executed.

3.4 Embedded flash memory

The devices feature 512 Kbytes of embedded flash memory for storing programs and data.
The flash memory supports high-cycle data area of up to 100 K cycles.
The flash memory interface features:
• dual-bank operating modes
• read-while-write (RWW)
This allows a read operation to be performed from one bank while an erase or program
operation is performed to the other bank. Each bank contains 32 pages of 8 Kbytes.
The flash memory embeds a 2-Kbyte OTP (one-time programmable) for user data, and up
to 96 Kbytes supporting high cycling capability (100 K cycles), to be used for data
(EEPROM emulation).

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Option bytes are available to set the flash memory protection mechanisms:
• Different product states for protecting memory content from debug access
• Write protection (WRP) to protect areas against erasing and programming. Two areas
per bank can be selected with 8-Kbyte granularity.
• Sector group write-protection (WRPSG), protecting up to 32 groups of four sectors
(32 Kbytes) per bank
• Two secure-only areas (one per user flash memory bank). When enabled, this area is
accessible only if the STM32 device operates in Secure-access mode
• One HDP area per bank providing temporal isolation for startup code
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• Single-error detection and correction
• Double-error detection
• ECC fail address report

3.4.1 FLASH security and protections

Sensitive information is stored in the flash memory and it is important to protect the memory
against unwanted operations such as reading confidential areas, illegal programming of
immutable sectors, or malicious flash memory erasing.
For that purpose FLASH implements the following protection mechanisms:
• TrustZone backed watermark and block security protection
• Temporal isolation protection (HDP)
• Configuration protection
• User flash memory write protection
• Device non-volatile security life cycle and application boot state management
• OTP locking
Refer to the product reference manual for a detailed description of the security mechanisms.

3.4.2 FLASH privilege protection

Each flash memory sector can be programmed on the fly as privileged or unprivileged.

3.5 Embedded SRAMs

Four SRAMs are embedded in the STM32H533xx devices, each with specific features.
SRAM1, SRAM2, and SRAM3 are the main SRAMs.
These SRAMs are made of several blocks that can be powered down in Stop mode to
reduce consumption:
• SRAM1: 128 Kbytes
• SRAM2: 80 Kbytes with ECC
• SRAM3: 64 Kbytes
• BKPSRAM (backup SRAM): 2 Kbytes with ECC. The BKPSRAM can be retained in all
low-power modes and when VDD is off in VBAT mode.

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Note: The ECC is supported by SRAM2, and BKPSRAM when enabled with the SRAM2_ECC,
and BKPRAM_ECC user option bits.

3.5.1 SRAMs TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM1,
SRAM2, SRAM3, can be programmed as secure or non-secure by blocks, using the
MPCBB (block-based memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions
can be programmed as secure or non-secure with watermark, using the TZSC (TrustZone
security controller) in the GTZC (global TrustZone controller).

3.5.2 SRAMs privilege protection

The SRAM1, SRAM2, SRAM3, can be programmed as privileged or non-privileged by
blocks, using the MPCBB. The granularity of SRAM privilege block based is a page of
512 bytes. Backup SRAM regions can be programmed as privileged or non-privileged with
watermark, using the TZSC (TrustZone security controller) in the GTZC (global TrustZone
controller).

3.6 Security overview

The STM32H533xx security enables the possibility to reopen the debug mode even if the
product is in secure state.
The reopening of the debug mode is controlled with a debug authentication procedure which
permits the authentication of the host.
The sensible assets such as keys or secret codes must be protected when opening the
debug mode. The protection is made via code protection and hardware keys storage
solutions where all root of trust can be protected thanks to hardware mechanisms.
In cases where sensitive information cannot be protected, a partial or a full regression can
be launched in order to allow a debugging. Regressions are enabled by a debug
authentication method.
The STM32H533xx design also permits the developers to introduce their own root of trust
solution (OEM-iROT), including their installation in a non-trusted environment thanks to a
secure firmware install (SFI) solution.
The STM32H533xx boot stages are isolated via a hardware mechanism called HDPL
(temporal isolation level). The HDPL guarantees isolation of the different boot stages: ST
assets, iROT (immutable root of trust), uROT (updatable root of trust), secure operating
system and non-secure applications.
STM32H533xx devices embed a hardware key storage solution with the following
characteristics:
• Feature a dedicated flash memory area per boot stages with access-control based on
HDPL and which can be secure or non-secure.
• The keys can be stored encrypted with a derived key related to the current execution
context (HDPL, regression counter called EPOCH, secure or non-secure).
• One crypto accelerator hardware DPA resistant (SAES), connected via hardware key
bus to a non-DPA protected accelerator.

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STM32H533xx devices are powered by an Arm Cortex-M33 microcontroller, which is

associated with all the TrustZone isolation infrastructure. This design permits to benefit from
a run time isolation to run secure applications.

3.7 Boot modes

At startup, a BOOT0 pin and NSBOOTADD[31:8]/SECBOOTADD[31:8] option bytes are
used to select the boot memory address that includes:
• Boot from any address in user flash memory
• Boot from system memory
– Bootloader
– ST immutable root of trust (ST-iROT)
– Root security service (RSS)
– Debug authentication library (RSS-DA)

Embedded bootloader
The embedded bootloader is located in the system memory, programmed by ST during
production. It is used to reprogram the flash memory by using USART, I2C, I3C, SPI,
FDCAN, or USB in device mode through the DFU (device firmware upgrade).
Refer to AN2606 STM32 microcontroller system memory boot mode.

Embedded root security services (RSS)

The embedded RSS are located in the secure information block, programmed by ST during
production.
Refer to AN4992 Overview secure firmware install (SFI).

Embedded immutable root of trust (ST-iROT)

The embedded ST-iROT in the system memory, programmed by ST during production. ST-
iROT is the immutable root of trust managing the secure boot and secure install of the first
updatable level to execute in a boot sequence.

Embedded debug authentication (ST-DA)

The embedded ST-DA in the system memory, programmed by ST during production. ST-DA
is the library that manages the debug authentication protocol by allowing to securely reopen
the debug or to launch regressions on secured products in the field.
For further information, refer to AN6008 “Getting started with debug authentication (DA) for
STM32H5 MCUs”.

3.7.1 STM32H533xx boot modes

Table 3 and Table 4, respectively, provide the detail of the boot mode when TrustZone is
disabled (TZEN = 0xC3) and enabled (TZEN = 0xB4).

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Table 3. STM32H533xx boot mode when TrustZone is disabled (TZEN = 0xC3)

BOOT_UBE Boot address
BOOT0 ST programmed default
PRODUCT_STATE FLASH_OP option-byte Boot area
pin value
TSR[29:22] selection

Boot address
defined by user
0 NA NSBOOTADD[31:8] Flash: 0x0800 0000
Open option byte
NSBOOTADD[31:8]
1 NA NA Bootloader Bootloader
Provisioning x NA NA RSS RSS
Boot address
Provisioned, defined by user
x NA NSBOOTADD[31:8] Flash: 0x0800 0000
Closed, Locked option byte
NSBOOTADD[31:8]

Table 4. STM32H533xx boot mode when TrustZone is enabled (TZEN = 0xB4)

BOOT_UBE Boot address
BOOT0 ST programmed
PRODUCT_STATE FLASH_OP option-byte Boot area
pin default value
TSR[29:22] selection

Boot address defined

SECBOOTADD
Open 0 x by user option byte Flash: 0x0C00 0000
[31:8]
SECBOOTADD[31:8]
- 1 0xB4 NA Bootloader Bootloader
- 1 0xC3 NA ST-iROT ST-iROT
Provisioning x NA NA RSS RSS
0xC3 ST-iROT ST-iROT ST-iROT
Provisioned, x Boot address defined
TZ_Closed, SECBOOTADD
x 0xB4 by user option byte Flash: 0x0C00 0000
Closed, Locked [31:8]
SECBOOTADD[31:8]

When TrustZone is enabled (TZEN=0xB4), the boot space must be in secure area. The
SECBOOTADD0[24:0] option bytes are used to select the boot secure memory address. A
unique boot entry option can be selected by setting the SECBOOT_LOCK option bit.

3.8 Global TrustZone controller (GTZC)

GTZC is used to configure TrustZone and privileged attributes within the full system.
The GTZC includes three different sub-blocks:
• TZSC: TrustZone security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the non-secure area size for the watermark memory peripheral controller

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(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
• TZIC: TrustZone illegal access controller
This sub-block gathers all security illegal access events in the system and generates a
secure interrupt towards NVIC.
• MPCBB: MPCBB: block-based memory protection controller
This sub-block controls secure states of all memory blocks (512-byte pages) of the
associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone
system product having segmented SRAM with programmable-security and privileged
attributes.
The GTZC main features are:
• Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
• MPCBB and TZIC accessible only with secure transactions
– Enable illegal access events that may trigger a secure interrupt
• Secure and non-secure access supported for privileged/non-privileged part of TZSC
• Set of registers to define product security settings:
– Secure/privilege regions for external memories
– Secure/privilege access mode for securable peripherals
– Secure/privilege access mode for securable legacy masters

3.9 TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTSR2 register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the access permissions based on secure
and non-secure state.
• SAU: up to eight SAU configurable regions are available for security attribution.
• IDAU: It provides a first memory partition as non-secure or non-secure callable
attributes. It is then combined with the results from the SAU security attribution and the
higher security state is selected.
Based on IDAU security attribution, the flash memory, system SRAMs and peripherals
memory space is aliased twice for secure and non-secure states. However, the external
memories space is not aliased.

3.9.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-
aware type as follows:
• securable: peripheral protected by an AHB/APB firewall gate controlled from TZSC to
define security properties
• TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing
a specific TrustZone behavior such as a subset of registers being secure

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3.9.2 Default TrustZone security state

The default system security state is detailed below:
• CPU:
– Cortex-M33 is in secure state after reset. The boot address must be in secure
address.
• Memory map:
– SAU is fully secure after reset. Consequently, all memory map is fully secure. Up
to eight SAU configurable regions are available for security attribution.
• Flash memory:
– Flash memory security area is defined by watermark user options.
– Flash memory block based area is non-secure after reset.
• SRAMs:
– All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
• External memories:
– FMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) is secure.
• Peripherals
– Securable peripherals are non-secure after reset.
– TrustZone-aware peripherals are non-secure after reset. Their secure
configuration registers are secure.
• All GPIOs are secure after reset.
• Interrupts:
– NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-
secure state.
• TZIC: All illegal access interrupts are disabled after reset.

3.10 Power supply management

The power controller (PWR) main features are:
• Power supplies and supply domains
– Core domain (VCORE)
– VDD domain
– Backup domain (VBAT)
– Analog domain (VDDA)
– VDDIO2 domain
– VDDUSB for USB transceiver
• System supply voltage regulation
– Voltage regulator (LDO)
• Power supply supervision
– POR/PDR monitor
– BOR monitor
– PVD monitor

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• Power management
– Operating modes
– Voltage scaling control
– Low-power modes
• VBAT battery charging
• TrustZone security and privileged protection

3.10.1 Power supply schemes

The devices require a 1.71 to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
• VDDA = 1.62 V (ADCs), 1.8 V (DACs), or 2.1 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for ADCs, DACs and voltage reference
buffer. This voltage level is independent from VDD, and must preferably be connected to
VDD when these peripherals are not used.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. It is
independent from VDD, and must preferably be connected to VDD when the USB is not
used.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 10 I/Os (PD6, PD7, PG9:14, PB8, PB9). This
voltage level is independent from VDD, voltage and must preferably be connected to
VDD when those pins are not used.
• VBAT = 1.2 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
VREF+ can be grounded when ADC and DAC are not active.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled.
VREF- must always be equal to VSSA.
The devices embed an LDO regulator to provide the VCORE supply for digital peripherals,
SRAM1, SRAM2, SRAM3 and embedded flash memory. The LDO generates this voltage on
VCAP pin connected to an external capacitor of 2x 2.2 μF (typical).
This regulator can provide four different voltages (voltage scaling), and can operate in Stop
modes.

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Figure 2. STM32H533xx power supply overview

VDDA domain
A/D converters
VDDA
D/A converters
VSSA
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS

VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temperature sensor Core
3 x PLL
VSS Internal RC oscillators SRAM1
SRAM2
Standby circuitry SRAM3
VDD (Wakeup logic, IWDG)
VCORE
VCAP Digital
peripherals
LDO regulator

Flash memory
Low-voltage detector

Backup domain
LSE crystal 32kHz oscillator
VBAT Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
MSv64011V1

During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain
below VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
• During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-
down transient phase.

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Figure 3. Power-up/down sequence

V

3.6
VDDX(1)

VDD

VBOR0

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1

1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.

3.10.2 Power supply supervisor

The devices have an integrated ultra-low-power brownout reset (BOR) active in all modes;
The BOR ensures proper operation of the devices after power on and during power down.
The devices remain in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD
is higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor that compares the independent
supply voltages VDDA, VDDUSB and VDDIO2 to ensure that the peripheral is in its functional
supply range.
The devices support dynamic voltage scaling to optimize power consumption in Run mode.
The voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system maximum operating frequency.
The main regulator operates in the following ranges:
• VOS0 (VCORE = 1.35 V) with CPU and peripherals running at up to 250 MHz
• VOS1 (VCORE = 1.2 V) with CPU and peripherals running at up to 200 MHz
• VOS2 (VCORE = 1.1 V) with CPU and peripherals running at up to 150 MHz
• VOS3 (VCORE = 1.0 V) with CPU and peripherals running at up to 100 MHz

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Low-power modes
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the CSI, the
HSI, the HSI48 and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
The system clock when exiting from Stop mode can be either HSI up to 64 MHz or CSI
(4 MHz), depending on software configuration.
• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
PLL, the HSI, the CSI, the HSI48 and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active in Standby mode.
The I/Os state during Standby mode can be retained.
After entering Standby mode, SRAMs and register contents are lost except for registers
and backup SRAM in the Backup domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), an RTC event occurs (alarm,
periodic wake-up, timestamp), or a tamper detection. The tamper detection can be
raised either due to external pins or due to an internal failure detection.
The system clock after wake-up is HSI at 32 MHz.

3.10.3 Reset mode

To improve the consumption under reset, the I/Os state under and after reset is “analog
state” (the I/O Schmitt trigger is disabled).

3.10.4 VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or an
external super-capacitor.
The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers
and 2-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.

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3.10.5 PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security secures the following configuration:
• Low-power mode
• Wake-up (WKUP) pins
• Voltage detection and monitoring
• VBAT mode
Some of the PWR configuration bits security is defined by the security of other peripherals:
• The voltage scaling (VOS) configuration is secure when the system clock selection is
secure in RCC.
• The I/O pull-up/pull-down in Standby mode configuration is secure when the
corresponding GPIO is secure.
• The backup domain write protection is secure when the RTC is secure.

3.11 Peripheral interconnect matrix

Several peripherals have direct connections between them, that allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run and Sleep modes.

3.12 Reset and clock controller (RCC)

The clock controller distributes the clocks coming from the different oscillators to the core
and to the peripherals. It also manages the clock gating for low-power modes and ensures
the clock robustness. It features:
• Clock prescaler: in order to get the best trade-off between speed and current
consumption, the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
• Clock security system: clock sources can be changed safely on the fly in Run mode
through a configuration register.
• Clock management: in order to reduce the power consumption, the clock controller
can stop the clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 4 to 50 MHz high-speed external crystal or ceramic resonator (HSE), can supply a
PLL. The HSE can also be configured in bypass mode for an external clock.
– 64 MHz high-speed internal RC oscillator (HSI), trimmable by software, can
supply a PLL.
– 4 MHz low-power internal oscillator (CSI), trimmable by software, can supply a
PLL.
– System PLL, which can be fed by HSE, HSI or CSI, with a maximum frequency at
250 MHz.

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• RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48),
can be used to drive the USB.
• UCPD kernel clock, derived from HSI clock. The HSI RC oscillator must be enabled
prior to the UCPD kernel clock use.
• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
• Peripheral clock sources: several peripherals have their own independent clock
whatever the system clock. Three PLLs, each having three independent outputs
allowing the highest flexibility, can generate independent clocks for the ADC, USB,
SDMMC, RNG, FDCAN1, OCTOSPI.
• Startup clock: after reset, the microcontroller restarts by default with an internal
32 MHz clock (HSI/2). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock automatically switches to HSI and a software interrupt
is generated if enabled. LSE failure can also be detected and generates an interrupt.
• Clock-out capability:
– MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application.
– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT mode).
Several prescalers allow AHB and APB frequencies configuration. The maximum frequency
of the AHB and the APB clock domains is 250 MHz.

3.12.1 RCC TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security secures some RCC system configuration and peripheral
configuration clock from being read or modified by non-secure accesses: when a peripheral
is secure, the related peripheral clock, reset, clock source selection and clock enable during
low-power modes control bits are secure.
A peripheral is in secure state:
• when its corresponding SEC security bit is set in the TZSC (TrustZone security
controller), for securable peripherals.
• when a security feature of this peripheral is enabled through its dedicated bits, for
TrustZone-aware peripherals.

3.13 Clock recovery system (CRS)

The devices embed a special block that allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. The
trimming is based on the external synchronization signal, derived from USB SOF
signalization, from LSE oscillator, from an external signal on CRS_SYNC pin, or generated

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by user software. For faster lock-in during startup, automatic and manual trimming actions
can be combined.

3.14 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
Ten IOs (PD6, PD7, PG9:14, PB8, PB9) can be independently supplied by a dedicated
VDDIO supply.

3.14.1 GPIOs TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a non-secure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.

3.15 Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, GPDMA1, GPDMA2,
SDMMC1) and the slaves (flash memory, FMC, OCTOSPI, SRAMs, AHB and APB)
peripherals. It also ensures a seamless and efficient operation even when several high-
speed peripherals work simultaneously.

3.16 General purpose direct memory access controller (GPDMA)

The GPDMA controller is a bus master and system peripheral. It used to perform
programmable data transfers between memory-mapped peripherals and/or memories via
linked-lists, upon the control of an off-loaded CPU. The GPDMA main features are:
• Dual bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep mode
• Transfers arbitration based on a four-grade programmed priority at a channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)

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• Per channel event generation, on any of the following events: transfer complete or half
transfer complete or data transfer error or user setting error, and/or update linked-list
item error or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable per
event
• 8 concurrent DMA channels:
– Per channel FIFO for queuing source and destination transfers
– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– 6 channels with linear source and destination addressing: either fixed or
contiguously incremented addressing, programmed at a block level, between
successive single transfers
– Four channels with 2D source and destination addressing: programmable signed
address offsets between successive burst transfers (non-contiguous addressing
within a block, combined with programmable signed address offsets between
successive blocks, at a second 2D/repeated block level)
– Support for scatter-gather (multi-buffer transfers), data interleaving and
de-interleaving via 2D addressing
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting including FIFO level and event flags
• TrustZone support:
– Support for secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source/destination and link sub-levels
– Secure and non-secure interrupts reporting, resulting from any of the respectively
secure and non-secure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a non-secure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at a channel
level
– Privileged-aware AHB slave port

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3.17 Interrupts and events

3.17.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels
and to handle up to 125 maskable interrupt channels plus the 16 interrupt lines of the
Cortex-M33.
The NVIC benefits are the following:
• closely coupled NVIC giving low-latency interrupt processing
• interrupt entry vector table address passed directly to the core
• early processing of interrupts
• processing of late arriving higher priority interrupts
• support for tail chaining
• processor state automatically saved
• interrupt entry restored on interrupt exit with no instruction overhead
• TrustZone support: NVIC registers banked across secure and non-secure states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.

3.17.2 Extended interrupt/event controller (EXTI)

The extended interrupts and event controller (EXTI) manages the individual CPU and
system wake-up through configurable event inputs. It provides wake-up requests to the
power control, and generates an interrupt request to the CPU NVIC and events to the CPU
event input. For the CPU an additional event generation block (EVG) is needed to generate
the CPU event signal.
The EXTI wake-up requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes. The
EXTI also includes the EXTI multiplexer IO port selection.
The EXTI main features are the following:
• All event inputs allowed to wake up the system
• Configurable events (signals from I/Os or peripherals able to generate a pulse)
– Selectable active trigger edge
– Interrupt pending status register bit independent for the rising and falling edge
– Individual interrupt and event generation mask, used for conditioning the CPU
wake-up, interrupt and event generation
– Software trigger possibility
• TrustZone secure events
– The access to control and configuration bits of secure input events can be made
secure
• EXTI IO port selection

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3.18 Cyclic redundancy check calculation unit (CRC)

The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and that can be
stored at a given memory location.

3.19 Flexible memory controller (FMC)

The FMC includes three memory controllers:
• NOR/PSRAM memory controller
• NAND memory controller
The main features of the FMC controller are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (four memory banks)
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data
– Ferroelectric RAM (FRAM)
• 8-,16- bit data bus width
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO

3.19.1 LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to
specific LCD interfaces.
This LCD parallel interface capability makes it easy to build cost effective graphic
applications using LCD modules with embedded controllers or high-performance solutions
using external controllers with dedicated acceleration.

3.19.2 FMC TrustZone security

When the TrustZone security is enabled, the whole FMC banks are secure after reset. Non-
secure area can be configured using the TZSC MPCWMx controller.
• The FMC NOR/PSRAM bank:
– Up to two non-secure area can be configured thought the TZSC MPCWM2
controller with a 64-Kbyte granularity
• The FMC NAND bank:

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– Can be either configured as fully secure or fully non-secure using the TZSC
MPCWM3 controller
The FMC registers can be configured as secure through the TZSC controller.

3.20 Octo-SPI interface (OCTOSPI)

The OCTOSPI supports most external serial memories such as serial PSRAMs, serial
NAND and serial NOR flash memories, HyperRAMs™ and HyperFlash™ memories, with
the following functional modes:
• Indirect mode: all the operations are performed using the OCTOSPI registers.
• Status-polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation.
The OCTOSPI supports the following protocols with associated frame formats:
• the standard frame format with the command, address, alternate byte, dummy cycles
and data phase
• the HyperBus™ frame format
The OCTOSPI offers the following features:
• Three functional modes: Indirect, Status-polling, and Memory-mapped
• Read and write support in Memory-mapped mode
• Supports for single, dual, quad and octal communication
• Dual-quad mode, where eight bits can be sent/received simultaneously by accessing
two quad memories in parallel.
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• HyperBus support
• Integrated FIFO for reception and transmission
• 8-, 16-, and 32-bit data accesses allowed
• DMA channel for Indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error

3.20.1 OCTOSPI TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a
granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.

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3.21 Delay block (DLYB)

The delay block (DLYB) is used to generate an output clock dephased from the input clock.
The phase of the output clock must be programmed by the user application. The output
clock is then used to clock the data received by another peripheral such as an SDMMC or
Octo-SPI interface. The delay is voltage and temperature dependent, that may require the
application to re-configure and recenter the output clock phase with the received data.
The delay block main features are:
• Input clock frequency ranging from 25 to 250 MHz
• Up to 12 oversampling phases

3.22 Analog-to-digital converter (ADC1 and ADC2)

The devices embed two successive approximation analog-to-digital converters.

Table 5. ADC features

Mode/feature ADC1 ADC2

Resolution 12 bit
Maximum sampling speed up to 5 Msps (12-bit resolution)
Dual mode operation X
Hardware offset calibration X
Hardware linearity calibration -
Single-end input X
Differential input X
Injected channel conversion X
Oversampling Up to x256
Data register 16 bits
Data register FIFO depth 3 stages
DMA support X
Parallel data output to ADF -
Offset compensation X
Gain compensation -
Number of analog watchdogs 3
Option register X

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3.22.1 Analog temperature sensor

This sensor generates a voltage (VSENSE) that varies linearly with temperature. It is
internally connected to an ADC input channel used to convert the output voltage into a
digital value.
The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the
temperature measurement. As the offset of the temperature sensor varies from chip to chip
due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect only temperature changes.
To improve the measurement accuracy, each device is individually factory-calibrated by ST.
The calibration data are stored in the system memory area, accessible in read-only mode.

3.22.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC. The VREFINT is internally connected to ADC input channel.
The precise voltage of VREFINT is individually measured for each part by
STMicroelectronics during production test and stored in the system memory area. It is
accessible in read-only mode.

3.22.3 VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage using
ADC or input channel. As the VBAT voltage may be higher than the VDDA, and thus outside
the ADC input range, the VBAT pin is internally connected to a bridge divider by four. As a
consequence, the converted digital value is a quarter of the VBAT voltage.

3.23 Digital temperature sensor (DTS)

The devices embeds a sensor that converts the temperature into a square wave, whose
frequency is proportional to the temperature. The PCLK or the LSE clock can be used as
reference clock for the measurements. Use the formula given in the product reference
manual to calculate the temperature according to the measured frequency stored in the
DTS_DR register.

3.24 Digital to analog converter (DAC)

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode, and can be used in conjunction with the DMA controller. In
12-bit mode, the data may be left- or right-aligned.
The DAC features two output channels, each with its own converter. In dual DAC channel
mode, conversions can be done independently or simultaneously when both channels are
grouped together for synchronous update operations. An input reference pin, VREF+
(shared with others analog peripherals) is available for better resolution. An internal
reference can also be set on the same input.
The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to allow a high drive output current. An individual

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calibration can be applied on each DAC output channel. The DAC output channels support
a low power mode, the Sample and hold mode.
The digital interface supports the following features:
• One DAC interface, maximum two output channels
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and triangular-wave generation
• Sawtooth wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• Double data DMA capability to reduce the bus activity
• External triggers for conversion
• DAC output channel buffered/unbuffered modes
• Buffer offset calibration
• Each DAC output can be disconnected from the DAC_OUTx output pin
• DAC output connection to on chip peripherals
• Sample and Hold mode for low-power operation in Stop mode. The DAC voltage can
be changed autonomously with the DMA while the device is in Stop mode.
• Voltage reference input

3.25 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as reference for ADCs and
DACs, and also as reference for external components through the VREF+ pin.
The internal voltage reference buffer supports voltages: 1.8 V, 2.048 V and 2.5 V.
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.

3.26 Digital camera interface (DCMI)

DCMI is a synchronous parallel interface able to receive a high-speed data flow from an
external 8-, 10-, 12- or 14-bit CMOS camera module, supporting YCbCr4:2:2/RGB565
progressive video and compressed data (JPEG) formats. It can be used with black and
white cameras, X24 and X5 cameras (it is assumed that all preprocessing such as resizing
is performed in the camera module).
Main features:
• 8-, 10-, 12-, or 14-bit parallel interface
• Embedded/external line and frame synchronization
• Continuous or snapshot mode
• Crop feature
• Support of the following data formats:

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– 8/10/12/14-bit progressive video: monochrome or raw Bayer

– YCbCr 4:2:2 progressive video
– RGB 565 progressive video
– Compressed data: JPEG

3.27 Parallel synchronous slave interface (PSSI)

The PSSI peripheral and the DCMI (digital camera interface) use the same circuitry. As a
result, these two peripherals cannot be used at the same time: when using the PSSI, the
DCMI registers cannot be accessed, and vice versa. In addition, the PSSI and the DCMI
share the same alternate functions and the same interrupt vector.
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
enables the transmitter to send a data valid signal that indicates when the data is valid, and
the receiver to output a flow control signal that indicates when it is ready to sample the data.
The PSSI peripheral main features are the following:
• Slave mode operation
• 8-bit or 16-bit parallel data input or output
• 4-word (16-byte) FIFO
• Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate
function output
When selected, these inputs can either enable the transmitter to indicate when the data is
valid, or allow the receiver to indicate when it is ready to sample the data, or both.

3.28 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
non-deterministic random bit generator (NDRBG).
The true random generator:
• delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage
• can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG)
• produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise)
• embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration)
• has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored)

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3.29 Secure advanced encryption standard hardware accelerator

(SAES) and encryption standard hardware accelerator (AES)
The devices embed two AES accelerators: SAES and AES. The SAES with hardware
unique key embeds protection against differential power analysis (DPA) and related side
channel attacks. The SAES can share its current key register information with the faster
AES using a dedicated hardware bus.
The SAES and the AES can be used to both encrypt and decrypt data using the AES
algorithm. It is a fully compliant implementation of the advanced encryption standard (AES)
as defined by Federal Information Processing Standards Publication (FIPS PUB 197, Nov
2001).
Multiple chaining modes are supported for key sizes of 128 or 256 bits. ECB, CBC, CTR,
CCM, GCM and GMAC chaining are supported by the AES and SAES.
SAES and AES support DMA single transfers for incoming and outgoing data (two DMA
channels required).
The SAES supports the selection of all the following key sources, while the AES support
only the first:
• 256-bit software key, written by the application in the key registers (write only)
• 256-bit derived by hardware secure key management.
The SAES and AES peripherals support:
• Compliant implementation of standard NIST Special Publication 197, Advanced
Encryption Standard (AES) and Special Publication 800-38A, Recommendation for
Block Cipher Modes of Operation
• 128-bit data block processing
• Support for cipher keys length of 128-bit and 256-bit
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode
– Counter (CTR) mode
– Galois counter mode (GCM)
– Galois message authentication code (GMAC) mode
– Counter with CBC-MAC (CCM) mode
• 528 or 743 clock cycle latency in ECB encryption mode for SAES processing one
128-bit block of data with, respectively, 128-bit or 256-bit key
• 51 or 75 clock cycle latency in ECB encryption mode for AES processing one 128-bit
block of data with, respectively, 128-bit or 256-bit key
• Integrated round key scheduler to compute the last round key for AES ECB/CBC
decryption
• 256-bit register for storing the cryptographic key (four 32-bit registers), with key
atomicity enforcement
• 128-bit registers for storing initialization vectors (four 32-bit registers)
• One 32-bit INPUT buffer and one 32-bit OUTPUT buffer
• Automatic data flow control with support of single-transfer direct memory access (DMA)
using two channels (one for incoming data, one for processed data)

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• Data swapping logic to support 1-, 8-, 16- or 32-bit data

• Possibility for software to suspend a message if the SAES/AES needs to process
another message with a higher priority (suspend/resume operation)

Table 6. AES/SAES features

AES/SAES modes/features(1) AES SAES

ECB, CBC chaining X X

CTR, CCM, GCM chaining X X
AES 128-bit ECB encryption in cycles 51 528
DHUK and BHK key selection - X
Side-channel attacks resistance - X
Shared key between SAES and AES X
1. X = supported.

3.30 HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256, SHA-512) and the HMAC (keyed-hash message
authentication code) algorithm. HMAC is suitable for applications requiring message
authentication.
The HASH computes FIPS (Federal information processing standards) approved digests of
length of 160, 224, 256, 512 bits, for messages of up to (264 – 1).
The HASH main features are:
• Suitable for data authentication applications, compliant with:
– Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
– Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
• Fast computation of SHA-1, SHA-224, SHA-256 and SHA-512
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit string
– Word swapping supported: bits, bytes, half-words and 32-bit words
• Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)
• Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size

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• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
• 8 × 32-bit words (H0 to H7) for output message digest
• Automatic data flow control with support of direct memory access (DMA) using one
channel. Single or fixed burst of 4 supported.
• Interruptible message digest computation, on a per-32-bit word basis
– Re-loadable digest registers
– Hashing computation suspend/resume mechanism, including using DMA

3.31 On-the-fly decryption engine (OTFDEC)

The OTFDEC allows the decryption of the on-the-fly AHB traffic based on the read request
address information, for example execute-in-place of a code stored encrypted. Four
independent and non-overlapping encrypted regions can be defined in OTFDEC.
OTFDEC uses AES-128 in counter mode to achieve the lowest possible latency. As a
consequence, each time the content of one encrypted region is changed the entire region
must be re-encrypted with a different cryptographic context (key or initialization vector). This
constraint makes OTFDEC suitable to decrypt read-only data or code, stored in external
NOR flash.
Note: When OTFDEC is used in conjunction with OCTOSPI, it is mandatory to access the flash
memory using the Memory-mapped mode of the flash memory controller.
When security is enabled in the product, OTFDEC can be programmed only by a secure
host.
The OTFDEC main features are the following:
• On-the-fly 128-bit decryption during OCTOSPI memory-mapped read operations
(single or multiple)
– Use of AES in counter (CTR) mode, with two 128-bit keystream buffers
– Support for any read size
– Physical address of the reads is used for the encryption/decryption
• Up to 4 independent encrypted regions
– Granularity of the region definition: 4096 bytes
– Region configuration write locking mechanism
– Each region has its own 128-bit key, two bytes firmware version, and eight bytes
application-defined nonce. At least one of those must be changed each time an
encryption is performed by the application.
• Encryption keys confidentiality and integrity protection
– Write-only registers, with software locking mechanism
– Availability of 8-bit CRC as public key information
• Support for OCTOSPI pre-fetching mechanism
• Possibility to select an enhanced encryption mode to add a proprietary layer of
protection on top of AES stream cipher (execute only)
• AMBA® AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated, and write accesses are ignored)
• Secure only programming if TrustZone security is enabled

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• Encryption mode

3.32 Public key accelerator (PKA)

The PKA is used for the computation of cryptographic public key primitives, specifically
those related to RSA, Diffie-Hellmann or ECC (elliptic curve cryptography) over GF(p)
(Galois fields). To achieve high performance at a reasonable cost, these operations are
executed in the Montgomery domain.
All needed computations are performed within the accelerator, so no further
hardware/software elaboration is needed to process the inputs or the outputs.
The PKA main features are:
• Acceleration of RSA, DH and ECC over GF(p) operations, based on the Montgomery
method for fast modular multiplications. More specifically:
– RSA modular exponentiation, RSA Chinese remainder theorem (CRT)
exponentiation
– ECC scalar multiplication, point on curve check, complete addition, double base
ladder, projective to affine
– ECDSA signature generation and verification
• Capability to handle operands up to 4160 bits for RSA/DH and 640 bits for ECC
• Arithmetic and modular operations such as addition, subtraction, multiplication,
modular reduction, modular inversion, comparison, and Montgomery multiplication
• Built-in Montgomery domain inward and outward transformations
• Protection against differential power analysis (DPA) and related side-channel attacks.

3.33 Timers and watchdogs

The devices include two advanced control timers, up to seven general-purpose timers, two
basic timers, six low-power timers, two watchdog timers and two SysTick timers.
Table 7 compares the features of the advanced control, general-purpose and basic timers.

Table 7. Timer features

DMA Capture/
Counter Counter Prescaler Complementary
Type Timer request compare
resolution type factor outputs
generation channels

Advanced
TIM1, TIM8 16 bits 4 3
control
Up, down,
General TIM2, TIM5 32 bits up/down 4 No
Any integer
purpose TIM3, TIM4 16 bits between 1 and Yes 4 No
65536
General
TIM12, TIM15 16 bits Up 2 1
purpose
Basic TIM6, TIM7 16 bits Up 0 No

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3.33.1 Advanced-control timers (TIM1, TIM8)

These timers can be seen as a three-phase PWM multiplexed on six channels. They have
complementary PWM outputs with programmable inserted dead-times. They can also be
seen as complete general-purpose timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability
(0 - 100 %)
• One-pulse mode output
In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in the next
section) using the same architecture, so the advanced-control timers can work together with
the TIMx timers via the Timer Link feature for synchronization or event chaining.

3.33.2 General-purpose timers

(TIM2, TIM3, TIM4, TIM5, TIM12, TIM15)
The devices embed up to seven synchronizable general-purpose timers (see Table 7), each
of them can be used to generate PWM outputs, or act as a simple time base.
• TIM2 and TIM5
Full-featured general-purpose timers with 32-bit auto-reload up/downcounter and 32-bit
prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in Debug mode.
All have independent DMA request generation and support quadrature encoders.
• TIM3 and TIM4
Full-featured general-purpose timers with 16-bit auto-reload up/downcounter and 16-bit
prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output.
They can work together, or with the other general-purpose timers via the Timer Link
feature for synchronization or event chaining.
The counters can be frozen in Debug mode. All have independent DMA request
generation and support quadrature encoders.
• TIM12, and 15
General-purpose timers with mid-range features.
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM12 and TIM15 have two channels and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.

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The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in Debug mode.

3.33.3 Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit timebase.

3.33.4 Low-power timers

(LPTIM1, LPTIM2)
The devices embed six low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wake up the system from Stop mode.
The low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)
• Selectable clock
– Internal clock sources: LSE, LSI, HSI or APB clock
– External clock source over LPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
• 16-bit ARR autoreload register
• 16-bit capture/compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable digital glitch filter
• Configurable output: pulse, PWM
• Configurable I/O polarity
• Encoder mode
• Repetition counter
• Up to two independent channels for:
– Input capture
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on ten events
• DMA request generation on the following events:
– Update event
– Input capture

3.33.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for

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application timeout management. It is hardware or software configurable through the option

bytes. The counter can be frozen in Debug mode.

3.33.6 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.

3.33.7 SysTick timer

The Cortex-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
• SysTick, secure instance
• SysTick, non-secure instance
When TrustZone is disabled, only one SysTick timer is available. This timer (secure or non-
secure) is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.

3.34 Real-time clock (RTC), tamper and backup registers

3.34.1 Real-time clock (RTC)

The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date,
month, year, in BCD (binary-coded decimal) format
• Binary mode with 32-bit free-running counter
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Two programmable alarms
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
• 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable
resolution and period
• TrustZone support:

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– RTC fully securable

– Alarm A, alarm B, wake-up timer and timestamp individual secure or non-secure
configuration
– Alarm A, alarm B, wake-up timer and timestamp individual privileged protection
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be one of the following:
• 32.768 kHz external crystal (LSE)
• external resonator or oscillator (LSE)
• internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake up
the device from the low-power modes.

3.34.2 Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks.
32 32-bit backup registers are retained in all low-power modes and in VBAT mode. The
backup registers, as well as other secrets in the device, are protected by this anti-tamper
detection circuit with eight tamper pins and nine internal tampers. The external tamper pins
can be configured for edge detection, or level detection with or without filtering, or active
tamper that increases the security level by auto checking that the tamper pins are not
externally opened or shorted.
TAMP main features:
• A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches
and cryptographic peripherals.
• 32 32-bit backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the Backup domain that
remains powered-on by VBAT when the VDD power is switched off.
• Up to 8 tamper pins for 8 external tamper detection events:
– Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks
– Flexible active tamper I/O management: from 4 meshes (each input associated to
its own exclusive output) to 7 meshes (single output shared for up to 7 tamper
inputs)
– Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management
– Configurable digital filter
Note: As input, only PC13, PA0, PA1, and PA2 are functional in Standby and VBAT modes. As
output, only PC13, and PA1 are functional in Standby and VBAT modes.
• Internal tamper events to protect against transient or environmental perturbation
attacks

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• Each tamper can be configured in two modes:

– Hardware mode: immediate erase of secrets on tamper detection, including
backup registers erase
– Software mode: erase of secrets following a tamper detection launched by
software
• Any tamper detection can generate an RTC time stamp event.
• TrustZone support:
– Tamper secure or non-secure configuration.
– Backup registers configuration in 3 configurable-size areas:
- 1 read/write secure area
- 1 write secure/read non-secure area
- 1 read/write non-secure area
• Tamper configuration and backup registers privilege protection
• Monotonic counter

3.35 Inter-integrated circuit interface (I2C)

The device embeds three I2C. Refer to Table 8 for the implemented features.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and Master modes, multimaster capability
– Standard-mode (Sm), with a bit rate up to 100 Kbit/s
– Fast-mode (Fm), with a bit rate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
– 7- and 10-bit addressing modes, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBus) specification rev 1.3 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
commun.ication speed to be independent from the PCLK reprogramming
• Wake-up from Stop capability
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

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Table 8. I2C implementation

I2C features(1) I2C1 I2C2 I2C3

Standard-mode (up to 100 Kbit/s) X X X

Fast-mode (up to 400 Kbit/s) X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X
Programmable analog and digital noise filters X X X
SMBus/PMBus hardware support X X X
Independent clock X X X
Wakeup capability X X X
1. X: supported

3.36 Improved inter-integrated circuit (I3C)

The I3C interface handles communication between the MCU and others, like sensors and
host processor(s), all connected on an I3C bus.
The peripheral implements the required features of the MIPI I3C specification v1.1. It can
control I3C bus-specific sequencing, protocol, arbitration and timing, and can act as
controller (formerly known as master) or as target (formerly known as slave). When acting
as controller the peripheral improves the features of the I2C interface, preserving some
backward compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C
fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that the latter does not
perform clock stretching.
The I3C peripheral can be used with DMA to off-load the CPU.

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Table 9. I3C peripheral controller/target features versus MIPI v1.1

MIPI When When
Feature Comments
v1.1 controller target

I3C SDR message X X X -

Mandatory when controller, and the I3C bus is
Legacy I2C message (Fm/Fm+) X X - mixed with (external) legacy I2C target(s).
Optional in MIPI v1.1 when target.
HDR DDR message X - -
Optional in MIPI v1.1
HDR-TSL/TSP, HDR-BT X - -
Dynamic address assignment X X X -
No (intended) support of I3C peripheral as a
Static address X X -
target on an I2C bus.
Grouped addressing X X - Optional in MIPI v1.1
CCCs X X X Mandatory and some optional CCCs supported.
Error detection and recovery X X X -
In-band interrupt (with MDB) X X X -
Secondary controller X X X -
Hot-join mechanism X X X -
Target reset X X X -
Synchronous timing control X X -
Asynchronous timing control 0 X X -
Asynchronous timing control 1, 2, 3 X - -
Optional in MIPI v1.1
Device to device tunneling X X -
Multi-lane data transfer X X -
Monitoring device early termination X - -

3.37 Universal synchronous/asynchronous receiver transmitter

(USART/UART) and low-power universal asynchronous
receiver transmitter (LPUART)
The devices have four embedded universal synchronous receiver transmitters
(USART1/USART2/USART3/USART6), two universal asynchronous receiver transmitters
(UART4/UART5), and one low-power universal asynchronous receiver transmitter
(LPUART1).

Table 10. USART, UART and LPUART features

USART UART LPUART
Mode/feature(1)
1/2/3/6 4/5 1

Hardware flow control for modem X X X

Continuous communication using DMA X X X

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Table 10. USART, UART and LPUART features (continued)

USART UART LPUART
Mode/feature(1)
1/2/3/6 4/5 1

Multiprocessor communication X X X
Synchronous mode (master/slave) X - -
Smartcard mode X - -
Single-wire half-duplex communication X X X
IrDA SIR ENDEC block X X -
LIN mode X X -
Dual-clock domain and wake-up from Stop mode X(2) X(2) X(2)
Receiver timeout interrupt X X -
Modbus communication X X -
Auto-baud rate detection X X -
Driver enable X X X
USART data length 7, 8, and 9 bits
Tx/Rx FIFO X X X
Tx/Rx FIFO size 8 bytes
1. X = supported.
2. Wake-up supported from Stop mode.

3.37.1 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
The USART offers a flexible means to perform full-duplex data exchange with external
equipments requiring an industry standard NRZ asynchronous serial data format. A very
wide range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.
High-speed data communications up to 20 Mbauds are possible by using the DMA (direct
memory access) for multibuffer configuration.
The USART main features are:
• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or by 8, to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK

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• Auto baud rate detection

• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous Master/Slave mode and clock output/input for synchronous
communications
• SPI slave transmission underrun error flag
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wake-up from stop capability
• LIN master synchronous break send capability and LIN slave break detection capability
– 13-bit break generation and 10/11 bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16 bit duration for Normal mode
• Smartcard mode
– Supports the T=0 and T=1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for Smartcard operation
• Support for Modbus communication
– Timeout feature
– CR/LF character recognition

3.37.2 Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum
power consumption. It also supports half-duplex single-wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher-speed clock can be used to
reach higher baud-rates.
The LPUART interface can be served by the DMA controller.

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The LPUART main features are:

• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
• Higher baud rates can be achieved by using a higher frequency clock source
• Two internal FIFOs to transmit and receive data
Each FIFO can be enabled/disabled by software and come with status flags for FIFOs
states.
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Programmable data word length (7 or 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– Busy and end of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Four error detection flags:
– Overrun error
– Noise detection
– Frame error
– Parity error
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Wake-up from Stop capability

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3.38 Serial peripheral interface (SPI) / inter-integrated sound

interfaces (I2S)
The devices embed four serial peripheral interfaces (SPI) that can be used to communicate
with external devices while using the specific synchronous protocol. The SPI protocol
supports half-duplex, full-duplex and simplex synchronous, serial communication with
external devices.
The interface can be configured as master or slave and can operate in multi-slave or multi-
master configurations. The device configured as master provides communication clock
(SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied
optionally just to setup communication with concrete slave and to assure it handles the data
flow properly. The Motorola data format is used by default, but some other specific modes
are supported as well.
The SPI main features are:
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only
• Multi master or multi slave mode capability
• Dual-clock domain, separated clock for the peripheral kernel that can be independent
of PCLK
• Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode
• Protection of configuration and setting
• Hardware or software management of SS for both master and slave
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO x MOSI swap capability
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• SPI Motorola and TI formats support
• Hardware CRC feature can secure communication at the end of transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode
• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun at slave, mode fault at master
• Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability
• Programmable number of data in transaction
• Configurable FIFO thresholds (data packing)
• Configurable behavior at slave underrun condition (support of cascaded circular
buffers)
• Wake-up from Stop capability
• Optional status pin RDY signalizing the slave device ready to handle the data flow.

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Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in full-duplex communication modes, and can be
configured to operate with configurable resolution as input or output channel.
I2S main features:
• Full duplex communication
• Simplex communication (only transmitter or receiver)
• Master or slave operations
• 8-bit programmable linear prescaler
• Data length may be 16, 24 or 32 bits
• Channel length can be 16 or 32 in master, any value in slave
• Programmable clock polarity
• Error flags signaling for improved reliability: Underrun, Overrun and Frame Error
• Embedded Rx and TxFIFOs
• Supported I2S protocols:
– I2S Philips standard
– MSB-Justified standard (Left-Justified)
– LSB-Justified standard (Right-Justified)
– PCM standard (with short and long frame synchronization)
• Data ordering programmable (LSb or MSb first)
• DMA capability for transmission and reception
• Master clock can be output to drive an external audio component. The ratio is fixed at
256 x FWS (where FWS is the audio sampling frequency)

Table 11. SPI features

SPI1, SPI2, SPI3
SPI feature
(full feature set instances)

Data size Configurable from 4 to 32-bit

CRC computation CRC polynomial length configurable from 5 to 33-bit
Size of FIFOs 16x 8-bit
Number of transfered data Unlimited, expandable
I2S feature Yes

3.39 Secure digital input/output and MultiMediaCards interface

(SDMMC)
The SD/SDIO, embedded MultiMediaCard (e•MMC™) host interface (SDMMC) provides an
interface between the AHB bus and SD memory cards, SDIO cards and e•MMC devices.
The MultiMediaCard system specifications are available through the MultiMediaCard
association website at www.mmca.org, published by the MMCA technical committee.
SD memory card and SD I/O card system specifications are available through the SD card
Association website at www.sdcard.org.
The SDMMC features include the following:

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• Compliance with Embedded MultiMediaCard System Specification Version 5.1

Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit
(HS200 SDMMC_CK speed limited to maximum allowed I/O speed) (HS400 is not
supported).
• Full compatibility with previous versions of MultiMediaCards (backward compatibility).
• Full compliance with SD memory card specifications version 6.0
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Full compliance with SDIO card specification version 4.0
Card support for two different databus modes: 1-bit (default) and 4-bit
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Data transfer up to 208 Mbyte/s for the 8-bit mode
(Depending maximum allowed I/O speed).
• Data and command output enable signals to control external bidirectional drivers
• IDMA linked list support
The MultiMediaCard/SD bus connects cards to the host.
The current version of the SDMMC supports only one SD/SDIO/e•MMC card at any one
time and a stack of e•MMC.

Table 12. SDMMC features

Mode/feature(1) SDMMC1 SDMMC2

Variable delay (SDR104, HS200) X X

SDMMC_CKIN X X
SDMMC_CDIR, SDMMC_D0DIR X -
SDMMC_D123DIR X -
1. X = supported.

3.40 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN module, a shared
message RAM memory and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and
transmits FIFOs.
The FDCAN main features are:
• Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4
• CAN FD with maximum 64 data bytes supported
• CAN error logging
• AUTOSAR and J1939 support
• Improved acceptance filtering

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• 2 receive FIFOs of three payloads each (up to 64 bytes per payload)

• Separate signaling on reception of high priority messages
• Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload)
• Configurable transmit Event FIFO
• Programmable loop-back test mode
• Maskable module interrupts
• Two clock domains: APB bus interface and CAN core kernel clock
• Power-down support

3.41 USB full speed (USB)

USB main features
• USB specification version 2.0 full-speed compliant
• Host and device functions
• 2048 bytes of dedicated SRAM data buffer memory with 32-bit access
• USB clock recovery
• Configurable number of endpoints from 1 to 8
• Cyclic redundancy check (CRC) generation/checking, non-return-to-zero inverted
(NRZI) encoding/decoding and bit-stuffing
• Isochronous transfers support
• Double-buffered bulk/isochronous endpoint support
• USB suspend/resume operations
• Frame-locked clock pulse generation
• USB 2.0 Link power management support
• Battery charging specification revision 1.2 support in device

3.42 USB Type-C / USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Cable and
Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB power delivery
requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB power delivery message transmission and reception
• FRS (fast role swap) support

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The digital controller handles notably:

• USB Type-C level detection with debounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB power delivery payload, generating interrupts (DMA
compatible)
• USB power delivery timing dividers (including a clock pre-scaler)
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB power delivery messages and FRS signaling.

3.43 High-definition multimedia interface (HDMI) - consumer

electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wake up the MCU from Stop mode on data reception.

3.44 Development support

3.44.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.

3.44.2 Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device.
Real-time instruction and data flow activity be recorded and then formatted for display on
the host computer that runs the debugger software. TPA hardware is commercially available
from common development tool vendors.
The ETM operates with third party debugger software tools.

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4 Pinout, pin description and alternate function

4.1 Pinout/ballout schematics

Figure 4. WLCSP39 pinout

A PA14 PA15 PB3 PB4 VCAP VDD

B PA12 PA13 BOOT0 VBAT VSS

PC15- PC14-
C PA11 PB7 PB8 PC13 OSC32_ OSC32_
OUT IN

PH1-
PH0-
D PA8 PA3 PA1 OSC_
OSC_IN
OUT

E PB15 PA5 PA4 PA2 PA0 NRST

F VSS PA6 PA7 VSS VSSA

G VDD VCAP PB1 PB0 VDD VDDA

MSv73002V1

1. The above figure shows the package top view.

Figure 5. LQFP48 pinout

BOOT0
VCAP

PA15
PA14
VDD
VSS

PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37

VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3
PA4
PA5
PA6
PA7

MSv73001V1

1. The above figure shows the package top view.

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Figure 6. UFQFPN48 pinout

BOOT0
VCAP

PA15
PA14
VDD
VSS

PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
UFQFPN48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 Exposed pad 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
VSS

PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3
PA4
PA5
PA6
PA7

MSv68851V4

1. The above figure shows the package top view.

Figure 7. LQFP64 pinout

BOOT0
VCAP

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

VBAT 1 48 VDD
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD

PC4
PC5
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3

PA4
PA5
PA6
PA7

MSv67303V2

1. The above figure shows the package top view.

62/231 DS14539 Rev 1

STM32H533xx Pinout, pin description and alternate function

Figure 8. LQFP100 pinout

BOOT0
VCAP

PC10
PC12
PC11

PA14
PA15
VDD
VSS

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD
PE15
PB10
VCAP
PE12
PE13
PE14
PE8
PE9
PE10
PB1
PB2
PE7
PC4
PC5
PB0
VSS
VDD

PE11
PA4
PA5
PA6
PA7
PA3

MSv67304V3

1. The above figure shows the package top view.

Figure 9. UFBGA100 ballout

1 2 3 4 5 6 7 8 9 10 11 12

A PB9 PB8 BOOT0 PB5 PB3 PD6 PD4 PD3 PD1 PC11 PA15 PC10

B PE0 PE4 PE3 PB6 PB4 PD7 PD5 PD2 PD0 PC12 PA14 PA13

C PE2 PE5 VSS VCAP PB7 VDDIO2 VSS VDDUSB PA12 PA11

D VBAT PE6 VDD VDD PA10 PA9

PC14- PC15-
E PC13 PA8 PC9 PC8
OSC32_IN OSC32_OUT

PH1-
F PH0-OSC_IN PC7 PC6
OSC_OUT

UFBGA100
G PC0 NRST PD14 PD15

H PC2 PC3 PC1 PD11 PD12 PD13

J VREF+ VSSA VDD VDD PD9 PD10

K VDDA PA1 VSS PA2 PB1 PE12 VCAP VSS PB14 PD8

L PA3 PA4 PA0 PA7 PB2 VDD VSS PE10 PE13 PE15 PB12 PB15

M PA6 PA5 PC4 PC5 PB0 PE7 PE8 PE9 PE11 PE14 PB10 PB13

MSv72399V1

1. The above figure shows the package top view.

DS14539 Rev 1 63/231

66
Pinout, pin description and alternate function STM32H533xx

Figure 10. LQFP144 pinout

VDDIO2
BOOT0
VCAP

PG15

PG14
PG13
PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
VDD

VDD
VSS

VSS

PG9

VSS
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS

PG0
PG1
VDD

PC4
PC5
PB0
PB1
PB2

PF12
VSS
VDD
PF13
PF14
PF15

PE7
PE8
PE9
VSS

VSS
VDD
PE10

PE12
PE13
PE14
PE15
PB10
VCAP

VDD
PA3

PA4
PA5
PA6
PA7

PF11

PE11

MSv67305V3

1. The above figure shows the package top view.

64/231 DS14539 Rev 1

STM32H533xx Pinout, pin description and alternate function

Figure 11. UFBGA144 ballout

1 2 3 4 5 6 7 8 9 10 11 12

A VSS PB9 PB7 PB4 PG15 PG12 PG11 PD7 PD4 PD2 PC10 VSS

B PE2 PE0 PB8 PB6 PB3 PG14 PG10 PD6 PD3 PC12 PA14 PA10

C VBAT PE4 PE3 BOOT0 VDDIO2 VSS VDDIO2 PD5 PD1 VDDUSB PA12 PA11

PC15- PC14-
D PE5 VSS VCAP PG13 PG9 PD0 PC11 VSS PA9 PA8
OSC32_OUT OSC32_IN

E PF1 PF0 PC13 PE6 VDD PB5 VDD PA15 PA13 PC9 PC8 PC7

F PF5 PF4 PF3 PF2 VSS VDD VSS VDD PC6 PG8 PG7 PG6

G PF6 PF7 PF9 PF8 VDD VSS VDD PD11 PD15 PG3 PG4 PG5

PH1-
H PH0-OSC_IN PF10 VREF- VSS VDD VSS PB14 PB15 PD12 PD14 PG2
OSC_OUT

J NRST PC0 VREF+ VDDA PA7 PB1 PG1 VCAP VSS PD8 PD9 PD13

K PC2 PC1 VSSA PA2 PC4 PB2 PF15 PE9 PE12 PE15 PB13 PD10

L PC3 PA0 PA1 PA5 PC5 PF11 PF14 PE7 PE10 PE14 PB10 PB12

M VSS PA3 PA4 PA6 PB0 PF12 PF13 PG0 PE8 PE11 PE13 M12

MSv73000V1

1. The above figure shows the package top view.

DS14539 Rev 1 65/231

66
Pinout, pin description and alternate function STM32H533xx

4.2 Pin description

Table 13. Legend/abbreviations used in the pinout table
Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/output pin
FT 5V-tolerant I/O
TT 3.6V-tolerant I/O
Bidirectional reset pin with embedded weak pull-up
RST
resistor
Option for TT or FT I/Os(1)
_a I/O, with analog switch function supplied by VDDA

I/O structure _c I/O with USB Type-C power delivery function

_d I/O with USB Type-C power delivery dead battery function
_f I/O, Fm+ capable
_h I/O with high-speed low-voltage mode
_s I/O supplied only by VDDIO2
_t I/O with tamper function functional in VBAT mode
_u I/O, with USB function supplied by VDDUSB
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.

66/231 DS14539 Rev 1

 STM32H533xx
Table 14. STM32H533xx pin/ball definition

Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
TRACECLK, LPTIM1_IN2, SPI4_SCK,
- - - - 1 C1 1 B1 PE2 I/O FT_h - OCTOSPI1_IO2, FMC_A23, -
DCMI_D3/PSSI_D3, EVENTOUT

TRACED0, TIM15_BKIN, FMC_A19,

- - - - 2 B3 2 C3 PE3 I/O FT_h - TAMP_IN6/TAMP_OUT3
EVENTOUT

TRACED1, TIM15_CH1N, SPI4_NSS,

- - - - 3 B2 3 C2 PE4 I/O FT_h - FMC_A20, DCMI_D4/PSSI_D4, TAMP_IN7/TAMP_OUT8
DS14539 Rev 1

EVENTOUT

TRACED2, TIM15_CH1, SPI4_MISO,

- - - - 4 C2 4 D3 PE5 I/O FT_h - FMC_A21, DCMI_D6/PSSI_D6, TAMP_IN8/TAMP_OUT7
EVENTOUT

TRACED3, TIM1_BKIN2, TIM15_CH2,

- - - - 5 D2 5 E4 PE6 I/O FT_h - SPI4_MOSI, FMC_A22, TAMP_IN3/TAMP_OUT6
DCMI_D7/PSSI_D7, EVENTOUT
- - - - - D3 - E5 VDD S - - - -

- - - - - C3 - A1 VSS S - - - -

B8 1 1 1 6 D1 6 C1 VBAT S - - - -

- - - - - C9 - A12 VSS S - - - -

TAMP_IN1/TAMP_OUT2/TAMP_
(4)
C7 2 2 2 7 E3 7 E3 PC13 I/O FT_t EVENTOUT OUT3, RTC_OUT1/RTC_TS,
WKUP4

- - - - - K3 - C6 VSS S - - - -

PC14-
C11 3 3 3 8 E1 8 D2 OSC32_IN I/O FT - EVENTOUT OSC32_IN
(OSC32_IN)
67/231
 Table 14. STM32H533xx pin/ball definition (continued)
68/231

Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
PC15-
OSC32_OUT
C9 4 4 4 9 E2 9 D1 I/O FT - EVENTOUT OSC32_OUT
(OSC32_
OUT)

I3C2_SDA, I2C2_SDA, FMC_A0,

- - - - - - 10 E2 PF0 I/O FT_f - -
EVENTOUT
I3C2_SCL, I2C2_SCL, FMC_A1,
- - - - - - 11 E1 PF1 I/O FT_f - -
EVENTOUT
DS14539 Rev 1

- - - - - - 12 F4 PF2 I/O FT_h - I2C2_SMBA, FMC_A2, EVENTOUT -

- - - - - - 13 F3 PF3 I/O FT_h - FMC_A3, EVENTOUT -

- - - - - - 14 F2 PF4 I/O FT_h - FMC_A4, EVENTOUT -

- - - - - - 15 F1 PF5 I/O FT_h - I3C1_SCL, FMC_A5, EVENTOUT -

- - - - 10 K10 16 D4 VSS S - - - -

- - - - 11 D10 17 E7 VDD S - - - -

- - - - - - 18 G1 PF6 I/O FT_h - OCTOSPI1_IO3, EVENTOUT -

- - - - - - 19 G2 PF7 I/O FT_h - OCTOSPI1_IO2, EVENTOUT -

- - - - - - 20 G4 PF8 I/O FT_h - OCTOSPI1_IO0, EVENTOUT -

- - - - - - 21 G3 PF9 I/O FT_h - OCTOSPI1_IO1, EVENTOUT -

PSSI_D15, OCTOSPI1_CLK,
- - - - - - 22 H3 PF10 I/O FT_h - -
DCMI_D11/PSSI_D11, EVENTOUT

STM32H533xx
PH0-OSC_IN
D10 5 5 5 12 F1 23 H1 I/O FT - EVENTOUT OSC_IN
(PH0)

PH1-
D8 6 6 6 13 F2 24 H2 OSC_OUT I/O FT - EVENTOUT OSC_OUT
(PH1)
 Table 14. STM32H533xx pin/ball definition (continued)

STM32H533xx
Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
E11 7 7 7 14 G2 25 J1 NRST I/O RST - - -

SPI4_MISO, SPI2_RDY, FMC_A25,

- - - 8 15 G1 26 J2 PC0 I/O FT_a - ADC12_INP10
OCTOSPI1_IO7, EVENTOUT

TRACED0, SPI2_MOSI/I2S2_SDO, ADC12_INP11, ADC12_INN10,

- - - 9 16 H3 27 K2 PC1 I/O FT_ah - SPI4_MOSI, OCTOSPI1_IO4, TAMP_IN3/TAMP_OUT5,
EVENTOUT WKUP6

PWR_CSLEEP, TIM4_CH4,
DS14539 Rev 1

- - - 10 17 H1 28 K1 PC2 I/O FT_a - SPI2_MISO/I2S2_SDI, OCTOSPI1_IO5, ADC12_INP12, ADC12_INN11

OCTOSPI1_IO2, EVENTOUT

PWR_CSTOP, LPUART1_TX,
- - - 11 18 H2 29 L1 PC3 I/O FT_a - SPI2_MOSI/I2S2_SDO, OCTOSPI1_IO6, ADC12_INP13, ADC12_INN12
OCTOSPI1_IO0, EVENTOUT

- - - - - J3 30 F6 VDD S - - - -
- - - - - L7 - D10 VSS S - - - -

F10 8 8 12 19 J2 31 K3 VSSA S - - - -

- - - - 20 - - H4 VREF- S - - - -
- - - - 21 J1 32 J3 VREF+ S - - - -

G11 9 9 13 22 K1 33 J4 VDDA S - - - -

TIM2_CH1, TIM5_CH1, TIM8_ETR,

TIM15_BKIN, SPI4_SCK, SPI3_RDY, ADC12_INP0, ADC12_INN1,
E9 10 10 14 23 L3 34 L2 PA0 I/O FT_at (4) USART2_CTS/USART2_NSS, TAMP_IN2/TAMP_OUT1,
UART4_TX, FDCAN2_RX, TIM2_ETR, WKUP1
EVENTOUT
69/231
 Table 14. STM32H533xx pin/ball definition (continued)
70/231

Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
TIM2_CH2, TIM5_CH2, TIM15_CH1N,
LPTIM1_IN1, OCTOSPI1_DQS,
(4) ADC12_INP1,
D6 11 11 15 24 K2 35 L3 PA1 I/O FT_aht USART2_RTS, UART4_RX,
TAMP_IN5/TAMP_OUT4
OCTOSPI1_IO3, USART6_CK,
EVENTOUT

TIM2_CH3, TIM5_CH3, LPUART1_TX, ADC12_INP14,

E7 12 12 16 25 K4 36 K4 PA2 I/O FT_at (4) TIM15_CH1, LPTIM1_IN2, USART2_TX, TAMP_IN4/TAMP_OUT3,
EVENTOUT WKUP2
DS14539 Rev 1

TIM2_CH4, TIM5_CH4,
OCTOSPI1_CLK, TIM15_CH2,
D4 13 13 17 26 L1 37 M2 PA3 I/O FT_ah - SPI2_NSS/I2S2_WS, ADC12_INP15
SPI3_MOSI/I2S3_SDO, USART2_RX,
EVENTOUT
B10 - - 18 27 - 38 F5 VSS S - - - -

A11 - - 19 28 J10 39 F8 VDD S - - - -

TIM5_ETR, LPTIM2_CH1,
SPI3_MOSI/I2S3_SDO,
E5 14 14 20 29 L2 40 M3 PA4 I/O TT_a - SPI1_NSS/I2S1_WS, ADC12_INP18, DAC1_OUT1
SPI3_NSS/I2S3_WS, USART2_CK,
DCMI_HSYNC/PSSI_DE, EVENTOUT

TIM2_CH1, TIM8_CH1N,
ADC12_INP19, ADC12_INN18,
E3 15 15 21 30 M2 41 L4 PA5 I/O TT_ah - SPI1_SCK/I2S1_CK, PSSI_D14,
DAC1_OUT2
TIM2_ETR, EVENTOUT

TIM1_BKIN, TIM3_CH1, TIM8_BKIN,

STM32H533xx
SPI1_MISO/I2S1_SDI, OCTOSPI1_IO3,
F4 16 16 22 31 M1 42 M4 PA6 I/O FT_ah - ADC12_INP3
DCMI_PIXCLK/PSSI_PDCK,
EVENTOUT
 Table 14. STM32H533xx pin/ball definition (continued)

STM32H533xx
Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
TIM1_CH1N, TIM3_CH2, TIM8_CH1N,
F6 17 17 23 32 L4 43 J5 PA7 I/O FT_ah - SPI1_MOSI/I2S1_SDO, OCTOSPI1_IO2, ADC12_INP7, ADC12_INN3
FMC_NWE, EVENTOUT

TIM2_CH4, LPTIM2_ETR, I2S1_MCK,

- - - 24 33 M3 44 K5 PC4 I/O FT_a - ADC12_INP4
USART3_RX, EVENTOUT

TIM1_CH4N, PSSI_D15, SPI4_SCK,

- - - 25 34 M4 45 L5 PC5 I/O FT_ah - ADC12_INP8, ADC12_INN4
OCTOSPI1_DQS, EVENTOUT
DS14539 Rev 1

- - - - - L6 - G5 VDD S - - - -

- - - - - - - F7 VSS S - - - -

TIM1_CH2N, TIM3_CH3, TIM8_CH2N,

G7 18 18 26 35 M5 46 M5 PB0 I/O FT_ah - SPI3_MISO/I2S3_SDI, OCTOSPI1_IO1, ADC12_INP9, ADC12_INN5
USART2_TX, UART4_CTS, EVENTOUT

TIM1_CH3N, TIM3_CH4, TIM8_CH3N,

SPI3_SCK, SPI2_NSS/I2S2_WS,
G5 19 19 27 36 K5 47 J6 PB1 I/O FT_ah - ADC12_INP5
OCTOSPI1_IO0, USART3_RX,
EVENTOUT

RTC_OUT2, TIM8_CH4N, SPI1_RDY,

LPTIM1_CH1, SPI2_SCK/I2S2_CK,
- 20 20 28 37 L5 48 K6 PB2 I/O FT_ah - SPI3_MOSI/I2S3_SDO, LSCO
OCTOSPI1_CLK, OCTOSPI1_DQS,
SDMMC1_CMD, EVENTOUT

OCTOSPI1_NCLK,
- - - - - - 49 L6 PF11 I/O FT_ah - ADC1_INP2
DCMI_D12/PSSI_D12, EVENTOUT

- - - - - - 50 M6 PF12 I/O FT_ah - FMC_A6, EVENTOUT ADC1_INP6, ADC1_INN2

- - - - - - 51 G6 VSS S - - - -

- - - - - - 52 G7 VDD S - - - -
71/231

- - - - - - 53 M7 PF13 I/O FT_ah - FMC_A7, EVENTOUT ADC2_INP2

 Table 14. STM32H533xx pin/ball definition (continued)
72/231

Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
- - - - - - 54 L7 PF14 I/O FT_fah - FMC_A8, EVENTOUT ADC2_INP6, ADC2_INN2

- - - - - - 55 K7 PF15 I/O FT_fh - I3C1_SDA, FMC_A9, EVENTOUT -

- - - - - - 56 M8 PG0 I/O FT_h - FMC_A10, EVENTOUT -

- - - - - - - H5 VSS S - - - -

- - - - - - - H6 VDD S - - - -

SPI2_MOSI/I2S2_SDO, FMC_A11,
- - - - - - 57 J7 PG1 I/O FT_h - -
DS14539 Rev 1

EVENTOUT

TIM1_ETR, OCTOSPI1_IO4,
- - - - 38 M6 58 L8 PE7 I/O FT_ah - -
FMC_D4/FMC_AD4, EVENTOUT

TIM1_CH1N, OCTOSPI1_IO5,
- - - - 39 M7 59 M9 PE8 I/O FT_ah - -
FMC_D5/FMC_AD5, EVENTOUT

TIM1_CH1, OCTOSPI1_IO6,
- - - - 40 M8 60 K8 PE9 I/O FT_ah - -
FMC_D6/FMC_AD6, EVENTOUT
- - - - - - 61 H7 VSS S - - - -

- - - - - - 62 - VDD S - - - -

TIM1_CH2N, OCTOSPI1_IO7,
- - - - 41 L8 63 L9 PE10 I/O FT_ah - -
FMC_D7/FMC_AD7, EVENTOUT

TIM1_CH2, SPI1_RDY, SPI4_NSS,

- - - - 42 M9 64 M10 PE11 I/O FT_ah - OCTOSPI1_NCS, FMC_D8/FMC_AD8, -
EVENTOUT

TIM1_CH3N, SPI4_SCK,

STM32H533xx
- - - - 43 K8 65 K9 PE12 I/O FT_h - -
FMC_D9/FMC_AD9, EVENTOUT

TIM1_CH3, SPI4_MISO,
- - - - 44 L9 66 M11 PE13 I/O FT_h - -
FMC_D10/FMC_AD10, EVENTOUT
 Table 14. STM32H533xx pin/ball definition (continued)

STM32H533xx
Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
TIM1_CH4, SPI4_MOSI,
- - - - 45 M10 67 L10 PE14 I/O FT_h - -
FMC_D11/FMC_AD11, EVENTOUT

TIM1_BKIN, TIM1_CH4N,
- - - - 46 L10 68 K10 PE15 I/O FT_h - -
FMC_D12/FMC_AD12, EVENTOUT

TIM2_CH3, TIM8_CH1, LPTIM2_IN1,

I2C2_SCL, SPI2_SCK/I2S2_CK,
- 21 21 29 47 M11 69 L11 PB10 I/O FT_f - -
USART3_TX, OCTOSPI1_NCS,
EVENTOUT
DS14539 Rev 1

G3 22 22 30 48 K9 70 J8 VCAP S - - - -

F8 23 23 31 49 - 71 J9 VSS S - - - -

G9 24 24 32 50 - 72 - VDD S - - - -

TIM1_BKIN, TIM8_CH3,
OCTOSPI1_NCLK, I2C2_SDA,
- 25 25 33 51 L11 73 L12 PB12 I/O FT_h - SPI2_NSS/I2S2_WS, UCPD1_FRSTX, -
USART3_CK, FDCAN2_RX, UART5_RX,
EVENTOUT
TIM1_CH1N, TIM8_CH2, LPTIM2_CH1,
I2C2_SMBA, SPI2_SCK/I2S2_CK,
- 26 26 34 52 M12 74 K11 PB13 I/O FT_c - USART3_CTS/USART3_NSS, UCPD1_CC1
LPUART1_RX, FDCAN2_TX,
SDMMC1_D0, UART5_TX, EVENTOUT

TIM1_CH2N, TIM12_CH1, TIM8_CH2N,

USART1_TX, SPI2_MISO/I2S2_SDI,
- 27 27 35 53 K11 75 H8 PB14 I/O FT_c - UCPD1_CC2
USART3_RTS, UART4_RTS,
EVENTOUT
73/231
 Table 14. STM32H533xx pin/ball definition (continued)
74/231

Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
RTC_REFIN, TIM1_CH3N, TIM12_CH2,
TIM8_CH3N, USART1_RX,
SPI2_MOSI/I2S2_SDO,
E1 28 28 36 54 L12 76 H9 PB15 I/O FT_h - PVD_IN
SPI1_MOSI/I2S1_SDO, UART4_CTS,
OCTOSPI1_CLK, DCMI_D2/PSSI_D2,
UART5_RX, EVENTOUT

USART3_TX, FMC_D13/FMC_AD13,
- - - - 55 K12 77 J10 PD8 I/O FT_h - -
EVENTOUT
DS14539 Rev 1

USART3_RX, FDCAN2_RX,
- - - - 56 J11 78 J11 PD9 I/O FT_h - -
FMC_D14/FMC_AD14, EVENTOUT
LPTIM2_CH2, USART3_CK,
- - - - 57 J12 79 K12 PD10 I/O FT_h - -
FMC_D15/FMC_AD15, EVENTOUT

LPTIM2_IN2,
USART3_CTS/USART3_NSS,
- - - - 58 H10 80 G8 PD11 I/O FT_h - -
UART4_RX, OCTOSPI1_IO0,
FMC_A16/FMC_CLE, EVENTOUT
LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1,
I3C1_SCL, USART3_RTS, UART4_TX,
- - - - 59 H11 81 H10 PD12 I/O FT_fh - -
OCTOSPI1_IO1, FMC_A17/FMC_ALE,
DCMI_D12/PSSI_D12, EVENTOUT

LPTIM1_CH1, TIM4_CH2, LPTIM2_CH1,

- - - - 60 H12 82 J12 PD13 I/O FT_fh - I3C1_SDA, OCTOSPI1_IO3, FMC_A18, -
DCMI_D13/PSSI_D13, EVENTOUT

- - - - - - 83 M1 VSS S - - - -

STM32H533xx
- - - - - - 84 - VDD S - - - -

TIM4_CH3, FMC_D0/FMC_AD0,
- - - - 61 G11 85 H11 PD14 I/O FT_h - -
EVENTOUT
 Table 14. STM32H533xx pin/ball definition (continued)

STM32H533xx
Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
TIM4_CH4, FMC_D1/FMC_AD1,
- - - - 62 G12 86 G9 PD15 I/O FT_h - -
EVENTOUT

- - - - - - 87 H12 PG2 I/O FT_h - TIM8_BKIN, FMC_A12, EVENTOUT -

- - - - - - 88 G10 PG3 I/O FT_h - TIM8_BKIN2, FMC_A13, EVENTOUT -

- - - - - - 89 G11 PG4 I/O FT_h - TIM1_BKIN2, FMC_A14, EVENTOUT -

- - - - - - 90 G12 PG5 I/O FT_h - TIM1_ETR, FMC_A15, EVENTOUT -

DS14539 Rev 1

I3C1_SDA, SPI1_RDY, OCTOSPI1_NCS,

- - - - - - 91 F12 PG6 I/O FT_h - UCPD1_FRSTX, FMC_NE3, -
DCMI_D12/PSSI_D12, EVENTOUT

I3C1_SCL, USART6_CK,
- - - - - - 92 F11 PG7 I/O FT_h - UCPD1_FRSTX, FMC_INT, -
DCMI_D13/PSSI_D13, EVENTOUT

TIM8_ETR, SPI3_MOSI/I2S3_SDO,
- - - - - - 93 F10 PG8 I/O FT_h - -
USART6_RTS, EVENTOUT

- - - - - - 94 - VSS S - - - -

- - - - - - 95 - VDD S - - - -

TIM3_CH1, TIM8_CH1, I2S2_MCK,

USART6_TX, SDMMC1_D0DIR,
- - - 37 63 F12 96 F9 PC6 I/O FT_h - FMC_NWAIT, I3C2_SCL, -
OCTOSPI1_IO5, SDMMC1_D6,
DCMI_D0/PSSI_D0, EVENTOUT

TRGIO, TIM3_CH2, TIM8_CH2,

I2S3_MCK, USART6_RX,
SDMMC1_D123DIR, FMC_NE1,
- - - 38 64 F11 97 E12 PC7 I/O FT_h - -
I3C2_SDA, OCTOSPI1_IO6,
SDMMC1_D7, DCMI_D1/PSSI_D1,
75/231

EVENTOUT
 Table 14. STM32H533xx pin/ball definition (continued)
76/231

Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
TRACED1, TIM3_CH3, TIM8_CH3,
USART6_CK, UART5_RTS,
- - - 39 65 E12 98 E11 PC8 I/O FT_h - FMC_NE2/FMC_NCE, FMC_INT, -
FMC_ALE, SDMMC1_D0,
DCMI_D2/PSSI_D2, EVENTOUT

MCO2, TIM3_CH4, TIM8_CH4,

I2C3_SDA, AUDIOCLK, UART5_CTS,
- - - 40 66 E11 99 E10 PC9 I/O FT_fh - OCTOSPI1_IO0, FMC_CLE, UCPD1_DB2
DS14539 Rev 1

SDMMC1_D1, DCMI_D3/PSSI_D3,
EVENTOUT

MCO1, TIM1_CH1, TIM8_BKIN2,

I2C3_SCL, SPI1_RDY, SPI4_MOSI,
D2 29 29 41 67 E10 100 D12 PA8 I/O FT_fh - USART1_CK, I3C2_SCL, USB_SOF, -
FMC_NOE, DCMI_D3/PSSI_D3,
EVENTOUT

TIM1_CH2, LPUART1_TX, I2C3_SMBA,

SPI2_SCK/I2S2_CK, USART1_TX,
- 30 30 42 68 D12 101 D11 PA9 I/O FT_h - UCPD1_DB1
FMC_NWE, DCMI_D0/PSSI_D0,
EVENTOUT

TIM1_CH3, LPUART1_RX, LPTIM2_IN2,

UCPD1_FRSTX, USART1_RX,
- 31 31 43 69 D11 102 B12 PA10 I/O FT_h - -
FDCAN2_TX, SDMMC1_D0,
DCMI_D1/PSSI_D1, EVENTOUT

TIM1_CH4, LPUART1_CTS,
SPI2_NSS/I2S2_WS, UART4_RX,
C1 32 32 44 70 C12 103 C12 PA11 I/O FT_u - -
USART1_CTS/USART1_NSS,

STM32H533xx
FDCAN1_RX, USB_DM, EVENTOUT
 Table 14. STM32H533xx pin/ball definition (continued)

STM32H533xx
Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
TIM1_ETR, LPUART1_RTS,
SPI2_SCK/I2S2_CK, UART4_TX,
B2 33 33 45 71 C11 104 C11 PA12 I/O FT_u - -
USART1_RTS, FDCAN1_TX, USB_DP,
EVENTOUT

PA13(JTMS/ (5)
B4 34 34 46 72 B12 105 E9 I/O FT JTMS/SWDIO, EVENTOUT -
SWDIO)

- - - - 73 C10 106 C10 VDDUSB S - - - -

DS14539 Rev 1

F2 35 35 47 74 - 107 - VSS S - - - -

G1 36 36 48 75 - 108 - VDD S - - - -

PA14(JTCK/
A1 37 37 49 76 B11 109 B11 I/O FT - JTCK/SWCLK, EVENTOUT -
SWCLK)

JTDI, TIM2_CH1, HDMI_CEC,

SPI1_NSS/I2S1_WS,
PA15 (5) SPI3_NSS/I2S3_WS, USART1_TX,
A3 38 38 50 77 A11 110 E8 I/O FT -
(JTDI) UART4_RTS, OCTOSPI1_NCS,
FMC_NBL1, DCMI_D11/PSSI_D11,
TIM2_ETR, EVENTOUT

I3C2_SCL, SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
- - - 51 78 A12 111 A11 PC10 I/O FT_h - -
OCTOSPI1_IO1, SDMMC1_D2,
DCMI_D8/PSSI_D8, EVENTOUT

I3C2_SDA, SPI3_MISO/I2S3_SDI,
USART3_RX, UART4_RX,
- - - 52 79 A10 112 D9 PC11 I/O FT_h - -
OCTOSPI1_NCS, SDMMC1_D3,
DCMI_D4/PSSI_D4, EVENTOUT
TRACED3, TIM15_CH1, LPTIM2_CH2,
SPI3_MOSI/I2S3_SDO, USART3_CK,
- - - 53 80 B10 113 B10 PC12 I/O FT_h - -
77/231

UART5_TX, SDMMC1_CK,
DCMI_D9/PSSI_D9, EVENTOUT
 Table 14. STM32H533xx pin/ball definition (continued)
78/231

Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
TIM8_CH4N, UART4_RX, FDCAN1_RX,
- - - - 81 B9 114 D8 PD0 I/O FT_h - -
FMC_D2/FMC_AD2, EVENTOUT

UART4_TX, FDCAN1_TX,
- - - - 82 A9 115 C9 PD1 I/O FT_h - -
FMC_D3/FMC_AD3, EVENTOUT

TRACED2, TIM3_ETR, TIM15_BKIN,

- - - 54 83 B8 116 A10 PD2 I/O FT_h - UART5_RX, SDMMC1_CMD, WKUP7
DCMI_D11/PSSI_D11, EVENTOUT
DS14539 Rev 1

SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_NSS,
- - - - 84 A8 117 B9 PD3 I/O FT_h - WKUP8
FMC_CLK, DCMI_D5/PSSI_D5,
EVENTOUT

USART2_RTS, OCTOSPI1_IO4,
- - - - 85 A7 118 A9 PD4 I/O FT_h - -
FMC_NOE, EVENTOUT
TIM1_CH4N, SPI2_RDY, USART2_TX,
- - - - 86 B7 119 C8 PD5 I/O FT_h - FDCAN1_TX, OCTOSPI1_IO5, -
FMC_NWE, EVENTOUT

- - - - - - 120 - VSS S - - - -

- - - - - C8 121 C5 VDDIO2 S - - - -

I3C2_SCL, I2C3_SCL,
SPI3_MOSI/I2S3_SDO, USART2_RX,
- - - - 87 A6 122 B8 PD6 I/O FT_sh - OCTOSPI1_IO6, SDMMC1_CK, -
FMC_NWAIT, DCMI_D10/PSSI_D10,
EVENTOUT

STM32H533xx
I3C2_SDA, I2C3_SDA,
SPI1_MOSI/I2S1_SDO,
- - - - 88 B6 123 A8 PD7 I/O FT_sh - SPI3_MISO/I2S3_SDI, USART2_CK, -
OCTOSPI1_IO7, SDMMC1_CMD,
FMC_NE1/FMC_NCE, EVENTOUT
 Table 14. STM32H533xx pin/ball definition (continued)

STM32H533xx
Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
SPI1_MISO/I2S1_SDI, USART6_RX,
OCTOSPI1_IO6, SDMMC1_D0,
- - - - - - 124 D7 PG9 I/O FT_sh - -
FMC_NE2/FMC_NCE,
DCMI_VSYNC/PSSI_RDY, EVENTOUT

SPI1_NSS/I2S1_WS, SDMMC1_D1,
- - - - - - 125 B7 PG10 I/O FT_sh - FMC_NE3, DCMI_D2/PSSI_D2, -
EVENTOUT

LPTIM1_IN2, SPI1_SCK/I2S1_CK,
DS14539 Rev 1

- - - - - - 126 A7 PG11 I/O FT_sh - SDMMC1_D2, DCMI_D3/PSSI_D3, -

EVENTOUT

LPTIM1_IN1, PSSI_D15, USART6_RTS,

- - - - - - 127 A6 PG12 I/O FT_sh - SDMMC1_D3, FMC_NE4, -
DCMI_D11/PSSI_D11, EVENTOUT

TRACED0, LPTIM1_CH1,
- - - - - - 128 D6 PG13 I/O FT_sh - USART6_CTS/USART6_NSS, -
FMC_A24, EVENTOUT

TRACED1, LPTIM1_ETR, LPTIM1_CH2,

- - - - - - 129 B6 PG14 I/O FT_sh - USART6_TX, OCTOSPI1_IO7, -
FMC_A25, EVENTOUT
- - - - - - 130 - VSS S - - - -

- - - - - - 131 - VDD S - - - -

SPI4_RDY,
- - - - - - 132 A5 PG15 I/O FT_h - USART6_CTS/USART6_NSS, -
DCMI_D13/PSSI_D13, EVENTOUT
79/231
 Table 14. STM32H533xx pin/ball definition (continued)
80/231

Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
JTDO/TRACESWO, TIM2_CH2,
I3C2_SCL, I2C2_SDA,
PB3(JTDO/ SPI1_SCK/I2S1_CK,
A5 39 39 55 89 A5 133 B5 I/O FT_h - -
TRACESWO) SPI3_SCK/I2S3_CK, LPUART1_TX,
FDCAN2_TX, CRS_SYNC, UART5_TX,
EVENTOUT

NJTRST, TIM3_CH1, OCTOSPI1_CLK,

LPTIM1_CH2, SPI1_MISO/I2S1_SDI,
DS14539 Rev 1

PB4 (5) SPI3_MISO/I2S3_SDI,

A7 40 40 56 90 B5 134 A4 I/O FT_h -
(NJTRST) SPI2_NSS/I2S2_WS, I2C3_SDA,
I3C2_SDA, DCMI_D7/PSSI_D7,
EVENTOUT

TIM3_CH2, OCTOSPI1_NCLK,
I2C1_SMBA, SPI1_MOSI/I2S1_SDO,
USART6_TX, SPI3_MOSI/I2S3_SDO,
- 41 41 57 91 A4 135 E6 PB5 I/O FT_h - -
FDCAN2_RX, I3C2_SCL,
DCMI_D10/PSSI_D10, UART5_RX,
EVENTOUT

TIM4_CH1, I3C1_SCL, I2C1_SCL,

HDMI_CEC, USART6_RX, USART1_TX,
- 42 42 58 92 B4 136 B4 PB6 I/O FT_f - LPUART1_TX, FDCAN2_TX, -
OCTOSPI1_NCS, DCMI_D5/PSSI_D5,
UART5_TX, EVENTOUT

TIM4_CH2, I3C1_SDA, I2C1_SDA,

SPI4_MISO,
USART6_CTS/USART6_NSS,
C3 43 43 59 93 C5 137 A3 PB7 I/O FT_fa - WKUP5

STM32H533xx
USART1_RX, LPUART1_RX,
FDCAN1_TX, FMC_NL,
DCMI_VSYNC/PSSI_RDY, EVENTOUT

B6 44 44 60 94 A3 138 C4 BOOT0 I B - - -
 Table 14. STM32H533xx pin/ball definition (continued)

STM32H533xx
Additional functions
Alternate functions
Pin name (function
Pin number(1)

after reset)(2)(3)

I/O structure
Pin type

Notes
UFQFPN48

UFBGA100

UFBGA144
WLCSP39

LQFP100

LQFP144
LQFP48

LQFP64
TIM4_CH3, I3C1_SCL, I2C1_SCL,
SPI4_RDY, SPI3_NSS/I2S3_WS,
C5 45 45 61 95 A2 139 B3 PB8 I/O FT_fsh - SDMMC1_CKIN, UART4_RX, -
FDCAN1_RX, SDMMC1_D4,
DCMI_D6/PSSI_D6, EVENTOUT

TIM4_CH4, I3C1_SDA, I2C1_SDA,

SPI2_NSS/I2S2_WS,
- - - - 96 A1 140 A2 PB9 I/O FT_fsh - SPI3_SCK/I2S3_CK, SDMMC1_CDIR, -
DS14539 Rev 1

UART4_TX, FDCAN1_TX, SDMMC1_D5,

DCMI_D7/PSSI_D7, EVENTOUT

LPTIM1_ETR, TIM4_ETR, LPTIM2_CH2,

LPTIM2_ETR, SPI3_RDY, FDCAN1_RX,
- - - - 97 B1 141 B2 PE0 I/O FT_h - -
FMC_NBL0, DCMI_D2/PSSI_D2,
EVENTOUT

A9 46 46 62 98 C4 142 D5 VCAP S - - - -

- 47 47 63 99 - 143 - VSS S - - - -

- 48 48 64 100 - 144 - VDD S - - - -

- - - - - - - C7 VDDIO2 S - - - -

1. A non-connected I/O in a given package is configured as an output tied to VSS. When VREF+ pad is not available on a package, the internal voltage reference buffer
(VREFBUF) is not available and must be kept disabled.
2. PC13, PC14 and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current, the use of PC13 to PC15 GPIOs in output
mode is limited: The speed must not exceed 2 MHz with a maximum load of 30 pF. These GPIOs must not be used as current sources (for example to drive a LED).
3. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the
system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
4. As a tamper input, only PC13, PA0, PA1, and PA2 are functional in Standby and VBAT mode. As a tamper output, only PC13, and PA1 are functional in Standby and VBAT
mode
5. After reset, these pins are configured as JTAG/SW debug alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated too.
81/231
 4.3 Alternate functions
82/231

Table 15. Alternate function AF0 to AF7(1)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/I2C1/2/3/L
Port I3C1/2/LPTIM2/LP CEC/I3C1/LPTIM1/S OCTOSPI/SPI1/I2S1/SPI2/I SDMMC1/SPI2/I2S
LPTIM1/ TIM3/4/5/ PTIM1/2/SPI1/I2S1/SP
SYS UART1/OCTOSPI/ PI1/I2S1/SPI2/I2S2/S 2S2/SPI3/I2S3/SPI4/UART 2/SPI3/I2S3/USAR
TIM1/2 8/12/15 I3/I2S3/TIM15/USART
TIM1/8 PI3/I2S3/SPI4 4/USART6/USB_PD T1/2/3/6
1

USART2_CTS/USA
PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR TIM15_BKIN SPI4_SCK SPI3_RDY
RT2_NSS

PA1 - TIM2_CH2 TIM5_CH2 - TIM15_CH1N LPTIM1_IN1 OCTOSPI1_DQS USART2_RTS

PA2 - TIM2_CH3 TIM5_CH3 LPUART1_TX TIM15_CH1 LPTIM1_IN2 - USART2_TX

SPI2_NSS/
PA3 - TIM2_CH4 TIM5_CH4 OCTOSPI1_CLK TIM15_CH2 SPI3_MOSI/I2S3_SDO USART2_RX
I2S2_WS
DS14539 Rev 1

SPI3_MOSI/
PA4 - - TIM5_ETR LPTIM2_CH1 SPI1_NSS/I2S1_WS SPI3_NSS/I2S3_WS USART2_CK
I2S3_SDO

SPI1_SCK/
PA5 - TIM2_CH1 - TIM8_CH1N - - -
I2S1_CK

PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO/I2S1_SDI OCTOSPI1_IO3 -

SPI1_MOSI/I2S1_SD
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - - -
Port A

PA8 MCO1 TIM1_CH1 - TIM8_BKIN2 I2C3_SCL SPI1_RDY SPI4_MOSI USART1_CK

SPI2_SCK
PA9 - TIM1_CH2 - LPUART1_TX I2C3_SMBA - USART1_TX
/I2S2_CK

PA10 - TIM1_CH3 - LPUART1_RX LPTIM2_IN2 - UCPD1_FRSTX USART1_RX

SPI2_NSS/ USART1_CTS/
PA11 - TIM1_CH4 - LPUART1_CTS - UART4_RX
I2S2_WS USART1_NSS

SPI2_SCK/
PA12 - TIM1_ETR - LPUART1_RTS - UART4_TX USART1_RTS
I2S2_CK

STM32H533xx
PA13 JTMS/SWDIO - - - - - - -

PA14 JTCK/SWCLK - - - - - - -

SPI1_NSS/
PA15 JTDI TIM2_CH1 - - HDMI_CEC SPI3_NSS/I2S3_WS USART1_TX
I2S1_WS
 Table 15. Alternate function AF0 to AF7(1) (continued)

STM32H533xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/I2C1/2/3/L
Port I3C1/2/LPTIM2/LP CEC/I3C1/LPTIM1/S OCTOSPI/SPI1/I2S1/SPI2/I SDMMC1/SPI2/I2S
LPTIM1/ TIM3/4/5/ PTIM1/2/SPI1/I2S1/SP
SYS UART1/OCTOSPI/ PI1/I2S1/SPI2/I2S2/S 2S2/SPI3/I2S3/SPI4/UART 2/SPI3/I2S3/USAR
TIM1/2 8/12/15 I3/I2S3/TIM15/USART
TIM1/8 PI3/I2S3/SPI4 4/USART6/USB_PD T1/2/3/6
1

SPI3_MISO/
PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - OCTOSPI1_IO1 USART2_TX
I2S3_SDI

PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N SPI3_SCK SPI2_NSS/I2S2_WS OCTOSPI1_IO0 USART3_RX

SPI3_MOSI/I2S3_S
PB2 RTC_OUT2 - - TIM8_CH4N SPI1_RDY LPTIM1_CH1 SPI2_SCK/I2S2_CK
DO

JTDO/ SPI1_SCK/
PB3 TIM2_CH2 - I3C2_SCL I2C2_SDA SPI3_SCK/I2S3_CK -
TRACESWO I2S1_CK

SPI1_MISO/ SPI2_NSS/
PB4 NJTRST - TIM3_CH1 OCTOSPI1_CLK LPTIM1_CH2 SPI3_MISO/I2S3_SDI
I2S1_SDI I2S2_WS
DS14539 Rev 1

SPI1_MOSI/ SPI3_MOSI/
PB5 - - TIM3_CH2 OCTOSPI1_NCLK I2C1_SMBA USART6_TX
I2S1_SDO I2S3_SDO

PB6 - - TIM4_CH1 I3C1_SCL I2C1_SCL HDMI_CEC USART6_RX USART1_TX

Port B

USART6_CTS/USART6_NS
PB7 - - TIM4_CH2 I3C1_SDA I2C1_SDA SPI4_MISO USART1_RX
S

PB8 - - TIM4_CH3 I3C1_SCL I2C1_SCL SPI4_RDY SPI3_NSS/I2S3_WS SDMMC1_CKIN

PB9 - - TIM4_CH4 I3C1_SDA I2C1_SDA SPI2_NSS/I2S2_WS SPI3_SCK/I2S3_CK SDMMC1_CDIR

PB10 - TIM2_CH3 TIM8_CH1 LPTIM2_IN1 I2C2_SCL SPI2_SCK/I2S2_CK - USART3_TX

SPI2_NSS/
PB12 - TIM1_BKIN TIM8_CH3 OCTOSPI1_NCLK I2C2_SDA UCPD1_FRSTX USART3_CK
I2S2_WS

SPI2_SCK/ USART3_CTS/USA
PB13 - TIM1_CH1N TIM8_CH2 LPTIM2_CH1 I2C2_SMBA -
I2S2_CK RT3_NSS

SPI2_MISO/
PB14 - TIM1_CH2N TIM12_CH1 TIM8_CH2N USART1_TX - USART3_RTS
I2S2_SDI

SPI2_MOSI/I2S2_SD
PB15 RTC_REFIN TIM1_CH3N TIM12_CH2 TIM8_CH3N USART1_RX SPI1_MOSI/I2S1_SDO -
O
83/231
 Table 15. Alternate function AF0 to AF7(1) (continued)
84/231 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/I2C1/2/3/L
Port I3C1/2/LPTIM2/LP CEC/I3C1/LPTIM1/S OCTOSPI/SPI1/I2S1/SPI2/I SDMMC1/SPI2/I2S
LPTIM1/ TIM3/4/5/ PTIM1/2/SPI1/I2S1/SP
SYS UART1/OCTOSPI/ PI1/I2S1/SPI2/I2S2/S 2S2/SPI3/I2S3/SPI4/UART 2/SPI3/I2S3/USAR
TIM1/2 8/12/15 I3/I2S3/TIM15/USART
TIM1/8 PI3/I2S3/SPI4 4/USART6/USB_PD T1/2/3/6
1

PC0 - - - - - - SPI4_MISO SPI2_RDY

SPI2_MOSI/I2S2_SD
PC1 TRACED0 - - - - SPI4_MOSI -
O

PWR_CSLEE
PC2 - TIM4_CH4 - - SPI2_MISO/I2S2_SDI OCTOSPI1_IO5 -
P

SPI2_MOSI/I2S2_SD
PC3 PWR_CSTOP - - LPUART1_TX - OCTOSPI1_IO6 -
O

PC4 - TIM2_CH4 - LPTIM2_ETR - I2S1_MCK - USART3_RX

PC5 - TIM1_CH4N - - PSSI_D15 - SPI4_SCK -

DS14539 Rev 1

PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK - USART6_TX

Port C

PC7 TRGIO - TIM3_CH2 TIM8_CH2 - - I2S3_MCK USART6_RX

PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - USART6_CK

PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA AUDIOCLK - -

PC10 - - - I3C2_SCL - - SPI3_SCK/I2S3_CK USART3_TX

PC11 - - - I3C2_SDA - - SPI3_MISO/I2S3_SDI USART3_RX

PC12 TRACED3 - TIM15_CH1 LPTIM2_CH2 - - SPI3_MOSI/I2S3_SDO USART3_CK

PC13 - - - - - - - -

PC14 - - - - - - - -

PC15 - - - - - - - -

STM32H533xx
 Table 15. Alternate function AF0 to AF7(1) (continued)

STM32H533xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/I2C1/2/3/L
Port I3C1/2/LPTIM2/LP CEC/I3C1/LPTIM1/S OCTOSPI/SPI1/I2S1/SPI2/I SDMMC1/SPI2/I2S
LPTIM1/ TIM3/4/5/ PTIM1/2/SPI1/I2S1/SP
SYS UART1/OCTOSPI/ PI1/I2S1/SPI2/I2S2/S 2S2/SPI3/I2S3/SPI4/UART 2/SPI3/I2S3/USAR
TIM1/2 8/12/15 I3/I2S3/TIM15/USART
TIM1/8 PI3/I2S3/SPI4 4/USART6/USB_PD T1/2/3/6
1

PD0 - - - TIM8_CH4N - - - -

PD1 - - - - - - - -

PD2 TRACED2 - TIM3_ETR - TIM15_BKIN - - -

USART2_CTS/USA
PD3 - - - - - SPI2_SCK/I2S2_CK -
RT2_NSS

PD4 - - - - - - - USART2_RTS

PD5 - TIM1_CH4N - - - SPI2_RDY - USART2_TX

SPI3_MOSI/I2S3_SD
PD6 - - - I3C2_SCL I2C3_SCL - USART2_RX
O
DS14539 Rev 1

SPI1_MOSI/I2S1_SD
Port D

PD7 - - - I3C2_SDA I2C3_SDA SPI3_MISO/I2S3_SDI USART2_CK

O

PD8 - - - - - - - USART3_TX

PD9 - - - - - - - USART3_RX

PD10 - - - LPTIM2_CH2 - - - USART3_CK

USART3_CTS/USA
PD11 - - - LPTIM2_IN2 - - -
RT3_NSS

PD12 - LPTIM1_IN1 TIM4_CH1 LPTIM2_IN1 - I3C1_SCL - USART3_RTS

PD13 - LPTIM1_CH1 TIM4_CH2 LPTIM2_CH1 - I3C1_SDA - -

PD14 - - TIM4_CH3 - - - - -

PD15 - - TIM4_CH4 - - - - -
85/231
 Table 15. Alternate function AF0 to AF7(1) (continued)
86/231 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/I2C1/2/3/L
Port I3C1/2/LPTIM2/LP CEC/I3C1/LPTIM1/S OCTOSPI/SPI1/I2S1/SPI2/I SDMMC1/SPI2/I2S
LPTIM1/ TIM3/4/5/ PTIM1/2/SPI1/I2S1/SP
SYS UART1/OCTOSPI/ PI1/I2S1/SPI2/I2S2/S 2S2/SPI3/I2S3/SPI4/UART 2/SPI3/I2S3/USAR
TIM1/2 8/12/15 I3/I2S3/TIM15/USART
TIM1/8 PI3/I2S3/SPI4 4/USART6/USB_PD T1/2/3/6
1

PE0 - LPTIM1_ETR TIM4_ETR LPTIM2_CH2 LPTIM2_ETR - SPI3_RDY -

PE2 TRACECLK LPTIM1_IN2 - - - SPI4_SCK - -

PE3 TRACED0 - - - TIM15_BKIN - - -

PE4 TRACED1 - - - TIM15_CH1N SPI4_NSS - -

PE5 TRACED2 - - - TIM15_CH1 SPI4_MISO - -

PE6 TRACED3 TIM1_BKIN2 - - TIM15_CH2 SPI4_MOSI - -

PE7 - TIM1_ETR - - - - - -
Port E

PE8 - TIM1_CH1N - - - - - -
DS14539 Rev 1

PE9 - TIM1_CH1 - - - - - -

PE10 - TIM1_CH2N - - - - - -

PE11 - TIM1_CH2 - - SPI1_RDY SPI4_NSS OCTOSPI1_NCS -

PE12 - TIM1_CH3N - - - SPI4_SCK - -

PE13 - TIM1_CH3 - - - SPI4_MISO - -

PE14 - TIM1_CH4 - - - SPI4_MOSI - -

PE15 - TIM1_BKIN - TIM1_CH4N - - - -

STM32H533xx
 Table 15. Alternate function AF0 to AF7(1) (continued)

STM32H533xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/I2C1/2/3/L
Port I3C1/2/LPTIM2/LP CEC/I3C1/LPTIM1/S OCTOSPI/SPI1/I2S1/SPI2/I SDMMC1/SPI2/I2S
LPTIM1/ TIM3/4/5/ PTIM1/2/SPI1/I2S1/SP
SYS UART1/OCTOSPI/ PI1/I2S1/SPI2/I2S2/S 2S2/SPI3/I2S3/SPI4/UART 2/SPI3/I2S3/USAR
TIM1/2 8/12/15 I3/I2S3/TIM15/USART
TIM1/8 PI3/I2S3/SPI4 4/USART6/USB_PD T1/2/3/6
1

PF0 - - - I3C2_SDA I2C2_SDA - - -

PF1 - - - I3C2_SCL I2C2_SCL - - -

PF2 - - - - I2C2_SMBA - - -

PF3 - - - - - - - -

PF4 - - - - - - - -

PF5 - - - - - I3C1_SCL - -

PF6 - - - - - - - -

PF7 - - - - - - - -
Port F
DS14539 Rev 1

PF8 - - - - - - - -

PF9 - - - - - - - -

PF10 - - - - PSSI_D15 - - -

PF11 - - - - - - - -

PF12 - - - - - - - -

PF13 - - - - - - - -

PF14 - - - - - - - -

PF15 - - - - - I3C1_SDA - -
87/231
 Table 15. Alternate function AF0 to AF7(1) (continued)
88/231 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

CEC/DCMI/I2C1/2/3/L
Port I3C1/2/LPTIM2/LP CEC/I3C1/LPTIM1/S OCTOSPI/SPI1/I2S1/SPI2/I SDMMC1/SPI2/I2S
LPTIM1/ TIM3/4/5/ PTIM1/2/SPI1/I2S1/SP
SYS UART1/OCTOSPI/ PI1/I2S1/SPI2/I2S2/S 2S2/SPI3/I2S3/SPI4/UART 2/SPI3/I2S3/USAR
TIM1/2 8/12/15 I3/I2S3/TIM15/USART
TIM1/8 PI3/I2S3/SPI4 4/USART6/USB_PD T1/2/3/6
1

PG0 - - - - - - - -

SPI2_MOSI/I2S2_S
PG1 - - - - - - -
DO

PG2 - - - TIM8_BKIN - - - -

PG3 - - - TIM8_BKIN2 - - - -

PG4 - TIM1_BKIN2 - - - - - -

PG5 - TIM1_ETR - - - - - -

PG6 - - - I3C1_SDA - SPI1_RDY - -

DS14539 Rev 1

PG7 - - - I3C1_SCL - - - USART6_CK

Port G

SPI3_MOSI/I2S3_SD
PG8 - - - TIM8_ETR - - USART6_RTS
O

PG9 - - - - - SPI1_MISO/I2S1_SDI - USART6_RX

PG10 - - - - - SPI1_NSS/I2S1_WS - -

PG11 - LPTIM1_IN2 - - - SPI1_SCK/I2S1_CK - -

PG12 - LPTIM1_IN1 - - PSSI_D15 - - USART6_RTS

USART6_CTS/USA
PG13 TRACED0 LPTIM1_CH1 - - - - -
RT6_NSS

PG14 TRACED1 LPTIM1_ETR - - LPTIM1_CH2 - - USART6_TX

USART6_CTS/USA
PG15 - - - - - SPI4_RDY -
RT6_NSS

PH0 - - - - - - - -
Port H

PH1 - - - - - - - -

STM32H533xx
1. Refer to the next table for AF8 to AF15.
 Table 16. Alternate function AF8 to AF15(1)

STM32H533xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/S FDCAN1/2/FMC[NAND16)/ CRS/FMC[NAND1 FMC[NAND16)/ FMC[NAND16)/FMC DCMI/FMC[NAND16

TIM2/UART
DMMC1/UA FMC[NORmux)/FMC[NOR_RAM)/ 6)/I3C2/OCTOSPI/ OCTOSPI/SDM [NORmux)/FMC[NO )/FMC[NORmux)/FM SYS
5/USART6
RT4/5 I2C3/I3C2/OCTOSPI SDMMC1/USB_ MC1/USB_PD R_RAM)/SDMMC1 C[NOR_RAM)

PA0 UART4_TX FDCAN2_RX - - - - TIM2_ETR EVENTOUT

PA1 UART4_RX OCTOSPI1_IO3 - - - - USART6_CK EVENTOUT

PA2 - - - - - - - EVENTOUT

PA3 - - - - - - - EVENTOUT

DCMI_HSYNC/PSSI
PA4 - - - - - - EVENTOUT
_DE

PA5 - - - - - PSSI_D14 TIM2_ETR EVENTOUT

DCMI_PIXCLK/PSSI
PA6 - - - - - - EVENTOUT
_PDCK
DS14539 Rev 1

Port A

PA7 - - OCTOSPI1_IO2 - - FMC_NWE - EVENTOUT

PA8 - I3C2_SCL USB_SOF - FMC_NOE DCMI_D3/PSSI_D3 - EVENTOUT

PA9 - - - - FMC_NWE DCMI_D0/PSSI_D0 - EVENTOUT

PA10 - FDCAN2_TX - - SDMMC1_D0 DCMI_D1/PSSI_D1 - EVENTOUT

PA11 - FDCAN1_RX USB_DM - - - - EVENTOUT

PA12 - FDCAN1_TX USB_DP - - - - EVENTOUT

PA13 - - - - - - - EVENTOUT

PA14 - - - - - - - EVENTOUT

DCMI_D11/PSSI_D1
PA15 UART4_RTS OCTOSPI1_NCS - - FMC_NBL1 TIM2_ETR EVENTOUT
1
89/231
 Table 16. Alternate function AF8 to AF15(1) (continued)
90/231 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/S FDCAN1/2/FMC[NAND16)/ CRS/FMC[NAND1 FMC[NAND16)/ FMC[NAND16)/FMC DCMI/FMC[NAND16

TIM2/UART
DMMC1/UA FMC[NORmux)/FMC[NOR_RAM)/ 6)/I3C2/OCTOSPI/ OCTOSPI/SDM [NORmux)/FMC[NO )/FMC[NORmux)/FM SYS
5/USART6
RT4/5 I2C3/I3C2/OCTOSPI SDMMC1/USB_ MC1/USB_PD R_RAM)/SDMMC1 C[NOR_RAM)

PB0 UART4_CTS - - - - - - EVENTOUT

PB1 - - - - - - - EVENTOUT

PB2 - OCTOSPI1_CLK OCTOSPI1_DQS - SDMMC1_CMD - - EVENTOUT

PB3 LPUART1_TX FDCAN2_TX CRS_SYNC - - - UART5_TX EVENTOUT

PB4 - I2C3_SDA I3C2_SDA - - DCMI_D7/PSSI_D7 - EVENTOUT

PB5 - FDCAN2_RX I3C2_SCL - - DCMI_D10/PSSI_D10 UART5_RX EVENTOUT

PB6 LPUART1_TX FDCAN2_TX OCTOSPI1_NCS - - DCMI_D5/PSSI_D5 UART5_TX EVENTOUT

Port B

DCMI_VSYNC/PSSI_R
PB7 LPUART1_RX FDCAN1_TX - - FMC_NL - EVENTOUT
DY
DS14539 Rev 1

PB8 UART4_RX FDCAN1_RX - - SDMMC1_D4 DCMI_D6/PSSI_D6 - EVENTOUT

PB9 UART4_TX FDCAN1_TX - - SDMMC1_D5 DCMI_D7/PSSI_D7 - EVENTOUT

PB10 - OCTOSPI1_NCS - - - - - EVENTOUT

PB12 - FDCAN2_RX - - - - UART5_RX EVENTOUT

PB13 LPUART1_RX FDCAN2_TX - - SDMMC1_D0 - UART5_TX EVENTOUT

PB14 UART4_RTS - - - - - - EVENTOUT

PB15 UART4_CTS - OCTOSPI1_CLK - - DCMI_D2/PSSI_D2 UART5_RX EVENTOUT

STM32H533xx
 Table 16. Alternate function AF8 to AF15(1) (continued)

STM32H533xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/S FDCAN1/2/FMC[NAND16)/ CRS/FMC[NAND1 FMC[NAND16)/ FMC[NAND16)/FMC DCMI/FMC[NAND16

TIM2/UART
DMMC1/UA FMC[NORmux)/FMC[NOR_RAM)/ 6)/I3C2/OCTOSPI/ OCTOSPI/SDM [NORmux)/FMC[NO )/FMC[NORmux)/FM SYS
5/USART6
RT4/5 I2C3/I3C2/OCTOSPI SDMMC1/USB_ MC1/USB_PD R_RAM)/SDMMC1 C[NOR_RAM)

PC0 - FMC_A25 OCTOSPI1_IO7 - - - - EVENTOUT

PC1 - - OCTOSPI1_IO4 - - - - EVENTOUT

PC2 - OCTOSPI1_IO2 - - - - - EVENTOUT

PC3 - OCTOSPI1_IO0 - - - - - EVENTOUT

PC4 - - - - - - - EVENTOUT

PC5 - - OCTOSPI1_DQS - - - - EVENTOUT

SDMMC1_D0
PC6 FMC_NWAIT I3C2_SCL OCTOSPI1_IO5 SDMMC1_D6 DCMI_D0/PSSI_D0 - EVENTOUT
DIR

SDMMC1_D1
Port C

PC7 FMC_NE1 I3C2_SDA OCTOSPI1_IO6 SDMMC1_D7 DCMI_D1/PSSI_D1 - EVENTOUT

23DIR
DS14539 Rev 1

PC8 UART5_RTS FMC_NE2/FMC_NCE FMC_INT FMC_ALE SDMMC1_D0 DCMI_D2/PSSI_D2 - EVENTOUT

PC9 UART5_CTS OCTOSPI1_IO0 - FMC_CLE SDMMC1_D1 DCMI_D3/PSSI_D3 - EVENTOUT

PC10 UART4_TX OCTOSPI1_IO1 - - SDMMC1_D2 DCMI_D8/PSSI_D8 - EVENTOUT

PC11 UART4_RX OCTOSPI1_NCS - - SDMMC1_D3 DCMI_D4/PSSI_D4 - EVENTOUT

PC12 UART5_TX - - - SDMMC1_CK DCMI_D9/PSSI_D9 - EVENTOUT

PC13 - - - - - - - EVENTOUT

PC14 - - - - - - - EVENTOUT

PC15 - - - - - - - EVENTOUT
91/231
 Table 16. Alternate function AF8 to AF15(1) (continued)
92/231 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/S FDCAN1/2/FMC[NAND16)/ CRS/FMC[NAND1 FMC[NAND16)/ FMC[NAND16)/FMC DCMI/FMC[NAND16

TIM2/UART
DMMC1/UA FMC[NORmux)/FMC[NOR_RAM)/ 6)/I3C2/OCTOSPI/ OCTOSPI/SDM [NORmux)/FMC[NO )/FMC[NORmux)/FM SYS
5/USART6
RT4/5 I2C3/I3C2/OCTOSPI SDMMC1/USB_ MC1/USB_PD R_RAM)/SDMMC1 C[NOR_RAM)

PD0 UART4_RX FDCAN1_RX - - FMC_D2/FMC_AD2 - - EVENTOUT

PD1 UART4_TX FDCAN1_TX - - FMC_D3/FMC_AD3 - - EVENTOUT

PD2 UART5_RX - - - SDMMC1_CMD DCMI_D11/PSSI_D11 - EVENTOUT

PD3 - - - - FMC_CLK DCMI_D5/PSSI_D5 - EVENTOUT

PD4 - - OCTOSPI1_IO4 - FMC_NOE - - EVENTOUT

PD5 - FDCAN1_TX OCTOSPI1_IO5 - FMC_NWE - - EVENTOUT

PD6 - - OCTOSPI1_IO6 SDMMC1_CK FMC_NWAIT DCMI_D10/PSSI_D10 - EVENTOUT

PD7 - - OCTOSPI1_IO7 SDMMC1_CMD FMC_NE1/FMC_NCE - - EVENTOUT

Port D

PD8 - - - - FMC_D13/FMC_AD13 - - EVENTOUT

DS14539 Rev 1

PD9 - FDCAN2_RX - - FMC_D14/FMC_AD14 - - EVENTOUT

PD10 - - - - FMC_D15/FMC_AD15 - - EVENTOUT

PD11 UART4_RX OCTOSPI1_IO0 - - FMC_A16/FMC_CLE - - EVENTOUT

PD12 UART4_TX OCTOSPI1_IO1 - - FMC_A17/FMC_ALE DCMI_D12/PSSI_D12 - EVENTOUT

PD13 - OCTOSPI1_IO3 - - FMC_A18 DCMI_D13/PSSI_D13 - EVENTOUT

PD14 - - - - FMC_D0/FMC_AD0 - - EVENTOUT

PD15 - - - - FMC_D1/FMC_AD1 - - EVENTOUT

STM32H533xx
 Table 16. Alternate function AF8 to AF15(1) (continued)

STM32H533xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/S FDCAN1/2/FMC[NAND16)/ CRS/FMC[NAND1 FMC[NAND16)/ FMC[NAND16)/FMC DCMI/FMC[NAND16

TIM2/UART
DMMC1/UA FMC[NORmux)/FMC[NOR_RAM)/ 6)/I3C2/OCTOSPI/ OCTOSPI/SDM [NORmux)/FMC[NO )/FMC[NORmux)/FM SYS
5/USART6
RT4/5 I2C3/I3C2/OCTOSPI SDMMC1/USB_ MC1/USB_PD R_RAM)/SDMMC1 C[NOR_RAM)

PE0 - FDCAN1_RX - - FMC_NBL0 DCMI_D2/PSSI_D2 - EVENTOUT

PE2 - OCTOSPI1_IO2 - - FMC_A23 DCMI_D3/PSSI_D3 - EVENTOUT

PE3 - - - - FMC_A19 - - EVENTOUT

PE4 - - - - FMC_A20 DCMI_D4/PSSI_D4 - EVENTOUT

PE5 - - - - FMC_A21 DCMI_D6/PSSI_D6 - EVENTOUT

PE6 - - - - FMC_A22 DCMI_D7/PSSI_D7 - EVENTOUT

PE7 - - OCTOSPI1_IO4 - FMC_D4/FMC_AD4 - - EVENTOUT

Port E

PE8 - - OCTOSPI1_IO5 - FMC_D5/FMC_AD5 - - EVENTOUT

PE9 - - OCTOSPI1_IO6 - FMC_D6/FMC_AD6 - - EVENTOUT

DS14539 Rev 1

PE10 - - OCTOSPI1_IO7 - FMC_D7/FMC_AD7 - - EVENTOUT

PE11 - - - - FMC_D8/FMC_AD8 - - EVENTOUT

PE12 - - - - FMC_D9/FMC_AD9 - - EVENTOUT

PE13 - - - - FMC_D10/FMC_AD10 - - EVENTOUT

PE14 - - - - FMC_D11/FMC_AD11 - - EVENTOUT

PE15 - - - - FMC_D12/FMC_AD12 - - EVENTOUT

93/231
 Table 16. Alternate function AF8 to AF15(1) (continued)
94/231 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/S FDCAN1/2/FMC[NAND16)/ CRS/FMC[NAND1 FMC[NAND16)/ FMC[NAND16)/FMC DCMI/FMC[NAND16

TIM2/UART
DMMC1/UA FMC[NORmux)/FMC[NOR_RAM)/ 6)/I3C2/OCTOSPI/ OCTOSPI/SDM [NORmux)/FMC[NO )/FMC[NORmux)/FM SYS
5/USART6
RT4/5 I2C3/I3C2/OCTOSPI SDMMC1/USB_ MC1/USB_PD R_RAM)/SDMMC1 C[NOR_RAM)

PF0 - - - - FMC_A0 - - EVENTOUT

PF1 - - - - FMC_A1 - - EVENTOUT

PF2 - - - - FMC_A2 - - EVENTOUT

PF3 - - - - FMC_A3 - - EVENTOUT

PF4 - - - - FMC_A4 - - EVENTOUT

PF5 - - - - FMC_A5 - - EVENTOUT

PF6 - - OCTOSPI1_IO3 - - - - EVENTOUT

PF7 - - OCTOSPI1_IO2 - - - - EVENTOUT

Port F

PF8 - - OCTOSPI1_IO0 - - - - EVENTOUT

DS14539 Rev 1

PF9 - - OCTOSPI1_IO1 - - - - EVENTOUT

PF10 - OCTOSPI1_CLK - - - DCMI_D11/PSSI_D11 - EVENTOUT

PF11 - OCTOSPI1_NCLK - - - DCMI_D12/PSSI_D12 - EVENTOUT

PF12 - - - - FMC_A6 - - EVENTOUT

PF13 - - - - FMC_A7 - - EVENTOUT

PF14 - - - - FMC_A8 - - EVENTOUT

PF15 - - - - FMC_A9 - - EVENTOUT

STM32H533xx
 Table 16. Alternate function AF8 to AF15(1) (continued)

STM32H533xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/S FDCAN1/2/FMC[NAND16)/ CRS/FMC[NAND1 FMC[NAND16)/ FMC[NAND16)/FMC DCMI/FMC[NAND16

TIM2/UART
DMMC1/UA FMC[NORmux)/FMC[NOR_RAM)/ 6)/I3C2/OCTOSPI/ OCTOSPI/SDM [NORmux)/FMC[NO )/FMC[NORmux)/FM SYS
5/USART6
RT4/5 I2C3/I3C2/OCTOSPI SDMMC1/USB_ MC1/USB_PD R_RAM)/SDMMC1 C[NOR_RAM)

PG0 - - - - FMC_A10 - - EVENTOUT

PG1 - - - - FMC_A11 - - EVENTOUT

PG2 - - - - FMC_A12 - - EVENTOUT

PG3 - - - - FMC_A13 - - EVENTOUT

PG4 - - - - FMC_A14 - - EVENTOUT

PG5 - - - - FMC_A15 - - EVENTOUT

PG6 - - OCTOSPI1_NCS UCPD1_FRSTX FMC_NE3 DCMI_D12/PSSI_D12 - EVENTOUT

PG7 - - - UCPD1_FRSTX FMC_INT DCMI_D13/PSSI_D13 - EVENTOUT

Port G

PG8 - - - - - - - EVENTOUT
DS14539 Rev 1

DCMI_VSYNC/PSSI_R
PG9 - OCTOSPI1_IO6 - SDMMC1_D0 FMC_NE2/FMC_NCE - EVENTOUT
DY

PG10 - - - SDMMC1_D1 FMC_NE3 DCMI_D2/PSSI_D2 - EVENTOUT

PG11 - - SDMMC1_D2 - - DCMI_D3/PSSI_D3 - EVENTOUT

PG12 - - SDMMC1_D3 - FMC_NE4 DCMI_D11/PSSI_D11 - EVENTOUT

PG13 - - - - FMC_A24 - - EVENTOUT

PG14 - OCTOSPI1_IO7 - - FMC_A25 - - EVENTOUT

PG15 - - - - - DCMI_D13/PSSI_D13 - EVENTOUT

PH0 - - - - - - - EVENTOUT
Port H

PH1 - - - - - - - EVENTOUT

1. Refer to the previous table for AF0 to AF7.

95/231
Electrical characteristics STM32H533xx

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes, and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = VDDA = 3.3 V (for
the 1.71 ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 12.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 13.

Figure 12. Pin loading conditions Figure 13. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19210V MS19211V

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5.1.6 Power supply scheme

Figure 14. STM32H523xx/H533xx power supply scheme

STM32H5

VCAP1/2
[ȝ) 100 nF
Core domain
LDO enabled LDO disabled LDO
(bypass mode) Voltage
VDDLDO
regulator
VDDIO2 VDDIO2

ȝ) 100 nF
VDDIO2
IOs

Two different possible use cases VDD

100 nF
VDD
IOs
VDD
VDD
ȝ) 100 nF
VDD
domain
VSS Power switch

Two different possible use cases

Backup
VBAT
domain
ȝ) 100 nF
Battery

BKUP
IOs
VDD
Two different possible use cases

VDDUSB VDDUSB
ȝ) 100 nF
USB FS
IOs

VDDA VDDA
ȝ) 100 nF

Ÿ
VREF+ Analog domain
100 nF
VREF+ VREF-
ȝ) VSSA
ȝ)
Three different possible use cases
Defines different use case options
Internal VREFBUF
enabled
Define power domaines
MSv74500V1

Note: Refer to “Getting started with STM32H5 Series hardware development” (AN5711) for more
details.
Caution: Each power supply pair must be decoupled with filtering ceramic capacitors as shown
above. These capacitors must be placed as close as possible to or below the appropriate

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pins on the underside of the PCB to ensure the good functionality of the device. It is not
recommended to remove filtering capacitors to reduce PCB size or cost. This might cause
incorrect operation of the device.

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 17, Table 18, and Table 19
may cause permanent damage to the device. These are stress ratings only and the
functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability. Device mission profile
(application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended
mission profiles are available on demand.

Table 17. Voltage characteristics(1)

Symbol Ratings Min Max Unit

External main supply voltage (including VDDA,

VDDx - VSS -0.3 4.0 V
VDDUSB, VDDIO2(2)(3)(4), VBAT, and VREF+)

VDDIOx(4) - I/O supply when HSLV(2) = 0 -0.3 4.0

V
VSS I/O supply when HSLV (2)
=1 -0.3 2.75
min (min(VDD, VDDA, VDDUSB,
Input voltage on FT_xxx pins except FT_c pins VSS - 0.3 V
VDDIO2) + 4.0, 6.0 V)(6)(7)
min (min(VBAT, VDDA, VDDUSB,
Input voltage on FT_t in VBAT mode VSS - 0.3
VDDIO2) + 4.0V, 6.0 V)

VIN(5) Input voltage on TT_xx pins VSS - 0.3 4.0

min (min(VDD, VDDA, VDDUSB,
Input voltage on BOOT0 pin VSS V
VDDIO2) + 4.0, 6.0 V)(6)
Input voltage on FT_c pins VSS - 0.3 5.5
Input voltage on any other pins VSS - 0.3 4.0
VREF+-VDDA Allowed voltage difference for VREF+ > VDDA - 0.4
Variations between different VDDX power pins
|∆VDDx| - 50.0
of the same domain mV
|VSSx-VSS| Variations between all the different ground pins - 50.0
1. All main power (VDD, VDDAVDDUSB, VDDIO2, VREF+, VBAT) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481.
3. If HSLV = 0.
4. VDDIO1 or VDDIO2. VDDIO1 = VDD.
5. VIN maximum must always be respected. Refer to the maximum allowed injected current values.
6. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
7. This formula must be applied on power supplies related to the I/O structure described by the pin definition table.

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Table 18. Current characteristics

Symbol Ratings Max Unit

∑IVDD Total current into sum of all VDD power lines (source)(1) 350
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 350
IVDD Maximum current into each VDD power pin (source)(1) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
IIO(PIN) Output current sunk/sourced by any I/O and control pin 20 mA
(2)
Total output current sunk by sum of all I/Os and control pins 140
∑IIO(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 140
IINJ(PIN)(3)(4) Injected current on FT_xxx, TT_xx, NRST pins -5 / 0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDDIO2, and VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os, and does not occur for input voltages
lower than the specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 17 for the
minimum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).

Table 19. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150 °C

TJ Maximum junction temperature 130(1) °C
1. The junction temperature is limited to 105 °C in the VOS0 voltage range.

5.3 Operating conditions

5.3.1 General operating conditions

Table 20. General operating conditions
Symbol Parameter Operating conditions Min Typ Max Unit

Standard operating HSLV(1) = 0 1.71(2) - 3.6

VDD V
voltage HSLV (1)
=1 1.71 (2)
- 2.7
At least one I/O in PB8, PB9, PD6, PD7,
1.08 - 3.6
PG[9:14] is used, HSLV(1) = 0
PB8, PB9, PD6, PD7,
VDDIO2 PG[9:14] I/Os supply At least one I/O in PB8, PB9, PD6, PD7, V
1.08 - 2.7
voltage PG[9:14] is used, HSLV(1) = 1
PB8,PB9, PD6,PD7, PG[9:14] not use 0 3.6

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Table 20. General operating conditions (continued)

Symbol Parameter Operating conditions Min Typ Max Unit

USB is used 3.0 - 3.6

VDDUSB USB supply voltage V
USB is not used 0 - 3.6
ADC is used 1.62 -
DAC is used 1.8 -
VDDA Analog supply voltage 3.6 V
VREFBUF is used 2.1 -
ADC, DAC, and VREFBUF are not used 0 -
Backup domain
VBAT - 1.2 - 3.6 V
supply voltage
min (min
(VDD,
VDDA,
VDDUSB,
All I/Os except FT_c and TT_xx -0.3 -
VDDIO2)
+ 3.6V,
5.5 V)
(3)(4)

min (min
VIN I/O input voltage (VBAT, V
VDDA,
VDDUSB,
Input voltage on FT_t in VBAT mode -0.3 -
VDDIO2)
+ 3.6 V,
5.5 V)
(3)(4)

FT_c I/O -0.3 - 5.0

VDDIOx +
TT_xx I/O -0.3 -
0.3
VOS0(5)
1.30 1.35 1.40
(max frequency for AHB and APB: 250 MHz)
VOS1
1.15 1.20 1.26
(max frequency for AHB and APB: 200 MHz)
Internal regulator ON V
VOS2
1.05 1.10 1.15
(max frequency for AHB and APB: 150 MHz)
VOS3
0.95 1.00 1.05
(max frequency for AHB and APB: 100 MHz)
VCORE
Regulator OFF: VOS0(5) 1.32 1.35 1.40
external VCORE voltage VOS1 1.17 1.20 1.26
must be supplied from V
external regulator on VOS2 1.07 1.10 1.15
VCAP pins VOS3 0.97 1.00 1.05
SVOS3 - 1.0 -
Stop mode SVOS4 - 0.9 - V
SVOS5 - 0.74 -

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Table 20. General operating conditions (continued)

Symbol Parameter Operating conditions Min Typ Max Unit
(5)
VOS0 - - 250
VOS1 - - 200
fHCLK AHB clock frequency MHz
VOS2 - - 150
VOS3 - - 100
VOS0(5) - - 250

fPCLKx APB1, APB2, APB3 VOS1 - - 200

MHz
(x=1,2,3) clock frequency VOS2 - - 150
VOS3 - - 100
WLCSP39
See Table 137 for
LQFP48 appropriate thermal
UFQFPN48 resistance and package.
Power dissipation is
Power dissipation at LQFP64 calculated according to
PD TA = 85 °C mW
LQFP100 ambient temperature
for suffix 6(6)
(TA), maximum junction
LQFP144 temperature (TJ), and
UFBGA100 selected thermal
resistance.
UFBGA144
WLCSP39
See Table 137 for
LQFP48 appropriate thermal
UFQFPN48 resistance and package.
Power dissipation is
Power dissipation at LQFP64 calculated according to
PD TA = 105 °C mW
LQFP100 ambient temperature
for suffix 7(6)
(TA), maximum junction
LQFP144 temperature (TJ), and
UFBGA100 selected thermal
resistance.
UFBGA144

Ambient temperature Maximum power dissipation -40 - 105

for the suffix 7 version Low dissipation or LDO bypass mode -40 - 125
TA °C
Ambient temperature
Maximum power dissipation -40 - 85
for the suffix 6 version

Junction temperature VOS0 -40 - 105

TJ °C
range VOS1, VOS2, and VOS3 -40 - 130
1. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481.
2. When RESET is released functionality is guaranteed down to BOR level 0 minimum voltage.
3. This formula must be applied on power supplies related to the I/O structure described by the pin definition table. Maximum
I/O input voltage is the smallest value between min (VDD, VDDA, VDDIO2) + 3.6 V and 5.5 V.
4. For operation with voltages higher than min (VDD, VDDA, VDDIO2) + 0.3V, the internal pull-up and pull-down resistors must
be disabled.
5. In VOS0 mode the max TJ is 105 °C.

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6. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 19).

Table 21. Maximum allowed clock frequencies

Symbol(1)(2) Parameter VOS0 VOS1 VOS2 VOS3 Unit

fCPU CPU 250 200 150 100

fHCLK AHB 250 200 150 100
fPCLK APB 250 200 150 100
- FMC 250 200 150 100
foctospi_ker_ck OCTOSPI[1:2] 250 200 150 100
fsdmmc_ker_ck SDMMC[1:2] 250 200 150 100
- HDMI_CEC 4 4 4 4
ffdcan_ker_ck FDCAN 250 200 150 100
fI2C_ker_ck I2C[1:4] 250 200 150 100
fI3C_ker_ck I3C 250 200 150 100
flptim_ker_ck LPTIM[1:2] 250 200 150 100
ftim_ker_ck TIM[1:8], TIM12, TIM15 250 200 150 100
frng_clk RNG 50 50 50 50
SPI(I2S)1,2,3 125 100 75 50 MHz
fspi_ker_ck
SPI4 125 100 75 50
flpuart_ker_ck LPUART1 250 200 150 100
fusart_ker_ck USART/UART 250 200 150 100
fusb_ker_ck USB FS 50 50 50 50
fadc_ker_ck ADC/DAC 125 100 75 50
fdac_pclk DAC 250 200 150 100
fusb_ker_ck USBPD 64 64 64 64
frtc_ker_ck RTC 1 1 1 1
- DCMI 250 200 150 100
1. Specified by design - Not tested in production.
2. The maximum kernel clock frequencies can be limited by the maximum peripheral clock frequency
(refer to each peripheral electrical characteristics).

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5.3.2 VCAP external capacitor

Stabilization for the embedded LDO regulator is achieved by connecting an external
capacitor CEXT to the VCAPx (one or two pins, depending upon the package). CEXT is
specified in Table 22. VCAP operating conditions. Two external capacitors must be
connected to VCAP pins (refer to AN5711 “STM32H5 Series hardware development”).

Figure 15. External capacitor CEXT

C

ESR

R Leak
MS19044V2

Table 22. Supply voltage and maximum frequency configuration

Symbol Parameter Conditions

CEXT External capacitor for LDO enabled 2.2 μF(1)

ESR Equivalent series resistance of the external capacitor < 100 mΩ
1. This value corresponds to CEXT typical value. A variation of ±20% is tolerated

5.3.3 Operating conditions at power-up/down

Subject to general operating conditions for TA.
v

Table 23. Operating conditions at power-up/down (regulator ON)

Symbol Parameter Min Max Unit

VDD rise time rate 0 ∞

TVDD
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
TVDDA
VDDA fall time rate 10 ∞
TVDDUSB rise time rate 0 ∞
TVDDUSB μs/V
TVDDUSB fall time rate 10 ∞
TVDDIO2 rise time rate 0 ∞
TVDDIO2
TVDDIO2 fall time rate 10 ∞
TVBAT rise time rate 0 ∞
TVBAT
TVBAT fall time rate 10 ∞

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5.3.4 Embedded reset and power control block characteristics

The parameters given in Table 24 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 20.

Table 24. Embedded reset and power control block characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

tRSTTEMPO(2) Reset temporization after BOR0 detection VDD rising - 377 550 μs

Power-on/down reset threshold Rising edge 1.62 1.67 1.71

VPOR/PDR V
(BORH_EN =0) Falling edge 1.58 1.62 1.68

Brownout reset threshold 1 Rising edge 2.04 2.10 2.15

VBOR1
(BORH_EN =1) Falling edge 1.95 2.00 2.06

Brownout reset threshold 2 Rising edge 2.34 2.41 2.47

VBOR2 V
(BORH_EN =1) Falling edge 2.25 2.31 2.37

Brownout reset threshold 3 Rising edge 2.63 2.70 2.78

VBOR3
(BORH_EN =1) Falling edge 2.54 2.61 2.68
Rising edge 1.90 1.96 2.01
VPVD0 PVD threshold 0
Falling edge 1.81 1.86 1.91
Rising edge 2.05 2.10 2.16
VPVD1 PVD threshold 1
Falling edge 1.96 2.01 2.06
Rising edge 2.19 2.26 2.32
VPVD2 PVD threshold 2
Falling edge 2.10 2.15 2.21
Rising edge 2.35 2.41 2.47
VPVD3 PVD threshold 3 V
Falling edge 2.25 2.31 2.37
Rising edge 2.49 2.56 2.62
VPVD4 PVD threshold 4
Falling edge 2.39 2.45 2.51
Rising edge 2.64 2.71 2.78
VPVD5 PVD threshold 5
Falling edge 2.55 2.61 2.68
Rising edge 2.78 2.86 2.94
VPVD6 PVD threshold 6
Falling edge 2.69 2.76 2.83
VPOR/PDR Hysteresis for power-on/down reset Hysteresis in Run mode - 43 -
Hysteresis voltage of BOR (unless mV
Vhyst_BOR_PVD - - 100 -
BORH_EN = 0) and PVD
IDD_BOR_PVD(2) BOR and PVD consumption from VDD - - - 0.630
µA
IDD_POR_PDR POR and PDR consumption from VDD - 0.8 - 1.2

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Table 24. Embedded reset and power control block characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

Rising edge 1.66 1.71 1.76

VAVD0 VDDA voltage monitor 0 threshold
Falling edge 1.56 1.61 1.66
Rising edge 2.06 2.12 2.19
VAVD1 VDDA voltage monitor 1threshold
Falling edge 1.96 2.02 2.08
V
Rising edge 2.42 2.50 2.58
VAVD2 VDDA voltage monitor 2 threshold
Falling edge 2.35 2.42 2.49
Rising edge 2.74 2.83 2.91
VAVD3 VDDA voltage monitor 3 threshold
Falling edge 2.64 2.72 2.80
VIO2VM VDDIO2 voltage monitor threshold - - 0.9 - V
Vhyst_AVD Hysteresis of VDDA voltage monitor - - 100 - mV
Power voltage detector consumption
IDD_AVD_IO2VM(2) - - - 0.25
from VDD (AVD, IO2VM)
µA
VDDA analog voltage detector
IDD_AVD_A(2) - - - 0.25
consumption from VDDA (resistor bridge)
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Specified by design - Not tested in production

5.3.5 Embedded reference voltage

The parameters given in Table 25 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 20.

Table 25. Embedded reference voltage

Symbol Parameter Conditions Min Typ Max Unit

VREFINT(1) Internal reference voltage -40 °C < TJ < +130 °C 1.180 1.216 1.255 V
ADC sampling time when reading the
tS_vrefint(2)(3) - 4.3 - -
internal reference voltage
VBAT sampling time when reading the
tS_vbat 9 - - µs
internal VBAT voltage
Start time of reference voltage buffer
tstart_vrefint(3) - - - 4.4
when the ADC is enabled
Irefbuf(3) Reference buffer consumption for ADC VDD = 3.3 V 9 13.5 23 µA
Internal reference voltage spread over
∆VREFINT(3) -40 °C < TJ < +130 °C - 5 15 mV
the temperature range
Average temperature
TCoeff Average temperature coefficient - 20 70 ppm/°C
coefficient
VDDcoeff Average voltage coefficient 3.0 V < VDD < 3.6 V - 10 1370 ppm/V

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Table 25. Embedded reference voltage (continued)

Symbol Parameter Conditions Min Typ Max Unit
(3)
VREFINT_DIV1 1/4 reference voltage - 25 -
VREFINT_DIV2(3) 1/2 reference voltage - - 50 - %VREFINT
(3)
VREFINT_DIV3 3/4 reference voltage - 75 -
1. VREFINT does not take into account package and soldering effects.
2. The shortest sampling time for the application can be determined by multiple iterations.
3. Specified by design - Not tested in production.

Table 26. Internal reference voltage calibration value

Symbol Parameter Memory address

VREFINT_CAL Raw data acquired at 30 °C, VDDA = 3.3 V 0x08FF F810 - 0x08FF F811

5.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The flash memory access time is adjusted with the minimum wait-state number,
depending on the fHCLK frequency (refer to the tables “FLASH recommended number
of wait states and programming delay” available in the reference manual).
• When the peripherals are enabled, the AHB clock frequency is the CPU frequency and
the APB clock frequency is AHB frequency.
The parameters given in the following tables are derived from tests performed under supply
voltage conditions summarized in Table 20, and, unless otherwise specified, at ambient
temperature.
The maximum current consumption is given for LDO regulator ON and VDD = 3.6 V. The
typical current consumption is given for VDD = 3V at ambient temperature.

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Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory, 2-way instruction cache ON, PREFETCH ON

Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C

250 30.8 33 57 70 -
VOS0 215 26.7 29 50 63 -
200 24.5 26 47 59 -
200 21.3 23 40 49 65
180 19.5 21 37 46 62
VOS1
All peripherals 168 18.1 19 34 44 60
disabled 150 16.2 18 31 40 57
150 14.8 16 28 36 49
VOS2
100 10.3 11 21 28 42
100 9.5 10 19 25 36
VOS3 60 6.1 7 14 19 31
Supply current in
IDD(Run) 25 3.1 4 9 14 25 mA
Run mode
250 66.5 69 87 101 -
VOS0 215 57.4 60 76 90 -
200 53.3 56 71 84 -
200 46.5 49 61 72 86
VOS1 180 42.3 44 56 66 81
All peripherals
150 35.1 37 47 57 72
enabled
150 32.2 34 43 51 63
VOS2
100 22.0 23 30 37 49
100 20.1 21 27 33 47
VOS3 60 12.7 14 18 23 36
25 6.0 7 11 15 27
1. Evaluated by characterization - Not tested in production.

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Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory, 1-way instruction cache ON, PREFETCH ON
Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C

250 27.6 30 51 64 -
VOS0
200 22.1 24 43 55 -
200 19.1 21 36 46 64
VOS1 180 17.7 19 34 43 58
Supply current All peripherals
IDD(Run) 150 14.6 16 29 38 54 mA
in Run mode disabled
150 13.4 15 26 33 47
VOS2
100 9.3 10 20 27 40
100 8.5 9 17 23 35
VOS3
25 2.8 4 9 14 25
1. Evaluated by characterization - Not tested in production.

Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from SRAM with cache 1-way
Max(1)
Symbol

fHCLK Typ
Parameter Conditions Unit
(MHz) LDO TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C

250 26.8 29 50 63 -
VOS0 215 23.6 25 45 57 -
200 21.4 23 42 54 -
200 18.6 20 35 45 60
VOS1 180 17.1 19 33 52 58
IDD Supply current All peripherals
150 14.1 15 28 37 53 mA
(Run) in Run mode disabled
150 13.0 14 25 33 46
VOS2
100 9.1 10 19 26 40
100 8.3 9 17 23 34
VOS3 60 5.4 6 13 18 29
25 2.8 3 9 14 25
1. Evaluated by characterization - Not tested in production.

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Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from SRAM with cache 2-way
Max(1)
fHCLK Typ
Symbol Parameter Conditions Unit
(MHz) LDO TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C

250 30.1 32 55 69 -
VOS0 200 26.1 28 49 62 -
168 24.1 26 46 59 -
150 20.8 22 39 48 64
100 19.1 21 36 46 62
VOS1
Supply current All peripherals 250 17.6 19 34 43 59
IDD(Run) mA
in Run mode disabled 200 15.8 17 31 40 56
150 14.5 16 28 35 49
VOS2
100 10.1 11 21 28 41
250 9.2 10 19 25 36
VOS3 200 6.0 7 14 19 30
168 3.0 4 9 14 25
1. Evaluated by characterization - Not tested in production.

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Table 31. Typical consumption in Run mode with CoreMark running

from flash memory and SRAM(1)
Conditions
fHCLK Typ Typ
Symbol Parameter Unit Unit
(MHz) LDO LDO
Peripheral Code

250 30.8 123.1

All peripherals
200 24.5 122.5
disabled,
instruction cache FLASH 168 18.1 107.7
2-way,
150 14.8 98.9
prefetch ON
100 9.5 94.8

All peripherals 250 27.6 110.4

disabled, 200 19.1 95.4
instruction cache FLASH
1-way, 150 13.4 89.4
prefetch ON 100 8.5 85.3
Supply current
IDD(Run) mA μA/MHz
in Run mode 250 30.1 120.5
All peripherals 200 20.8 103.9
disabled,
SRAM 168 17.6 104.8
instruction cache
2-way 150 14.5 97.0
100 9.2 92.4
250 26.8 107.3
All peripherals
disabled, 200 18.6 92.8
SRAM
instruction cache 150 13.0 86.8
1-way
100 8.3 82.6
1. Evaluated by characterization - Not tested in production.

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Table 32. Typical consumption in Run mode with SecureMark running from
flash memory and SRAM(1)
Conditions
fHCLK Typ Typ
Symbol Parameter Unit Unit
(MHz) LDO LDO
Peripheral Code

250 32.8 131.2

180 20.9 116.2
All peripherals disabled,
instruction cache 2-way, FLASH 168 19.4 115.6
prefetch ON
150 16.1 107.2
Supply 100 10.3 102.5
IDD(Run) current in mA μA/MHz
Run mode 250 30.0 120.0
180 19.1 106.4
All peripherals disabled,
instruction cache 1-way, FLASH 168 17.9 106.3
prefetch ON
150 14.7 98.3
100 9.5 94.6
1. Evaluated by characterization - Not tested in production.

Table 33. Typical and maximum current consumption in Sleep mode

Max(1)
fHCLK Typ
Symbol Parameter Conditions TJ = Unit
(MHz) LDO TJ = TJ = TJ =
25°C 85°C 105°C 130°

250 6.3 7 18 27 -
VOS0
200 4.9 6 15 25 -
200 4.2 5 12 20 35
180 4.1 5 12 20 35
VOS1
Supply 168 3.6 4 12 19 35
All peripherals
IDD(sleep) current in mA
disabled 150 3.3 4 11 18 34
sleep mode
150 3.0 4 10 16 29
VOS2
100 2.4 3 9 15 28
100 2.2 3 8 13 24
VOS3
60 1.7 2 7 12 23
1. Evaluated by characterization - Not tested in production.

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Table 34. Typical and maximum current consumption in Stop mode

Max(1)
Symbol

Typ
Parameter Conditions Unit
LDO TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C

SVOS3 0.26 0.79 6.34 11.45 22.31

Flash memory in
low power mode, SVOS4 0.19 0.59 5.05 9.21 18.13
SRAMs ON
SVOS5 0.15 0.43 3.97 7.42 14.99
Flash memory in SVOS3 0.27 0.81 6.36 11.47 22.35
normal mode,
SRAMs ON SVOS4 0.21 0.61 5.07 9.24 18.17
IDD Supply current
Flash memory in SVOS3 0.20 0.65 5.08 9.21 18.05 mA
(stop) in Stop
low power mode,
SVOS4 0.15 0.48 4.05 7.41 14.68
SRAMs OFF except SRAM2
16 Kbytes ON SVOS5 0.10 0.32 2.84 5.32 10.81
Flash memory in SVOS3 0.21 0.70 5.49 9.93 19.42
low power mode,
SVOS4 0.16 0.52 4.37 7.99 15.79
SRAMs OFF except SRAM2
ON SVOS5 0.16 0.36 3.20 5.98 12.12
1. Evaluated by characterization - Not tested in production.

Table 35. Typical and maximum current consumption in Standby mode

Conditions Typ(1) Max(1)

Symbol Parameter Unit
Backup RTC and TJ = TJ = TJ = TJ =
1.8 V 2.4 V 3V 3.3 V
RAM LSE(2) 25 °C 85 °C 105 °C 130 °C

Supply OFF OFF 2.6 2.8 3.0 3.2 4.3 8.8 16.5 42.6
current in ON OFF 3.8 4.1 4.4 4.6 6.4 16.9 31.5 75.7
IDD(standby) standby μA
mode, OFF ON 2.9 3.2 3.5 3.7 5.3 10.0 17.8 44.6
IWDG OFF ON ON 4.2 4.5 4.9 5.1 7.4 18.1 32.8 77.7
1. Evaluated by characterization - Not tested in production.
2. LSE is in medium-low drive mode.

Table 36. Typical and maximum current consumption in VBAT mode

Conditions Typ(1) Max(1)

Symbol Parameter Unit
Backup RTC and TJ = TJ = TJ = TJ =
1.62 V 2.4 V 3V 3.3 V
RAM LSE(2) 25 °C 85 °C 105 °C 130 °C

OFF OFF 0.01 0.01 0.02 0.02 0.2 2.0 4.9 14.9

Supply current ON OFF 1.1 1.1 1.2 1.30 2.7 12.7 23.8 52.2
IDD(VBAT) μA
in VBAT mode OFF ON 0.5 0.5 0.5 0.6 1.2 3.2 6.2 16.9
ON ON 1.6 1.6 1.6 1.8 3.7 13.9 25.1 54.2

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1. Evaluated by characterization - Not tested in production.

2. LSE is in medium-low drive mode.

I/O system current consumption

All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 57.
To estimate the current consumption for the output pins, consider also external pull-downs
or loads.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the Schmitt trigger
circuits used to discriminate the input value. Unless this specific configuration is required by
the application, this current consumption can be avoided by configuring the I/Os in analog
mode. This is notably the case of ADC input pins, to be configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done by using pull-up/down resistors, or by configuring the pins in
output mode.
In addition to the internal peripheral current consumption, the I/Os used by an application
also contribute to the current consumption. When an I/O pin switches, it uses the current
from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the
capacitive load (internal or external) connected to the pin:

I SW = V DDx × f SW × C L

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration
• All peripherals are disabled unless otherwise mentioned
• The I/O compensation cell is enabled
• fHCLK is the CPU clock, fPCLK = frcc_cpu_ck, and fHCLK = frcc_cpu_ck.

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The given value is calculated by measuring the difference of current consumption:

• with all peripherals clocked off
• with only one peripheral clocked on
• frcc_cpu_ck = 250 MHz (Scale 0), frcc_cpu_ck = 200 MHz (Scale 1), frcc_cpu_ck = 150 MHz
(Scale 2), frcc_cpu_ck= 100 MHz (Scale 3)
• the ambient operating temperature is 25 °C and VDD = 3.0 V

Table 37. Peripheral current consumption in Sleep mode

IDD (typ)
Bus Peripheral Unit
VOS0 VOS1 VOS2 VOS3

SRAM1 0.82 0.71 0.67 0.59

BKPRAM 0.84 0.74 0.67 0.61
CRC 0.28 0.23 0.19 0.20
DCACHE 0.72 0.63 0.58 0.51
FLASH 9.62 8.41 7.66 6.99
AHB1 GPDMA1 0.48 0.43 0.38 0.35 μA/MHz
GPDMA2 0.75 0.67 0.6 0.55
GTZC1 0.98 0.85 0.79 0.71
ICACHE 0.78 0.67 0.62 0.56
RAMCFG 0.57 0.5 0.44 0.41
AHB1 0.43 0.4 0.36 0.34

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Table 37. Peripheral current consumption in Sleep mode (continued)

IDD (typ)
Bus Peripheral Unit
VOS0 VOS1 VOS2 VOS3

ADC12 2.16 1.89 1.73 1.56

DAC1 1.28 1.12 1.02 0.92
DCMI 3.41 3 2.75 2.51
GPIOA 0.06 0.05 0.05 0.05
GPIOB 0.05 0.05 0.06 0.05
GPIOC 0.04 0.04 0.04 0.03
GPIOD 0.07 0.07 0.06 0.04
GPIOE 0.1 0.06 0.08 0.05
GPIOF 0.11 0.07 0.08 0.06
AHB2 μA/MHz
GPIOG 0.06 0.03 0.04 0.02
GPIOH 0.05 0.05 0.04 0.02
HASH1 1.1 0.96 0.88 0.8
PKA 5.03 4.41 4.04 3.66
RNG1 0.87 0.76 0.71 0.64
SAES 6.2 5.81 5.57 5.5
SRAM2 1.29 1.12 1.05 0.95
SRAM3 0.68 0.6 0.54 0.48
AHB2 1.45 1.28 1.18 1.08
FMC 3.96 3.47 3.2 2.92
OSPI1 1.76 1.56 1.44 1.32
AHB4 OTFDEC1 1.3 1.13 1.06 0.97 uA/MHz
SDMMC1 9.07 7.97 7.31 6.66
AHB4 0.47 0.42 0.37 0.35

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Table 37. Peripheral current consumption in Sleep mode (continued)

IDD (typ)
Bus Peripheral Unit
VOS0 VOS1 VOS2 VOS3

CEC 0.15 0.12 0.12 0.12

CRS 0.26 0.22 0.21 0.21
FDCAN1 6.36 5.58 5.12 4.66
I2C1 0.54 0.47 0.45 0.42
I2C2 0.57 0.51 0.47 0.47
I3C1 0.29 0.27 0.25 0.24
LPTIM2 1.03 0.9 0.83 0.79
SPI2/I2S2 1.11 0.98 0.9 0.84
SPI3/I2S3 1.07 0.94 0.86 0.82
TIM12 1.35 1.19 1.09 1.03
TIM7 0.53 0.47 0.43 0.4
TIM6 0.53 0.47 0.42 0.4
APB1 TIM5 2.82 2.49 2.27 2.09 μA/MHz
TIM4 2.41 2.13 1.94 1.79
TIM3 2.37 2.08 1.91 1.76
TIM2 2.79 2.45 2.24 2.05
DTS 1.54 1.33 1.23 1.15
UART4 1.16 1.03 0.93 0.88
UART5 1.15 1.02 0.92 0.88
UCPD1 1.14 0.98 0.9 0.85
USART2 1.28 1.13 1.04 0.96
USART3 1.29 1.14 1.06 0.98
USART6 1.27 1.13 1.02 0.97
WWDG1 1.41 0.29 0.27 0.25
APB1 0.32 1.26 1.14 1.03
SPI1/I2S1 1.01 0.89 0.81 0.74
SPI4 1.06 0.94 0.86 0.77
TIM1 4.64 4.09 3.75 3.42
TIM15 2.41 2.14 1.96 1.78
APB2 μA/MHz
TIM8 4.55 4 3.69 3.34
USART1 1.30 1.15 1.05 0.94
USBFS 2.48 2.17 1.99 1.78
APB2 0.68 0.59 0.53 0.51

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Table 37. Peripheral current consumption in Sleep mode (continued)

IDD (typ)
Bus Peripheral Unit
VOS0 VOS1 VOS2 VOS3

LPTIM1 0.93 0.82 0.73 0.65

LPUART1 0.86 0.77 0.68 0.61
RTCAPB 2.11 1.85 1.69 1.51
APB3 SBS 0.45 0.38 0.35 0.32 uA/MHz
VREFBUF 0.09 0.09 0.05 0.04
I3C2 2.55 2.25 2.03 1.84
APB3 0.52 0.46 0.42 0.39

Wake-up time from low-power modes

The times given in Table 38 are measured starting from the wake-up event trigger up to the
first instruction executed by the CPU:
• for Stop or Sleep modes: the wake-up event is WFE.
• WKUP (PA1) pin is used to wake-up from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD = 3.0 V.

Table 38. Low-power mode wake-up timings(1)

Symbol Parameter Conditions Typ Max Unit

Instruction cache enabled 15 16 CPU

Wake-up time from
tWUSLEEP clock
Sleep mode Instruction cache disabled 15 16 cycles
SVOS3, HSI 64 MHz, flash memory in normal mode 4.0 4.8
SVOS3, HSI 64 MHz, flash memory in low-power mode 7.9 11.5
SVOS4, HSI 64 MHz, flash memory in normal mode 13.8 16.0
SVOS4, HSI 64 MHz, flash memory in low-power mode 17.7 21.9

Wake-up time from SVOS5, HSI 64 MHz, flash memory in low-power mode 31.4 36.8
tWUSTOP
Stop mode SVOS3, CSI 4 MHz, flash memory in normal mode 25.5 31.0 µs
SVOS3, CSI 4 MHz, flash memory in low power mode 27.7 34.2
SVOS4, CSI 4 MHz, flash memory in normal mode 35.3 40.8
SVOS4, CSI 4 MHz, flash memory in low-power mode 37.5 44.0
SVOS5, CSI 4 MHz, flash memory in low-power mode 51.2 58.9
Wake-up time from
tWUSTBY VCAP capacitors discharged 506.0 653.6
Standby mode
1. Evaluated by characterization - Not tested in production.

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5.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal must respect the Table 39 in addition to Table 57. The external
clock can be low-swing (analog) or digital. In case of a low-swing analog input clock, the
clock squarer must be activated (refer to RM0481).

Table 39. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock External digital/analog

fHSE_ext 4 25 50 MHz
source frequency clock
Digital OSC_IN input
VHSEH 0.7 VDD - VDD
high-level voltage
External digital clock V
Digital OSC_IN input
VHSEL VSS - 0.3 VDD
low-level voltage
Digital OSC_IN input
tw(HSEH)/tw(HSEL) (2) External digital clock 7 - - ns
high or low time

Visw(HSEH) Analog low-swing

(3) OSC_IN peak-to-peak 0.2 - 2/3 VDD V
(VHSEH -VHSEH) External analog low
amplitude
swing clock
Analog low-swing
DuCyHSE 45 50 55 %
OSC_IN duty cycle
Analog low-swing
External analog low
tr(HSE)/tf(HSE) OSC_IN rise and fall 0.05 / fHSE_ext - 0.3 / fHSE_ext ns
swing clock, 10% to 90%
times
1. Specified by design - Not tested in production..
2. The rise and fall times for a digital input signal are not specified, but the VHSEH and VHSEL conditions must be fulfilled
anyway.
3. The DC component of the signal must ensure that the signal peaks are located between VDD and VSS.

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Figure 16. High-speed external clock source AC timing diagram

VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t

THSE

External fHSE_ext
IL
clock source OSC_IN
STM32

ai17528b

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal must respect the Table 40 in addition to Table 57. The external
clock can be low-swing (analog) or digital. In case of a low-swing analog input clock, the
clock squarer must be activated (refer to RM0481).

Table 40. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fLSE_ext External digital/analog clock - 32.768 1000 kHz
frequency
Digital OSC32_IN input
VLSEH 0.7 VDD - VDD
high-level voltage
External digital clock V
Digital OSC32_IN input
VLSEL VSS - 0.3 VDD
low-level voltage
Digital OSC_IN input high
tw(LSEH)/tw(LSEL) External digital clock 250 - - ns
or low time
Analog low-swing OSC_IN
Visw_H 0.6 - 1.225
high-level voltage
Analog low-swing OSC_IN
Visw_L 0.35 - 0.8 V
low-level voltage External analog low swing
ViswLSE Analog low-swing OSC_IN clock
0.5 - 0.875
(VLSEH -VLSEL) peak-to-peak amplitude
Analog low-swing OSC_IN
DuCyLSE 45 50 55 %
duty cycle
Analog low-swing OSC_IN External analog low swing
tr(LSE)/tf(LSE) - 100 200 ns
rise and fall times clock, 10% to 90%
1. Specified by design - Not tested in production.

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Note: For information on selecting the crystal, refer to AN2867 “Oscillator design guide for ST
microcontrollers” available from www.st.com.

Figure 17. Low-speed external clock source AC timing diagram

VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t

TLSE

External fLSE_ext
OSC32_IN IL
clock source
STM32

ai17529b

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic
resonator oscillator.
All the information given in this paragraph are based on characterization results obtained
with typical external components specified in Table 41. In the application, the resonator and
the load capacitors must be placed as close as possible to the oscillator pins to minimize
output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).

Table 41. 4-50 MHz HSE oscillator characteristics(1)

Symbol Parameter Operating conditions(2) Min Typ Max Unit

F Oscillator frequency - 4 - 50 MHz

RF Feedback resistor - - 200 - kΩ
During startup(3) - - 10
VDD = 3 V, Rm = 20 Ω,
- 0.44 -
CL = 10 pF at 4 MHz
VDD = 3 V, Rm = 20 Ω,
- 0.44 -
CL = 10 pF at 8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, Rm = 20 Ω, mA
- 0.55 -
CL = 10 pF at 16 MHz
VDD = 3 V, Rm = 20 Ω,
- 0.67 -
CL = 10 pF at 32 MHz
VDD = 3 V, Rm = 20 Ω,
- 1.17 -
CL = 10 pF at 48 MHz
Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms

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1. Evaluated by design - Not tested in production.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 to 20 pF range (typical), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 usually have the
same size. The crystal manufacturer typically specifies a load capacitance, which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate for the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to AN2867 “Oscillator design guide for ST
microcontrollers”, available from www.st.com.

Figure 18. Typical application with an 8 MHz crystal

Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain

REXT(1) OSC_OU T STM32

CL2
ai17530b

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph is based on design simulation results
obtained with typical external components specified in Table 42. In the application, the
resonator and the load capacitors must be placed as close as possible to the oscillator pins
to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package,
accuracy).

Table 42. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

F Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 01
- 333 -
Medium low drive capability
LSEDRV[1:0] = 10
IDD LSE current consumption - 462 - nA
Medium high drive capability
LSEDRV[1:0] = 11
- 747 -
High drive capability

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Table 42. Low-speed external user clock characteristics(1) (continued)

Symbol Parameter Conditions(2) Min Typ Max Unit

LSEDRV[1:0] = 01
- - 0.75
Medium low drive capability
Maximum critical crystal LSEDRV[1:0] = 10
Gmcritmax - - 1.7 µA/V
gm Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Specified by design - Not tested in production.
2. Refer to the note and caution paragraphs below the table, and to AN2867 “Oscillator design guide for ST
microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to when a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and can vary significantly
with the crystal manufacturer

Note: For information on selecting the crystal, refer to AN2867 “Oscillator design guide for ST
microcontrollers”, available from www.st.com.

Figure 19. Typical application with a 32.768 kHz crystal

Resonator with
integrated CL1
capacitors OSC32_IN fLSE

Bias
32.768 kHz
RF controlled
resonator
gain

OSC32_OUT STM32
CL2
ai17531d

Note: An external resistor is not required between OSC32_IN and OSC32_OUT, and it is
forbidden to add one.

5.3.8 Internal clock source characteristics

The parameters given in Table 43 to Table 46 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 20.

48 MHz high-speed internal RC oscillator (HSI48)

Table 43. HSI48 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 HSI48 frequency VDD = 3.3 V, TJ= 30 °C 47.5(1) 48 48.5(1) MHz

TRIM(3) User trimming step - - 0.175 0.250
USER TRIM %
User trimming coverage ±32 steps ±4.70 ±5.6 -
COVERAGE(2)
DuCy(HSI48)(3) Duty cycle - 45 - 55 %

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Table 43. HSI48 oscillator characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

Accuracy of the HSI48 oscillator over

ACCHSI48_REL(3) TJ = -40 to 130 °C -4.5 - 4 %
temperature (reference is 30 °C)

HSI48 oscillator frequency drift with VDD = 3.0 to 3.6 V - 0.025 0.05
∆VDD(HSI48) %
VDD (reference is 3.3 V) VDD = 1.71 to 3.6 V - 0.05 0.1
tsu(HSI48)(3) HSI48 oscillator start-up time - - 2.1 4.0 μs
(3)
IDD(HSI48) HSI48 oscillator power consumption - - 350 400 μA
Next transition jitter accumulated
NT jitter(3) - - ±0.15 -
jitter on 28 cycles
ns
Paired transition jitter accumulated
PT jitter(3) - - ±0.25 -
jitter on 56 cycles(4)
1. Calibrated during manufacturing tests.
2. Evaluated by characterization - Not tested in production.
3. Specified by design - Not tested in production.
4. Jitter measurements are performed without clock sources activated in parallel.

64 MHz high-speed internal RC oscillator (HSI)

Table 44. HSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency VDD = 3.3 V, TJ = 30 °C 63.7(2) 64.0(2) 64.3(2) MHz

Trimming is not a multiple of 32(3) - 0.24 0.32
(3)
Trimming is 128, 256, and 384 -5.2 -1.8 -
TRIM User trimming step Trimming is 64, 192, 320, and 488(3) -1.4 -0.8 - %

Other trimmings are multiples of 32 (not

-0.6 -0.25 -
including multiples of 64 and 128)(3)
DuCy(HSI) Duty cycle - 45 - 55 %
Frequency drift with VDD
∆VDD(HSI) VDD= 1.71 to 3.6 V -0.12 - 0.03
(reference is 3.3 V)
Frequency drift over TJ= -20 to 105 °C -1(4) - 1(4) %
∆TEMP(HSI) temperature (reference
is 64 MHz) TJ= -40 to 130 °C -2(4) - 1(4)

tsu(HSI) Start-up time - - 1.4 2.0 μs

At 1% of target frequency - 4 8
tstab(HSI) Stabilization time μs
At 1% of target frequency - - 4
IDD(HSI) Power consumption - - 300 450 μA
1. Specified by design - Not tested in production, unless otherwise specified.
2. Calibrated during manufacturing tests.
3. Trimming value of HSICAL[8:0.]
4. Guaranteed by characterization - Not tested n production.

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4 MHz low-power internal RC oscillator (CSI)

Table 45. CSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fCSI Frequency VDD = 3.3 V, TJ = 30 °C 3.96(2) 4 4.04(2) MHz

Trimming is not a multiple of 16 - 0.40 0.75
Trimming is not a multiple of 32 -4.75 -2.75 0.75
TRIM User trimming step %
Other trimmings are a multiple of 32
-0.43 0.00 0.75
(not including multiples of 64 and 128)
DuCy(CSI) Duty cycle - 45 - 55 %

Frequency drift over TJ= 0 to 85 °C -3.7(3) - 4.5(3) %

∆TEMP(CSI)
temperature TJ= -40 to TJ = 130 °C -11(3) - 7.5(3) %
∆VDD(CSI) Frequency drift over VDD VDD= 1.71 to 3.6 V -0.06 - 0.06 %
tsu(CSI) Start-up time - - 1 2 μs
Stabilization time
tstab(CSI) - - - 4 cycle
(to reach ± 3% of fCSI)
IDD(CSI) Power consumption - - 23 30 μA
1. Specified by design - Not tested in production, unless otherwise specified.
2. Calibrated during manufacturing tests.
3. Evaluated by characterization - Not tested in production.

Low-speed internal (LSI) RC oscillator

Table 46. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.3 V, TJ = 25 °C 31.4(1) 32 32.6(1)

fLSI Frequency TJ = -40 to 110 °C, VDD =1.71 to 3.6 V 29.76(2) - 33.6(2) kHz
TJ = -40 to 130 °C, VDD =1.71 to 3.6 V 29.4(2) - 33.6(2)
(3)
tsu(LSI) Start-up time - - 80 130
Stabilization time μs
tstab(LSI)(3) - - 120 170
(5% of final value)
IDD(LSI)(3) Power consumption - - 130 280 nA
1. Calibrated during manufacturing tests.
2. Evaluated by characterization - Not tested in production.
3. Specified by design - Not tested in production.

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5.3.9 PLL characteristics

The parameters given in Table 47 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 20.

Table 47. PLL characteristics (wide VCO frequency range)(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock - 2 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1 - 250(2)

PLL multiplier output clock VOS1 1 - 200(2)

fPLL_P_OUT
P, Q, R VOS2 1 - 150(2) MHz
VOS3 1 - 100(2)
fVCO_OUT PLL VCO output - 128 - 560(2)
Normal mode - 45 100(3) μs
tLOCK PLL lock time
Sigma-delta mode (fPLL_IN ≥ 8 MHz) - 60 120(3)
fVCO_OUT = 128 MHz - 60 -
fVCO_OUT = 200 MHz - 50 -
Cycle-to-cycle jitter ±ps
fVCO_OUT = 400 MHz - 20 -
fVCO_OUT = 560 MHz - 15 -
Normal mode (f PLL_IN = 2 MHz),
- ±0.2 -
Jitter fVCO_OUT = 560 MHz
Normal mode (f PLL_IN = 16 MHz),
- ±0.8 -
fVCO_OUT = 560 MHz
Long term jitter %
Sigma-delta mode (f PLL_IN = 2 MHz),
- ±0.2 -
fVCO_OUT = 560 MHz
Sigma-delta mode (f PLL_IN = 16 MHz),
- ±0.8 -
fVCO_OUT = 560 MHz
VDD - 330 420
fVCO_OUT = 560 MHz
PLL power consumption on VCORE - 630 -
IDD(PLL) μA
VDD VDD - 155 230
fVCO_OUT = 128 MHz
VCORE - 170 -
1. Specified by design - Not tested in production, unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation.
3. Evaluated by characterization - Not tested in production.

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Table 48. PLL characteristics (medium VCO frequency range)

Symbol Parameter Conditions Min(1) Typ(1) Max(1) Unit

PLL input clock - 1 - 2 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1.17 - 210

PLL multiplier output clock VOS1 1.17 - 210

fPLL_OUT
P, Q, R VOS2 1.17 - 160(2) MHz
(2)
VOS3 1.17 - 88
fVCO_OUT PLL VCO output - 150 - 420
Normal mode - 45 80(3)
tLOCK PLL lock time μs
Sigma-delta mode Forbidden
fVCO_OUT = 150 MHz - - 60 -
fVCO_OUT = 200 MHz - - 40 -
Cycle-to-cycle jitter
fVCO_OUT = 400 MHz - - 18 -
±ps
Jitter fVCO_OUT = 420 MHz - - 15 -
fVCO_OUT = 150 MHz fPLL_OUT = - 75 -
Period jitter
fVCO_OUT = 400 MHz 50 MHz - 25 -
Long term jitter Normal mode fVCO_OUT = 400 MHz - ±0.2 - %
VDD - 275 360
fVCO_OUT = 420 MHz
PLL power consumption on VCORE - 450 -
IDD(PLL) μA
VDD VDD - 160 240
fVCO_OUT = 150 MHz
VCORE - 165 -
1. Specified by design - Not tested in production, unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation.
3. Evaluated by characterization - Not tested in production.

5.3.10 Memory characteristics

Flash memory
The characteristics are given at TJ = -40 to 130 °C unless otherwise specified.
The devices are shipped to customers with the flash memory erased.

Table 49. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

Word program(2) - 2.5 3.6

IDD Supply current Sector erase - 1.8 4 mA
Mass erase - 2.0 4
1. Specified by design - Not tested in production

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2. Data is evaluated with a write of 50% of the programmed bits equal to 0.

Table 50. Flash memory programming(1)

Symbol Parameter Conditions Min(2) Typ Max(2) Unit

128 bits (user area) - 32 100

tprog Word program time µs
16 bits (OTP area) - 32 100
tERASE Sector erase time (8 Kbytes) - - 2 10 ms
tME Mass erase time - 0.52 2.6 s
Vprog Programming voltage 1.71 - 3.6 V
1. Data are valid for program memory and high-cycling data memory.
2. Specified by design - Not tested in production.

Table 51. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NPEND Endurance program memory TJ = -40 to +130 °C 10

kcycles
NDEND Endurance data memory TJ = -40 to +130 °C 100
1 kcycle at TA = 125 °C 10
tPRET Program memory, data retention 1 kcycles at TA = 85 °C 30
10 kcycles at TA = 55 °C 30
Years
100 kcycle at TA = 125 °C 1
tDRET Data retention for data memory 100 kcycles at TA = 85 °C 10
100 kcycles at TA = 55 °C 10
1. Evaluated by characterization - Not tested in production, unless otherwise specified.

5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed (toggling two LEDs through I/O ports), the device is
stressed by two electromagnetic events until a failure occurs. The failure is indicated by the
LEDs:
• Electrostatic discharge (ESD), positive and negative, is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows to resume normal operation.
The test results are given in Table 52. They are based on the EMS levels and classes
defined in AN1709 “EMC design guide for STM8, STM32 and legacy MCUs”.

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Table 52. EMS characteristics

Symbol Parameter Conditions Level/Class

VDD = 3.3 V, TA = 25 °C,

Voltage limits to apply on any I/O pin to
VFESD LQFP144, frcc_cpu_ck = 250 MHz, 3B
induce a functional disturbance
conform to IEC 61000-4-2
Fast transient voltage burst limits to apply VDD = 3.3 V, TA = 25 °C,
VFTB through 100 pF on VDD and VSS pins to LQFP144, frcc_cpu_ck = 250 MHz, 5A
induce a functional disturbance conform to IEC 61000-4-4

As a consequence, it is recommended to add a serial resistor (1 kΩ), located as close as

possible to the MCU, to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (such as control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST or on the oscillator pins for 1 s.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015 “Software
techniques for improving microcontrollers EMC performance”).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard, which specifies the test board and the pin loading.

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Table 53. EMI characteristics

Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/250 MHz

0.1 to 30 MHz 8
30 to 130 MHz 0
Peak VDD = 3.6 V, TA = 25 °C, LQFP144 package, dBµV
SEMI 130 MHz to 1 GHz 24
level(1) conforming to IEC61967-2
1 GHz to 2 GHz 18
EMI level 4 -
1. Refer to the EMI radiated test chapter of application note AN1709 “EMC design guide for STM8, STM32 and Legacy
MCUs” available from the ST website www.st.com.

5.3.12 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive pulse followed by a negative one) are applied to the pins
of each sample according to each pin combination. This test conforms to the
ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards.

Table 54. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)

Electrostatic discharge
TA = 25 °C conforming to
VESD(HBM) voltage (human body All packages 1C 1000(2)
ANSI/ESDA/JEDEC JS-001
model)
V
Electrostatic discharge
TA = +25 °C conforming to
VESD(CDM) voltage (charge device All packages C2a 500
ANSI/ESDA/JEDEC JS-002
model)
1. Evaluated by characterization - Not tested in production.
2. The electrostatic discharge is 2000 V for all pins, except for NRST, PB13 and PB14 for which the test fails at 2000 V and
passes at 1400 V.

Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.

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Table 55. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latchup class TJ = 130 °C, conforming to JESD78 II level A

5.3.13 I/O current injection characteristics

As a general rule, avoid current injection to the I/O pins, due to external voltage below VSS
or above VDD (for standard, 3.3 V-capable I/O pins) during the normal product operation. To
give an indication of the device robustness when an abnormal injection accidentally
happens, susceptibility tests are performed on a sample basis during the characterization.

Functional susceptibility to I/O current injection

While a simple application is executed, the device is stressed by injecting current into the
I/O pins (one at the time) programmed in floating input mode, and checked for functional
failures. The failure is indicated by an out of range parameter: ADC error above a certain
limit (higher than 5 LSB TUE), out of conventional limits (-5 / +0 µA range) of induced
leakage current on adjacent pins, or other functional failures (such as reset, oscillator
frequency deviation).
Table 56 shows I/Os current injection susceptibility data. Negative/positive induced leakage
currents are caused, respectively, by negative/positive injection.

Table 56. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on pins PC14, PC15, PB6, PB8,

0 0
PE8
Injected current on PB5, PB8, PC5, PD10, PE4,
IINJ 5 0 mA
PF6, PH1
Injected current on PA4, PA5, PB2, PD8 0 N/A
Injected current on all other pins 5 N/A
1. Evaluated by characterization - Not tested in production.

5.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under the conditions summarized in Table 20. All I/Os are CMOS and TTL
compliant (except for BOOT0).
Note: For information on GPIO configuration, refer to AN4899 “STM32 GPIO configuration for
hardware settings and low-power consumption”, available on www.st.com.

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Table 57. I/O static characteristics(1)

Symbol Parameter Condition Min Typ Max Unit

I/O input low level voltage

- - 0.3 VDDIOx(2)
except BOOT0
I/O input low level voltage
VIL 1.08 V < VDD < 3.6 V - - 0.4 VDDIOx - 0.1(3) V
except BOOT0
BOOT0 I/O input low level
- - 0.19 VDDIOx + 0.1(3)
voltage
I/O input high level
0.7 VDDIOx(2) - -
voltage except BOOT0
I/O input high level 0.52 VDDIOx +
VIH 1.08 V < VDD < 3.6 V - - V
voltage except BOOT0 0.18(3)
BOOT0 I/O input high 0.17 VDDIOx +
- -
level voltage 0.6(3)
TT_xx, FT_xxx and NRST
1.08 V < VDD < 3.6 V - 250 -
I/O input hysteresis
VHYS(3) mV
BOOT0 I/O input
1.71 V < VDD < 3.6 V - 200 -
hysteresis
0 < VIN ≤
- - ±200
Max(VDDXXX)(7)
Max(VDDXXX) <
FT_xx Input leakage
VIN ≤ Max(VDDXXX)+ - - 2500
current(3)
1 V) (5)(7)
Ileak(4) nA
Max(VDDXXX) < VIN ≤
- - 750
5.5 V (5)(7)
TT_xx Input leakage 0< VIN ≤ Max(VDDXXX)
(7) - - ±200
current
BOOT0 0< VIN ≤ VDDOX - - 15
Weak pull-up
RPU VIN = VSS 30 40 50
equivalent resistor(6)
kΩ
Weak pull-down
RPD VIN = VDD(7) 30 40 50
equivalent resistor(6)
CIO I/O pin capacitance - - 5 - pF
1. VDDIOx represents VDD or VDDIO2.
2. Compliant with CMOS requirements.
3. Specified by design - Not tested in production.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ieak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. VIN must be lower than Max(VDDXXX) + 3.6 V.
6. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10%).
7. Max(VDDXXX) is the maximum value of all the I/O supplies.

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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 20.

Figure 20. VIL/VIH for all I/Os except BOOT0

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins that can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 18).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 18).

Output voltage levels

Unless otherwise specified, the parameters given in Table 58 and Table 60 are derived from
tests performed under ambient temperature and VDD supply voltage conditions summarized
in Table 20. All I/Os are CMOS and TTL compliant.

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Table 58. Output voltage characteristics for all I/Os except PC13, PC14, and PC15
Symbol Parameter Conditions(1) Min Max Unit

CMOS port(2), IIO = 8 mA

VOL Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2), IIO = -8 mA
VOH Output high level voltage VDD− 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = 8 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = -8 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 20 mA
VOL(3) Output low level voltage - 1.3
2.7 V ≤ VDD ≤ 3.6 V
IIO = -20 mA
VOH(3) Output high level voltage VDD - 1.3 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 4 mA
VOL(3) Output low level voltage - 0.4 V
1.71 V ≤ VDD ≤ 3.6 V
IIO = -4 mA
VOH (3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD <3.6 V
IIO = 2 mA
VOL(3) Output low level voltage - 0.3 VDDIO2
1.08 V ≤ VDD ≤ 1.32 V
IIO = -2 mA
VOH (3) Output high level voltage 0.7 VDDIO2 -
1.71 V ≤ VDD < 1.32 V
IIO = 20 mA
- 0.4
2.3 V≤ VDD ≤3.6 V
Output low level voltage for IIO = 10 mA
VOLFM+(3) an FTf I/O pin in (FT I/O with - 0.4
1.71 V ≤ VDD ≤ 3.6 V
“f” option)
IIO = 4.5 mA
- 0.4
1.08 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17, and
the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute
maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design - Not tested in production.

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Table 59. Output voltage characteristics for FT_c I/Os (PB13/PB14)

Symbol Parameter Conditions(1) Min Max Unit

CMOS port(2), IIO = 2 mA

VOL Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2), IIO = -2 mA
VOH Output high level voltage VDD− 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = 2 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = -2 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
V
IIO = 1 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
IIO = -1 mA
VOH(3) Output high level voltage VDD - 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 0.1 mA
VOL(3) Output low level voltage - 0.4
1.71 V ≤ VDD ≤ 3.6 V
IIO = -0.1 mA
VOH (3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD < 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 17, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must
always respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design - Not tested in production.

Table 60. Output voltage characteristics for PC13(1)

Symbol Parameter Conditions(3) Min Max Unit

CMOS port(2), IIO = 3 mA

VOL Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2), IIO = -3 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = 3 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
V
TTL port(2), IIO = -3 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 1.5 mA
VOL(3) Output low level voltage - 0.4
1.71 V ≤ VDD ≤ 3.6 V
IIO = −1.5 mA
VOH(3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 17, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must
always respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design - Not tested in production.

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Table 61. Output voltage characteristics for PC14 and PC15(1)

Symbol Parameter Conditions(3) Min Max Unit

CMOS port(2), IIO = 0.5 mA

VOL Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
CMOS port(2), IIO = -0.5 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2), IIO = 0.5 mA
VOL(3) Output low level voltage - 0.4
2.7 V ≤ VDD ≤ 3.6 V
V
TTL port(2), IIO = -0.5 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤ 3.6 V
IIO = 0.25 mA
VOL(3) Output low level voltage - 0.4
1.71 V ≤ VDD ≤ 3.6 V
IIO = -0.25 mA
VOH(3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 17, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must
always respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Specified by design - Not tested in production.

Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of GPIOx_HSLVR register can be used to optimize the I/O speed when the
voltage is below 2.7 V.

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Table 62. Output timing characteristics (HSLV OFF)(1)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 8

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 10
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 14
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 5
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 16
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 5
00
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 18.0
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 36.0
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 17.0
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 34.0
Output high to low level C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 15.5
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 32.0
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 14.2
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 30.0
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12.2
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 27

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Table 62. Output timing characteristics (HSLV OFF)(1) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V 40

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 12
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 45
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 14
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 16
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 55
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 18
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 60
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 20
01
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 6.2
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 11.4
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.7
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 10.5
Output high to low level C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.1
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 9.5
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.5
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V 8.4
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V 3.7
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V 7.0

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Table 62. Output timing characteristics (HSLV OFF)(1) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 80

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 30
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 90
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 35
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 40
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 110
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 45
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 133
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 50
10
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.8
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 7.5
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.4
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 6.6
Output high to low level C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.9
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 5.7
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.5
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 4.7
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.9
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 3.7

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Table 62. Output timing characteristics (HSLV OFF)(1) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 40
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 120
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 50
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 140
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 60
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 166
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 70
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 200
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 80
11
C = 50 pF, 2.7 V≤ VDD ≤ 3.6 V - 3.3
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 6.3
C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.8
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 5.5
Output high to low level C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.3
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 4.6
C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.9
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 3.7
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.4
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 3
1. Specified by design - Not tested in production.
2. The maximum frequency is defined with the conditions (tr + tf) ≤ 2/3 T, Skew ≤ 1/20 T, and 45% < Duty cycle < 55%.
3. When 2 V < VDD < 2.7 V the maximum frequency is between values given for VDD = 1.98 V and VDD = 2.7 V.
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. When 2 V < VDD < 2.7 V the maximum trise/tfall is between values given for VDD = 1.98 V and VDD = 2.7 V.

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Output buffer timing characteristics (HSLV option enabled)

Table 63. Output timing characteristics (HSLV ON)(1)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 8

C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 10
Fmax(2) Maximum frequency C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 12 MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 14
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 16
00
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 17.8
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 15.8
Output high to low level
tr/tf(3) fall time and output low C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 14.4 ns
to high level rise time
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 13.1
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 11.4
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 40
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 45
Fmax(2) Maximum frequency C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 50 MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 55
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 60
01
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 7.2
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 6.5
Output high to low level
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 5.6 ns
to high level rise time
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 4.8
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 3.8
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 60
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 70
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 90 MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 110
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 140
10
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 5.3
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 4.6
Output high to low level
(3)(4)
tr/tf fall time and output low C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 3.8 ns
to high level rise time
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 3.0
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 2.2

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Table 63. Output timing characteristics (HSLV ON)(1) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 67

C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 100
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 120 MHz
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 155
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 200
11
C = 50 pF, 1.71 V ≤ VDD ≤ 2 V - 5.0
C = 40 pF, 1.71 V ≤ VDD ≤ 2 V - 4.1
Output high to low level
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V ≤ VDD ≤ 2 V - 3.3 ns
to high level rise time
C = 20 pF, 1.71 V ≤ VDD ≤ 2 V - 2.5
C = 10 pF, 1.71 V ≤ VDD ≤ 2 V - 1.8
1. Specified by design - Not tested in production.
2. The maximum frequency is defined with the conditions: (tr+tf) ≤ 2/3 T, Skew ≤ 1/20 T, 45% < Duty cycle < 55%.
3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform.
4. Compensation system enabled.

Table 64. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF)(1)
Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1

C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 1
00
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 83.0
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 79.0
Output high to low level fall
tr/tf(3) time and output low to high C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 46.0 ns
level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 72.0
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 68.0

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Table 64. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF)(1) (continued)
Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5

C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
01
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 24.5
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 22.2
Output high to low level fall
tr/tf(3) time and output low to high C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 20.0 ns
level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 17.8
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 15.0
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10
10
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 16.2
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 14.3
Output high to low level fall
tr/tf(3) time and output low to high C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 12.2 ns
level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10.0
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 7.9
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 20
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 23
Fmax(2)
(4) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 25 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 28
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 30
11
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 14.0
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 12.0
Output high to low level fall
tr/tf(3)(4) time and output low to high C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 10.0 ns
level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 8.0
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 6.0
1. Specified by design - Not tested in production.
2. The maximum frequency is defined with the conditions: (tr+tf) ≤ 2/3 T, Skew ≤ 1/20 T, 45% < Duty cycle < 55%.
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.

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Table 65. Output timing characteristics VDDIO2 1.2 V (HSLV ON)(1)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5

C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5
00
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 32.5
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 30.0
Output high to low level
tr/tf(3) fall time and output low C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 27.5 ns
to high level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 25.0
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 22.5
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 15.0
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 17.5
Fmax(2) Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 20.0 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 22.5
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 25.0
01
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 14.6
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 12.9
Output high to low level
tr/tf(3) fall time and output low C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 11.2 ns
to high level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 9.3
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 7.3
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 25
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 30
Fmax (2)(4)
Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 33 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 44
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 55
10
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 11.6
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 9.7
Output high to low level
tr/tf(3)(4) fall time and output low C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 7.8 ns
to high level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 6.1
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 4.3

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Table 65. Output timing characteristics VDDIO2 1.2 V (HSLV ON)(1) (continued)
Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 30

C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 35
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 44 MHz
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 55
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 77
11
C = 50 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 11.1
C = 40 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 9.2
Output high to low level
tr/tf(3)(4) fall time and output low C = 30 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 7.2 ns
to high level rise time
C = 20 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 5.4
C = 10 pF, 1.08 V ≤ VDDIO2 ≤ 1.32 V - 3.6
1. Specified by design - Not tested in production.
2. The maximum frequency is defined with the conditions: (tr+tf) ≤ 2/3 T, Skew ≤ 1/20 T, 45%<Duty cycle<55%.
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.

Table 66. Output timing characteristics for FT_c I/Os (PB13/PB14)(1)(2)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDDIO ≤ 3.6 V - 2

Fmax Maximum frequency MHz
C = 50 pF, 1.71 V ≤ VDDIO < 2.7 V - 1
00
C = 50 pF, 2.7 V ≤ VDDIO < 3.6 V - 166
tr/tf Output rise and fall time ns
C = 50 pF, 1.71 V ≤ VDDIO < 2.7 V - 330
C = 30 pF, 2.7 V ≤ VDDIO < 3.6 V - 10
Frmax Maximum frequency MHz
C = 30 pF, 1.71 V ≤ VDDIO < 2.7 V - 4
01
C = 30 pF, 2.7 V ≤ VDDIO < 3.6 V - 33
tr/tf Output rise and fall time ns
C = 30 pF, 1.71 V ≤ VDDIO < 2.7 V - 65
1. Specified by design - Not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of
GPIO port configuration register.

5.3.15 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 57).
Unless otherwise specified, the parameters in Table 67 are derived from tests performed
under the ambient temperature and VDD supply voltage conditions summarized in Table 20.

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Table 67. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

RPU(2) Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ

(2)
VF(NRST) NRST input filtered pulse 1.71 V < VDD < 3.6 V - - 50
ns
(2)
VNF(NRST) NRST input not filtered pulse 1.71 V < VDD < 3.6 V 350 - -
1. The pull-up is designed with a true resistance in series with a switchable PMOS. The PMOS contribution to
the series resistance is minimum (~10 % order).
2. Specified by design - Not tested in production.

Figure 21. Recommended NRST pin protection

VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter

0.1 μF

STM32

ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 57, otherwise the reset is not taken into account by the device.

5.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length to ensure its detection by the
event controller.

Table 68. EXTI input characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLEC Pulse length to event controller - 20 - - ns

1. Specified by design - Not tested in production.

5.3.17 FMC characteristics

Unless otherwise specified, the parameters given in tables 69 to 82 are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0

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Refer to Section 5.3.14 for more details on the input/output alternate function
characteristics.

Asynchronous waveforms and timings

Figures 22 through 24 represent asynchronous waveforms, tables 69 through 76 provide
the corresponding timings. The results shown in these tables are obtained with the following
FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• DataHoldTime(DATAHLD) = 0x1 (1 Tfmc_ker_ck for read operations and 2
Tfmc_ker_ck for write operations)
• ByteLaneSetup(NBLSET)=0x1
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, the Tfmc_ker_ck is the fHCLK clock period.

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Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)

FMC_NE

tv(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

tv(A_NE) t h(A_NOE)

FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)

FMC_NBL[1:0]

t h(Data_NE)

t su(Data_NOE) th(Data_NOE)

t su(Data_NE)

FMC_D[15:0] Data

t v(NADV_NE)

tw(NADV)

FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32753V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

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Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 Tfmc_ker_ck - 1 3 Tfmc_ker_ck + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2 Tfmc_ker_ck - 1 2 Tfmc_ker_ck + 1
FMC_NOE high to FMC_NE high hold
th(NE_NOE) Tfmc_ker_ck - 0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 1
th(A_NOE) Address hold time after FMC_NOE high 2 Tfmc_ker_ck - 1.5 - ns
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck + 11.5 -
tsu(Data_NOE) Data to FMC_NOEx high setup time 11.5 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1
1. Evaluated by characterization - Not tested in production.

Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT

timings(1)(2)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 Tfmc_ker_ck - 1 8 Tfmc_ker_ck + 1

tw(NOE) FMC_NOE low time 7 Tfmc_ker_ck - 1 7 Tfmc_ker_ck + 1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck -
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 Tfmc_ker_ck + 10 -
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4 Tfmc_ker_ck +10 -
invalid
1. Evaluated by characterization - Not tested in production.
2. NWAIT pulse width is equal to one fmc_ker_ck cycle.

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Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)

FMC_NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)

FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)

FMC_D[15:0] Data
t v(NADV_NE)

tw(NADV)
FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32754V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3 Tfmc_ker_ck - 1 3 Tfmc_ker_ck + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 1 Tfmc_ker_ck+ 0.5
tw(NWE) FMC_NWE low time Tfmc_ker_ck - 1 Tfmc_ker_ck +1
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck - 1 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck -1 -
ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck -1 -
tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck + 1
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1
1. Evaluated by characterization - Not tested in production.

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Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT

timings(1)(2)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8 Tfmc_ker_ck - 1 8 Tfmc_ker_ck+ 1

tw(NWE) FMC_NWE low time 6 Tfmc_ker_ck - 1 6 Tfmc_ker_ck+ 1
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 Tfmc_ker_ck + 10 - ns

FMC_NEx hold time after FMC_NWAIT

th(NE_NWAIT) 4 Tfmc_ker_ck + 10 -
invalid
1. Evaluated by characterization - Not tested in production.
2. NWAIT pulse width is equal to one fmc_ker_ck cycle.

Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)

FMC_ NE
tv(NOE_NE) t h(NE_NOE)

FMC_NOE

t w(NOE)

FMC_NWE

tv(A_NE) th(A_NOE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)
tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32755V1

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Table 73. Asynchronous multiplexed PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4 Tfmc_ker_ck - 1 4 Tfmc_ker_ck + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2 Tfmc_ker_ck - 1 2 Tfmc_ker_ck +0.5
ttw(NOE) FMC_NOE low time Tfmc_ker_ck - 1 Tfmc_ker_ck+ 1
FMC_NOE high to FMC_NE high hold
th(NE_NOE) Tfmc_ker_ck - 0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 3
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 0.5 Tfmc_ker_ck + 1 ns
FMC_AD(address) valid hold time after
th(AD_NADV) Tfmc_ker_ck + 0.5 -
FMC_NADV high
th(A_NOE) Address hold time after FMC_NOE high 2 Tfmc_ker_ck - 0.5 -
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck +11.5 -
tsu(Data_NOE) Data to FMC_NOE high setup time 11.5 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. Evaluated by characterization - Not tested in production.

Table 74. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) (2)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9 Tfmc_ker_ck - 1 9 Tfmc_ker_ck + 1

tw(NOE) FMC_NOE low time 6 Tfmc_ker_ck - 1 6 Tfmc_ker_ck + 1
FMC_NWAIT valid before FMC_NEx ns
tsu(NWAIT_NE) 5 Tfmc_ker_ck +10 -
high
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4 Tfmc_ker_ck +10 -
invalid
1. Evaluated by characterization - Not tested in production.
2. NWAIT pulse width is equal to one fmc_ker_ck cycle.

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Table 75. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4 Tfmc_ker_ck -1 4 Tfmc_ker_ck +1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 1 Tfmc_ker_ck +0.5
tw(NWE) FMC_NWE low time 2 Tfmc_ker_ck - 1 2 Tfmc_ker_ck + 1
FMC_NWE high to FMC_NE high hold
th(NE_NWE) Tfmc_ker_ck - 0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 3
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 1 Tfmc_ker_ck + 1 ns
FMC_AD(adress) valid hold time after
th(AD_NADV) Tfmc_ker_ck - 1 -
FMC_NADV high
th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck - 1 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck - 1 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) Data hold time after FMC_NEx high - Tfmc_ker_ck + 0.5
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck - 0.5 -
1. Evaluated by characterization - Not tested in production.

Table 76. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9 Tfmc_ker_ck - 1 9 Tfmc_ker_ck + 1

tw(NWE) FMC_NWE low time 7 Tfmc_ker_ck -1 7 Tfmc_ker_ck + 1
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 Tfmc_ker_ck + 10 - ns

FMC_NEx hold time after FMC_NWAIT

th(NE_NWAIT) 4 Tfmc_ker_ck + 10 -
invalid
1. Evaluated by characterization - Not tested in production.
2. NWAIT pulse width is equal to one fmc_ker_ck cycle.

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Synchronous waveforms and timings

Figures 25 through 28 represent synchronous waveforms, tables 77 through 80 provide the
corresponding timings. The results shown in these tables are obtained with the following
FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash, DataLatency = 0 for PSRAM.
• With capacity load CL = 30 pF
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
• For 2.7 V < VDD < 3.6 V: maximum FMC_CLK = 100 MHz at CL = 20 pF
• For 1.71 V < VDD < 1.8 V: maximum FMC_CLK = 95 MHz at CL = 20 pF
• For 1.71 V < VDD < 1.8 V: maximum FMC_CLK = 100 MHz at CL = 15 pF

Figure 25. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)

FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32757V1

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Table 77. Synchronous multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2Tfmc_ker_ck - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 1
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x = 0…2) Tfmc_ker_ck - 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16…25) Tfmc_ker_ck- 0.5 -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1 ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck + 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 1 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3.5 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 1.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
1. Evaluated by characterization - Not tested in production.

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Figure 26. Synchronous multiplexed PSRAM write timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)

FMC_AD[15:0] AD[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

td(CLKH-NBLH)

FMC_NBL

MS32758V1

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Table 78. Synchronous multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2Tfmc_ker_ck - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 1
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0…2) Tfmc_ker_ck - 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16…25) Tfmc_ker_ck - 0.5 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1
ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck + 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 1 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 1
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck-0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
1. Evaluated by characterization - Not tested in production.

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Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK)

FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)

FMC_D[15:0] D1 D2

tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

Table 79. Synchronous non-multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 -

t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 1
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0…2) Tfmc_ker_ck- 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16…25) Tfmc_ker_ck- 0.5 - ns
td(CLKL-NOEL) FMC_CLK ow to FMC_NOE low - 1
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck + 0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 3.5 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1.5 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -
1. Evaluated by characterization - Not tested in production.

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Figure 28. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)

FMC_CLK

td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx

td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE

td(CLKL-Data) td(CLKL-Data)

FMC_D[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL

MS32760V1

Table 80. Synchronous non-multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

t(CLK) FMC_CLK period 2Tfmc_ker_ck - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 1
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0…2) Tfmc_ker_ck - 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16…25) Tfmc_ker_ck - 0.5 -
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck+ 0.5 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 1.5
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck - 0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -

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1. Evaluated by characterization - Not tested in production.

NAND controller waveforms and timings

Figures 29 through 32 represent synchronous waveforms, tables 81 and 82 provide the
corresponding timings. The results are obtained with the following FMC configuration and a
capacitive load (CL) of 30 pF:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
• Capacitive load CL = 30 pF
In all timing tables, Tfmc_ker_ck is the HCLK clock period.

Figure 29. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)

FMC_NOE (NRE)

tsu(D-NOE) th(NOE-D)

FMC_D[y:0]

MSv73150V1

1. y = 7 or 15, depending upon the NAND flash memory interface.

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Figure 30. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) tw(NWE) th(NWE-ALE)

FMC_NWE

FMC_NOE (NRE)

td(D-NWE)

tv(NWE-D) th(NWE-D)

FMC_D[y:0]

MSv73151V1

1. y = 7 or 15, depending upon the NAND flash memory interface.

Figure 31. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)
FMC_NOE

tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32769V1

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Figure 32. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)

FMC_NWE

FMC_N OE

td(D-NWE)

tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32770V1

Table 81. Switching characteristics for NAND flash read cycles(1)

Symbol Parameter Min Max Unit

tw(N0E) FMC_NOE low width 4Tfmc_ker_ck - 0.5 4Tfmc_ker_ck+ 0.5

FMC_D[15-0] valid data before
tsu(D-NOE) 12 -
FMC_NOE high
FMC_D[15-0] valid data after ns
th(NOE-D) 0 -
FMC_NOE high
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck + 0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 2Tfmc_ker_ck - 1 -
1. Evaluated by characterization - Not tested in production.

Table 82. Switching characteristics for NAND flash write cycles(1)

Symbol Parameter Min Max Unit

tw(NWE) FMC_NWE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck + 0.5

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2Tfmc_ker_ck + 0.5 -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5Tfmc_ker_ck - 2.5 -
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3Tfmc_ker_ck + 0.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2Tfmc_ker_ck - 1 -
1. Evaluated by characterization - Not tested in production.

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5.3.18 Octo-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 83 and Table 84 are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0
Refer to Section 5.3.14 for more details on the input/output alternate function
characteristics.

Table 83. OCTOSPI characteristics in SDR mode(1)(2)(3)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V < VDD < 3.6 V,

- - 110
OCTOSPI clock CL = 15 pF
F(CLK) MHz
frequency 2.7 V < VDD < 3.6 V,
- - 150
CL =15 pF
tw(CLKH) OCTOSPI clock high and PRESCALER[7:0] = n t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
t low time, even division (= 0, 1, 3, 5,...,255) t(CLK)/2 - 0.5 - t(CK)/2 + 0.5
w(CLKL)

(n/2) * t(CLK) / (n/2) * t(CLK)/

tw(CLKH) -
OCTOSPI clock high and PRESCALER[7:0] = n (n + 1) - 0.5 (n + 1) + 0.5
low time, odd division (= 2, 4, 6, ...,254) (n/2 + 1) * t(CLK)/ (n/2 + 1) * t(CLK)/
tw(CLKL) - ns
(n + 1) - 0.5 (n + 1) + 0.5
ts(IN) Data input setup time - 4 - -
th(IN) Data input hold time - 1 - -
tv(OUT) Data output valid time - - 0.5 1
th(OUT) Data output hold time - 0 - -
1. All values apply to Octal and Quad-SPI mode.
2. Evaluated by characterization - Not tested in production.
3. Delay block bypassed.

Figure 33. OCTOSPI SDR read/write timing diagram

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V3

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Table 84. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V < VDD < 3.6 V,

- - 100(4)
OCTOSPI clock CL = 15 pF
FCLK MHz
frequency 2.7 V < VDD < 3.6 V,
- - 125(4)
CL = 15 pF
tw(CLKH) OCTOSPI clock PRESCALER[7:0] = n t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
ns
tw(CLKL) high and low time (= 0, 1, 3, 5, ..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
(n/2) * t(CLK)/ (n/2) * t(CLK)/
tw(CLKH) -
OCTOSPI clock PRESCALER[7:0] = n (n + 1) - 0.5 (n + 1) + 0.5
ns
high and low time (= 2, 4, 6, 8, ...254) (n/2 + 1) * t(CLK)/ (n/2 + 1) * t(CLK)/
tw(CLKL) -
(n + 1) - 0.5 (n + 1) + 0.5
tsr(IN),
Data input setup time - 4 - -
tsf(IN)
thr(IN),
Data input hold time - 1.5 - -
thf(IN)
DHQC = 0 - 2.5 3.5
tvr(OUT) ns
Data output valid time DHQC = 1, t(CLK)/4 +
tvf(OUT) - t(CLK)/4 + 1
Prescaler [7:0] = 1, 2... 0.5
DHQC = 0 1.5 - -
thr(OUT)
Data output hold time DHQC = 1,
thf(OUT) t(CLK)/4 - 1 - -
Prescaler [7:0] = 1, 2...
1. All values apply to Octal and Quad-SPI mode.
2. Evaluated by characterization - Not tested in production.
3. Delay block bypassed.
4. DHQC must be set to reach the mentioned frequency.

Table 85. OCTOSPI characteristics in DTR mode (with DQS) / hyperbus(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V < VDD < 3.6 V,

- - 125(3)(4)
CL = 15 pF
FCLK OCTOSPI clock frequency MHz
2.7 V < VDD < 3.6 V,
- - 125(3)(5)
CL = 15 pF
tw(CLKH) OCTOSPI clock PRESCALER[7:0] = n t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
t high and low time = (0, 1, 3, 5, ..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
w(CLKL)

(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) -
OCTOSPI clock PRESCALER[7:0] = n (n+1) - 0.5 (n+1) + 0.5
ns
high and low time = (2, 4, 6, 8, ...254) (n/2+1)*t(CLK)/ (n/2+1)*t(CLK)/
tw(CLKL) -
(n+1) - 0.5 (n+1) + 0.5
tv(CLK) Clock valid time - - - t(CLK) + 2
th(CLK) Clock hold time - t(CLK)/2 - 1 - -

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Table 85. OCTOSPI characteristics in DTR mode (with DQS) / hyperbus(1)(2) (continued)
Symbol Parameter Conditions Min Typ Max Unit

VODr(CLK CLK, NCLK crossing level on

(5) VDD = 1.8 V 1000 - 1080
) CLK rising edge
VODf(CLK mV
CLK, NCLK crossing level on
) VDD = 1.8 V 930 - 1040
(5) CLK falling edge

tw(CS) Chip select high time - 3 * t(CLK) - -

tv(DQ) Data input valid time - 3 - -
tv(DS) Data strobe input valid time - 1 - - ns
th(DS) Data strobe input hold time - 0 - -
tv(RWDS) Data strobe output valid time - - - 3 * t(CLK)
tsr(DQ),
Data input setup time - -0.5 - -
tsf(DQ)
thr(DQ),
Data input hold time - 2 - -
thf(DQ)
DHQC = 0 - 2.5 3.5
tvr(OUT) ns
Data output valid time DHQC = 1, all prescaler t(CLK)/4
tvf(OUT) - t(CLK)/4 + 1
values (except 0) + 0.5
DHQC = 0 1.5 - -
thr(OUT)
Data output hold time DHQC = 1, all prescaler
thf(OUT) t(CLK)/4 - 1 - -
values (except 0)
1. Evaluated by characterization - Not tested in production.
2. Delay block activated.
3. Maximum frequency value are given for a maximum RWDS to DQ skew of ± 1.0 ns.
4. DHQC must be set to reach the mentioned frequency.
5. PF10/PB5, PB4/PB5 and PA3/PB5 are recommended to be in line with crossing specification.

Figure 34. OCTOSPI timing diagram - DTR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output D0 D1 D2 D3 D4 D5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input D0 D1 D2 D3 D4 D5

MSv36879V4

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Figure 35. OCTOSPI hyperbus clock

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

tf(NCLK) t(NCLK) tw(NCLKL) tw(NCLKH) tr(NCLK)

NCLK

VOD(CLK)
CLK
MSv47732V3

Figure 36. OCTOSPI hyperbus read

tw(CS)

NCS

tv(CLK) t ACC= Initial access th(CLK)

CLK, NCLK

tv(RWDS) tv(DS) th(DS)

RWDS

tv(OUT) th(OUT) Latency count tv(DQ) ts(DQ) th(DQ)

47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

DQ[7:0] A B A B

Command address
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS. MSv47733V3

Figure 37. OCTOSPI hyperbus write

tw(CS)

NCS

Read write recovery Access latency

tv(CLK) th(CLK)

CLK, NCLK

tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

Low = 1x latency count
RWDS

Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)

Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B

Command address Host drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS.
MSv47734V3

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5.3.19 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 86 are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 20, with the following configuration:

Table 86. Delay block characteristics

Symbol Parameter Conditions Min Typ Max Unit

tinit Initial delay - 640 1040 1760 ps

t∆ Unit delay - 38 44 54 ps

5.3.20 DCMI interface characteristics

Unless otherwise specified, the parameters given in Table 87 are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 20, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load CL = 30 pF
• Measurement points done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling VOS0 selected

Table 87. DCMI characteristics(1)

Symbol Parameter Min Max Unit

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel clock input - 100 MHz
DPIXEL Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 2.5 -
th(DATA) Data hold time 2 -
ns
tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC and DCMI_VSYNC input setup times 2.5 -
th(HSYNC), th(VSYNC) DCMI_HSYNC and DCMI_VSYNC input hold times 1.5 -
1. Evaluated by characterization - Not tested in production.

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Figure 38. DCMI timing diagrams

1/DCMI_PIXCLK

DCMI_PIXCLK

tsu(HSYNC) th(HSYNC)

DCMI_HSYNC

tsu(VSYNC) th(HSYNC)

DCMI_VSYNC
tsu(DATA) th(DATA)

DATA[0:13]

MS32414V2

5.3.21 PSSI interface characteristics

Unless otherwise specified, the parameters given in Table 87 and Table 88 are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 20 and Section 5.3.1, with the following configuration:
• PSSI_PDCK polarity: falling
• PSSI_RDY and PSSI_DE polarity: low
• Bus width: 16 lines
• DATA width: 32 bits
• Capacitive load CL= 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling VOS0 selected

Table 88. PSSI transmit characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio PSSI_PDCK/fHCLK - - 0.4 -

2.7 V ≤ VDD ≤ 3.6 V - 90(2)
PSSI_PDCK PSSI clock input MHz
1.71 V ≤ VDD ≤ 3.6 V - 86
Dpixel PSSI clock input duty cycle 30 70 %

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Table 88. PSSI transmit characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

2.7 V ≤ VDD ≤ 3.6 V - 11

tov(DATA) Data output valid time
1.71 V ≤ VDD ≤ 3.6 V - 11.5
toh(DATA) Data output hold time 5.5 -
tov((DE) DE output valid time - 11.5 ns
toh(DE) DE output hold time 1.71 V ≤ VDD ≤ 3.6 V 5.5 -
tsu(RDY) RDY input setup time 0.5 -
th(RDY) RDY input hold time 0.5 -
1. Evaluated by characterization - Not tested in production.
2. This maximal frequency does not consider receiver setup and hold timings.

Table 89. PSSI receive characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio PSSI_PDCK/fHCLK - 0.4 -

PSSI_PDCK PSSI clock input 1.71 V ≤ VDD ≤ 3.6 V - 100 MHz
Dpixel PSSI clock input duty cycle - 30 70 %
tsu(DATA) Data input setup time 2.5 -
th(DATA) Data input hold time 2.5 -
tsu((DE) DE input setup time 1.5 -
1.71 V ≤ VDD ≤ 3.6 V ns
th(DE) DE input hold time 2 -
tov(RDY) RDY output valid time - 16.5
toh(RDY) RDY output hold time 5.5 -
1. Evaluated by characterization - Not tested in production.

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Figure 39. PSSI transmit timing diagram

tc(PDCK)
tw(PDCKH) tw(PDCKL)
tf(PDCK) tr(PDCK)
PSSI_PDCK
(input) CKPOL = 0

CKPOL = 1

tov(DATA) toh(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)
PSSI_DE
(output)

DEPOL = 0
tov(DE) toh(DE)

DEPOL = 1
PSSI_RDY

RDYPOL = 0
(input)

tsu(RDY) th(RDY)

RDYPOL = 1
MSv65388V1

Figure 40. PSSI receive timing diagram

tc(PDCK)
tw(PDCKH) tw(PDCKL)
tf(PDCK) tr(PDCK)
PSSI_PDCK

CKPOL = 0
(input)

CKPOL = 1

tsu(DATA)
thDATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
tsu(DE)
th(DE)
PSSI_DE

DEPOL = 0
(output)

DEPOL = 1
tov(RDY) toh(RDY)
PSSI_RDY

RDYPOL = 0
(input)

RDYPOL = 1
MSv65389V1

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5.3.22 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 90 are derived from tests
performed under the ambient temperature, fHCLK frequency and VDDA supply voltage
conditions summarized in Table 20.

Table 90. 12-bit ADC characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog
supply
VDDA - 1.62 - 3.6 V
voltage for
ADC ON

Positive
VREF+ reference - 1.62 - VDDA
voltage
V
Negative
VREF- reference - VSSA
voltage

ADC clock
fADC 1.62V ≤ VDDA ≤ 3.6 V 1.5 - 75 MHz
frequency

fADC=
1.8V ≤ VDDA≤3.6V - 5.00 -
75 MHz
Continuous
mode
fADC=
1.6V ≤ VDDA≤3.6V 4.66
70 MHz
Resolution SMP
-40°C ≤ TJ ≤ 130°C
= 12 bits =2.5
fADC=
2.4V ≤ VDDA≤3.6V 4.00 -
Single or 60 MHz
Discontinuous
mode fADC=
1.6V ≤ VDDA≤3.6V 3.33 -
50MHz

Sampling
rate for fast Continuous fADC=
1.6V ≤ VDDA≤3.6V - 5.77 -
channels mode 75 MHz
(VIN[0:5])
Resolution fADC= SMP
2.4V ≤ VDDA≤3.6V -40°C ≤ TJ ≤ 130°C 5.77 -
= 10 bits Single or 75 MHz =2.5
Discontinuous
fS(3) with mode
RAIN = 47 Ω fADC=
1.6V ≤ VDDA≤3.6V 5.00 - MSPS
and 65 MHz
CPCB = 22 pF
Resolution fADC=
All modes 1.6V ≤ VDDA≤3.6V -40°C ≤ TJ ≤ 130°C - 6.82 -
= 8 bits 75 MHz
SMP
=2.5
Resolution fADC=
All modes 1.6V ≤ VDDA≤3.6V -40°C ≤ TJ ≤ 130°C - 8.33 -
= 6 bits 75 MHz

Resolution fADC=
- 2.30 -
= 12 bits 35 MHz

Resolution fADC=
- 2.70 -
Sampling = 10 bits 35 MHz
SMP
rate for slow All modes(4) 1.6V ≤ VDDA≤3.6V -40°C ≤ TJ ≤ 130°C
=2.5
channels Resolution fADC=
- 4.50 -
= 8 bits 50 MHz

Resolution fADC=
- 5.50 -
= 6 bits 50 MHz

External
tTRIG Resolution = 12 bits - - 15 1/fADC
trigger period

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Table 90. 12-bit ADC characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Conversion
VAIN(2) voltage - 0 - VREF+
range
V
Common
VREF/2− VREF/2+
VCMIV mode input - VREF/2
10% 10%
voltage

Resolution = 12 bits, TJ = 130°C (Tolerance 4 LSBs) - - 321

Resolution = 12 bits, TJ = 125°C - - 220

Resolution = 10 bits, TJ = 130°C - - 1039

External Resolution = 10 bits, TJ = 125°C - - 2100

RAIN(5) input Ω
impedance Resolution = 8 bits, TJ = 130°C - - 6327

Resolution = 8 bits, TJ = 125°C - - 12000

Resolution = 6 bits, TJ = 130°C - - 47620

Resolution = 6 bits, TJ = 125°C - - 80000

Internal
sample and
CADC - - 3 - pF
hold
capacitor

tADCVREG_ ADC LDO

- - 5 10 µs
STUP startup time

ADC
conversion
tSTAB power-up LDO already started 1 - -
cycle
time

Offset
tOFF_CAL calibration - 1335
time

Trigger CKMODE = 00 1.5 2 2.5

conversion
latency for CKMODE = 01 - - 2.5
regular and
tLATR injected CKMODE = 10 2.5
channels
without
aborting the CKMODE = 11 2.25
conversion

Trigger CKMODE = 00 2.5 3 3.5

conversion
latency for CKMODE = 01 - - 3.5
regular and 1/fADC
injected CKMODE = 10 - - 3.5
tLATRINJ
channels
when a
regular
CKMODE = 11 - - 3.25
conversion is
aborted

Sampling
tS - 2.5 - 640.5
time

Total
conversion
time tS + 0.5
tCONV N-bits resolution
(including +N
sampling
time)

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Table 90. 12-bit ADC characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

ADC fs = 5 MSPS - 600 -

consumption
on fs = 1 MSPS - 190 -
IDDA_D(ADC) VDDA and
VREF,
Differential fs = 0.1 MSPS - 50 -
mode

ADC fs = 5 MSPS - 500 -

consumption
IDDA_SE(ADC) on VDDA and fs = 1 MSPS - 150 -
VREF Single-
ended mode fs = 0.1 MSPS - 50 - µA

fADC= 75 MHz - 265 -

fADC= 50 MHz 175 -

ADC fADC= 25 MHz - 90 -

IDD(ADC) consumption
on VDD fADC= 12.5 MHz - 45 -

fADC= 6.25 MHz - 22 -

fADC= 3.125 MHz - 11 -

1. Specified by design - Not tested in production.

2. The voltage booster on ADC switches must be used for VDDA < 2.7 V (embedded I/O switches).
3. These values are valid on UFBGA144 package.
4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
5. The tolerance is two LSBs for 12-bit, 10-bit and 8-bit resolutions, otherwise specified.

Table 91. Minimum sampling time versus RAIN(1)(2)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channel Slow channel(3)

47 3.75E-08 6.12E-08
68 3.94E-08 6.25E-08
100 4.36E-08 6.51E-08
150 5.11E-08 7.00E-08
12 bits
220 6.54E-08 7.86E-08
330 8.80E-08 9.57E-08
470 1.17E-07 1.23E-07
680 1.60E-07 1.65E-07

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Table 91. Minimum sampling time versus RAIN(1)(2) (continued)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channel Slow channel(3)

47 3.19E-08 5.17E-08
68 3.35E-08 5.28E-08
100 3.66E-08 5.45E-08
150 4.35E-08 5.83E-08
220 5.43E-08 6.50E-08
330 7.18E-08 7.89E-08
10 bits
470 9.46E-08 1.00E-07
680 1.28E-07 1.33E-07
1000 1.81E-07 1.83E-07
1500 2.63E-07 2.63E-07
2200 3.79E-07 3.76E-07
3300 5.57E-07 5.52E-07
47 2.64E-08 4.17E-08
68 2.76E-08 4.24E-08
100 3.02E-08 4.39E-08
150 3.51E-08 4.66E-08
220 4.27E-08 5.13E-08
330 5.52E-08 6.19E-08
470 7.17E-08 7.72E-08
680 9.68E-08 1.00E-07
8 bits
1000 1.34E-07 1.37E-07
1500 1.93E-07 1.94E-07
2200 2.76E-07 2.74E-07
3300 4.06E-07 4.01E-07
4700 5.73E-07 5.62E-07
6800 8.21E-07 7.99E-07
10000 1.20E-06 1.17E-06
15000 1.79E-06 1.74E-06

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Table 91. Minimum sampling time versus RAIN(1)(2) (continued)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channel Slow channel(3)

47 2.14E-08 3.16E-08
68 2.23E-08 3.21E-08
100 2.40E-08 3.31E-08
150 2.68E-08 3.52E-08
220 3.13E-08 3.87E-08
330 3.89E-08 4.51E-08
470 4.88E-08 5.39E-08
680 6.38E-08 6.79E-08
6 bits
1000 8.70E-08 8.97E-08
1500 1.23E-07 1.24E-07
2200 1.73E-07 1.73E-07
3300 2.53E-07 2.49E-07
4700 3.53E-07 3.45E-07
6800 5.04E-07 4.90E-07
10000 7.34E-07 7.11E-07
15000 1.09E-06 1.05E-06
1. Specified by design - Not tested in production.
2. Data valid up to 130 °C, with a 22 pF PCB capacitor, and VDDA = 1.6 V.
3. Slow channels correspond to all ADC inputs except for the fast channels.

Figure 41. ADC conversion timing diagram

CLK

Mux Sampling(1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1/2 SMP Number of CLK clock cycles = ADC resolution / 2

Total conversion time: 0.5 +Tsamp + N/2

1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details).

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Table 92. ADC accuracy(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Fast and Single ended - ±3.5 ±12

ET Total unadjusted error slow
channels Differential - ±2.5 ±7.5

- Single ended - ±3 ±5.5

EO Offset error
- Differential - ±2 ±3.5
- Single ended - ±3.5 ±11
EG Gain error LSB
- Differential ±2.5 ±7
- Single ended - ±0.75 +2/-1
ED Differential linearity error
- Differential - ±0.75 +2/-1
Fast and Single ended - ±2 ±6.5
EL Integral linearity error slow
channels Differential - ±1 ±4

Single ended - 10.8 -

ENOB Effective number of bits Bits
Differential - 11.5 -

Signal-to-noise and Single ended - 68 -

SINAD
distortion ratio Differential - 71 -
Single ended - 70 -
SNR Signal-to-noise ratio dB
Differential - 72 -
Single ended - -70 -
THD Total harmonic distortion
Differential - -80 -
1. Evaluated by characterization for BGA packages. The values for LQFP package can differ. Not tested in production.
2. ADC DC accuracy values are measured after internal calibration in continuous mode.

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins, which may potentially inject negative currents.

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Figure 42. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

1. Example of an actual transfer curve.

2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
5. EO = Offset error: deviation between the first actual transition and the first ideal one.
6. EG = Gain error: deviation between the last ideal transition and the last actual one.
7. ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
8. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.

Figure 43. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter

Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 90 for the values of RAIN, and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 57). A high Cparasitic value downgrades conversion accuracy. To remedy
this, fADC should be reduced.
3. Refer to Table 57 for the value of Ilkg.

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General PCB design guidelines

It is recommended to perform power supply decoupling as shown in Figure 44 or Figure 45,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors must be
ceramic (good quality), and placed as close as possible to the chip.

Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA)

STM32

VREF+(1)

1 μF // 100 nF
VDDA

1 μF // 100 nF

VSSA/VREF-(1)

MSv50648V2

1. VREF+ input is not available on all packages (refer to Table 15), VREF- is available only on LQFP100 and
UFBGA144 packages. When VREF+ is not available, it is internally connected to VSSA.

Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA)

STM32

VREF+/VDDA(1)

1 μF // 100 nF

VREF-/VSSA(1)

MSv50649V1

1. VREF+ input is not available on all packages (refer to Table 15), VREF- is available only on LQFP100 and
UFBGA144 packages. When VREF- is not available, it is internally connected to VSSA. If VREF- is not
available, it is connected internally to VDDA.

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5.3.23 DAC characteristics

Table 93. DAC characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.8 3.3 3.6

VREF+ Positive reference voltage - 1.80 - VDDA V
VREF- Negative reference voltage - - VSSA -
Connected
5 - -
DAC output buffer to VSSA
RL Resistive load
ON Connected kΩ
25 - -
to VDDA
RO Output impedance DAC output buffer OFF 10.3 13 16
Output impedance sample VDD = 2.7 V - - 1.6
DAC output buffer
RBON and hold mode, output kΩ
ON VDD = 2.0 V - - 2.6
buffer ON
Output impedance sample VDD = 2.7 V - - 17.8
DAC output buffer
RBOFF and hold mode, output kΩ
OFF VDD = 2.0 V - - 18.7
buffer OFF
CL DAC output buffer OFF - - 50 pF
Capacitive load
CSH Sample and Hold mode - 0.1 1 µF
VDDA
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT −0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 2.05 3
Settling time (full scale: for
a 12-bit code transition Normal mode, DAC ±1 LSB - 1.97 2.87
between the lowest and output buffer ON,
±2 LSB - 1.67 2.84
the highest input codes CL ≤ 50 pF,
tSETTLING RL ≥ 5 ㏀ ±4 LSB - 1.66 2.78 µs
when DAC_OUT reaches
the final value of ±0.5LSB, ±8 LSB - 1.65 2.7
±1LSB, ±2LSB, ±4LSB,
±8LSB) Normal mode, DAC output buffer
- 1.7 2
OFF, ±1LSB CL= 10 pF
Wake-up time from off Normal mode, DAC output buffer
- 5 7.5
state (setting the ENx bit in ON, CL ≤ 50 pF, RL = 5 kΩ
tWAKEUP(2) the DAC control register) µs
until the final value of Normal mode, DAC output buffer
- 2 5
±1LSB is reached OFF, CL ≤ 10 pF

DC VDDA supply rejection Normal mode, DAC output buffer

PSRR - -80 -28 dB
ratio ON, CL ≤ 50 pF, RL = 5 kΩ

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Table 93. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Sampling time in Sample MODE<2:0>_V12 = 100/101

- 0.7 2.6
and Hold mode (BUFFER ON)
CL= 100 nF ms
MODE<2:0>_V12 = 110
(code transition between - 11.5 18.7
tSAMP (BUFFER OFF)
the lowest and the highest
input code when
MODE<2:0>_V12=111(3)
DAC_OUT reaches the - 0.3 0.6 µs
(INTERNAL BUFFER OFF)
±1LSB final value)
Ileak (4)
Output leakage current - - - nA
Internal sample and hold
CIint - 1.8 2.2 2.6 pF
capacitor
Middle code offset trim
tTRIM Minimum time to verify each code 50 - - µs
time

Middle code offset for VREF+ = 3.6 V - 850 -

Voffset µV
1 trim code step VREF+ = 1.8 V - 425 -
No load,
middle code - 360 -
DAC output buffer (0x800)
ON No load,
worst code - 490 -
DAC quiescent (0xF1C)
IDDA(DAC) µA
consumption from VDDA No load,
DAC output buffer middle/
- 20 -
OFF worst code
(0x800)
Sample and Hold mode, 360*TON/
- -
CSH= 100 nF (TON+TOFF)(5)
No load,
middle code - 170 -
DAC output buffer (0x800)
ON No load,
worst code - 170 -
(0xF1C)
DAC consumption from No load,
IDDV(DAC) µA
VREF+ DAC output buffer middle/
- 160 -
OFF worst code
(0x800)
Sample and Hold mode, buffer ON, 170*TON/
- -
CSH= 100 nF (worst code) (TON+TOFF)(5)
Sample and Hold mode, buffer 160*TON/
- -
OFF, CSH= 100 nF (worst code) (TON+TOFF)(5)
1. Specified by design - Not tested in production, unless otherwise specified.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
3. DACx_OUT pin is not connected externally (internal connection only).
4. Refer to Table 57.

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5. TON is the refresh phase duration, TOFF is the hold phase duration. Refer to the reference manual for more details.

Table 94. DAC accuracy(1)

Symbol Parameter Conditions Min Typ Max Unit

Differential non DAC output buffer ON −2 - 2

DNL LSB
linearity(2) DAC output buffer OFF −2 - 2
- Monotonicity 10 bits - - - -
DAC output buffer ON,
−4 - 4
CL ≤ 50 pF, RL ≥ 5 kΩ
INL Integral non linearity(3)
DAC output buffer OFF,
−4 - 4
CL ≤ 50 pF, no RL

DAC output buffer ON, VREF+ = 3.6 V - - ±12

Offset error at code CL ≤ 50 pF, RL ≥ 5 kΩ VREF+ = 1.8 V - - ±25
Offset
0x800 (3) LSB
DAC output buffer OFF,
- - ±8
CL ≤ 50 pF, no RL
Offset error at code DAC output buffer OFF,
Offset1 - - ±5
0x001(4) CL ≤ 50 pF, no RL
Offset error at code VREF+ = 3.6 V - - ±5
DAC output buffer ON,
OffsetCal 0x800 after factory
CL≤50 pF, RL ≥5 kΩ VREF+ = 1.8 V - - ±7
calibration
DAC output buffer ON,
- - ±1
CL ≤ 50 pF, RL ≥ 5 kΩ
Gain Gain error(5) %
DAC output buffer OFF,
- - ±1
CL ≤ 50 pF, no RL
DAC output buffer ON,
- - ±30
CL ≤ 50 pF, RL ≥ 5 kΩ
TUE Total unadjusted error
DAC output buffer OFF,
±12 LSB
CL ≤ 50 pF, no RL
Total unadjusted error DAC output buffer ON,
TUECal - - ±23
after calibration CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON, CL ≤ 50 pF, RL ≥
- 67.8 -
5 kΩ, 1 kHz, BW = 500 kHz
SNR Signal-to-noise ratio(6)
DAC output buffer OFF, CL ≤ 50 pF, no
- 67.8 -
RL,1 kHz, BW = 500 kHz
DAC output buffer ON,
- −78.6 -
Total harmonic CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
THD dB
distortion(6) DAC output buffer OFF,
- −78.6 -
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON,
- 67.5 -
Signal-to-noise and CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
SINAD
distortion ratio(6) DAC output buffer OFF,
- 67.5 -
CL ≤ 50 pF, no RL, 1 kHz

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Table 94. DAC accuracy(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit
DAC output buffer ON,
- 10.9 -
Effective number of CL≤50 pF, RL ≥ 5 kΩ, 1 kHz
ENOB bits
bits DAC output buffer OFF,
- 10.9 -
CL ≤ 50 pF, no RL, 1 kHz
1. Evaluated by characterization - Not tested in production.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5 dBFS with Fsampling = 1 MHz.

Figure 46. 12-bit buffered/non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)
RL

12-bit DAC_OUTx
digital to
analog
converter
CL

ai17157V3

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly, without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.

5.3.24 Analog temperature sensor characteristics

Table 95. Analog temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

VSENSE linearity with temperature (from VSENSOR voltage) - - 3

TL(1) °C
VSENSE linearity with temperature (from ADC counter) - - 3
Average slope (from VSENSOR voltage) - 2 -
Avg_Slope(2) mV/°C
Average slope (from ADC counter) - 2 -
V30(3) Voltage at 30 °C ± 5 °C - 0.62 - V
tstart_run Startup time in Run mode (buffer startup) - - 25.2
µs
(1)
tS_temp ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5

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1. Specified by design - Not tested in production.

2. Evaluated by characterization - Not tested in production.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 bytes.

Table 96. Temperature sensor calibration values

Symbol Parameter Memory address

Temperature sensor raw data acquired value at 30 °C,

TS_CAL1 0x08FF F814 -0x08FF F815
VDDA = 3.3 V
Temperature sensor raw data acquired value at 130 °C,
TS_CAL2 0x08FF F818 - 0x08FF F819
VDDA = 3.3 V

5.3.25 Digital temperature sensor characteristics

Table 97. Digital temperature sensor characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fDTS(2) Output clock frequency - 500 750 1150 kHz

TLC(2) Temperature linearity coefficient VOS2 1660 2100 2750 Hz/°C

Temperature offset TJ = −40 to 30 °C -13 - 4

TTOTAL_ERROR(2) °C
measurement, all VOS TJ = 30 °C to TJmax -7 - 2
VOS2 0 - 0
Additional error due to supply
TVDD_CORE VOS0, VOS1, °C
variation -1 - 1
VOS3
tTRIM Calibration time - - - 2 ms
Wake-up time from off state
tWAKE_UP - - 67 116 μs
until DTS ready bit is set
IDDCORE_DTS DTS consumption on VDD_CORE - 8.5 30 70 μA
1. Specified by design - Not tested in production, unless otherwise specified.
2. Evaluated by characterization - Not tested in production.

5.3.26 VCORE monitoring characteristics

Table 98. VCORE monitoring characteristics(1)

Symbol Parameter Min Typ Max Unit

TS_VCORE ADC sampling time when reading the VCORE voltage 1 - - μs

1. Specified by design - Not tested in production.

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5.3.27 Temperature and VBAT monitoring

Table 99. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 4 x 26 - kΩ

Q Ratio on VBAT measurement - 4 - -
(1)
Er Error on Q -10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring 3.50 3.575 3.63
V
VBATlow Low supply monitoring - 1.36 -
IVBATbuf Sensor buffer consumption - 3.8 6.5 µA
1. Specified by design - Not tested in production.

Table 100. VBAT charging characteristics

Symbol Parameter Condition Min Typ Max Unit

VBRS in PWR_CR3 = 0 - 5 -
RBC Battery charging resistor kΩ
VBRS in PWR_CR3 = 1 - 1.5 -

Table 101. Temperature monitoring characteristics

Symbol Parameter Min Typ Max Unit

TEMPhigh High temperature monitoring - 126 -

°C
TEMPlow Low temperature monitoring - -37 -

5.3.28 Voltage booster for analog switch

Table 102. Voltage booster for analog switch characteristics(1)

Symbol Parameter Condition Min Typ Max Unit

VDD Supply voltage - 1.71 2.6 3.6 V

tSU(BOOST) Booster startup time - - - 50 µs
1.71 V ≤ VDD ≤ 2.7 V - - 125
IDD(BOOST) Booster consumption µA
2.7 V < VDD < 3.6 V - - 250
1. Evaluated by characterization - Not tested in production.

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5.3.29 VREFBUF characteristics

Table 103. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VRS = 000 2.8 3.3 3.6

Normal mode at
VRS = 001 2.4 - 3.6
VDDA = 3.3 V
Analog supply VRS = 010 2.1 - 3.6
VDDA V
voltage VRS = 000 1.62 - 2.80
Degraded mode(2) VRS = 001 1.62 - 2.40
VRS = 010 1.62 - 2.10
VRS = 000 2.498(3) 2.5000 2.5035(3)
Normal mode at
VRS = 001 2.0460 2.0490 2.0520
30 °C, ILOAD = 100 µA
VREFBUF_ Voltage reference VRS = 010 1.8010 1.8040 1.8060
V
OUT buffer output VRS = 000 VDDA − 150 mV - 2.5035
Degraded mode(2) VRS = 001 VDDA − 150 mV - 2.0520
VRS = 010 VDDA − 150 mV - 1.8060
Trim step
TRIM - - - ±0.05 ±0.1 %
resolution

CL Load capacitor - - 0.5 1 1.50 uF

Equivalent serial
esr - - - - 2 Ω
resistor of CL
Iload Static load current - - - - 4 mA

Iload = 500 µA - 200 -

ppm/
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V
V
Iload = 4 mA - 100 -

ppm/
Iload_reg Load regulation 500 µA ≤ Iload ≤ 4 mA Normal mode - 50 -
mA

Temperature ppm/
Tcoeff -40 °C < TJ < +130 °C - - - 100
coefficient °C

Power supply DC - - 60 -
PSRR dB
rejection 100 kHz - - 40 -
CL= 0.5 µF - - 300 -
tSTART Start-up time CL= 1 µF - - 500 - µs
CL= 1.5 µF - - 650 -

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Table 103. VREFBUF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Control of
maximum DC
current drive on
IINRUSH - - 8 - mA
VREFBUF_OUT
during startup
phase(4)(4)

ILOAD = 0 µA - - 15 25
VREFBUF
IDDA(VREF
consumption from ILOAD = 500 µA - - 16 30 µA
BUF) VDDA
ILOAD = 4 mA - - 32 50

1. Specified by design - Not tested in production, unless otherwise specified.

2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. Evaluated by characterization - Not tested in production.
4. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 2.1 V - 3.6 V, 2.4 V -3.6 V and 2.8 V - 3.6 V for VRS = 010, 001, and 000, respectively.

5.3.30 Timer characteristics

The parameters given in Table 104 are guaranteed by design.
Refer to Section 5.3.14 for details on the input/output alternate function characteristics
(output compare, input capture, external clock, PWM output).

Table 104. TIMx characteristics(1)(2)

Symbol Parameter Conditions(3) Min Max Unit

AHB/APBx prescaler = 1, 2, or 4,
1 - tTIMxCLK
fTIMxCLK = 250 MHz
tres(TIM) Timer resolution time
AHB/APBx prescaler > 4,
1 - tTIMxCLK
fTIMxCLK = 125 MHz

Timer external clock

fEXT 0 fTIMxCLK / 2 MHz
frequency on CH1 to CH4 fTIMxCLK = 250 MHz
ResTIM Timer resolution - 16 / 32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Specified by design - Not tested in production.
3. The maximum timer frequency on APB1 or APB2 is up to 250 MHz, by setting the TIMPRE bit in the RCC_CFGR register,
if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1,
otherwise TIMxCLK = 4 x Frcc_pclkx1 or TIMxCLK = 4 x Frcc_pclkx2.

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5.3.31 Low-power timer characteristics

Table 105. LPTIMx characteristics(1)(2)

Symbol Parameter Min Max Unit

tres(TIM) Timer resolution time 1 - tTIMxCLK

fLPTIMxCLK Timer kernel clock 0 250

MHz
fEXT Timer external clock frequency on Input1 and Input2 0 fLPTIMxCLK/2

ResTIM Timer resolution - 16 bit

tMAX_COUNT Maximum possible count - 65536 tTIMxCLK

1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM6 timers.

2. Specified by design - Not tested in production.

5.3.32 Communication interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are specified by design, not tested in production, when the I2C
peripheral is properly configured (refer to the product reference manual - RM0481)
The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but still present. Only
FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to
Section 5.3.14 for the I2C I/Os characteristics
All I2C SDA and SCL I/Os embed an analog filter, refer to Table 106 for its characteristics.

Table 106. I2C analog filter characteristics(1)(2)

Symbol Parameter Min Max Unit

tAF Maximum pulse width of spikes suppressed by analog filter 50(3) 160(4) ns
1. Evaluated by characterization - Not tested in production.
2. Measurement points are done at 50% VDD.
3. Spikes with widths below tAF(min) are filtered.
4. Spikes with widths above tAF(max) are not filtered.

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USART interface characteristics

Unless otherwise specified, the parameters given in Table 107 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• VOS level set to VOS0
Refer to Section 5.3.14 for more details on the input/output alternate function characteristics
(NSS, CK, TX, RX for USART).

Table 107. USART characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master receiver
31
1.71 V < VDD < 3.6 V
Master transmitter
31/6(2)
2.7 V < VDD < 3.6 V
Master transmitter
31/6(2)
1.71 V < VDD < 3.6 V
fCK USART clock frequency - - MHz
Slave receiver
83
1.71 V < VDD < 3.6 V
Slave transmitter
34/6(2)
2.7 V < VDD < 3.6 V
Slave transmitter
32/6(2)
1.71 V < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode tker(3) + 6.5 - -
th(NSS) NSS hold time Slave mode 2.5 - -
tw(CKH)
CK high and low time Master mode 1/fck/2 -1 1/fck/2 1/fck/2 +1
tw(CKL)
Master mode 13 - -
tsu(RX) Data input setup time
Slave mode 3.5 - -
Master mode 0.5 - -
th(RX) Data input hold time
Slave mode 1.5 - - ns
Slave mode,
- 14.5/38.5(2)
2.7 V < VDD < 3.6 V
11.5
Slave mode,
- 15.5/71.5(2)
1.71 V < VDD < 3.6 V
tv(TX) Data output valid time
Master mode,
- 3/24.5(2)
2.7 V < VDD < 3.6 V
2.5
Master mode,
- 3/54(2)
1.71 V < VDD < 3.6 V

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Table 107. USART characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Slave mode 7.5 - -

th(TX) Data output hold time ns
Master mode 0 - -
1. Evaluated by characterization - Not tested in production.
2. For PB14 with OSPEEDRy[1:0] = 01.
3. Tker is the usart_ker_ck_pres clock period.

Figure 47. USART timing diagram in Master mode

1/fCK
CK output

CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CK output

CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(CKH)
tsu(RX) tw(CKL)
RX
INPUT MSB IN BIT6 IN LSB IN
th(RX)
TX
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX)
MSv65386V4

1. Measurement points are done at 0.5VDD and with external CL = 30 pF.

Figure 48. USART timing diagram in Slave mode

NSS
input
1/fCK th(NSS)
tsu(NSS) tw(CKH)

CPHA = 0
CK input

CPOL = 0
CPHA = 0
CPOL = 1

tw(CKL) tv(TX) th(TX)

TX output First bit OUT Next bits OUT Last bit OUT

th(RX)
tsu(RX)

RX input First bit IN Next bits IN Last bit IN

MSv65387V4

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I3C interface characteristics

The I3C interface meets the timings requirements of the MIPI® I3C specification v1.1.
The I3C peripheral supports:
• I3C SDR-only as controller
• I3C SDR-only as target
• I3C SCL bus clock frequency up to 12.5 MHz
The parameters given in Table 108 are obtained with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS 0
The timings are in line with MIPI specification, except for the ones given in Table 108 and
Table 109. For tSU_OD and tSU_PP this can be mitigated by increasing the corresponding
SCL low duration in the I3C_TIMINGR0 register. For tSCO this can be mitigated by enabling
and adjusting the clock stall time both on the address ACK phase and on the data read Tbit
phase in the I3C_TIMINGR2 register. This can also be mitigated by increasing the SCL low
duration in the I3C_TIMINGR0 register. For further details refer to AN5879.

Table 108. I3C open-drain measured timing

I3C open drain mode
(specification) Timing
Symbol Parameter Conditions Unit
measurements
Min Max

SDA data setup time Controller

tSU_OD 3 - 16.5 ns
during open drain mode 1.71 V < VDD < 3.6 V

Table 109. I3C push-pull measured timing

I3C open drain mode
(specification) Timing
Symbol Parameter Conditions Unit
measurements
Min Max

SDA signal data setup in Controller

tSU_PP 3 - 12 ns
push-pull mode 1.71 V < VDD < 3.6 V

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 110 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V

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• VOS level set to VOS0

Refer to Section 5.3.14 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).

Table 110. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master receiver mode

- - 135/3(2)
2.7 V < VDD < 3.6 V
Master receiver mode
- - 120/3(2)
1.71 V < VDD < 2.7 V
Master transmitter mode
135/3(2)
2.7 V < VDD < 3.6 V
fSCK Master transmitter mode
SPI clock frequency - - 120/3(2) MHz
1/tSCK 1.71 V < VDD < 2.7 V
Slave receiver mode
- - 120
1.71 V < VDD < 3.6 V
Slave transmitter mode
- - 43(3)/6(4)
2.7 V < VDD < 3.6 V
Slave transmitter mode
- - 41.5(3)/6(4)
1.71 V < VDD < 2.7 V
tsu(NSS) NSS setup time Slave mode 3.5 - - ns
th(NSS) NSS hold time Slave mode 4.5 - - ns
tw(SCKH)
SCK high and low time Master mode tSCK(5) - 1 tSCK(5) tSCK(5) + 1 ns
tw(SCKL)
tsu(MI) Master mode 3.5 - -
Data input setup time ns
tsu(SI) Slave mode 2 - -
th(MI) Master mode 1 - -
Data input hold time ns
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 6.5 13 15 ns
tdis(SO) Data output disable time Slave mode 7.5 13 18 ns
Slave mode
(after enable edge), - 10/26.5(4) 11.5/35.5(4)
2.7 V < VDD < 3.6 V
tv(SO)
Slave mode
Data output valid time ns
(after enable edge), - 11/61.5(4) 12/76(4)
1.71 V < VDD < 2.7 V
Master mode
tv(MO) - 1.5 2
(after enable edge)
Slave mode
th(SO) 6.5/20.5(4) - -
(after enable edge)
Data output hold time ns
Master mode
th(MO) 0 - -
(after enable edge)
1. Evaluated by characterization - Not tested in production.

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2. When using PB13.

3. Maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which must fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
4. When using PB14.
5. tSCK = tker_ck * Baud rate prescaler.

Figure 49. SPI timing diagram - Master mode

High
(1)
SS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output

CPOL=0

CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output

CPOL=0

CPHA=1
CPOL=1
tsu(MI) th(MI)

MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT

tv(MO) th(MO)
MSv69586V2

1. The SS input can be configured to active low or active high.

Figure 50. SPI timing diagram - Slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

th(SI)
tsu(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

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Figure 51. SPI timing diagram - Slave mode and CPHA = 1

SS input(1)

tc(SCK) th(SS)
tsu(SS) tw(SCKH)
CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv69585V2

1. The SS input can be configured to active low or active high.

I2S Interface characteristics

Unless otherwise specified, the parameters given in Table 111 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.14 for more details on the input/output alternate function characteristics
(CK,SD,WS).

Table 111. I2S dynamic characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK I2S main clock output - - 50

Master transmitter - 50
MHz
fCK I2S clock output Slave transmitter (TX) - 21
Slave receiver (RX) - 50

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Table 111. I2S dynamic characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

tv(WS) WS valid time - 2

Master mode
th(WS) WS hold time 1 -
tsu(WS) WS setup time 3 -
Slave mode
th(WS) WS hold time 1.5 -
tsu(SD_MR) Master receiver 4 -
Data input setup time
tsu(SD_SR) Slave receiver 2 -
ns
th(SD_MR) Master receiver 1 -
Data input hold time
th(SD_SR) Slave receiver 1.5 -
tv(SD_ST) Slave transmitter (after enable edge) - 14
Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 1
th(SD_ST) Slave transmitter (after enable edge) 5.5 -
Data output hold time
th(SD_MT) Master transmitter (after enable edge) 0 -
1. Evaluated by characterization - Not tested in production.

Figure 52. I2S slave timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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Figure 53. I2S master timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

USB full speed (FS) characteristics

The USB interface is fully compliant with the USB specification version 2.0.

Table 112. USB DC electrical characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

VDD USB full speed transceiver operating voltage - 3.0(2) - 3.6 V

VDI(3) Differential input sensitivity Over VCM range 0.2 - -
VCM(3) Differential input common mode range Includes VDI range 0.8 - 2.5 V
VSE(3) Single ended receiver input threshold - 0.8 - 2.0
VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
V
VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
Pull down resistor on PA11, PA12
RPD(3) VIN = VDD 14.25 - 24.8
(USB_DP/DM)
kΩ
Pull-up resistor on PA12 (USB_DP) VIN = VSS, during idle 0.9 1.25 1.575
RPU(3)
Pull-up resistor on PA12 (USB_DP) VIN = VSS during reception 1.425 2.25 3.09
1. All the voltages are measured from the local ground potential.
2. The USB full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical
characteristics, which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Specified by design - Not tested in production.

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4. RL is the load connected on the USB full speed drivers.

Figure 54. USB timings - definition of data signal rise and fall time

Cross over
points
Differential
data lines

VCRS

VSS

tf tr
ai14137b

Table 113. USB startup time

Symbol Parameter Max Unit

tSTARTUP(1) USB transceiver startup time 1 μs

1. Specified by design - Not tested in production.

Table 114. USB electrical characteristics(1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit

trLS Rise time in LS(2) CL = 200 to 600 pF 75 300 ns

tfLS Fall time in LS(2) CL = 200 to 600 pF 75 300 ns
trfmLS Rise/fall time matching in LS tr/tf 80 125 %
trFS Rise time in FS(2) CL = 50 pF 4 20 ns
tfFS Fall time in FS(2) CL = 50 pF 4 20 ns
trfmFS Rise/fall time matching in FS tr/tf 90 111 %
VCRS Output signal crossover voltage (LS/FS) - 1.3 2.0 V
ZDRV Output driver impedance(3) Driving high or low 28 44 Ω
1. Specified by design - Not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed information, refer to USB specification -
chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.

Table 115. USB BCD DC electrical characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Primary detection mode consumption - - - 300

IDD(USBBCD) μA
Secondary detection mode consumption - - - 300
RDAT_LKG Data line leakage resistance - 300 - - kΩ
VDAT_LKG Data line leakage voltage - 0.0 - 3.6 V

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Table 115. USB BCD DC electrical characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Dedicated charging port resistance

RDCP_DAT - - - 200 Ω
across D+/D-
VLGC_HI Logic high - 2.0 - 3.6
VLGC_LOW Logic low - - - 0.8
VLGC Logic threshold - 0.8 - 2.0
V
VDAT_REF Data detect voltage - 0.25 - 0.4
VDP_SRC D+ source voltage - 0.5 - 0.7
VDM_SRC D- source voltage - 0.5 - 0.7
IDP_SINK D+ sink current - 25 - 175
μA
IDM_SINK D- sink current - 25 - 175
1. Specified by design - Not tested in production.

SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 116 and Table 117 are derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD supply
voltage summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL= 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.14 for more details on the input/output characteristics.

Table 116. Dynamic characteristics: SD/MMC characteristics, VDD = 2.7 to 3.6 V(1)
Symbol Parameter Conditions Min Typ Max Unit

130/6
fPP(2) Clock frequency in data transfer mode - - - (3) MHz

tW(CKL) Clock low time 8.5 9.5 -

fPP =52MHz ns
tW(CKH) Clock high time 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) mode

tISU Input setup time HS - 3 - -

tIH Input hold time HS - 1 - - ns
tIDW(5) Input valid window (variable window) - 4.5 - -

CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) mode

tOV Output valid time HS - - 6.5 7/38(3)

ns
tOH Output hold time HS - 3.5 - -

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STM32H533xx Electrical characteristics

Table 116. Dynamic characteristics: SD/MMC characteristics, VDD = 2.7 to 3.6 V(1)
Symbol Parameter Conditions Min Typ Max Unit

CMD, D inputs (referenced to CK) in SD default mode

tISUD Input setup time SD - 3 -

ns
tIHD Input hold time SD - 1.5 -

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD - - 1.5 2/33(3)

ns
tOHD Output hold default time SD - 0 - -
1. Evaluated by characterization - Not tested in production.
2. CL applied is 20 pF.
3. When using PB13 & PB14.
4. For SD 1.8 V support, an external voltage converter is needed.
5. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Table 117. Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V(1)
Symbol Parameter Conditions Min Typ Max Unit

110/6
fPP(2) Clock frequency in data transfer mode - - - (3) MHz

tW(CKL) Clock low time 8.5 9.5 -

fPP =52 MHz ns
tW(CKH) Clock high time 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC mode

tISU Input setup time HS - 2.5 - -

tIH Input hold time HS - 2 - - ns
tIDW(4) Input valid window (variable window) - 4 - -

CMD, D outputs (referenced to CK) in eMMC mode

tOV Output valid time HS - - 6.5 7/5(3)

ns
tOH Output hold time HS - 3.5 - -
1. Evaluated by characterization - Not tested in production.
2. CL = 20 pF.
3. When using PB13 and PB14.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

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Figure 55. SDIO high-speed/eMMC timing

MSv72345V1

Figure 56. SD default speed timings

CK
tOV tOH

D, CMD output MSv69710V1

Figure 57. DDR mode timings

D input Valid data Valid data

tISU tIH tISU tIH

tW(CKH)

CK

tW(CKL)
tOV tOV
tOH tOH

D output Valid data Valid data

MSv69158V1

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STM32H533xx Electrical characteristics

JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 118 and Table 119 for JTAG/SWD
are derived from tests performed under the ambient temperature, frcc_c_ck frequency and
VDD supply voltage summarized in Table 20, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL= 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.14 for more details on the input/output characteristics:

Table 118. Dynamic JTAG characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

FTCK 2.7 V < VDD < 3.6 V - - 47.5

TCK clock frequency MHz
1/tc(TCK) 1.71 V < VDD < 3.6 V - - 45
tisu(TMS) TMS input setup time - 3.5 - -
tih(TMS) TMS input hold time - 1.5 - -
tisu(TDI) TDI input setup time - 2.5 - -
tih(TDI) TDI input hold time - 1.5 - - ns
2.7V < VDD < 3.6 V - 8 10.5
tov(TDO) TDO output valid time
1.71 < VDD < 3.6 V - 8 11
toh(TDO) TDO output hold time - 6.5 - -
1. Evaluated by characterization - Not tested in production.

Table 119. Dynamic SWD characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

FSWCLK 2.7 V < VDD < 3.6 V - - 80

SWCLK clock frequency MHz
1/tc(SWCLK) 1.71 V < VDD < 3.6 V - - 71
tisu(SWDIO) SWDIO input setup time - 1.5 - -
tih(SWDIO) SWDIO input hold time - 1.5 - -
2.7 V < VDD < 3.6 V - 10.5 12.5 ns
tov(SWDIO) SWDIO output valid time
1.71 V < VDD < 3.6 V - 10.5 14.0
toh(SWDIO) SWDIO output hold time - 8.5 - -
1. Evaluated by characterization - Not tested in production.

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Figure 58. JTAG timing diagram

tc(TCK)

TCK

tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS

tov(TDO) toh(TDO)

TDO

MSv40458V1

Figure 59. SWD timing diagram

tc(SWCLK)

SWCLK

tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)

tov(SWDIO) toh(SWDIO)

SWDIO
(transmit)

MSv40459V1

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STM32H533xx Package information

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

6.1 Device marking

Refer to “Reference device marking schematics for STM32 microcontrollers and
microprocessors” (TN1433), available on www.st.com, for the location of pin 1 / ball A1 as
well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.

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6.2 WLCSP39 package information (B0MM)

This WLCSP is a 39-ball, 2.76 x 2.78 mm, 0.4 mm pitch, wafer level chip scale array
package.

Figure 60. WLCSP39 - Outline

A1 ball pad corner
11 9 7 5 3 1
10 8 6 4 2

B Øb (39 balls)
C
Ø ddd M C A B
Øeee M C
E E1 D
SE
E
(Datum A)
F

e (Datum B)

SD
D1

D
aaa (4X)
BOTTOM VIEW

A1 ball pad corner

1 3 5 7 9 11
2 4 6 8 10

B
(Datum A)
C
E D

E
(Datum B)
F

A D
c
TOP VIEW
Back side coating
Silicon
Solder balls
A3

A2 A

C Seating plane
A1
SIDE VIEW B0MM_WLCSP39_ME_V1

1. Drawing is not to scale.

2. The A1 corner must be identified on the top surface of the package by using a marking or a physical
feature. A distinguish feature is allowable on the bottom surface of the package to identify the A1 corner.
Exact shape of each corner is optional.

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Table 120. WLCSP39 - Mechanical data

Millimeters Inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 0.58 - - 0.0228

(3)
A1 - 0.17 - - 0.0067 -
A2 - 0.38 - - 0.0150 -
A3 - 0.025 - - 0.0010 -
(4)
b 0.23 0.26 0.28 0.0091 0.0102 0.0110
(5)
D 2.76 BSC 0.1087 BSC
D1 2.000 BSC 0.0787 BSC
E 2.78 BSC 0.1094 BSC
E1 2.078 BSC 0.0818 BSC
e(6) 0.40 BSC 0.0157 BSC
SD(7) 0.200 BSC 0.0079 BSC
SE(7) 0.346 BSC 0.0136 BSC
(8)
N 39
aaa(9) 0.02 BSC 0.0008 BSC
bbb(9) 0.06 BSC 0.0024 BSC
(9)
ccc 0.03 BSC 0.0012 BSC
(9)
ddd 0.015 BSC 0.0006 BSC
eee(9) 0.05 BSC 0.0020 BSC
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The profile height, A, is the distance from the seating plane to the highest point on the package. It is
measured perpendicular to the seating plane.
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to datum C.
5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance.
6. e represents the solder balls grid pitch(es).
7. Basic dimensions SD and SE are defining the ball matrix position with respect to datums A and B.
8. N represents the total number of balls.
9. The tolerance of position that controls the location of the balls within the matrix with respect to each other.

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Figure 61. WLCSP39 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Figure 62. WLCSP39 - Marking example (package top view)

Ball A1 identifier

Product identification

Date code
Revision code

Y WW
MSv73084V1

204/231 DS14539 Rev 1

STM32H533xx Package information

6.3 LQFP48 package information (5B)

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 63. LQFP48 - Outline(15)

BOTTOM VIEW

4x N/4 TIPS
aaa C A-B D
2 1
(2)
R1

H
R2

B
B-
D 1/4

N
O
(6)

TI
C
SE
B GAUGE PLANE
E 1/4

0.25
S
B
bbb H A-B D 4x
L
3
(13) (L1)
0.05 (N – 4)x e (1) (11)

A A2 C SECTION A-A

(12) ccc C
A1 ddd C A-B D
b
D (4)
(2) (5)
D1
(10) D (3) (9) (11)
N b WITH PLATING

1
2 E 1/4
(3) A 3
(6) B (3)
D 1/4 c c1
E1 E (11) (11)
(2) (4)
(5)
A A b1 BASE METAL
(Section A-A) (11)

SECTION B-B

TOP VIEW

5B_LQFP48_ME_V1

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Table 121. LQFP48 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
(2)(5)
D1 7.00 BSC 0.2756 BSC
E(4) 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 48
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
(1)(7)
bbb 0.20 0.0079
ccc(1)(7) 0.08 0.0031
(1)(7)
ddd 0.08 0.0031

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STM32H533xx Package information

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 64. LQFP48 - Footprint example

0.50
1.20

36 25
37 24 0.30

0.20

9.70 7.30

48 13
1 12

5.80

9.70
5B_LQFP48_FP_V1

1. Dimensions are expressed in millimeters.

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6.4 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 65. LQFP64 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4

0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A

(13) (N – 4)x e

C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C

D (4)

(5) (2) D1 (9) (11)

(10)
D (3) b WITH PLATING
N (4)

1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)

A A SECTION B-B
(Section A-A)

TOP VIEW 5W_LQFP64_ME_V1

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STM32H533xx Package information

Table 122. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 66. LQFP64 - Footprint example

48 33

0.30
49 0.5 32

12.70

10.30

10.30
64 17

1.20
1 16

7.80

12.70
5W_LQFP64_FP_V2

1. Dimensions are expressed in millimeters.

210/231 DS14539 Rev 1

STM32H533xx Package information

6.5 UFQFPN48 package information (A0B9)

This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 67. UFQFPN48 – Outline

D1 EXPOSED PAD

E2 E1
e

PIN 1 idenfier
L
D2
BOTTOM VIEW
A
A3
A1
SEATING PLANE

C
DETAIL A
ddd C
LEADS COPLANARITY
FRONT VIEW

A1 A
SEATING PLANE

ddd C
PIN 1 IDENTIFIER C
LASER MAKER AREA

TOP VIEW

A0B9_UFQFPN48_ME_V4

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect
and solder this back-side pad to PCB ground.

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Table 123. UFQFPN48 – Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
(2)
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
D1 5.400 5.500 5.600 0.2126 0.2165 0.2205
D2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
(2)
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
E1 5.400 5.500 5.600 0.2126 0.2165 0.2205
E2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm.
3. Dimensions D2 and E2 are not in accordance with JEDEC.

Figure 68. UFQFPN48 – Footprint example

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80 A0B9_UFQFPN48_FP_V3

1. Dimensions are expressed in millimeters.

212/231 DS14539 Rev 1

STM32H533xx Package information

6.6 LQFP100 package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 69. LQFP100 - Outline(15)

ș2 ș
(2)
R1

H
R2

B
B-
N
O
(6)

TI
C
SE
D1/4 B GAUGE PLANE

S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)

BOTTOM VIEW SECTION A-A

(N-4) x e (13)

C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)

SIDE VIEW

D (4)
(11) c
(2) (5) D1 c1 (11)

D (3)
(10) (4)
N

b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B

D1/4 (6) (2)

A B
(5)

E1 E

SECTION A-A

A A

TOP VIEW 1L_LQFP100_ME_V3

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Table 124. LQFP100 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - 1.50 1.60 - 0.0590 0.0630

(12)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
E(4) 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
N(13) 100
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
(1)
bbb 0.20 0.0079
ccc(1) 0.08 0.0031
(1)
ddd 0.08 0.0031

214/231 DS14539 Rev 1

STM32H533xx Package information

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 70. LQFP100 - Footprint example

75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

1L_LQFP100_FP_V1

1. Dimensions are expressed in millimeters.

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6.7 UFBGA100 package information (A0C2)

This UFBGA is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Note: See list of notes in the notes section.

Figure 71. UFBGA100 - Outline(13)

E1

e SE

M
L
K
SD J
H
G
D1
F
E
D
C
e
B
A

A1 ball pad 1 2 3 4 5 6 7 8 9 10 11 12
corner Øb (N balls)
BOTTOM VIEW Ø eee M C A B
Ø fff M C

DETAIL A

Mold resin
A ccc C
SIDE VIEW
C
Substrate

B E
A
A1 ball pad
corner
(9)
Seating plane
(8)

(DATUM A) A1 A2
C
Detail A
D ddd C
Solder balls

(DATUM B)

aaa C
TOP VIEW (4X)
A0C2_UFBGA_ME_V8

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Table 125. UFBGA100 - Mechanical data

millimeters(1) inches(12)
Symbol
Min. Typ. Max. Min. Typ. Max.

A(2)(3) - - 0.60 - - 0.0236

(4)
A1 0.05 - - 0.0020 - -
A2 - 0.43 - - 0.0169 -
(5)
b 0.23 0.28 0.33 0.0090 0.0110 0.0130
(6)
D 7.00 BSC 0.2756 BSC
D1 5.50 BSC 0.2165 BSC
E 7.00 BSC 0.2756 BSC
E1 5.50 BSC 0.2165 BSC
(9)
e 0.50 BSC 0.0197 BSC
N(11) 100
SD(12) 0.25 BSC 0.0098 BSC
SE(12) 0.25 BSC 0.0098 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.08 0.0031
eee 0.15 0.0059
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. UFBGA stands for ulta profile fine pitch ball grid array: 0.50 mm < A ≤ 0.65 mm / fine
pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metalized markings, or other feature of package body or

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integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to 4 decimal digits.
13. Drawing is not to scale.

Figure 72. UFBGA100 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 126. UFBGA100 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values

Pitch 0.50 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the solder mask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm

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STM32H533xx Package information

6.8 LQFP144 package information (1A)

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 73. LQFP144 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
(6) B GAUGE PLANE

0.25
D 1/4
S
B
L
3
E 1/4 (L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D SECTION A-A
bbb H A-B D 4x

(N-4)x e
C
A
0.05 (12) ddd C A-B D
A2 A1 b ccc C

D (4)
D1 (2) (5)
(10) (3) D (9) (11)
N (4)
b WITH PLATING

1
2
3 E 1/4

(11) (11)
c c1
(6)
D 1/4 (2)
(3) A B (3) (5)

E1 E b1 BASE METAL
(11)

SECTION B-B

A A
(Section A-A)

TOP VIEW
1A_LQFP144_ME_V2

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Table 127. LQFP144 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 22.00 BSC 0.8661 BSC
(2)(5)
D1 20.00 BSC 0.7874 BSC
E(4) 22.00 BSC 0.8661 BSC
E1(2)(5) 20.00 BSC 0.7874 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 144
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

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Figure 74. LQFP144 - Footprint example

108 73
1.35

109 0.35 72

0.50

19.90 17.85
22.60

144 37

1 36

19.90
22.60
1A_LQFP144_FP

1. Dimensions are expressed in millimeters.

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6.9 UFBGA144 package information (A0Y2)

This UFBGA is a 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array
package.
Note: See list of notes in the notes section.

Figure 75. UFBGA144 - Outline(13)

E1

e SE

M
L
K
J
e
H
SD
G
D1
E
D
C
B
A

A1 ball pad
corner 1 2 3 4 5 6 7 8 9 10 11 12
Øb (144 balls)
BOTTOM VIEW Ø eee M C A B
Ø fff M C

DETAIL A

A
SIDE VIEW C

B E
8 A1 ball A
pad corner
ccc C Mold resin

Seating
(DATUM A) plane
7

Substrate A1 A2
D
Solder balls
ddd C
(DATUM B)

DETAIL A
(4x)
aaa C

TOP VIEW A02Y_UFBGA144_ME_V3

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Table 128. UFBGA144 - Mechanical data

millimeters(1) inches(12)
Symbol
Min. Typ. Max. Min. Typ. Max.

A(2)(3) - - 0.60 - - 0.0236

(4)
A1 0.05 - - 0.0020 - -
A2 - 0.43 - - 0.0169 -
(5)
b 0.35 0.40 0.45 0.0138 0.0157 0.0177
(6)
D 10.00 BSC 0.3937 BSC
D1 8.80 BSC 0.3465 BSC
E 10.00 BSC 0.3937 BSC
E1 8.80 BSC 0.3465 BSC
(9)
e 0.80 BSC 0.0315 BSC
N(11) 144
SD(12) 0.40 BSC 0.0157 BSC
SE(12) 0.40 BSC 0.0157 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.10 0.0039
eee 0.15 0.0059
fff 0.08 0.0031

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. UFBGA stands for ulta profile fine pitch ball grid array: 0.50 mm < A ≤ 0.65 mm / fine
pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metalized markings, or other feature of package body or

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integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to 4 decimal digits.
13. Drawing is not to scale.

Figure 76. UFBGA144 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 129. UFBGA144 - Example of PCB design rules (0.80 mm pitch BGA)
Dimension Values

Pitch 0.80 mm
Dpad 0.400 mm
0.550 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm

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6.10 Package thermal characteristics

The maximum chip-junction temperature, TJmax in degrees Celsius, can be calculated using
the following equation:
TJmax = TAmax + (PDmax × ΘJA)
Where:
• TAmax is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax),
• PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/Omax represents the maximum power dissipation on output pins:
PI/Omax = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 130. Package thermal characteristics

Symbol Definition Parameter Value Unit

WLCSP39 (2.76 x 2.78 mm) 65.3

UFQFPN48 (7 x 7 mm) 28.5
LQFP48 (7 x 7 mm) 51.2

Thermal resistance LQFP64 (10 x 10 mm) 44.2

ΘJA °C/W
junction-ambient LQFP100 (14 x 14 mm) 36.4
UFBGA100 (7 x 7 mm) 50
LQFP144 (20 x 20 mm) 37.9
UFBGA144 (10 x 10 mm) 45.5
WLCSP39 (2.76 x 2.78 mm) 38
UFQFPN48 (7 x 7 mm) 12.9
LQFP48 (7 x 7 mm) 28.6

Thermal resistance LQFP64 (10 x 10 mm) 26.6

ΘJB °C/W
junction-board LQFP100 (14 x 14 mm) 22.3
UFBGA100 (7 x 7 mm) 35.8
LQFP144 (20 x 20 mm) 26.7
UFBGA144 (10 x 10 mm) 33.4

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Table 130. Package thermal characteristics (continued)

Symbol Definition Parameter Value Unit

WLCSP39 (2.76 x 2.78 mm) 3.4

UFQFPN48 (7 x 7 mm) 10.2
LQFP48 (7 x 7 mm) 14.2

Thermal resistance LQFP64 (10 x 10 mm) 12

ΘJC °C/W
junction-case LQFP100 (14 x 14 mm) 9.3
UFBGA100 (7 x 7 mm) 15
LQFP144 (20 x 20 mm) 9.4
UFBGA144 (10 x 10 mm) 14.6

6.10.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
• For information on thermal management, refer to “Thermal management guidelines for
STM32 32-bit Arm Cortex MCUs applications” (AN5036) available from www.st.com.

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Ordering information STM32H533xx

7 Ordering information

Example: STM32 H 533 V E T 6 TR

Device family

STM32 = Arm based 32-bit microcontroller

Product type

H = high performance

Device subfamily

533 = STM32H533xx devices

Pin count

C = 48 pins
R = 64 pins
H = 39 balls
V = 100 pins/balls
Z = 144 pins/balls

Flash memory size

E = 512 Kbytes

Package
U = UFQFPN
T = LQFP
I = UFBGA (7 x 7 mm)
K= UFBGA (10 x 10)
Y = WLCSP

Temperature range

6 = Temperature range, -40 to 85 °C

7 = Temperature range, -40 to 105 °C, and up to 125 °C at low dissipation (130 °C juntion)

Packing

TR = tape and reel

xxx = programmed parts

For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.

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STM32H533xx Important security notice

8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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Revision history STM32H533xx

9 Revision history

Table 131. Document revision history

Date Revision Changes

02-Apr-2024 1 Initial release.

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IMPORTANT NOTICE – READ CAREFULLY

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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2024 STMicroelectronics – All rights reserved

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