Laboratory exercises

Digital Electronics 1 course

Laboratory 4
Basic Logic Gates-Physical Implementation
M. Camacho 1S. Mendieta 1 , I. Pinzón 1
1
Electronics Engineering School, Engineering Faculty, Pedagogical and Technological University of Colombia, Tunja, Colombia

SUMMARY display, this controller uses a

communication protocol called Serial
In the following laboratory activity, the Peripheral Interface (SPI).[1]
different integrated circuit gates are
recognized, implementing their operations, The FPGA can be programmed using a
references, and connections between them, hardware description language, such as
with the support of knowledge in terms of VHDL or Verilog, in terms of software.
operations with Boolean algebra, truth You could, for instance, create a VHDL
tables and other basic topics for digital program to manage the switches and
electronics. LEDs. The program could set up the
corresponding pins as inputs or outputs
1. OBJECTIVE and read or write to or from their state as
necessary.
● Recognize some physical features
of real logic gates, and to check its Is possible to use a pre-existing module in
impact on the operation of the the FPGA that implements the SPI
circuits by means of Quartus controller for the display for the 7-segment
implemented on FPGA. display. Then, could create a VHDL
program that instructs the controller to
2. INTRODUCTION send the required data so that the desired
numbers are displayed on the display.

An array of programmable gates, RAM In essence, the Cyclone II EP2C20F484C7

and ROM memory blocks, and other parts FPGA is a programmable logic device
are found in the Cyclone II with a few input/output pins for
EP2C20F484C7 FPGA, a programmable connecting external components, also has
logic device that makes it possible to many components like switches for input
implement intricate digital circuits. With a or leds like outputs. Complex digital
484-pin package and a 1V operating circuitry that operates these devices can be
voltage requirement, the FPGA is implemented using programming in a
available. hardware description language like Verilog
or VHDL.[2]
The Cyclone II EP2C20F484C7 FPGA has
several input and output pins that can be
used to connect external devices. 3. ACTIVITIES

A 4-digit 7-segment display controller is The activity consists of designing and

also built into the FPGA. To receive data simulating the operation of a
from the FPGA and display it on the seven-segment display to visualize the
identification numbers and their date of 8 0 1 0 0 0 7 0 0 0 1 1 1 1 112
birth as shown in Figure 1.
9 0 0 0 0 0 1 1 0 0 1 1 1 1 109
10 0 1 0 1 0

11 0 0 1 0 0 1 0 0 0 1 0 0 1 109

12 0 0 0 1 1 0 0 0 0 0 1 1 0 115

13 1 1 1 0 1 1 1 1 1 1 0 1 1 8

14 1 0 0 1 1 1 1 1 0 0 1 1 1 48

15 0 0 1 0 0 1 0 0 0 1 0 0 1 109

16 1 1 1 0 1 1 1 1 1 1 0 1 1 8

17 0 0 1 0 0 1 0 0 0 1 0 0 1 109

18 0 0 0 0 0 0 1 0 0 0 0 0 0 126
Figure 1. example table with the ID number and date of
birth 19 0 0 0 0 0 0 1 0 0 0 0 0 0 126

20 0 0 1 0 0 1 0 0 0 1 0 0 1 109
Based on figure 1, the data is obtained for
the ID number 1002528372 and the 21 0 0 1 0 0 1 0 0 0 1 0 0 1 0
date of birth 12/29/2002, as shown in
figure 2. Table 1. Truth table. Own elaboration

From this table the canonical output

3.1. ID M. Camacho
equations are obtained.

Inp
Input binary Output Binary a=A'C + CD + A'D + BC'D' + AB'C'
ut Out
de put b=A'D + A'B' + BC + AC'D' + B'D
ci dec Output c=A'B'C' + A'D' + A'BC + C'D' + BD'
ma ima decima d=D + A'C + BC'
l A B C D E l a b c d e f g l e=A'C'D + A'CD' + B'D + DCD
0 0 0 0 0 0 1 1 0 0 1 1 1 1 48 f=A'B'C'D + A'CD' + BC'D'
0 0 0 0 1 0 0 0 0 0 0 0 1
g= CD + A'B + AB'D + AB'C
1 126

2 0 0 0 1 0 0 0 0 0 0 0 0 1 126

3 0 0 0 1 1 2 0 0 1 0 0 1 0 109

4 0 0 1 0 0 5 0 1 0 0 1 0 0 87 Image 2. Simulation Quartus. Own elaboration

5 0 0 1 0 1 2 0 0 1 0 0 1 0 109

6 0 0 1 1 0 8 0 0 0 0 0 0 0 127
Image 3. Pin Planner Quartus. Own elaboration

7 0 0 1 1 1 3 0 0 0 0 1 1 0 121
 3.2 ID S. Mendieta.

Table 2. Truth table. Own elaboration

a = W'X'Y'Z' + V'WYZ' + V'WX

b = V'XY'Z + V'W'XYZ' + V'WX'YZ' +

VW'X'Y'Z'

c = V'W'X'YZ + V'WX'YZ' + V'WXY'Z +

 VW'X'Y' + VW'Y'Z' Image 6. Operation 0000. Own elaboration.

d = V'W'X'Y'Z' + V'WYZ' + V'WXZ' +

V'WXY

e = V'WY'Z + V'WYZ' + V'WX +

W'X'Y'Z' + V'W'Y'Z'

f= W'Y'Z' + V'W'X'YZ + V'WY'Z +

V'WYZ' + VW'X'Y' + V'WXZ

g= V'W'X'Y' + V'X'Z' + V'WY + V'WXZ

+ W'X'Z' + VW'X'Y

Image x. Operation 0001. Own elaboration.

Image 4. Simulation Quartus. Own elaboration

Image 5. Pin Planner Quartus. Own elaboration

Image x. Operation 0011. Own elaboration.

 3.3. ID. I. Pinzón

Table 3. Truth table. Own elaboration

a = A'B'E + B'C'E + B'C'D + AB'CD'E' +

A'CD + A'BD'E' + A'C'E

b = A'C'D' + A'BCD + B'CD'E' + B'C'DE'

+ A'B'CE + A'BC'E + AB'C'E

c = A'B' + A'C'E + A'CE' + B'C'D +

B'CD'E'

d = B'C'E + B'C'D + AB'CD'E' + A'B'DE'

+ A'BC'D' + A'BDE + A'BCE'

e = B'C'DE' + A'BC'D' + A'BCD +

A'C'D'E + A'BC'E + AB'C'E

f = A'C'E + A'CE' + A'B'D + B'C'D

g = A'B'DE + A'BD' + AB'C'D' + A'B'CE'

+ A'CDE + B'CD'E'
Imagen x. ID number display in the FPGA.
Own elaboration.
 Anexx

Code M. Camacho

library ieee;

use ieee.std_logic_1164.all;

entity lab4 is

port

a, b, c, d, e : in std_logic;

A_o, B_o, C_o, D_o, E_o, F_o, G_o : out std_logic;

led0, led1, led2 : out std_logic_vector(6 downto 0)

);

end lab4;

architecture Behavioral of lab4 is

begin

A_o <= not((not a and d and e) or (not b and not c and e) or (not b and not c
and d) or (not b and c and not d and not e) or (not a and not b and c) or (not a and b
and not c and not d) or (not a and c and not d and not e));

B_o <=not( (not a and not b and e) or (not b and not c and e) or (not b and not
c and d) or (a and not b and c and not d and not e) or (not a and not b and not c) or
(not a and c and d) or (not a and b and not d and not e) or (not a and not c and e));
 C_o <= not((not a and not b and not c and not d) or (not a and not b and c and
d) or (not a and not d and not e) or (not a and c and not e) or (a and not b and not c
and d) or (not b and not c and d and not e));

D_o <= not((not a and e) or (not a and not b and d) or (not b and c and not d
and not e) or (a and not b and not c));

E_o <=not((not a and not b and not d and e) or (not a and not b and d and not
e) or (not a and not c and e) or (not a and b and d and e) or (not b and not c and e) or
(not b and not c and d) or (a and not b and c and not d and not e));

F_o <= not((not a and not b and not c and not d and e) or (not a and c and not
d and not e) or (a and not b and not c and d) or (not a and not b and d and not e));

G_o <= not((not a and d and e) or (not a and not b and c) or (not a and b and
not c and e) or (not a and c and not d and not e) or (a and not b and not c and not d and
e) or (not b and c and not d and not e));

led0 <= "1111111";

led1 <= "1111111";

led2 <= "1111111";

end Behavioral;

Code S. Mendieta

2.1. Option 1

library ieee;
use ieee.std_logic_1164.all;

entity Lab4_opcion2 is

port

V_i : in std_logic ;

W_i : in std_logic ;

X_i : in std_logic ;

Y_i : in std_logic ;

Z_i : in std_logic ;

a_o : out std_logic;

b_o : out std_logic;

c_o : out std_logic;

d_o : out std_logic;

e_o : out std_logic;

f_o : out std_logic;

g_o : out std_logic

);

end Lab4_opcion2;

architecture Behavioral of Lab4_opcion2 is

begin

a_o <= not((not W_i and not X_i and not Y_i and not Z_i) or (not V_i and W_i and
Y_i and not Z_i) or (not V_i and W_i and X_i));

b_o <= not((not V_i and X_i and not Y_i and Z_i) or (not V_i and not W_i and X_i
and Y_i and not Z_i) or

(not V_i and W_i and not X_i and Y_i and not Z_i) or (V_i and not W_i and
not X_i and not Y_i and not Z_i));
c_o <= not( (not V_i and not W_i and not X_i and Y_i and Z_i) or (not V_i and W_i
and not X_i and Y_i and not Z_i) or

(not V_i and W_i and X_i and not Y_i and Z_i) or (V_i and not W_i and not X_i
and not Y_i) or (V_i and not W_i and not Y_i and not Z_i));

d_o <= not((not V_i and not W_i and not X_i and not Y_i and not Z_i) or

(not V_i and W_i and Y_i and not Z_i) or (not V_i and W_i and X_i and not Z_i)
or (not V_i and W_i and X_i and Y_i));

e_o <= not((not V_i and W_i and not Y_i and Z_i) or (not V_i and W_i and Y_i and
not Z_i) or (not V_i and W_i and X_i) or

(not W_i and not X_i and not Y_i and not Z_i) or (not V_i and not W_i and not
Y_i and not Z_i));

f_o <= not((not W_i and not Y_i and not Z_i) or (not V_i and not W_i and not X_i
and Y_i and Z_i) or

(not V_i and W_i and not Y_i and Z_i) or (not V_i and W_i and Y_i and not Z_i)
or (V_i and not W_i and not X_i and not Y_i) or

(not V_i and W_i and X_i and Z_i));

g_o <= not((not V_i and not W_i and not X_i and not Y_i) or (not V_i and not X_i
and not Z_i) or (not V_i and W_i and Y_i) or

(not V_i and W_i and X_i and Z_i) or (not W_i and not X_i and not Z_i) or (V_i
and not W_i and not X_i and Y_i));

end Behavioral;

2.2. Option 2

library ieee;

use ieee.std_logic_1164.all;

entity Mux is

port

sel_i :in std_logic_vector(4 downto 0);

 sal_o :out std_logic_vector(6 downto 0)

);

end entity;

architecture Behavioral of mux is

begin

sal_o(6)<= '1' when sel_i = "00000" else

'1' when sel_i = "00001" else

'1' when sel_i = "00010" else

'0' when sel_i = "00011" else

'0' when sel_i = "00100" else

'0' when sel_i = "00101" else

'0' when sel_i = "00110" else

'0' when sel_i = "00111" else

'1' when sel_i = "01000" else

'0' when sel_i = "01001" else

'1' when sel_i = "01010" else

'1' when sel_i = "01011" else

'0' when sel_i = "01100" else

'1' when sel_i = "01101" else

'1' when sel_i = "01110" else

'1' when sel_i = "01111" else

'1' when sel_i = "10000" else

'0' when sel_i = "10001" else

'1' when sel_i = "10010" else

'1' when sel_i = "10011" else

 '0' when sel_i = "10100" else

'1';

sal_o(5)<= '1' when sel_i = "00000" else

'0' when sel_i = "00001" else

'0' when sel_i = "00010" else

'1' when sel_i = "00011" else

'1' when sel_i = "00100" else

'0' when sel_i = "00101" else

'0' when sel_i = "00110" else

'0' when sel_i = "00111" else

'0' when sel_i = "01000" else

'1' when sel_i = "01001" else

'1' when sel_i = "01010" else

'0' when sel_i = "01011" else

'0' when sel_i = "01100" else

'1' when sel_i = "01101" else

'1' when sel_i = "01110" else

'1' when sel_i = "01111" else

'1' when sel_i = "10000" else

'1' when sel_i = "10001" else

'0' when sel_i = "10010" else

'0' when sel_i = "10011" else

'1' when sel_i = "10100" else

'1';

sal_o(4)<= '1' when sel_i = "00000" else

'0' when sel_i = "00001" else

'0' when sel_i = "00010" else

 '0' when sel_i = "00011" else

'1' when sel_i = "00100" else

'0' when sel_i = "00101" else

'0' when sel_i = "00110" else

'0' when sel_i = "00111" else

'0' when sel_i = "01000" else

'1' when sel_i = "01001" else

'1' when sel_i = "01010" else

'0' when sel_i = "01011" else

'1' when sel_i = "01100" else

'1' when sel_i = "01101" else

'1' when sel_i = "01110" else

'1' when sel_i = "01111" else

'1' when sel_i = "10000" else

'0' when sel_i = "10001" else

'0' when sel_i = "10010" else

'0' when sel_i = "10011" else

'0' when sel_i = "10100" else

'1';

sal_o(3)<= '1' when sel_i = "00000" else

'0' when sel_i = "00001" else

'0' when sel_i = "00010" else

'0' when sel_i = "00011" else

'0' when sel_i = "00100" else

'0' when sel_i = "00101" else

'0' when sel_i = "00110" else

'0' when sel_i = "00111" else

 '0' when sel_i = "01000" else

'0' when sel_i = "01001" else

'1' when sel_i = "01010" else

'0' when sel_i = "01011" else

'1' when sel_i = "01100" else

'0' when sel_i = "01101" else

'1' when sel_i = "01110" else

'1' when sel_i = "01111" else

'0' when sel_i = "10000" else

'0' when sel_i = "10001" else

'0' when sel_i = "10010" else

'0' when sel_i = "10011" else

'0' when sel_i = "10100" else

'1';

sal_o(2)<= '0' when sel_i = "00000" else

'0' when sel_i = "00001" else

'0' when sel_i = "00010" else

'1' when sel_i = "00011" else

'0' when sel_i = "00100" else

'0' when sel_i = "00101" else

'0' when sel_i = "00110" else

'0' when sel_i = "00111" else

'0' when sel_i = "01000" else

'0' when sel_i = "01001" else

'1' when sel_i = "01010" else

'0' when sel_i = "01011" else

'0' when sel_i = "01100" else

 '1' when sel_i = "01101" else

'0' when sel_i = "01110" else

'0' when sel_i = "01111" else

'1' when sel_i = "10000" else

'1' when sel_i = "10001" else

'0' when sel_i = "10010" else

'0' when sel_i = "10011" else

'1' when sel_i = "10100" else

'1';

sal_o(1)<= '0' when sel_i = "00000" else

'0' when sel_i = "00001" else

'0' when sel_i = "00010" else

'0' when sel_i = "00011" else

'0' when sel_i = "00100" else

'1' when sel_i = "00101" else

'1' when sel_i = "00110" else

'0' when sel_i = "00111" else

'0' when sel_i = "01000" else

'0' when sel_i = "01001" else

'1' when sel_i = "01010" else

'0' when sel_i = "01011" else

'0' when sel_i = "01100" else

'1' when sel_i = "01101" else

'0' when sel_i = "01110" else

'0' when sel_i = "01111" else

'1' when sel_i = "10000" else

'0' when sel_i = "10001" else

 '0' when sel_i = "10010" else

'0' when sel_i = "10011" else

'0' when sel_i = "10100" else

'1';

sal_o(0)<= '1' when sel_i = "00000" else

'0' when sel_i = "00001" else

'0' when sel_i = "00010" else

'0' when sel_i = "00011" else

'0' when sel_i = "00100" else

'0' when sel_i = "00101" else

'0' when sel_i = "00110" else

'0' when sel_i = "00111" else

'0' when sel_i = "01000" else

'0' when sel_i = "01001" else

'1' when sel_i = "01010" else

'0' when sel_i = "01011" else

'1' when sel_i = "01100" else

'1' when sel_i = "01101" else

'1' when sel_i = "01110" else

'1' when sel_i = "01111" else

'1' when sel_i = "10000" else

'0' when sel_i = "10001" else

'0' when sel_i = "10010" else

'0' when sel_i = "10011" else

'0' when sel_i = "10100" else

'1';

end Behavioral;
 Code I. Pinzón

library ieee;

use ieee.std_logic_1164.all;

entity cedula is

port

A_i, B_i, C_i, D_i, E_i : in std_logic;

a_o, b_o, c_o, d_o, e_o, f_o, g_o : out std_logic

);

end cedula;

architecture Behavioral of cedula is

begin

a_o <= not((not B_i and not C_i and E_i) or (not B_i and not C_i and D_i) or
(not A_i and not B_i and C_i and not D_i) or (not A_i and B_i and not D_i and not E_i)or
(not A_i and B_i and C_i and D_i)) ;

b_o <= not((not A_i and not B_i and not D_i) or (not A_i and C_i and not E_i)
or (not B_i and not C_i and E_i) or (not B_i and not C_i and D_i) or (not A_i and not C_i
and not D_i) or (not A_i and B_i and D_i and E_i) or (not B_i and C_i and not D_i and not
E_i));

c_o <= not((not A_i and not B_i and not D_i) or (not A_i and C_i and not E_i)
or (not A_i and C_i and D_i) or (not B_i and C_i and not D_i and not E_i) or (not A_i and
B_i and not C_i and E_i) or (A_i and not B_i and not C_i and D_i) or (not B_i and not C_i
and D_i and not E_i)) ;

d_o <= not((A_i and not B_i and not C_i) or (not B_i and not C_i and E_i) or
(not B_i and not C_i and D_i) or (not A_i and C_i and not D_i and not E_i) or (not A_i and
not B_i and D_i and E_i) or (not A_i and B_i and C_i and not D_i) or (not A_i and B_i and
not D_i and not E_i) or (not A_i and B_i and C_i and not E_i)) ;

e_o <= not((not B_i and not C_i and E_i) or (not B_i and not C_i and D_i) or
(not A_i and not B_i and D_i and E_i) or (not A_i and B_i and not D_i and not E_i) or (not
A_i and B_i and C_i and not E_i)) ;

f_o <= not((not A_i and C_i and D_i) or (not A_i and not B_i and not D_i and
E_i) or (A_i and not B_i and not C_i and D_i) or (not A_i and B_i and C_i and not E_i) or
(not A_i and not C_i and not D_i and E_i) or (not A_i and not B_i and D_i and not E_i)) ;
 g_o <= not((not A_i and not B_i and C_i) or (not A_i and B_i and not C_i and
not D_i) or (not A_i and C_i and D_i and E_i) or (not A_i and not B_i and D_i and E_i) or
(A_i and not B_i and not C_i and not D_i and E_i)) ;

end Behavioral;