1.

DESIGN OF A 4-20mA TRANSMITTER FOR A BRIDGE TYPE

TRANSDUCER.

AIM:
To design the instrumentation ampliIier with the bridge type transducer and convert the
ampliIied voltage Irom the instrumentation ampliIier to 4-20mA current using op-amp.

SOFTWARE REQUIRED:
Or cad

THEORY:
In a number oI industrial and consumer applications physical quantities such as
temperature, pressure and light intensity are to be measured and controlled. These physical
quantities measured with the help oI transducers have to be ampliIied so that it can drive the
display system. This Iunction is perIormed by an instrumentation ampliIier.
The circuit uses a resistive transducer whose resistance changes as a Iunction oI the
physical quantity to be measured. The bridge is initially balanced by a dc supply so that V
1
V
2
.
As the physical quantity changes, the resistance R
T
oI the transducer also changes, causing an
unbalance in the bridge (V
1
=V
2
). This diIIerential voltage gets ampliIied by the three op-amp
diIIerential instrumentation ampliIier. The ampliIied voltage is converted to current using V-I
converter.
The important Ieatures oI instrumentation ampliIier are:
1. igh Gain Accuracy
2. igh CMRR
3. igh Gain Stability With Low Temperature CoeIIicient
4. Low Dc Output
5. igh Output Impedance





DESIGN:
A sensistor is a type oI resistor whose resistance changes with temperature.
Instrumentation AmpliIier:

0
=

2

1
+

(
1
-
2
)
Let V
1
2.3v
V
2
2.5v
V
0
4v
Assume R
'
45k
R 10k
V
0
R
2
/R
1
(190k/10k)(0.2v)
4v R
2
/R
1
(190k/10k)(0.2v)
4 2R
2
/R
1

R
2
/R
1
2.
Let R
1
50k
R
2
100k
V - I Converter:
Let V
0
4v
I
0
8mA
R V
0
/ I
0

R 500O




CIRCUIT DIAGRAM:


PINDIAGRAM of IC741:

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Use PSPICE simulator and run.
3. Note down the input voltages applied to the IA, output voltage oI IA and output current.
4. Vary the resistance value and note down the readings.
5. Plot the variation oI resistance Vs output current.



U5
uA741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2 0
V5
15Vdc
V9
15Vdc
U2
uA741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
U3
uA741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
0
V
R141
5k
2
1
R11
500
2 1
V12
15Vdc

R8
100k
2 1
0
R151
5k
2
1
R20
500
2 1 R4
10k
2
1
R121
5k
2 1
V111
15Vdc
R10
100k
2 1
0
R6
50k
2 1
V
0
0
R5
45k
2
1
0
R131
5.5k
2 1
V115
5Vdc
0
R7
50k
2 1
V
V8
15Vdc
V7
15Vdc
U10
LM741
3
2
7
4
6
1
5
+
-
V
+
V
-
OUT
OS1
OS2
0
V30
15Vdc
0
R3
45k
2
1
V4
15Vdc
0
0
TABULATION:
Sl.No Resistance
(kO)
Input
Voltage
(V
1
) volts
Input Voltage
(V
2
) volts
Output
Voltage
(V
0
)volts
Output
Current
(I
0
)mA






















RESULT:

Thus the instrumentation ampliIier with the bridge type transducer was designed
and the ampliIied voltage was converted to current.


2. AC/DC VOLTAGE REGULATOR USING SCR


AIM:

To construct a phase controlled voltage regulator using Iull wave rectiIier and SCR.


SOFTWARE:

Or Cad

THEORY:


In phase control the Thyristors are used as switches to connect the load circuit to the
input ac supply, Ior a part oI every input cycle. That is the ac supply voltage is chopped using
Thyristors during a part oI each input cycle. The thyristor switch is turned on Ior a part oI every
halI cycle, so that input supply voltage appears across the load and then turned oII during the
remaining part oI input halI cycle to disconnect the ac supply Irom the load. By controlling the
phase angle or the trigger angle - (delay angle), the output RMS voltage across the load can be
controlled. The trigger delay angle - is deIined as the phase angle (the value oI t) at which
the thyristor turns on and the load current begins to Ilow

CIRCUIT DIAGRAM:


R10
1k
2 1

X3
2N1595
0
R7
1k
2 1
V12
5Vdc
V10
FREQ = 1k
VAMPL = 5
VOFF = 0
R9
1k
2
1
D5
D1N4007
X2
2N1595
V
0
V8
FREQ = 1k
VAMPL = 5
VOFF = 0
0
V
GRAPH:





PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Use PSPICE simulator and run.
3. Note down the input voltages applied to the SCR, output voltage and current oI SCR.
4. Plot the Graph.











RESULT:

Thus the phase controlled voltage regulator using Iull wave rectiIier and SCR was
constructed and output was veriIied.


. DESIGN OF PROCESS CONTROL TIMER


AIM:

Design a sequential timer to switch on & oII 3 relays in a particular
sequence using timer IC.


SOFTWARE REQUIRED:

OrCad

THEORY:

The process control is the activities involved in ensuring a process is predictable, stable
and consistently operating at a level(target) oI perIormance with only normal variation. The IC
555 is highly stable device Ior generating accurate time delay oscillations. The process control
timer designed using timer IC555 is operated in either astable or monostable mode. There are
three timers used to trigger the other timers through a switch control. The output oI the next
timer is obtained aIter a delay with respect to the delay in the triggering oI the circuit.


DESIGN:

v
c
V
cc
(1 e
-t/RC
)

At t T, v
c
(2/3) V
cc

ThereIore, T1.1RC

ere, T1.1 ms

Assume C 0.1uF

R

1.1RC


R 10KO








CIRCUIT DIAGRAM:






TABULATION:



Timer 1


Time, t ms

Frequency

Timer 2


Time, t ms

Frequency

Timer 3


Time, t ms

Frequency






0
0
0
V
U9
555alt
1
2
3
4
5
6
7
8
GND
TRGGER
OUTPUT
RESET
CONTROL
THRESHOLD
DSCHARGE
VCC
10k
2
1
R5
1k
2
1
1 2
.1u
1
2
1k
2
1
5Vdc
0
C4
.1u
1
2
.1u
1
2
0
0
0
1 2
0
1 2
U3
555alt
1
2
3
4
5
6
7
8
GND
TRGGER
OUTPUT
RESET
CONTROL
THRESHOLD
DSCHARGE
VCC
.1u 1
2
V
V
10k
2
1
.1u
1
2
V
0
0
0
0
U7
555alt
1
2
3
4
5
6
7
8
GND
TRGGER
OUTPUT
RESET
CONTROL
THRESHOLD
DSCHARGE
VCC
.1u
1
2
.1u
1 2
.1u
1 2
10k
2
1
5Vdc
0
0
1k
2
1
V6
TD = 0
TF = 0
PW = 1m
PER = 2m
V1 = 5
TR = 0
V2 = 0
5Vdc
GRAPH:




PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Use PSPICE simulator and run.
3. Note down the input voltages applied and the output at each stage.
4. Plot the Graph.













RESULT:

Thus a sequential timer was designed to switch on & oII 3 relays in a particular
sequence using timer IC.


4a) AM MODULATOR / DEMODULATOR

AIM:
To construct Amplitude Modulator circuit using multiplier IC and Demodulator circuit
using envelop detector.

SOFTWARE REQUIRED:
OrCad

THEORY:
Modulation is achieved by varying one oI the three parameters, amplitude, Irequency and
phase in accordance with the message signal while keeping the other two parameters as
constant. ence the amplitude is varied in accordance with the instantaneous values oI the
low Irequency signals. The Irequency oI the carrier is much greater than the amplitude oI the
modulating signal to avoid over modulation.

CIRCUIT DIAGRAM:


Modulation Index


0
V2
FREQ = 10k
VAMPL = 5
VOFF = 0
U1
AD633/AD
1
2
3
4
6
7
8
5
X1
X2
Y1
Y2
Z
W
V
+
V
-
C4
.009u 1
2
C3
.1u
1 2
0
V4
15Vdc
V3
15Vdc
0
V1
FREQ = 1k
VAMPL = 5
VOFF = 0
0
R2
50k
2 1
D2
D1N4001
0
0
0
C1
.1u
1 2
0
0

GRAPH:




PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Use PSPICE simulator and run.
3. Note down the input voltages applied and output voltage
4. Also note down the demodulated output.
5. Plot the Graph and calculate the modulation index.











RESULT:
Thus the message signal was modulated and demodulated. The modulation index was
also calculated.
4.b FREQUENCY MODULATION


AIM:

To perIorm the Frequency modulation using IC 566 and to calculate the modulation
index Ior various modulating voltages.


HARDWARE REQUIRED:

Frequency generator, IC NE566, Resistors, Capacitor, CRO, Bread board and connecting
wires, RPS.



THEORY:

Frequency modulation is a process oI changing the Irequency oI a carrier wave in
accordance with the slowly varying base band signal. The main advantage oI this modulation
is that it can provide better discrimination against noise.

Frequency Modulation using IC 566:
A VCO is a circuit that provides an oscillating signal whose Irequency can be adjusted over a
control by Dc voltage. VCO can generate both square and triangular wave signal whose
Irequency is set by an external capacitor and resistor and then varied by an applied DC
voltage. IC 566 contains a current source to charge and discharge an external capacitor C
1
at a
rate set by an external resistor. R
1
and a modulating DC output voltage. The Schmitt trigger
circuit present in the IC is used to switch the current source between charge and discharge
capacitor and triangular voltage developed across the capacitor and the square wave Irom the
Schmitt trigger are provide as the output oI the buIIer ampliIier. The R2 and R3 combination
is a voltage divider, the voltage VC must be in the range 3/4 V
CC
V
C
V
CC
. The
modulating voltage must be less than 3/4V
CC
the Irequency Ic can be calculated using the
Iormula I
o
2 (V
CC
-Vc) R
1
C
1
V
CC.
For a Iixed value oI V
C
and a constant C
1
the Irequency
can be varied at 10:1 similarly Ior a constant R
1
C
1
product value the Irequency modulation
can be done at 10:1 ratio.











CIRCUIT DIAGRAM


PIN DIAGRAM:












GRAPH:

PROCEDURE:

1. The circuit connection is made as shown in the circuit diagram.
2. The modulating signal FM is given Irom a FG (1K)
3. For various values oI modulating voltage Vm the values oI Fmax and Fmin are
noted.
4.The values oI the modulation index are calculated.











RESULT:

Thus the FM circuit using IC566 was perIormed and the modulation index was Iound.



5. DESIGN OF FSK MODULATOR USING XR 2206

AIM:
To design a FSK Modulator using XR 2206.

COMPONENTS REQUIRED:
IC XR 2206, Resistors, Capacitors.

THEORY:
In digital data communication, binary code is transmitted by shiIting the carrier
Irequency between two preset Irequencies. This type oI the transmission is called Frequency
ShiIt Keying. The standard digital data input Irequency is 150.
Modem takes the digital electrical pulses Irom the terminal and converts it into the
analog signal that can be transmitted. The FSK technique is employed Ior the modulation oI
digital Signal.


CIRCUIT DIAGRAM:









GRAPH:






PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Give the message signal.
3. Check the output and veriIy.
4. Switch oII the input to Iind the carrier Irequency.
5. Plot the graph Ior input and output.
RESULT:
Thus a FSK was implemented using XR2206 and veriIied the results





6. PCB LAYOUT DESIGN USING CAD

AIM:

To draw the schematic oI simple electronic circuit and design a PCB layout using CAD

SOFTWARE REQUIRED:
OrCad

THEORY:

The Computer Aided analysis is essential and can provide inIormation about the
circuit perIormances. It permits.
Evaluation oI eIIects oI variation in elements such as resistors, transistors etc.
The assessment oI perIormance improvements or degradations.
Evaluation oI the eIIects oI noise and signal distortion without the need oI
expensive measuring instruments.
Sensitivity analysis to determine the permissible bounds due to the tolerances on
each and every element value or parameter oI active elements.
Evaluation oI the eIIects oI non-linear elements oI the circuit perIormance.
Optimiation oI the design oI electronic circuits in terms oI circuit parameters.

CIRCUIT DIAGRAM:
Cascode AmpliIier:



C107A
5u
1 2
51k
2
1
0
5u
1 2
0
25k
2
1
V3
FREQ = 1k
VAMPL = 200m
VOFF = 0
Q2
C107A
10u
1 2
0
3.3k
2
1
90k
2
1
.7k
2
1
14k
2
1
9Vdc
0
20u
1
2
OUTPUT LAYERS:

Global Layer


Top Layer


Bottom Layer


PROCEDURE:
1. Draw the circuit diagram using Pspice and get the simulated output.
2. Create .mnl Iile
Select the required Iile
Go to tools and select create netlist
Click Layout Irom the dialog box appearing and give OK.
Note the path in which the .mnl Iile is created.
3. To create PCB Design
Open OrCad Layout Plus
Make the data oI OrCad Layout Plus to deIault
Take the .mnl Iile and save it.
Select the obstacle Irom tools and select all the components.
Auto Place Board
Auto Auto route Board
View the Global Layer.
View the individual layers by selecting tools, layer. Give backspace and select the
layers.










RESULT:
Thus a schematic oI cascode ampliIier circuit was designed and a PCB layout
using CAD was obtained

7. PSUEDO-RANDOM SEQUENCE GENERATOR

AIM:
To stimulate and implement a PRBS Generator.

SOFTWARES REQUIRED:
PC with Xilinx ISE SoItware 9.1i

PROGRAM:

Simulation
module prbs(rand,clk,reset);
input clk,reset;
output rand;
wire rand;
reg |3:0|temp;
always (posedge reset)
begin
temp4hI;
end
always (posedge clk)
begin
iI(~reset)
begin
temptemp|0|`temp|1|,temp|3|,temp|2|,temp|1|};
end
end
assign rand temp|0|;
endmodule

Test Bench
module prbstest();
reg clk,reset;
wire rand;
prbs p1(rand,clk,reset);
initial
begin
Iorever begin
clk0;
#5 clk1;
#5 clk0;
end
end
initial
begin
reset1;
#12 reset0;
#90 reset1;
#12 reset0;
end
endmodule











PROCEDURE:
1. Write the coding.
2. Use Xilinx ISE simulator and run.
3. Note the output and veriIy.





















RESULT:
Thus a PRBS Generator is simulated in Verilog and implemented using Spartan3 FPGA
kit.


.MICROCONTROLLER BASED SYSTEM DESIGN
EXPT NO:

AIM:
To interIace a stepper motor with 8051 micro controller and operate it.
APPARATUS REQUIRED:
1.8051 micro controller kit
2. Stepper motor
3. InterIace card
THEORY:
A motor in which the rotor is able to assume only discrete stationary angular position is a
stepper motor. They are used in printer, disk drive process control machine tools etc.
Two-phase stepper motor has two pairs oI stator poles. Stepper motor windings A1, A2,
B1, B2 are cyclically excited with a DC current to run the motor in clockwise direction and
reverse phase sequence A1, B2, A2, B1 in anticlockwise stepping
Two-phase switching scheme:
In this scheme, any two adjacent stator windings are energied.

Anticlockwise Clockwise
Step A1 A2 B1 B2 Data Step A1 A2 B1 B2 Data
1 1 0 0 1 9 1 1 0 1 0 A
2 0 1 0 1 5 2 0 1 1 0 6
3 0 1 1 0 6 3 0 1 0 1 5
4 1 0 1 0 A 4 1 0 0 1 9



Address Decoding logic:

The 74138 chip is used Ior generating the address decoding logic to generate the device
select pulses CS1 and CS2 Ior selecting the IC 74175 in which latches the data bus to stepper
motor driving circuitry.
PROGRAM:

Address Opcode Label Mnemonics


Operand Comments
4100 90 41 1F START MOV DPTR #
TABLE
Load the start
address oI switching
scheme data
TABLE into Data
pointer.
4103 78 04 MOV R0, #04 Load the count in R0
4105 F0 LOOP MOV X A, DPTR Load the number in
TABLE into A
4106 C0 83 PUS DP Push DPTR Value to
stack
4108 C0 82 PUS DPL
410A 90 FF C0 MOV DPTR, #
0FFFC0
Load the motor port
address into DPTR.
410D F0 MOV X DPTR, A Send the value in A
to stepper motor port
address
410F 7C FF MOV R4,#0FF Delay loop to cause
a speciIic amount oI
time delay beIore
next data item is sent
to the motor
4110 7D FF DELAY MOV R5,#0FF
4112 DD FE DELAY1 DN R4, DELAY
1

4114 DC FA DJN R4,DELAY
4116 D0 82 POP DPL POP back DPTR
value Irom stack
4118 D0 83 POP DP
411A A3 INC DPTR Increment DPTR to
point to next item in
the TABLE
411B D8 E8 DJN R0, LOOP Decrement R0, iI not
ero repeat the loop
411D 80 E1 SJMP START Short jump to start
oI the program to
make the motor
rotate continuosly.
411F 09 05 06
0A
TABLE DB 09 05 06
0A
Value as per two
phase switching
scheme.





RESULT:

Enter the above program starting Irom location 4100 and execute the same, stepper motor
rotates. Varying the count at R4 and R5 can vary the speed. Entering the data in the look-up
TABLE in the reverse order can vary the direction oI rotation.
. SIMULATION OF ALU USING XILINX

AIM:
To stimulate and implement an ALU using Xilinx.

SOFTWARES REQUIRED:
PC with Xilinx ISE SoItware 9.1i ,

PROGRAM:
module ALU(out,Ilag,sel,clear,a,b);
output reg |3:0|out,Ilag;
input |3:0|a,b,sel;
input clear;
reg |4:0|t;
reg c,s,p,;
always (a or b or sel or clear)
begin
iI(~clear)
begin
t0;
c0;
s0;
p0;
0;
Ilag0;
end
else
begin
iI(sel|3|1'b0)
begin
case(sel|2:0|)
3'b000: begin tab; iI(t|4|1) c1; else c0; end
3'b001: begin ta-b; iI(t|4|1) c1; else c0; end
3'b010: ta|1:0|*b|1:0|;
deIault t9'b0;
endcase
iI(a|3|`b|3|) s1; else s0; end
else
begin case(sel|2:0|)
3'b000:ta,b;
3'b001:ta&b;
3'b010:ta`b;
3'b011:t(~a),(~b);
3'b100:t(~a)&(~b);
3'b101:ta~`b;
3'b110:t~a;
3'b111:t~b;
endcase
end
end
end
always (a or b or sel or clear)
begin
outt|3:0|;
pout|0|out|1|out|2|out|3|;
iI (t0) 1; else 0;
assign Ilag|0|p;
assign Ilag|1|s;
assign Ilag|2|c;
assign Ilag|3|;
end
endmodule

PROCEDURE:

1. Write the coding.
2. Use Xilinx ISE simulator and run.
3. Note the output and veriIy.






















RESULT:

Thus a ALU is simulated in Verilog and implemented using Spartan3 FPGA kit


10.DSP BASED DIGITAL FUNCTION GENERATOR

AIM
1o sLlmulaLe a slmple pulse generaLor uslng AuS2181 uS processor
AAkA1US kLUIkLD
1 AuS2181 unlL
2 AuS 2181 unlversal
3 C8C
4 l8M C keyboard

1nLCk
AuS 2181 ls hlghly advanced uS processor whlch works of on chlp serlal porL lL ls
capable of processlng 16blL arlLhmeLlc operaLlon wlLh ALu and AccumulaLor 1hls AuS2181 ls
sulLable for developlng appllcaLlons llke adapLlve fllLerlng lL1 exLernal preclslon arlLhmeLlc
eLcln Lhls experlmenL a slmple pulse generaLor ls sLlmulaLed uslng AuS2181
ln order Lo develop Lhls appllcaLlon l8M C keyboard ls connecLed Lo AuS2181Lhrough
Lhe lC porL of oxo2
1he l8M C keyboard up arrow ls used Lo lncrease Lhe ampllLude of Lhe pulse wave
down arrow ls used Lo decrease Lhe ampllLude lefL arrow ls used Lo decrease Lhe frequency
and rlghL arrow ls used Lo lncrease Lhe frequency
kC8LLM S1A1LMLN1
1 uSlnC AuS2181 generaLe Lhe square wave and measure Lhe ampllLude of Lhe
square wave and frequency
2 ldenLlfy scan codes for Lhe up arrow down arrow rlghL and lefL arrow by readlng
Lhe lC porL Lhrough whlch l8M C keyboard ls connecLed Lo Lhe lC porL of AuS2181
3 llnd Lhe sulLable loglc and wroLe a program Lo lncrease and decrease Lhe ampllLude
of square wave uslng C8C





FLOWCHART
























S1A81
Store the counter value in
memory
SLore v
max
and v
mln
ln reglsLer ay0
ay1
SeL v
max
Lo uAC porL
Apply delay
Send v
mln
Lo uAC porL
8ead keyboard porL
ress any arrow key
lf keyboard ls
u arrow
8
lncrease v
max
by 1
A






?es

















8
lf keyboard
ls down
uecrease v
max
by 1
Decrease
memory location
value
Increase memory
location value
lf keyboard ls
rlghL arrow
0x0074
lf keyboard ls
lefL arrow
0x0068
A
A
A
A
kCGkAM

module /ram maln _rouLlne
sLarL
ay0 0xfff max peak volLage
beg cnLr 0xfff delay counLer
do lnL unLll ce
axo 0x0000
lnL lo(0x14) ay0send max peak Lo uAC
ax1lo(0x102)read keyboard porL
dm(0x103) ax1 sLore Lhe scan cade for Lhe pressed key
ay1 0x0ff max upper byLes
arax1 and ay1
ax1ar
ay10x0073scan code for up arrow key
arax1ay1 do camparlslon
dm(0x103)ar
lf ne [ump beglf noL equal repeaL Lhe same square wave
ay ay0+1lf equal lncrease Lhe max peak volLage repeaL Lhe square wave
ay0ar
dm(0x106)ay0
[ump beg
ldle
end mod
LkLkCISL
ln Lhe glven program pulse generaLor ls sLlmulaLed only uslng up arrow key so Lhe
sLudenLs lnsLrucLed Lo sLlmulaLe Lhe same uslng down arrow lefL arrow rlghL arrow kkeys by
ldenLlfylng Lhe key codes
kCGkAM
module /ram maln_rouLlne
sLarL
ay0 0xfffmax peak volLage
ax1 0xff
dm(0x107)ax1
beg cnLr dm(0x107)delay counLer
do lnL unLll ce
ax00x0000
lnL lo(0x14) ax0 send mlnlmum peak Lo uAC
cnLr dm(0x107)
do lcL unLll ce
lcL lo(0x14)ay0send maxlmum peak Lo uAC
ax1lo(0x102) read keyboard porL
dm(ox103)ax1sLore scan code for pressed key
ay1ox0ff
arax1 and ay1
ax1 ar
ay10x0073scan code for up arrow key
arax1 ay1do comparlslon
dm(0x103)ar
lf ne [ump aaalf noL equal check for anoLher key
aray0+1 lncrease ampllLude
ay0ar
dm(0x106)ay0
[ump beg
aaa
ay10x0072scan code for down arrow key
arax1ay1do comparlslon
dm(0x108)ar
lf ne [ump bbblf noL equal check for anoLher key
aray01 decrease ampllLude
ay0ar
dm(0x106)ay0
[ump beg
bbb ay10x0072scan code for rlghL arrow key
arax1ay1do comparlslon
dm(0x109)ar
lf ne [ump ccclf noL equal check for anoLher key
ax1dm(0x107)
arax1+3 decrease frequency
dm(0x107)ar
[ump beg
ccc ay10x0074scan code for lefL arrow key
arax1ay1do comparlslon
dm(0x110)ar
lf ne [ump beglf noL equal check for anoLher key
ax1dm(0x107)
arax13 lncrease frequency
dm(0x107)ar
[ump beg
ldle
end mod
1A8ULA1ICN CCLUMN
AMLl1uuL
( v)
1lML L8lCu
(MS)





SCuA8L WAvL






1
Cn




1
Cll







MCDLL GkAn






v
vCL1S


1 msec









kLSUL1

1hus Lhe square wave ls generaLed uslng AuS2181 uS
Alu
nL1s0 LCCp6
nL1s1 LCCp18
nL1c0 LCCp24
nL1loglc_unlL LCCp36
nL1A0 LCCp38
nL1A1 LCCp41
nL180 LCCp69
nL181 LCCp78
nL1d_ouL10 LCCp33
nL1d_ouL11 LCCp34
module loglc_unlL(d_ouL1loglc_unlLs0s1c0A8)
ouLpuL 10 d_ouL1
lnpuL s0s1c0loglc_unlL
lnpuL 10 A
lnpuL 10 8
reg 10 d_ouL1
always [(s0s1A8loglc_unlL)
begln
lf(loglc_unlL 1b1)
begln
lf(s0 1b0 s1 1b0)
begln
d_ouL1 ( A 8)
end
else lf(s0 1b1 s1 1b0)
begln
d_ouL1 ( A | 8)
end
else lf(s0 1b0 s1 1b1)
begln
d_ouL1 ( A 8)
end
else
begln
d_ouL1 ( A 8)
end
end
else
begln
d_ouL1 4b00
end
end
endmodule