AV Mathematics-III for EC Engineering Semester 3

Course Code BMATEC301 CIE Marks 50

Teaching Hours/Week (L:T:P: S) 3:0:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 03
Examination type (SEE) Theory
Course objectives:
● Learn to use the Fourier series to represent periodical physical phenomena in
engineering analysis and to enable the student to express non-periodic functions to
periodic functions using the Fourier series and Fourier transforms.
● Analyze signals in terms of Fourier transforms
● Develop the knowledge of solving differential equations and their applications in
Electronics & Communication engineering.
● To find the association between attributes and the correlation between two variables
Teaching-Learning Process
Pedagogy (General Instructions):
These are sample Strategies, teachers can use to accelerate the attainment of the various course
outcomes.
1. In addition to the traditional lecture method, different types of innovative teaching methods
may be adopted so that the delivered lessons shall develop students’ theoretical and applied
Mathematical skills.
2. State the need for Mathematics with Engineering Studies and Provide real-life examples.
3. Support and guide the students for self–study.
4. You will assign homework, grading assignments and quizzes, and documenting students'
progress.
5. Encourage the students to group learning to improve their creative and analytical skills.
6. Show short related video lectures in the following ways:
● As an introduction to new topics (pre-lecture activity).
● As a revision of topics (post-lecture activity).
● As additional examples (post-lecture activity).
● As an additional material of challenging topics (pre-and post-lecture activity).
● As a model solution of some exercises (post-lecture activity).

Module-1: Fourier series and practical harmonic analysis

Periodic functions, Dirichlet’s condition. Fourier series expansion of functions with period 2𝜋
and with arbitrary period: periodic rectangular wave, Half-wave rectifier, rectangular pulse,
Saw tooth wave. Half-range Fourier series. Triangle and half range expansions, Practical
harmonic analysis, variation of periodic current.(8 hours)
(RBT Levels: L1, L2 and L3)
Module-2: Infinite Fourier Transforms
Infinite Fourier transforms, Fourier cosine and sine transforms, Inverse Fourier transforms,
Inverse Fourier cosine and sine transforms, discrete Fourier transform (DFT), Fast Fourier
transform (FFT). (8 hours)
(RBT Levels: L1, L2 and L3)
Module-3: Z Transforms
Definition, Z-transforms of basic sequences and standard functions. Properties: Linearity,
scaling, first and second shifting, multiplication by n. Initial and final value theorem. Inverse
Z- transforms. Application to difference equations. (8 hours)
(RBT Levels: L1, L2 and L3)

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 Module-4: Ordinary Differential Equations of Higher Order
Higher-order linear ODEs with constant coefficients - Inverse differential operator,
problems.Linear differential equations with variable Coefficients-Cauchy’s and Legendre’s
differential equations–Problems. Application of linear differential equations to L-C circuit and
L-C-R circuit.(8 hours)
(RBT Levels: L1, L2 and L3)
Module-5: Curve fitting, Correlation, and Regressions
Principles of least squares, Curve fitting by the method of least squares in the form
𝑦 = 𝑎 + 𝑏𝑥 , 𝑦 = 𝑎 + 𝑏𝑥 + 𝑐𝑥 2 , and 𝑦 = 𝑎𝑥 𝑏 . Correlation, Coefficient of correlation, Lines
of regression, Angle between regression lines, standard error of estimate, rank correlation.
(RBT Levels: L1, L2 and L3)(8 hours)
Course outcome (Course Skill Set)
At the end of the course, the student will be able to:
1. Demonstrate the Fourier series to study the behavior of periodic functions and their
applications in system communications, digital signal processing, and field theory.
2. To use Fourier transforms to analyze problems involving continuous-time signals
3. To apply Z-Transform techniques to solve difference equations
4. Understand that physical systems can be described by differential equations and solve
such equations
5. Make use of correlation and regression analysis to fit a suitable mathematical model for
statistical data
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam
(SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20
marks out of 50) and for the SEE minimum passing mark is 35% of the maximum marks (18
out of 50 marks). The student is declared as a pass in the course if he/she secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and
SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
● There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment
Test component.
● Each test shall be conducted for 25 marks. The first test will be administered after 40-50%
of the coverage of the syllabus, and the second test will be administered after 85-90% of the
coverage of the syllabus. The average of the two tests shall be scaled down to 25 marks
● Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based
then only one assignment for the course shall be planned. The schedule for assignments
shall be planned properly by the course teacher. The teacher should not conduct two
assignments at the end of the semester if two assignments are planned. Each assignment
shall be conducted for 25 marks. (If two assignments are conducted then the sum of the two
assignments shall be scaled down to 25 marks)
● The final CIE marks of the course out of 50 will be the sum of the scale-down marks of
tests and assignment/s marks.

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 Internal Assessment Test question paper is designed to attain the different levels of
Bloom’s taxonomy as per the outcome defined for the course.
Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common
question papers for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module
(with a maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored shall be proportionally reduced to 50 marks.
Suggested Learning Resources:
Books (Name of the author/Title of the Book/Name of the publisher/Edition and Year)
Text Books:
1. B. S. Grewal: “Higher Engineering Mathematics”, Khanna Publishers, 44thEd., 2021.
2. E. Kreyszig: “Advanced Engineering Mathematics”, John Wiley & Sons, 10thEd., 2018.

Reference Books:
1. V. Ramana: “Higher Engineering Mathematics” McGraw-Hill Education, 11thEd., 2017
2. Srimanta Pal & Subodh C.Bhunia: “Engineering Mathematics” Oxford University Press,
3rdEd., 2016.
3. N.P Bali and Manish Goyal: “A Textbook of Engineering Mathematics” Laxmi
Publications, 10thEd., 2022.
4. C. Ray Wylie, Louis C. Barrett: “Advanced Engineering Mathematics” McGraw–Hill
Book Co., New York, 6thEd., 2017.
5. Gupta C.B, Sing S.R and Mukesh Kumar: “Engineering Mathematic for Semester I and
II”, McGraw Hill Education(India) Pvt. Ltd 2015.
6. H.K. Dass and Er. Rajnish Verma: “Higher Engineering Mathematics” S.Chand
Publication, 3rdEd.,2014.
7. James Stewart: “Calculus” Cengage Publications, 7thEd., 2019.
Web links and Video Lectures (e-Resources):
• http://nptel.ac.in/courses.php?disciplineID=111
• http://www.class-central.com/subject/math(MOOCs)
• http://academicearth.org/
• VTU e-Shikshana Program
• VTU EDUSAT Program.

Activity-Based Learning (Suggested Activities in Class)/Practical-Based Learning

• Quizzes
• Assignments
• Seminar

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 Digital System Design using Verilog Semester 3
Course Code BEC302 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours 03
Examination nature (SEE) Theory/Practical
Course objectives:
This course will enable students to:
 To impart the concepts of simplifying Boolean expression using K-map techniques and Quine-
McCluskey minimization techniques.
 To impart the concepts of designing and analyzing combinational logic circuits.
 To impart design methods and analysis of sequential logic circuits.
 To impart the concepts of Verilog HDL-data flow and behavioural models for the design of digital
systems.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teacher can use to accelerate the attainment of the various course
outcomes.
 Lecture method (L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
 Show Video/animation films to explain the different concepts of Linear Algebra & Signal
Processing.
 Encourage collaborative (Group) Learning in the class.
 Ask at least three HOTS (Higher order Thinking)questions in the class, which promotes
critical thinking.
 Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather than
simply recall it.
 Topics will be introduced in a multiple representation.
 Show the different ways to solve the same problem and encourage the students to come up
with their own creative ways to solve them.
 Discuss how every concept can be applied to the real world-and when that's possible, it
helps improve the students' understanding.
 Adopt Flipped class technique by sharing the materials/Sample Videos prior to the class and
have discussions on the topic in the succeeding classes.
 Give Programming Assignments.
MODULE-1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms,
Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, Quine-
McCluskey Minimization
Technique. Quine-McCluskey using Don’t CareTerms.(Section3.1to3.5ofText1).
MODULE-2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and
Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices(PLDs)
(Section5.1to5.7 ofText2)
MODULE-3

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 Flip-Flops and its Applications: The Master-Slave Flip-flops(Pulse-Triggered flip-flops):SR flip-
flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous
Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using
clocked T, J K, D and SR flip-flops.(Section 6.4, 6.6 to 6.9 (Excluding 6.9.3)of Text2)
MODULE-4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of
Description. (Section1.1to1.6.2, 1.6.4 (only Verilog),2 of Text 3)
Verilog Data flow description: Highlights of Data flow description, Structure of Data flow
description.(Section2.1to2.2(only Verilog) of Text3)
MODULE-5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential
Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1).
(Section 3.1 to 3.4 (onlyVerilog)of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of structural
description, Structural description of ripple carry adder.(Section4.1 to 4.2 of Text 3)

PRACTICAL COMPONENT OF IPCC (Experiments can be conducted either using any circuit simulation
software or discrete components)

Sl.N Experiments
1 To simplify the given Boolean expressions and realize using Verilog program
2 To realize Adder/Subtractor(Full/half)circuits using Verilog data flow description.
3 To realize 4-bit ALU using Verilog program.
4 To realize the following Code converters using Verilog Behavioral description
a)Gray to binary and vice versa b)Binary to excess3 and vice versa
5 To realize using Verilog Behavioral description:8:1mux, 8:3encoder, Priority encoder
6 To realize using Verilog Behavioral description:1:8Demux, 3:8 decoder,2 –bit Comparator
7 To realize using Verilog Behavioral description:
Flip-flops: a)JK type b)SR type c)T type and d)D type
8 To realize Counters-up/down (BCD and binary)using Verilog Behavioral description.
Demonstration Experiments (For CIE only–not to be included for SEE)
Use FPGA/CPLD kits for down loading Verilog codes and check the output for interfacing
experiments.
9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor
in the specified direction (by N steps).
10 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate
its working.
Course outcomes (Course Skill Set):
At the end of the course the student will be able to:
1. Simplify Boolean functions using K-map and Quine-McCluskey minimization technique.
2. Analyze and design for combinational logic circuits.
3. Analyze the concepts of Flip Flops(SR, D,T and JK) and to design the synchronous sequential
circuits using Flip Flops.
4. Model Combinational circuits (adders, subtractors, multiplexers) and sequential circuits using
Verilog descriptions.

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 Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50)
and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The
student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100)
in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination)
taken together.
The IPCC means the practical portion integrated with the theory of the course. CIE marks for the
theory component are 25 marks and that for the practical component is 25 marks.
CIE for the theory component of the IPCC
 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests
(Two Tests, each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other
assessment methods mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the
syllabus and the second test after covering 85-90% of the syllabus.
 Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for
the theory component of IPCC (that is for 25 marks).
 The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of
IPCC.
CIE for the practical component of the IPCC
 15 marks for the conduction of the experiment and preparation of laboratory record, and 10
marks for the test to be conducted after the completion of all the laboratory sessions.
 On completion of every experiment/program in the laboratory, the students shall be evaluated
including viva-voce and marks shall be awarded on the same day.
 The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks
of all experiments’ write-ups are added and scaled down to 15 marks.
 The laboratory test (duration 02/03 hours) after completion of all the experiments shall be
conducted for 50 marks and scaled down to 10 marks.
 Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 25 marks.
 The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the
IPCC.

SEE for IPCC

Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by the student shall be proportionally scaled down to 50 Marks

The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion
will have a CIE component only. Questions mentioned in the SEE paper may include questions
from the practical component.
 The minimum marks to be secured in CIE to appear for SEE shall be 10 (40% of maximum
marks-25) in the theory component and 10 (40% of maximum marks -25) in the practical
component. The laboratory component of the IPCC shall be for CIE only. However, in SEE,
the questions from the laboratory component shall be included. The maximum of 04/05 sub-
questions are to be set from the practical component of IPCC, the total marks of all questions

@#12102023 EC(ACT) 30042024

 should not be more than 20 marks.
 SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to
qualify for the SEE. Marks secured will be scaled down to 50.
 The student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks
out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester
End Examination) taken together.
Suggested Learning Resources:
Books
1. Digital Logic Applications and Design by John MYarbrough,Thomson Learning,2001.
2. Digital Principles and Design by Donald DGivone,McGrawHill, 2002.
3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dream techpress.
ReferenceBooks:
1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning
2. Logic Design, by Sudhakar Samuel, Pearson/Sanguine, 2007
3. Fundamentals of HDL,by Cyril PR, Pearson/Sanguine2010
Web links and Video Lectures (e-Resources):

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Programming Assignments/Mini Projects can be given to improve programming skills.

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 TEMPLATE for IPCC (26.04.2022) Annexure-III

Electronic Principles and Circuits Semester 3

Course Code BEC303 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours
Examination nature (SEE) Theory/Practical/Viva-Voce /Term-work/Others
Course objectives:
This course will enable students to
 Design and analyse the BJT circuits as an amplifier and voltage regulation.
 Design of MOSFET Amplifiers and analyse the basic amplifier configurations using small signal equivalent
circuit models
 Design of operational amplifiers circuits as Comparators, DAC and filters.
 Understand the concept of positive and negative feedback.
 Analyze Power amplifier circuits in different modes of operation.
 Construct Feedback and Oscillator circuits using FET.
 Understand the thyristor operation and the different types of thyristors.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teacher can use to accelerate the attainment of the various course outcomes.
1. Lecture method (L) does not mean only traditional lecture method, but different type of teaching methods may
be adopted to develop the outcomes.
2. Show Video/animation films to explain evolution of communication technologies.
3. Encourage collaborative (Group) Learning in the class
4.Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes critical thinking
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking skills such as
the ability to evaluate, generalize, and analyze information rather than simply recall it.
6. Show the different ways to solve the same problem and encourage the students to come up with their own
creative ways to solve them.
7. Discuss how every concept can be applied to the real world - and when that's possible, it helps improve the
students' understanding.

MODULE-1
Transistor Biasing: Voltage Divider Bias, VDB Analysis, VDB Load line and Q point, Two supply Emitter Bias,
Other types of Bias.
BJT AC models: Base Biased Amplifier, Emitter Biased Amplifier, Small Signal Operation, AC Beta, AC Resistance
of the emitter diode, Two transistor models, Analyzing an amplifier, H parameters, Relations between R and H
parameters.
Voltage Amplifiers: Voltage gain, Loading effect of Input Impedance.
CC Amplifiers: CC Amplifier, Output Impedance.
[Text1]

MODULE-2
MOSFET
Biasing in MOS amplifier circuits: Fixing VGS, Fixing VG, Drain to Gate feedback resistor.
Small signal operation and modelling: The DC bias point, signal current in drain, voltage gain, small signal
equivalent circuit models, transconductance, The T equivalent circuit model.
MOSFET Amplifier configuration: Basic configurations, characterizing amplifiers, CS amplifier with and
without source resistance, The Common Gate Amplifier, Source follower.
[Text 2]

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 TEMPLATE for IPCC (26.04.2022) Annexure-III

MODULE-3

Linear Opamp Circuits: Summing Amplifier and D/A Converter, Nonlinear Op-amp Circuits: Comparator with
zero reference, Comparator with non-zero references. Comparator with Hysteresis.
Oscillator: Theory of Sinusoidal Oscillation, The Wein-Bridge Oscillator, RC Phase Shift Oscillator, The Colpitts
Oscillator, Hartley Oscillator, Crystal Oscillator.
The 555 timer: Monostable Operation, Astable Operation.
[Text1]
MODULE-4
Negative Feedback: Four Types of Negative Feedback, VCVS Voltage gain, Other VCVS Equations, ICVS
Amplifier, VCIS Amplifier, ICIS Amplifier (No Mathematical Derivation).
Active Filters: Ideal Responses, First Order Stages, VCVS Unity Gain Second Order Low pass Filters, VCVS Equal
Component Low Pass Filters, VCVS High Pass Filters, MFB Bandpass Filters, Bandstop Filters.
[Text1]

MODULE-5
Power Amplifiers: Amplifier terms, Two load lines, Class A Operation, Class B operation, Class B push pull
emitter follower, Class C Operation.
Thyristors: The four layer Diode, SCR, SCR Phase control, Bidirectional Thyristors, IGBTs, Other Thyristors.
[Text1]

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 TEMPLATE for IPCC (26.04.2022) Annexure-III

PRACTICAL COMPONENT OF IPCC (Experiments can be conducted either using any circuit simulation
software or discrete components)
Sl.NO Experiments
1 Design and Test
(i) Bridge Rectifier with Capacitor Input Filter
(ii) Zener voltage regulator

2 Design and Test

Biased Clippers – a)Positive, b) Negative , c) Positive-Negative
Positive and Negative Clampers with and without Reference.
3 Plot the transfer and drain characteristics of a JFET and calculate its drain resistance, mutual conductance
and amplification factor.

4 Plot the transfer and drain characteristics of n-channel MOSFET and calculate its parameters, namely;
drain resistance, mutual conductance and amplification factor.

5
Design and test Emitter Follower

6
Design and plot the frequency response of Common Source JFET/MOSFET amplifier

7
Test the Opamp Comparator with zero and non zero reference and obtain the Hysteresis curve.

8
Design and test Full wave Controlled rectifier using RC triggering circuit.

9 Design and test Precision Half wave and full wave rectifiers using Opamp

10 Design and test RC phase shift oscillator

Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:
1. Understand the characteristics of BJTs and FETs for switching and amplifier circuits.
2. Design and analyze amplifiers and oscillators with different circuit configurations and biasing conditions.
3. Understand the feedback topologies and approximations in the design of amplifiers and oscillators.
4. Design of circuits using linear ICs for wide range applications such as ADC, DAC, filters and timers.
5. Understand the power electronic device components and its functions for basic power electronic circuits.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a pass in the course if
he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal
Evaluation) and SEE (Semester End Examination) taken together.

The IPCC means the practical portion integrated with the theory of the course. CIE marks for the theory component
are 25 marks and that for the practical component is 25 marks.
CIE for the theory component of the IPCC
 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests (Two Tests,
each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other assessment methods
mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the syllabus and the second test after
covering 85-90% of the syllabus.

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 TEMPLATE for IPCC (26.04.2022) Annexure-III

 Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for the theory
component of IPCC (that is for 25 marks).
 The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of IPCC.
CIE for the practical component of the IPCC

 15 marks for the conduction of the experiment and preparation of laboratory record, and 10 marks for the
test to be conducted after the completion of all the laboratory sessions.
 On completion of every experiment/program in the laboratory, the students shall be evaluated including viva-
voce and marks shall be awarded on the same day.
 The CIE marks awarded in the case of the Practical component shall be based on the continuous evaluation of
the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of all experiments’ write-
ups are added and scaled down to 15 marks.
 The laboratory test (duration 02/03 hours) after completion of all the experiments shall be conducted for 50
marks and scaled down to 10 marks.
 Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory component of
IPCC for 25 marks.
 The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the IPCC.
SEE for IPCC
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for the
course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum of 3
sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by the student shall be proportionally scaled down to 50 Marks
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will have a CIE
component only. Questions mentioned in the SEE paper may include questions from the practical
component.
 The minimum marks to be secured in CIE to appear for SEE shall be 10 (40% of maximum marks-25) in the
theory component and 10 (40% of maximum marks -25) in the practical component. The laboratory
component of the IPCC shall be for CIE only. However, in SEE, the questions from the laboratory
component shall be included. The maximum of 04/05 sub-questions are to be set from the practical
component of IPCC, the total marks of all questions should not be more than 20 marks.
 SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to qualify for
the SEE. Marks secured will be scaled down to 50.

 The student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100)
in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken
together.

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 TEMPLATE for IPCC (26.04.2022) Annexure-III

Suggested Learning Resources:

Books
1. Albert Malvino, David J Bates, Electronic Principles, 7 th Edition, Mc Graw Hill Education, 2017, ISBN:978-0-
07-063424-4.
2. Microelectronic Circuits, Theory and Applications, Adel S Sedra, Kenneth C Smith, 6thEdition, Oxford,
2015.ISBN:978-0-19-808913-1

Web links and Video Lectures (e-Resources):

1. Integrated Electronics: Analog and Digital Circuits and Systems, Jacob Millman, Christos C. Halkias,
McGraw-Hill, 2015.
2. Electronic Devices and Circuit, Boylestad & Nashelsky, Eleventh Edition, Pearson, January 2015.

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

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 Network Analysis Semester 3
Course Code BEC304 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 3
Examination type (SEE) Theory
Course objectives:
1. Apply mesh and nodal techniques to solve an electrical network.
2. Solve different problems related to Electrical circuits using Network Theorems and Two
port network.
3. Familiarize with the use of Laplace transforms to solve network problems.
4. Study two port network parameters and their applications.
5. Study of RLC Series and parallel tuned circuit.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various
course outcomes.
These are sample Strategies, which teacher can use to accelerate the attainment of the various
course outcomes.
 Lecture method (L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
 Encourage collaborative (Group)Learning in the class.
 Ask at least three HOTS(Higher order Thinking)questions in the class, which
promotes critical thinking.
 Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather
than simply recall it.
 Topics will be introduced in a multiple representation.
 Show the different ways to solve the same problem and encourage the students to
come up with their own creative ways to solve them.
 Discuss how every concept can be applied to the real world-and when that's possible,
it helps improve the students' understanding.
 Adopt Flipped class technique by sharing the materials/Sample Videos prior to the class
and have discussions on the topic in the succeeding classes.

Module-1
Basic Concepts: Practical sources, Source transformations, Network reduction using Star -
Delta transformation, Loop and node analysis with linearly dependent and independent
sources for DC and AC networks.
Module-2
Network Theorems: Superposition, Millman's theorems, Thevenin's and Norton's
theorems, Maximum Power transfer theorem.
Module-3
Transient behavior and initial conditions: Behavior of circuit elements under switching
condition and their Representation, evaluation of initial and final conditions in RL, RC and

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 RLC circuits for AC and DC excitations.

Module-4
Laplace Transformation &Applications: Solution of networks, step, ramp and impulse
responses, waveform Synthesis.
Module-5
Two port network parameters: Definition of Z,Y, h and Transmission parameters, modelling
with these parameters, relationship between parameters sets.
Resonance:
Series Resonance: Variation of Current and Voltage with Frequency,
SelectivityandBandwidth,Q-Factor,CircuitMagnificationFactor,Selectivity with Variable
Capacitance, Selectivity with Variable Inductance.
Parallel Resonance: Selectivity and Bandwidth, Maximum Impedance Conditions with C,
Land f Variable, current in Anti-Resonant Circuit, The General Case-Resistance Present in
both Branches.

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Determine currents and voltages using source transformation/ source shifting/ mesh/
nodal analysis and reduce given network using star- delta transformation.
2. Solve problems by applying Network Theorems and electrical laws to reduce circuit
complexities and to arrive at feasible solutions.
3. Analyse the circuit parameters during switching transients and apply Laplace transform to
solve the given network
4. Evaluate the frequency response for resonant circuits and the network parameters for two
port networks

@#12102023 EC(ACT) 30042024

 Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam
(SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks
out of 50) and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50
marks). The student is declared as a pass in the course if he/she secures a minimum of 40% (40
marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE
(Semester End Examination) taken together.
Continuous Internal Evaluation:
 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment
Test component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of
the coverage of the syllabus, and the second test will be administered after 85-90% of the
coverage of the syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based
then only one assignment for the course shall be planned. The schedule for assignments shall
be planned properly by the course teacher. The teacher should not conduct two assignments at
the end of the semester if two assignments are planned. Each assignment shall be conducted
for 25 marks. (If two assignments are conducted then the sum of the two assignments shall be
scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests
and assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common
question papers for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with
a maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
Suggested Learning Resources:
Books
1. M.E.Van Valkenburg (2000), Network Analysis, Prentice Hall of India, 3rdedition, 2000,
ISBN:9780136110958.
2. Roy Choudhury-Networks and Systems, 2nd edition, New Age International Publications,
2006, ISBN: 9788122427677
ReferenceBooks:
3. Hayt, Kemmerly and Durbin-Engineering Circuit Analysis, TMH7th Edition, 2010.
4. J.David Irwin/ R.Mark Nelms- Basic Engineering Circuit Analysis
JohnWiley,8thed,2006.
5. Charles K Alexander and Mathew NO Sadiku-Fundamentals of Electric Circuits, Tata
McGraw-Hill,3rc1 Ed,2009.

@#12102023 EC(ACT) 30042024

 Web links and Video Lectures (e-Resources):
 .

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



@#12102023 EC(ACT) 30042024

 Template for Practical Course and if AEC is a practical Course Annexure-V

Analog and Digital Systems Design Laboratory Semester 3

Course Code BECL305 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 0:0:2 SEE Marks 50
Credits 01 Exam Hours 100
Examination type (SEE) Theory/Practical/Viva-Voce /Term-work/Others
Course objectives:
This laboratory course enables students to
 Understand the electronic circuit schematic and its working
 Realize and test amplifier and oscillator circuits for the given specifications
 Realize the opamp circuits for the applications such as DAC, implement mathematical functions and precision
rectifiers.
 Study the static characteristics of SCR and test the RC triggering circuit.
 Design and test the combinational and sequential logic circuits for their functionalities.
 Use the suitable ICs based on the specifications and functions.
Sl.NO Experiments (All the experiments has to be conducted using discrete components)
1 Design and set up the BJT common emitter voltage amplifier with and without feedback and determine the
gain- bandwidth product, input and output impedances.
2
Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator

3
Design and set up the circuits using opamp: i) Adder, ii) Integrator, iii) Differentiator and iv) Comparator

4 Design 4-bit R – 2R Op-Amp Digital to Analog Converter (i) for a 4-bit binary input using toggle switches
(ii) by generating digital inputs using mod-16
5 Design and implement (a) Half Adder & Full Adder using basic gates and NAND gates, (b) Half subtractor &
Full subtractor using NAND gates, (c) 4-variable function using IC74151(8:1MUX).
6 Realize (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD to Excess-3 code conversion
and vice versa
7 a) Realize using NAND Gates: i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii) T Flip-Flop b) Realize the
shift registers using IC7474/7495: (i) SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring counter and (vi) Johnson
counter.
8 Realize a) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop b) Mod-N
Counter using IC7490 / 7476 c) Synchronous counter using IC74192
Demonstration Experiments ( For CIE )
9 Design and Test the second order Active Filters and plot the frequency response,
i) Low pass and Highpass Filter
ii) Bandpass and Bandstop Filter

10 Design and test the following using 555 timer

i) Monostable Multivibraator
ii) Astable Multivibrator
11 Design and Test a Regulated Power supply

12 Design and test an audio amplifier by connecting a microphone input and observe the output using a loud
speaker.

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 Template for Practical Course and if AEC is a practical Course Annexure-V

Course outcomes (Course Skill Set):

At the end of the course the student will be able to:
1. Design and analyze the BJT/FET amplifier and oscillator circuits.
2. Design and test Opamp circuits to realize the mathematical computations, DAC and precision rectifiers.
3. Design and test the combinational logic circuits for the given specifications.
4. Test the sequential logic circuits for the given functionality.
5. Demonstrate the basic circuit experiments using 555 timer.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation (CIE):

CIE marks for the practical course are 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment is to be evaluated for conduction with an observation sheet and record write-up. Rubrics for
the evaluation of the journal/write-up for hardware/software experiments are designed by the faculty who is
handling the laboratory session and are made known to students at the beginning of the practical session.
 Record should contain all the specified experiments in the syllabus and each experiment write-up will be
evaluated for 10 marks.
 Total marks scored by the students are scaled down to 30 marks (60% of maximum marks).
 Weightage to be given for neatness and submission of record/write-up on time.
 Department shall conduct a test of 100 marks after the completion of all the experiments listed in the
syllabus.
 In a test, test write-up, conduction of experiment, acceptable result, and procedural knowledge will carry a
weightage of 60% and the rest 40% for viva-voce.
 The suitable rubrics can be designed to evaluate each student’s performance and learning ability.
 The marks scored shall be scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and marks of a test is the total CIE marks
scored by the student.
Semester End Evaluation (SEE):
 SEE marks for the practical course are 50 Marks.
 SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed
by the Head of the Institute.
 The examination schedule and names of examiners are informed to the university before the conduction of
the examination. These practical examinations are to be conducted between the schedule mentioned in the
academic calendar of the University.
 All laboratory experiments are to be included for practical examination.
 (Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be
strictly adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be
decided jointly by examiners.
 Students can pick one question (experiment) from the questions lot prepared by the examiners jointly.
 Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by examiners.
 General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and result in -60%,
Viva-voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks and scored marks shall

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 Template for Practical Course and if AEC is a practical Course Annexure-V

be scaled down to 50 marks (however, based on course type, rubrics shall be decided by the examiners)
 Change of experiment is allowed only once and 15% of Marks allotted to the procedure part are to be made
zero.
The minimum duration of SEE is 02 hours

Suggested Learning Resources:

1. David A Bell, “Fundamentals of Electronic Devices and Circuits Lab Manual”, 5th Edition, 2009, Oxford
University Press.
2. Albert Malvino, David J Bates, Electronic Principles, 7 th Edition, Mc Graw Hill Education, 2017.
3. Fundamentals of Logic Design, Charles H Roth Jr., Larry L Kinney, Cengage Learning, 7th Edition.

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 Electronic Devices Semester 3
Course Code BEC306A CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 3
Examination type (SEE) Theory

Course objectives: This course will enable students to:

• Understand the basics of semiconductor physics and electronic devices.
• Describe the mathematical models BJTs and FETs along with the constructional details.
• Understand the construction and working principles of optoelectronic devices
• Understand the fabrication process of semiconductor devices and CMOS process integration.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
These are sample Strategies, which teacher can use to accelerate the attainment of the various course
outcomes.
 Lecture method(L) does not mean only traditional lecture method, but different type of teaching
methods may be adopted to develop the outcomes.
 Encourage collaborative(Group)Learning in the class.
 Ask at least three HOTS(Higher order Thinking)questions in the class, which promotes critical
thinking.
 Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking skills
such as the ability to evaluate, generalize, and analyze information rather than simply recall it.
 Topics will be introduced in a multiple representation.
 Show the different ways to solve the same problem and encourage the students to come up with
their own creative ways to solve them.
 Discuss how every concept can be applied to the realworld-and when that's possible, it helps
improve the students' understanding.
 Adopt Flipped class technique by sharing the materials/Sample Videos prior to the class and have
discussions on the topic in the succeeding classes.

Module-1
Semiconductors
Bonding forces in solids, Energy bands, Metals, Semiconductors and Insulators, Direct and Indirect
semiconductors, Electrons and Holes, Intrinsic and Extrinsic materials, Conductivity and Mobility, Drift and
Resistance, Effects of temperature and doping on mobility, Hall Effect.
(Text1:3.1.1,3.1.2,3.1.3,3.1.4,3.2.1,3.2.3,3.2.4,3.4.1,3.4.2,3.4.3,3.4.5).

Module-2
PN Junctions
Forward and Reverse biased junctions-Qualitative description of Current flow at a junction, reverse bias, Reverse
bias breakdown- Zener breakdown, avalanche breakdown, Rectifiers.(Text1:5.3.1,5.3.3,5.4,5.4.1,5.4.2,5.4.3)
Optoelectronic Devices Photodiodes: Current and Voltage in an Illuminated Junction, Solar Cells,
Photodetectors. Light Emitting Diode: Light Emitting materials.
(Text1:8.1.1,8.1.2,8.1.3,8.2,8.2.1),
Module-3

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 Bipolar Junction Transistor
Fundamentals of BJT operation, Amplification with BJTS,BJT Fabrication, The coupled Diode model(Ebers-Moll
Model),Switching operation of a transistor, Cutoff, saturation, switching cycle, specifications, Drift in the base
region, Base narrowing, Avalanche breakdown.
(Text1:7.1,7.2,7.3,7.5.1,7.6,7.7.1,7.7.2, 7.7.3)

Module-4
Field Effect Transistors
Basic pn JFET Operation, Equivalent Circuit and Frequency Limitations, MOSFET-Two terminal MO Sstructure-
Energy band diagram, Ideal Capacitance
-Voltage Characteristics and Frequency Effects, Basic MOSFET Operation- MOSFET structure, Current-Voltage
Characteristics.
(Text2:9.1.1,9.4,9.6.1,9.6.2,9.7.1,9.7.2,9.8.1,9.8.2).
Module-5
Fabrication of p-n junctions
Thermal Oxidation, Diffusion, Rapid Thermal Processing, Ion implantation, chemical vapour deposition,
photolithography, Etching, metallization. (Text 1: 5.1)
Integrated Circuits
Background, Evolution of ICs, CMOS Process Integration, Integration of Other Circuit Elements.(Text
1:9.1,9.2,9.3.1,9.3.3).
Course outcome (Course Skill Set)
At the end of the course, the student will be able to :

1. Understand the principles of semiconductor Physics

2. Understand the principles and characteristics of different types of semiconductor devices
3. Understand the fabrication process of semiconductor devices
4. Utilize the mathematical models of semiconductor junctions for circuits and systems.
5. Identify the mathematical models of MOS transistors for circuits and systems.

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 Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50)
and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The
student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of
100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment
Test component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of
the coverage of the syllabus, and the second test will be administered after 85-90% of the
coverage of the syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then
only one assignment for the course shall be planned. The schedule for assignments shall be
planned properly by the course teacher. The teacher should not conduct two assignments at the
end of the semester if two assignments are planned. Each assignment shall be conducted for 25
marks. (If two assignments are conducted then the sum of the two assignments shall be scaled
down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for
the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Ben. G. Streetman, Sanjay Kumar Banerjee, "Solid State Electronic Devices",7thEdition,Pearson
Education,2016,ISBN978-93-325-5508-2.
2. Donald A Neamen, Dhrubes Biswas, "Semiconductor Physics and Devices", 4thEdition,McGraw Hill
Education, 2012,ISBN 978-0-07- 107010-2.
ReferenceBooks:
3. S.M.Sze,KwokK.Ng,"PhysicsofSemiconductorDevices",3rdEdition, Wiley,2018.
4. AdirBar-Lev,"SemiconductorandElectronicDevices",3rdEdition,PHI, 1993

Web links and Video Lectures (e-Resources):

@#12102023 EC(ACT) 30042024

  .

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



@#12102023 EC(ACT) 30042024

 Sensors and Instrumentation Semester 3
Course Code BEC306B CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 3
Examination type (SEE) Theory
Course objectives:
• Understand various technologies associated in manufacturing of sensors
• Acquire knowledge about types of sensors used in modern digital systems
• Get acquainted about material properties required to make sensors
• Understand types of instrument errors and circuits for multirange Ammeters and Voltmeters.
• Describe principle of operation of digital measuring instruments and Bridges.
• Understand the operations of transducers and instrumentation amplifiers.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teacher can use to accelerate the attainment of the various course
outcomes.
 Lecture method(L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
 Encourage collaborative(Group)Learning in the class.
 Ask at least three HOTS(Higher order Thinking)questions in the class, which promotes
critical thinking.
 Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking
skills such as the ability to evaluate, generalize, and analyze information rather than simply recall
it.
 Topics will be introduced in a multiple representation.
 Show the different ways to solve the same problem and encourage the students to come up
with their own creative ways to solve them.
 Discuss how every concept can be applied to the realworld-and when that's possible, it helps
improve the students' understanding.
 Adopt Flipped class technique by sharing the materials/Sample Videos prior to the class and
have discussions on the topic in the succeeding classes.
Module-1
Introduction to sensor based measurement systems:
General concepts and terminology, sensor classification, Primary Sensors, material for sensors,
microsensor technology. (Text 1)
Module-2
Self-generating Sensors-Thermoelectric sensors, piezoelectric sensors, pyroelectric sensors,
photovoltaic sensors, electrochemical sensors. (Text 1)
Module-3
Principles of Measurement: Static Characteristics, Error in Measurement, Types of Static Error.(Text
2: 1.2-1.6)
Multirange Ammeters, Multirange voltmeter.(Text2:3.2,4.4)
Digital Voltmeter: Ramp Technique, Dual slope integrating Type DVM, Direct Compensation type
and Successive Approximations type DVM (Text 2: 5.1-5.3, 5.5,5.6)
Module-4
Digital Multimeter: Digital Frequency Meter and Digital Measurement of Time, Function Generator.
Bridges: Measurement of resistance: Wheatstone's Bridge, AC Bridges - Capacitance and
Inductance Comparison bridge, Wien's bridge.

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 (Text2:refer 6.2,6.3 up to 6.3.2, 6.4 up to 6.4.2, 8.8, 11.2, 11.8 -11.10, 11.14).

Module-5
Transducers:Introduction,ElectricalTransducer,ResistiveTransducer,Resistive position Transducer,
Resistance Wire Strain Gauges, Resistance Thermometer, Thermistor, LVDT.
(Text2:13.1-13.3,13.5, 13.6 up to 13.6.1,13.7,13.8,13.11).
Instrumentation Amplifier using Transducer Bridge, Temperature indicators using Thermometer,
Analog Weight Scale(Text2:14.3.3, 14.4.1, 14.4.3).
Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Understand the material properties required to make sensors
2. Understand the principle of transducers for measuring physical parameters.
3. Describe the manufacturing process of sensors
4. Analyze the instrument characteristics and errors.
5. Describe the principle of operation and develop circuits for multirange Ammeters,
Voltmeters and Bridges to measure passive component values and frequency.

@#12102023 EC(ACT) 30042024

 Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for
the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is
declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. "Sensors and Signal Conditioning", Ramon Pallas Areny, JohnG. Webster,2nd edition, John Wiley
and Sons,2000
rd
2. H.S.Kalsi, "Electronic Instrumentation", Mc Graw Hill,3 Edition,2012,ISBN:9780070702066.

Reference Books
1. DavidA. Bell,"Electronic Instrumentation & Measurements", Oxford University Press PHI
2ndEdition, 2006,ISBN 81-203-2360-2.
2. D. HelfrickandW.D. Cooper, "Modern Electronic Instrumentation and Measuring
Techniques", Pearson, 1stEdition, 2015, ISBN: 9789332556065.

Web links and Video Lectures (e-Resources):

@#12102023 EC(ACT) 30042024

  .

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



@#12102023 EC(ACT) 30042024

 Computer Organization and Architecture Semester 3
Course Code BEC306C CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 3
Examination type (SEE) Theory
Course objectives: This course will enable students to:
• Explain the basic sub systems of a computer, their organization, structure and
operation.
• Illustrate the concept of programs as sequences of machine instructions.
• Demonstrate different ways of communicating with I/O devices
• Describe memory hierarchy and concept of virtual memory.
• Illustrate organization of simple pipelined processor and other computing systems.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teachers can use to accelerate the attainment of the various
course outcomes.
These are sample Strategies, which teacher can use to accelerate the attainment of the various
course outcomes.
 Lecture method (L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
 Encourage collaborative (Group) Learning in the class.
 Ask at least three HOTS(Higher order Thinking)questions in the class, which
promotes critical thinking.
 Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather
than simply recall it.
 Topics will be introduced in a multiple representation.
 Show the different ways to solve the same problem and encourage the students to
come up with their own creative ways to solve them.
 Discuss how every concept can be applied to the real world-and when that's possible,
it helps improve the students' understanding.
 Adopt Flipped class technique by sharing the materials/Sample Videos prior to the class
and have discussions on the topic in the succeeding classes.

Module-1
Basic Structure of Computers: Computer Types, Functional Units, Basic Operational
Concepts, Bus Structures, Software, Performance -Processor Clock, Basic Performance
Equation(upto1.6.2ofChap1ofText).
Machine Instructions and Programs: Numbers, Arithmetic Operations and Characters, IEEE
standard for Floating point Numbers, Memory Location and Addresses, Memory Operations,
Instructions and Instruction Sequencing (up to 2.4.6 of Chap 2 and 6.7.1 of Chap 6 of Text).
Module-2

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 Addressing Modes, Assembly Language, Basic Input and Output Operations, Stacks and
Queues, Subroutines, Additional Instructions (from2.4.7ofChap2, except 2.9.3, 2.11 & 2.12 of
Text).
Module-3
Input/ Output Organization: Accessing I/O Devices, Interrupts -Interrupt Hardware, Enabling
and Disabling Interrupts, Handling Multiple Devices,
Controlling Device Requests, Direct Memory Access
(upto4.2.4and4.4except4.4.1ofChap4ofText).

Module-4
Memory System: Basic Concepts, Semiconductor RAM Memories-Internal organization of
memory chips, Static memories, Asynchronous DRAMS, Read Only Memories, Cash
Memories, Virtual Memories, Secondary Storage- Magnetic Hard Disks
(5.1,5.2,5.2.1,5.2.2,5.2.3,5.3,5.5(except 5.5.1 to 5.5.4), 5.7 (except5.7.1), 5.9, 5.9.1 of Chap 5
of Text).
Module-5
Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete Instruction,
Multiple Bus Organization, Hardwired Control, Microprogrammed Control (up to 7.5 except
7.5.1 to7.5.6 of Chap 7 of Text).

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Explain the basic organization of a computer system.
2. Describe the addressing modes, instruction formats and program control statement.
3. Explain different ways of accessing an input/ output device including interrupts.
4. Illustrate the organization of different types of semiconductor and other secondary
storage memories.
5. Illustrate simple processor organization based on hard wired control and micro-
programmed control.

@#12102023 EC(ACT) 30042024

 Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam
(SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks
out of 50) and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50
marks). The student is declared as a pass in the course if he/she secures a minimum of 40% (40
marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE
(Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment
Test component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of
the coverage of the syllabus, and the second test will be administered after 85-90% of the
coverage of the syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based
then only one assignment for the course shall be planned. The schedule for assignments shall
be planned properly by the course teacher. The teacher should not conduct two assignments at
the end of the semester if two assignments are planned. Each assignment shall be conducted
for 25 marks. (If two assignments are conducted then the sum of the two assignments shall be
scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests
and assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common
question papers for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with
a maximum of 3 sub-questions), should have a mix of topics under that module.
Suggested Learning Resources:
Book
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky: Computer Organization, 5thEdition,Tata
McGrawHill,2002.

ReferenceBooks:
2. David A. Patterson, John L. Hennessy: Computer Organization and Design-The Hardware/
Software InterfaceARM Edition, 4th Edition, Elsevier,2009.
3. William Stallings: Computer Organization &Architecture,7th Edition, PHI, 2006.
4. Vincent P. Heuring & Harry F. Jordan: Computer Systems Design and Architecture, 2nd
Edition, Pearson Education, 2004.

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 Web links and Video Lectures (e-Resources):
 .

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



@#12102023 EC(ACT) 30042024

 Applied Numerical Methods for EC Engineers Semester 3
Course Code BEC306D CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 03
Examination type (SEE) Theory
Course objectives:
● To provide the knowledge and importance of error analysis in engineering problems
● To represent and solve an application problem using a system of linear equations
● Analyzeregression data to choose the most appropriate model for a situation.
● Familiarize with the ways of solving complicated mathematical problems numerically
● Prepare to solve mathematical models represented by initial or boundary value problems
Teaching-Learning Process
Pedagogy (General Instructions):
These are sample Strategies, teachers can use to accelerate the attainment of the various course
outcomes.
1. In addition to the traditional lecture method, different innovative teaching methods may be
adopted so that the delivered lessons shall develop students’ theoretical and applied
Mathematical skills.
2. State the need for Mathematics with Engineering Studies and Provide real-life examples.
3. Support and guide the students for self–study.
4. You will assign homework, grading assignments and quizzes, and documenting students'
progress.
5. Encourage the students to group learning to improve their creative and analytical skills.
6. Show short related video lectures in the following ways:
● As an introduction to new topics (pre-lecture activity).
● As a revision of topics (post-lecture activity).
● As additional examples (post-lecture activity).
● As an additional material of challenging topics (pre-and post-lecture activity).
● As a model solution of some exercises (post-lecture activity).

Module-1: Errors in computations and Root of the equations

Approximations and Round Off -Errors in computation: Error definitions, Round-Offerrors,
Truncation errors and the Taylor series-The Taylor series, Error Propagation, Total numerical
error,Absolute,Relative and percentage errors,Blunders, Formulation errors and data
uncertainty. Roots of equations: Simple fixed point iteration methods. Secant Method, Muller’s
method, and Graeffe’s Roots Squaring Method. Aitkin’s Method. (8 hours)
(RBT Levels: L1, L2 and L3)
Module-2: Solution of System of Linear Equations
Rank of the matrix, Echelon form, Linearly dependent and independent equations, Solutions
for linear equations, Partition method, Croute's Triangularisation method. Relaxation method.
Solution of non-linear simultaneous equations by Newton-Raphson method. Eigen Values and
properties, Eigen Vectors, Bounds on Eigen Values, Jacobi’s method, Given’s method for
symmetric matrices. (8 hours)
(RBT Levels: L1, L2 L3)

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 Module-3: Curve Fitting
Least-Squares Regression: Linear Regressions, Polynomial regressions, Multiple Linear
regressions, General Linear Least squares, Nonlinear Regressions, QR Factorization. Curve
Fitting with Sinusoidal Functions
Introduction to Splines,Linear Splines, Quadratic Splines, Cubic Splines. Bilinear
Interpolation. (8 hours)
(RBT Levels: L1, L2 L3)
Module-4: Numerical integration, Difference equations and Boundary Value Problems
Romberg’s method, Euler-Maclaurin formula, Gaussian integration for n = 2 and n=3.
Numerical double integration by trapezoidal and Simpson’s 1/3 rd rule. Solution of linear
difference equations.
Boundary-Value Problems, Introduction. The Shooting Method, Finite-Difference Methods
(8 hours)
(RBT Levels: L1, L2 and L3)
Module-5: Numerical solution of partial differential equations
Classifications of second-order partial differential equations,Finite difference approximations to
partial derivatives. Solution of:Laplace equation, Poisson equations, one-dimensional heat
equation and wave equations. (8 hours)
(RBT Levels: L1, L2 and L3)
Course outcome (Course Skill Set)
At the end of the course, the student will be able to:
1. Explain and measure errors in numerical computations
2. Test for consistency and solve a system of linear equations.
3. Construct a function which closely fits given n- n-points of an unknown function.
4. Understand and apply the basic concepts related to solving problems by
numericaldifferentiation and numerical integration.
5. Use appropriate numerical methods to study phenomena modelled as partial differential
equations.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam
(SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20
marks out of 50) and for the SEE, the minimum passing mark is 35% of the maximum marks
(18 out of 50 marks). The student is declared as a pass in the course if he/she secures a
minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal
Evaluation) and SEE (Semester End Examination) taken together.

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 Continuous Internal Evaluation:
● There are 25 marks for the CIE's Assignment component and 25 for the Internal
Assessment Test component.
● Each test shall be conducted for 25 marks. The first test will be administered after 40-50%
of the coverage of the syllabus, and the second test will be administered after 85-90% of
the coverage of the syllabus. The average of the two tests shall be scaled down to 25
marks
● Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-
based then only one assignment for the course shall be planned. The schedule for
assignments shall be planned properly by the course teacher. The teacher should not
conduct two assignments at the end of the semester if two assignments are planned. Each
assignment shall be conducted for 25 marks. (If two assignments are conducted then the
sum of the two assignments shall be scaled down to 25 marks)
● The final CIE marks of the course out of 50 will be the sum of the scale-down marks of
tests and assignment/s marks.
The Internal Assessment Test question paper is designed to attain the different levels of
Bloom’s taxonomy as per the outcome defined for the course.
Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common
question papers for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module
(with a maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each
module.
4. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books (Name of the author/Title of the Book/Name of the publisher/Edition and Year)
Text Books:
1. Steven C. Chapra & Raymond P. Canale: “Numerical Methods for Engineers and
Scientists”, McGraw Hill, 8th Edition, 2020.
2. Steven C. Chapra: “Applied Numerical Methods with MATLAB for Engineers and
Scientists”, McGraw Hill, Fifth Edition, 2023.
3. B. S. Grewal: “Numerical Methods in Engineering & Science with programs in C, C++
and MATLAB”, Khanna Publishers, 10hEd., 2015.
Reference Books:
1.John H. Mathews & Kurtis D. Frank: “Numerical Methods Using MATLAB”, PHI
Publications, 4th Edition, 2005.
2.Won Young Yang, Wenwu Cao, Tae Sang Chung, John Morris: “Applied Numerical
Methods Using MATLAB”, WILEY Interscience, Latest Edition, 2005.

Web links and Video Lectures (e-Resources):

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 • http://nptel.ac.in/courses.php?disciplineID=111
• http://www.class-central.com/subject/math(MOOCs)
• http://academicearth.org/
• VTU e-Shikshana Program
• VTU EDUSAT Program.

Activity-Based Learning (Suggested Activities in Class)/Practical-Based Learning

• Quizzes
• Assignments
• Seminar

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 Lab VIEW Programming Semester 3
Course Code BEC358A CIE Marks 50
Teaching Hours/Week (L:T:P: S) 0:0:2 SEE Marks 50
Credits 01 Total 100
Exam Hours 2
Examination type (SEE) Practical
Course objectives:
 Aware of various front panel controls and indicators.
 Connect and manipulate nodes and wires in the block diagram.
 Locate various tool bars and pull-down menus for the purpose of implementing specific functions.
 Locate and utilize the context help window.
 Familiar with LabVIEW and different applications using it.

Sl.NO VI Programs(using LabVIEW software)to realize the following:
1 Basic arithmetic operations: addition, subtraction, multiplication and division

2 Boolean operations: AND, OR, XOR, NOT and NAND

3 Sum of ‘n’ numbers using ‘for’ loop

4 Factorial of a given number using ‘for’ loop

5 Determine square of a given number

6 Factorial of a given number using ‘while‘ loop

7 Sorting even numbers using ‘while’ loop in an array

8 Finding the array maximum and array minimum

Demonstration Experiments (For CIE)

9 Build a Virtual Instrument that simulates a heating and cooling system. The system must be able to be controlled
manually or automatically.
10 Build a Virtual Instrument that simulates a Basic Calculator (using formula node).

11 Build a Virtual Instrument that simulates a Water Level Detector.

12 DemonstratehowtocreateabasicVIwhichcalculatestheareaandperimeterofacircle.

Course outcomes (Course Skill Set):

At the end of the course the student will be able to:
 Use LabVIEW to create data acquisition, analysis and display operations
 Create user interfaces with charts, graph and buttons
 Use the programming structures and data types that exist in LabVIEW
 Use various editing and debugging techniques.

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 Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation (CIE):

CIE marks for the practical course are 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment is to be evaluated for conduction with an observation sheet and record write-up. Rubrics for
the evaluation of the journal/write-up for hardware/software experiments are designed by the faculty who is
handling the laboratory session and are made known to students at the beginning of the practical session.
 Record should contain all the specified experiments in the syllabus and each experiment write-up will be
evaluated for 10 marks.
 Total marks scored by the students are scaled down to 30 marks (60% of maximum marks).
 Weightage to be given for neatness and submission of record/write-up on time.
 Department shall conduct a test of 100 marks after the completion of all the experiments listed in the
syllabus.
 In a test, test write-up, conduction of experiment, acceptable result, and procedural knowledge will carry a
weightage of 60% and the rest 40% for viva-voce.
 The suitable rubrics can be designed to evaluate each student’s performance and learning ability.
 The marks scored shall be scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and marks of a test is the total CIE marks
scored by the student.
Semester End Evaluation (SEE):
 SEE marks for the practical course are 50 Marks.
 SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed
by the Head of the Institute.
 The examination schedule and names of examiners are informed to the university before the conduction of
the examination. These practical examinations are to be conducted between the schedule mentioned in the
academic calendar of the University.
 All laboratory experiments are to be included for practical examination.
 (Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be
strictly adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be
decided jointly by examiners.
 Students can pick one question (experiment) from the questions lot prepared by the examiners jointly.
 Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by examiners.
 General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and result in -60%,
Viva-voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks and scored marks shall
be scaled down to 50 marks (however, based on course type, rubrics shall be decided by the examiners)
Change of experiment is allowed only once and 15% of Marks allotted to the procedure part are to be made
zero.

The minimum duration of SEE is 02 hours

Suggested Learning Resources:

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 1. VirtualInstrumentationusingLABVIEW,JovithaJerome,PHI,2011
2. VirtualInstrumentationusingLABVIEW,SanjayGupta,JosephJohn,TMH,McGrawHill,SecondEdition,2011.

@#12102023 EC(ACT) 30042024

 MATLAB Programming Semester 3
Course Code BEC358B CIE Marks 50
Teaching Hours/Week (L:T:P: S) 1:0:0 SEE Marks 50
Total Hours of Pedagogy 14 Total Marks 100
Credits 01 Exam Hours 1
Examination type (SEE) Theory
Course objectives:
 Understand the MATLAB commands and functions.
 Create and Execute the script and function files
 Work with built in function, saving and loading data and create plots.
 Work with the arrays, matrices, symbolic computations, files and directories.
 Learn MATLAB programming with script, functions and language specific features.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Adopt Problem Based Learning (PBL), which fosters students’ analytical skills, develop thinking
skills such as the ability to evaluate, generalize, and analyze information rather than simply recall
it.
2. Give programming assignments.
Module-1
Introduction: Basics of MATLAB, Simple arithmetic calculations, Creating and working with arrays and
numbers.

Module-2
Creating and printing simple plots, Creating, saving and executing a script file, Creating and executing a
function file, Working with arrays and matrices.

Module-3
Working with anonymous functions, Symbolic Computations, Importing and exporting data,
Working with files and directories.

Module-4
Interactive computations: Matrices and vectors, Matrix and array operations, Character strings, Command
line functions, Built-in functions, Saving and loading data, Plotting simple plots.

Module-5
Programming in MATLAB:Script Files, Function Files, Language specific Features.

Course outcome (Course Skill Set)

At the end of the course the student will be able to:
1. Understand the syntax of MATLAB for arithmetic computations, arrays, matrices.
2. Understand the built in function, saving and loading data, and create plots
3. Create program using symbolic computations, Importing and exporting data and files
4. Create program using character strings, Command line functions and Built-in functions.

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 Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50)
and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The
student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of
100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together
Continuous internal Examination (CIE)
 For the Assignment component of the CIE, there are 25 marks and for the Internal Assessment
Test component, there are 25 marks.
 The first test will be administered after 40-50% of the syllabus has been covered, and the second
test will be administered after 85-90% of the syllabus has been covered
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then
only one assignment for the course shall be planned. The teacher should not conduct two
assignments at the end of the semester if two assignments are planned.
 For the course, CIE marks will be based on a scaled-down sum of two tests and other methods of
assessment.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester End Examinations (SEE)

SEE paper shall be set for 50 questions, each of the 01 marks. The pattern of the question paper is MCQ
(multiple choice questions). The time allotted for SEE is 01 hour. The student has to secure a minimum of
35% of the maximum marks meant for SEE.
OR
MCQ (Multiple Choice Questions) are preferred for 01 credit courses, however, if course content demands the
general question paper pattern that followed for 03 credit course, then
1. The question paper will have ten questions. Each question is set for 10 marks.
2. There will be 2 questions from each module. Each of the two questions under a module may or may not
have the sub-questions (with maximum sub-questions of 02, with marks distributions 5+5, 4+6, 3+7).
3. The students have to answer 5 full questions, selecting one full question from each module.
4. The duration of the examinations shall be defined by the concerned board of studies

Suggested Learning Resources:

Book
1. Rudra Pratap, Getting Started with MATLAB – A quick Introduction for scientists and Engineers, Oxford
University Press, 2010.

Web links and Video Lectures (e-Resources):

 .

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



@#12102023 EC(ACT) 30042024

 C++ Basics Semester 4
Course Code BEC358C CIE Marks 50
Teaching Hours/Week (L: T:P: S) 0:0:2:0 SEE Marks 50
Total Hours of Pedagogy 24 Total Marks 100
Credits 1 Exam Hours 02

Examination nature (SEE) Practical

Course objectives:
 Understand object-oriented programming concepts, and apply them in solving problems.
 To create, debug and run simple C++ programs.
 Introduce the concepts of functions, friend functions, inheritance, polymorphism and function
overloading.
 Introduce the concepts of exception handling and multithreading.
Sl.No Experiments
1 Write a C++ program to find largest, smallest & second largest of three numbers using inline
functions MAX & Min.
2 Write a C++ program to calculate the volume of different geometric shapes like cube, cylinder
and sphere using function overloading concept.
3 Define a STUDENT class with USN, Name & Marks in 3 tests of a subject. Declare an array of 10
STUDENT objects. Using appropriate functions, find the average of the two better marks for each
student. Print the USN, Name & the average marks of all the students.
4 Write a C++ program to create class called MATRIX using two-dimensional array of integers, by
overloading the operator == which checks the compatibility of two matrices to be added and
subtracted. Perform the addition and subtraction by overloading + and – operators
respectively. Display the results by overloading the operator <<. If (m1 == m2) then m3 = m1 +
m2 and m4 = m1 – m2 else display error
5 Demonstrate simple inheritance concept by creating a base class FATHER with data members:
First Name, Surname, DOB & bank Balance and creating a derived class SON, which inherits:
Surname & Bank Balance feature from base class but provides its own feature: First Name & DOB.
Create & initialize F1 & S1 objects with appropriate constructors & display the FATHER & SON
details.
6 Write a C++ program to define class name FATHER & SON that holds the income respectively.
Calculate & display total income of a family using Friend function.
7 Write a C++ program to accept the student detail such as name & 3 different marks by get_data()
method & display the name & average of marks using display() method. Define a friend function
for calculating the average marks using the method mark_avg().
8 Write a C++ program to explain virtual function (Polymorphism) by creating a base class polygon
which has virtual function areas two classes rectangle & triangle derived from polygon & they
have area to calculate & return the area of rectangle & triangle respectively.
9 Design, develop and execute a program in C++ based on the following requirements: An
EMPLOYEE class containing data members & members functions: i) Data members: employee
number (an integer), Employee_ Name (a string of characters), Basic_ Salary (in integer), All_
Allowances (an integer), Net_Salary (an integer). (ii) Member functions: To read the data of
an employee, to calculate Net_Salary & to print the values of all the data members. (All_Allowances
= 123% of Basic, Income Tax (IT) =30% of gross salary (=basic_ Salary_All_Allowances_IT).
10 Write a C++ program with different class related through multiple inheritance & demonstrate the
use of different access specified by means of members variables & members functions.

11 Write a C++ program to create three objects for a class named count object with data members

@#12102023 EC(ACT) 30042024

 such as roll_no & Name. Create a members function set_data ( ) for setting the data values &
display ( ) member function to display which object has invoked it using „this‟ pointer.
12 Write a C++ program to implement exception handling with minimum 5 exceptions classes
including two built in exceptions.
Course outcomes (Course Skill Set):
At the end of the course the student will be able to:
1. Write C++ program to solve simple and complex problems
2. Apply and implement major object-oriented concepts like message passing, function overloading,
operator overloading and inheritance to solve real-world problems.
3. Use major C++ features such as Templates for data type independent designs and File I/O to deal
with large data set.
4. Analyze, design and develop solutions to real-world problems applying OOP concepts of C++
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall
be deemed to have satisfied the academic requirements and earned the credits allotted to each course.
The student has to secure not less than 35% (18 Marks out of 50) in the semester-end examination
(SEE).
Continuous Internal Evaluation (CIE):
CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment to be evaluated for conduction with observation sheet and record write-up.
Rubrics for the evaluation of the journal/write-up for hardware/software experiments designed by
the faculty who is handling the laboratory session and is made known to students at the beginning
of the practical session.
 Record should contain all the specified experiments in the syllabus and each experiment write-up
will be evaluated for 10 marks.
 Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
 Weightage to be given for neatness and submission of record/write-up on time.
 Department shall conduct 02 tests for 100 marks, the first test shall be conducted after the 8 th week
of the semester and the second test shall be conducted after the 14th week of the semester.
 In each test, test write-up, conduction of experiment, acceptable result, and procedural knowledge
will carry a weightage of 60% and the rest 40% for viva-voce.
 The suitable rubrics can be designed to evaluate each student’s performance and learning ability.
Rubrics suggested in Annexure-II of Regulation book
 The average of 02 tests is scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and average marks of two tests is
the total CIE marks scored by the student.
Semester End Evaluation (SEE):
SEE marks for the practical course is 50 Marks.
SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed by
the University
All laboratory experiments are to be included for practical examination.
(Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be
strictly adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be
decided jointly by examiners.
Students can pick one question (experiment) from the questions lot prepared by the internal
/external examiners jointly.
Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by
examiners.
General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and

@#12102023 EC(ACT) 30042024

 result in -60%, Viva-voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks
and scored marks shall be scaled down to 50 marks (however, based on course type, rubrics shall be
decided by the examiners)
Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made
zero.
The duration of SEE is 03 hours

Rubrics suggested in Annexure-II of Regulation book

Suggested Learning Resources:

1. Object oriented programming in TURBO C++, Robert Lafore, Galgotia Publications, 2002
2. The Complete Reference C++, Herbert Schildt, 4th Edition, Tata McGraw Hill, 2003.
3. Object Oriented Programming with C++, E Balaguruswamy, 4th Edition, Tata McGraw Hill, 2006.

@#12102023 EC(ACT) 30042024

 IoT for Smart Infrastructure Semester 3
Course Code BEC358D CIE Marks 50
Teaching Hours/Week (L: T:P: S) 1:0:0:0 SEE Marks 50
Total Hours of Pedagogy 14 Total Marks 100
Credits 01 Exam Hours 1
Examination type (SEE) Theory/Practical
Course objectives:
To provide an understanding of the concepts, principles, and applications of IoT in the context of
smart infrastructure.
To explore the role of IoT technologies in transforming infrastructure into smart, efficient, and
sustainable systems and analyse the challenges, opportunities, and considerations in implementing
IoT for smart infrastructure.
To examine real-world case studies and successful implementations of IoT in smart cities,
buildings, transportation, and energy management and explore future trends and emerging
technologies shaping the field of IoT for smart infrastructure.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teachers can use to accelerate the attainment of the various
course outcomes.
 Interactive Lectures: Conduct interactive lectures to present the theoretical concepts and
foundational knowledge of IoT for smart infrastructure.
 Case Studies and Group Discussions: Utilize case studies to analyse real-world
implementations of IoT in smart infrastructure projects. Divide students into groups and
assign them specific cases to discuss and analyse.
 Hands-on Workshops and Simulations: Organize hands-on workshops or simulations
where students can interact with IoT devices and technologies relevant to smart
infrastructure.
 Guest Lectures and Industry Experts: Invite guest speakers or industry experts who
have hands-on experience in implementing IoT in smart infrastructure projects. They can
share their insights, challenges, and success stories, providing students with a real-world
perspective
 Project-Based Learning: Assign students to work on individual or group projects related
to IoT for smart infrastructure. Provide a project brief with specific objectives and
deliverables. Students can apply their knowledge and skills to design, develop, or analyse
IoT solutions for smart infrastructure challenges.

Module-1
Introduction to IoT and Smart Infrastructure
Introduction to IoT: Definition of IoT and its basic components, Overview of IoT applications in
various industries, Importance of IoT in transforming infrastructure.
Smart Infrastructure Overview: Introduction to smart infrastructure and its key components,
Benefits and challenges of implementing smart infrastructure, Case studies showcasing
successful smart infrastructure projects.
IoT Technologies for Smart Infrastructure: Sensors and actuators: Types, functionalities, and
applications; Communication protocols: Wi-Fi, Bluetooth, cellular networks, and their use in IoT;

@#12102023 EC(ACT) 30042024

 Cloud computing and data analytics in IoT for infrastructure; Edge computing: Real-time
decision-making at the edge.
Security and Privacy in IoT for Smart Infrastructure: Security challenges and threats in
IoT, Privacy considerations and data protection in smart infrastructure, best practices and
solutions for ensuring IoT security and privacy.
Module-2
IoT Applications in Smart Cities
Introduction to Smart Cities - Definition and key features of smart cities, Role of IoT in
transforming cities into smart cities, Benefits and challenges of smart city implementations.
IoT Applications in Smart City Infrastructure - Smart transportation: Intelligent traffic
management and transportation systems, Smart buildings: Energy management and occupant
comfort; Smart grids: Optimizing energy distribution and consumption; Waste management,
water management, and environmental monitoring.
Case Studies of Smart City Implementations: Showcase of successful smart city projects around
the world; Analysis of the IoT technologies and strategies implemented; Lessons learned from
these case studies.
Future Trends in Smart Cities: Emerging technologies shaping the future of smart cities, Role of
IoT, AI, and 5G in advancing smart city infrastructure, Opportunities and challenges for future
smart city developments.

Module-3
IoT Applications in Smart Buildings
Introduction to Smart Buildings: Definition and key features of smart buildings, Benefits of IoT
in improving energy efficiency and occupant comfort, Challenges and considerations in
implementing smart building technologies.
IoT Technologies for Smart Buildings: Building automation systems and controls; Energy
management and monitoring using IoT devices; Indoor environmental quality monitoring and
optimization; Smart lighting and HVAC systems.
Case Studies of Smart Building Implementations: Showcase of successful smart building
projects; Analysis of IoT technologies and solutions deployed; Lessons learned from these case
studies.
Future Trends in Smart Buildings: Emerging technologies for smart buildings; Integration of IoT
with AI and machine learning; Potential impact of 5G on smart building applications.

Module-4
IoT Applications in Smart Transportation
Introduction to Smart Transportation: Definition and key features of smart transportation; Role
of IoT in intelligent traffic management and transportation systems; Challenges and
opportunities in implementing smart transportation solutions.
IoT Technologies for Smart Transportation: Traffic sensors and monitoring systems; Intelligent
transportation systems (ITS); Vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I)
communication; Real-time data analysis and predictive analytics.

@#12102023 EC(ACT) 30042024

 Case Studies of Smart Transportation Implementations: Showcase of successful smart
transportation projects; Analysis of IoT technologies and solutions deployed; Lessons learned
from these case studies.
Future Trends in Smart Transportation: Emerging technologies shaping the future of smart
transportation; Role of IoT, AI, and autonomous vehicles; Potential impact of 5G on smart
transportation applications.
Module-5
IoT for Smart Grids and Energy Management
Introduction to Smart Grids: Definition and key features of smart grids: Role of IoT in optimizing
energy distribution and consumption; Benefits and challenges of smart grid implementations. IoT
Technologies for Smart Grids: Smart meters and energy monitoring devices; Demand response
and load management; Grid optimization and fault detection using IoT; Renewable energy
integration and grid stability.
Case Studies of Smart Grid Implementations: Showcase of successful smart grid projects,
Analysis of IoT technologies and solutions deployed, Lessons learned from these case studies.
Future Trends in Smart Grids and Energy Management: Emerging technologies for smart grids;
Integration of IoT, AI, and blockchain in energy management; Potential impact of 5G on smart
grid applications.

Course outcome (Course Skill Set)

At the end of the course the student will be able to:

 Define and explain the core concepts and components of IoT and its relevance to smart
infrastructure. Identify and evaluate the key technologies and communication protocols
used in IoT for smart infrastructure.
 Assess the benefits, challenges, and ethical considerations associated with implementing
IoT in smart infrastructure projects and analyse & compare different IoT applications in
smart cities, buildings, transportation, and energy management.
 Examine real-world case studies of successful IoT implementations in smart infrastructure
and extract lessons learned. Demonstrate an understanding of security and privacy
considerations in IoT for smart infrastructure.
 Discuss the impact of emerging technologies, such as artificial intelligence and 5G, on the
future of IoT in smart infrastructure. Apply knowledge and critical thinking skills to propose
IoT-based solutions for smart infrastructure challenges.
 Work effectively in teams to analyse, design, and present IoT projects related to smart
infrastructure and communicate effectively and articulate the potential benefits and
limitations of IoT for smart infrastructure.

@#12102023 EC(ACT) 30042024

 Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam
(SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks
out of 50) and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50
marks). A student shall be deemed to have satisfied the academic requirements and earned the
credits allotted to each subject/ course if the student secures a minimum of 40% (40 marks out of
100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous internal Examination (CIE)

 For the Assignment component of the CIE, there are 25 marks and for the Internal Assessment
Test component, there are 25 marks.
 The first test will be administered after 40-50% of the syllabus has been covered, and the
second test will be administered after 85-90% of the syllabus has been covered
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based
then only one assignment for the course shall be planned. The teacher should not conduct two
assignments at the end of the semester if two assignments are planned.
 For the course, CIE marks will be based on a scaled-down sum of two tests and other methods
of assessment.
Internal Assessment Test question paper is designed to attain the different levels of
Bloom’s
taxonomy as per the outcome defined for the course.

Semester End Examinations (SEE)

SEE paper shall be set for 50 questions, each of the 01 marks. The pattern of the question paper is
MCQ (multiple choice questions). The time allotted for SEE is 01 hour. The student has to secure a
minimum of 35% of the maximum marks meant for SEE.
OR
MCQ (Multiple Choice Questions) are preferred for 01 credit courses, however, if course content
demands the general question paper pattern that followed for 03 credit course, then
1. The question paper will have ten questions. Each question is set for 10 marks.
2. There will be 2 questions from each module. Each of the two questions under a module may
or may not have the sub-questions (with maximum sub-questions of 02, with marks
distributions 5+5, 4+6, 3+7).
3. The students have to answer 5 full questions, selecting one full question from each module.

Suggested Learning Resources:

1. MindMatrix.io
2. "Internet of Things (A Hands-on-Approach)" by Arshdeep Bahga and Vijay Madisetti
3. "Building the Internet of Things: Implement New Business Models, Disrupt Competitors,
Transform Your Industry" by Maciej Kranz
4. "Smart Cities: Big Data, Civic Hackers, and the Quest for a New Utopia" by Anthony
M.
Townsend

@#12102023 EC(ACT) 30042024

 5. "Internet of Things for Architects: Architecting IoT solutions by implementing sensors,
communication infrastructure, edge computing, analytics, and security" by Perry Lea.

Web links and Video Lectures (e-Resources):

 makes.mindmatrix.io
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
 Sensor Deployment and Data Collection: Organize a hands-on activity where participants
work in groups to deploy sensors in a simulated smart infrastructure environment.
 Smart City Simulation Game: Develop a simulation game where participants take on
different roles representing stakeholders in a smart city.
 IoT Solution Design Challenge: Assign participants to design an IoT-based solution for a
specific smart infrastructure problem. They can work individually or in teams to identify
the problem, propose an IoT solution, outline the required components and technologies,
and create a prototype or presentation.
 Security and Privacy Risk Assessment: Conduct a group activity where participants
analyse the security and privacy risks associated with IoT deployments in smart
infrastructure.
 Field Visit to Smart Infrastructure Project: Organize a field visit to a smart infrastructure
project, such as a smart building, smart city district, or IoT-enabled transportation system.

@#12102023 EC(ACT) 30042024

 Annexure-II 1

ELECTROMAGNETIC THEORY Semester IV

Course Code BEC401 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 03
Examination type (SEE) THEORY
Course objectives:
Thiscoursewillenablestudentsto:
� Study the different coordinate systems, Physical significance of Divergence, Curl
andGradient.
� UnderstandtheapplicationsofCoulomb'slawandGausslawtodifferentchargedistributionsand
the applications of Laplace's and Poisson's Equations to solve real time problems
oncapacitanceofdifferent chargedistributions.
� Understand the physical significance of Biot-Savart's, Ampere's Law and Stokes'
theoremfordifferent current distributions.
� Infertheeffectsofmagneticforces,materialsandinductance.
� KnowthephysicalinterpretationofMaxwell'sequationsandapplicationsforPlanewavesforthe
irbehavior in different media.
� AcquireknowledgeofPoyntingtheorem anditsapplicationofpower flow

Teaching­Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
ThesearesampleStrategies,whichteacherscanusetoacceleratetheattainmentofthevariouscourseoutcomes.
These are sample Strategies, which teachers can use to accelerate the attainment of the various
courseoutcomes.
1. Lecturemethod (L)doesnot
meanonlytraditionallecturemethod,butdifferenttypesofteachingmethodsmaybe adopted
todeveloptheoutcomes.
2. Encouragecollaborative (Group) Learningintheclass.
3. AskatleastthreeHOTS (HigherOrderThinking)
questionsintheclass,whichpromotescriticalthinking.
4. Adopt Problem­Based Learning (PBL), which fosters students’ Analytical skills, and develops
thinking skillssuchastheabilityto evaluate,generalize,and
analyzeinformationratherthansimplyrecallit.
5. Topicswillbeintroducedinamultiplerepresentation.
6. Showthedifferentwaystosolvethesameproblemandencouragethestudentstocomeupwithcreati
ve ways to solvethem.
7. Discusshoweveryconceptcanbeappliedtothereal world
andwhenthat'spossible,ithelpsimprovethe student'sunderstanding.
8. Adopt the Flipped class technique by sharing the materials/Sample Videos before the class and
having discussionson thetopicinthesucceedingclasses.

Module­1
Revision of Vector Calculus – (Text 1: Chapter 1)
Coulomb’s Law, Electric Field Intensity and Flux density: Experimental law of Coulomb,
Electric field intensity, Field due to continuous volume charge distribution, Field of a line charge,
Field due to Sheet of charge, Electric flux density, Numerical Problems. (Text: Chapter 2.1 to
2.5, 3.1) RBT Level: L1, L2, L3

Module­2

EC(ACT) 30042024 1
 Annexure-II 2

Gauss’s Law and Divergence: Gauss ‘law, Application of Gauss’ law to Point Charge, line
charge, Surface charge and Volume Charge, Point (differential) form of Gauss law, Divergence.
Maxwell‘s First Equation (Electrostatics), Vector Operator ▼and divergence theorem,
Numerical Problems (Text: Chapter 3.2 to 3.7).Energy expended or work done in moving a
point charge in anElectric field, The line integral ((Text: Chapter 4.1 and 4.2) Current and
Current density, Continuity of current. (Text: Chapter 5.1, 5.2) RBT Level: L1, L2, L3

Module-3
Poisson’s and Laplace’s Equations: Derivation of Poisson‘s and Laplace‘s Equations, Examples
of the solution of Laplace‘s equation, Numerical problems on Laplace’s equation
(Text: Chapters 7.1 and 7.3)
Steady Magnetic Field: Biot­Savart Law, Ampere‘s circuital law, Curl, Stokes‘ theorem,
Magnetic flux and magnetic flux density.
(Text: Chapters 8.1 to 8.5) RBT Level: L1, L2, L3
Module-4
Magnetic Forces: Force on a moving charge, differential current elements, Force between
differential current elements, Numerical problems (Text: Chapter 9.1 to 9.3).
Magnetic Materials: Magnetization and permeability, Magnetic boundary conditions, the
magnetic circuit, problems (Text: Chapter 9.6 to 9.8) RBT Level: L1, L2, L3
Module-5
Faraday’s law of Electromagnetic Induction –Integral form and Point form, Numerical problems.
Inconsistency of Ampere’s law with continuity equation, displacement current, Conduction
current, Derivation of Maxwell‘s equations in point form, and integral form, Maxwell’s
equations for different media, Numerical problems (Text: Chapter10.1 to10.4)
Uniform Plane Wave: Wave propagation in free space, Uniform plane wave, Derivation of
plane wave equations from Maxwell’s equations,Poynting‘s Theorem and wave power, Skin
effect or Depth of penetration, Numerical problems. (Text: Chapter 12.1, 12.3, 12.4) RBT
Level: L1, L2, L3
Course outcome (Course Skill Set)
At the end of the course the student will be able to:

1. Evaluate problems on electrostatic force, electric field due to point, linear, volume
charges by applying conventional methods and charge in a volume.
2. Apply Gauss law to evaluate Electric fields due to different charge distributions and
Volume Charge distribution by using Divergence Theorem.
3. Determine potential and energy with respect to point charge and capacitance using
Laplace equation and Apply Biot-Savart’s and Ampere’s laws for evaluating Magnetic
field for different current configurations
4. Calculate magnetic force, potential energy and Magnetization with respect to magnetic
materials and voltage induced in electric circuits.
5. Apply Maxwell’s equations for time varying fields, EM waves in free space and
conductors and Evaluate power associated with EM waves using Poynting theorem

EC(ACT) 30042024 2
 Annexure-II 3

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50)
and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The
student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of
100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation:

� There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment
Test component.
� Each test shall be conducted for 25 marks. The first test will be administered after 40­50% of
the coverage of the syllabus, and the second test will be administered after 85­90% of the
coverage of the syllabus. The average of the two tests shall be scaled down to 25 marks
� Any two assignment methods mentioned in the 22OB2.4, if an assignment is project­based then
only one assignment for the course shall be planned. The schedule for assignments shall be
planned properly by the course teacher. The teacher should not conduct two assignments at the
end of the semester if two assignments are planned. Each assignment shall be conducted for 25
marks. (If two assignments are conducted then the sum of the two assignments shall be scaled
down to 25 marks)
� The final CIE marks of the course out of 50 will be the sum of the scale­down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester­End Examination:
Theory SEE will be conducted by the University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub­questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored shall be proportionally reduced to 50 marks.
Suggested Learning Resources:
Text Book:
1. W.H. Hayt and J.A. Buck, ―Engineering Electromagne�cs, 8th Edi�on, Tata McGraw­ Hill,
2014, ISBN­978­93­392­0327­6.
Reference Books:
1. Elements of Electromagnetics – Matthew N.O., Sadiku, Oxford University press, 4 thEdn.
2. Electromagnetic Waves and Radiating systems – E. C. Jordan and K.G. Balman, PHI, 2ndEdn.
3. Electromagnetics­ Joseph Edminister, Schaum Outline Series, McGraw Hill.
4. N. Narayana Rao, ―Fundamentals of Electromagne�cs for Engineering, Pearson
Web links and Video Lectures (e­Resources):
��NPTEL Video lectures : https://youtu.be/pGdr9WLto4A
� NPTEL Video lectures: https://youtu.be/xn2IpxI991M

EC(ACT) 30042024 3
 Annexure-II 4

ActivityBasedLearning(SuggestedActivitiesinClass)/Practical-Based Learning
� Group Discussion/Quiz
� Demonstration of Electromagnetic concepts.
� Case Study on Medical Imaging devices.

EC(ACT) 30042024 4
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EC(ACT) 30042024
TEMPLATE for IPCC (26.04.2022) Annexure-III

PRINCIPLES OF COMMUNICATION SYSTEMS Semester 4

Course Code BEC402 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2:0 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours 03
Examination nature (SEE) Theory/practical/Viva-Voce /Term-work/Others
Course objectives:
This course will enable students to
• Understand and analyse concepts of Analog Modulation schemes viz; AM, FM
• Design and analyse the electronic circuits for AM and FM modulation and demodulation.
• Understand the concepts of random variable and random process to model communication systems.
• Understand and analyse the concepts of digitization of signals.
• Evolve the concept of SNR in the presence of channel induced noise

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teacher can use to accelerate the attainment of the various course
outcomes.
1. Lecture method (L) does not mean only traditional lecture method, but different type of teaching methods
may be adopted to develop the outcomes.
2. Show Video/animation films to explain evolution of communication technologies.
3. Encourage collaborative (Group) Learning in the class.
4. Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes critical thinking.
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking skills such
as the ability to evaluate, generalize, and analyze information rather than simply recall it.
6. Show the different ways to solve the same problem and encourage the students to come up with their own
creative ways to solve them.
7. Discuss how every concept can be applied to the real world - and when that's possible, it helps improve the
students' understanding.
MODULE-1
Random Variables and Processes: Introduction, Probability, Conditional Probability, Random variables.
Statistical Averages: Function of a random variable, Moments, Random Processes, Mean, Correlation and
Covariance function: Properties of autocorrelation function, Cross–correlation functions, Gaussian Process:
Gaussian Distribution Function.
[Text 2: 5.1, 5.2,5.3,5.4,5.5,5.6,5.9]
RBT: L1, L2
MODULE-2
Amplitude Modulation Fundamentals: AM Concepts, Modulation index and Percentage of Modulation,
Sidebands and the frequency domain, AM Power, Single Sideband Modulation.
AM Circuits: Amplitude Modulators: Diode Modulator, Transistor Modulator, collector Modulator. Amplitude
Demodulators: Diode Detector, Balanced Modulators: Lattice Modulators.
Frequency Division Multiplexing: Transmitter-Multiplexer, Receiver-Demultiplexer.
[Text1: 3.1, 3.2,3.3,3.4,3.5,4.2,4.3,4.4,10.2]
RBT: L1, L2, L3

MODULE-3
Fundamentals of Frequency Modulation: Basic Principles of Frequency Modulation, Principles of Phase
Modulation, Modulation index and sidebands, Noise Suppression Effects of FM, Frequency Modulation versus
Amplitude Modulation.
FM Circuits: Frequency Modulators: Voltage Controlled Oscillators. , Frequency Demodulators: Slope Detectors,
Phase Locked Loops.
Communication Receiver: Super heterodyne receiver, Frequency Conversion: Mixing Principles, JFET Mixer.
[Text1: 5.1,5.2,5.3,5.4,5.5,6.1,6.3,9.2,9.3]
RBT: L1, L2, L3

EC(ACT) 30042024 1
TEMPLATE for IPCC (26.04.2022) Annexure-III

MODULE-4
Digital Representation of Analog Signals: Introduction, Why Digitize Analog Sources?, The Sampling process,
Pulse Amplitude Modulation, Time-Division Multiplexing, Pulse Position Modulation: Generation and Detection
of PPM wave. The Quantization Process. Pulse Code Modulation: Sampling, Quantization, Encoding, line Codes,
Differential encoding, Regeneration, Decoding, filtering, multiplexing.
[Text2: 7.1,7.2,7.3,7.4,7.5,7.6,7.8,7.9]
RBT: L1,L2,L3

MODULE-5
Baseband Transmission of Digital signals: Introduction, Intersymbol Interference, Eye Pattern, Nyquist
criterion for distortionless Transmission, Baseband M-ary PAM Transmission.
[Text2:8.1,8.4,8.5,8.6,8.7]
Noise: Signal to Noise Ratio, External Noise, Internal Noise, Semiconductor Noise, Expressing Noise Levels, Noise
in Cascade Stages.
[Text1:9.5]
RBT:L1,L2,L3

EC(ACT) 30042024 2
TEMPLATE for IPCC (26.04.2022) Annexure-III

PRACTICAL COMPONENT OF IPCC (Experiments can be conducted using MATLAB/SCILAB/OCTAVE)

Sl.NO Experiments
1 Basic Signals and Signal Graphing: a) unit Step, b) Rectangular, c) standard triangle d) sinusoidal and e)
Exponential signal.
2 Illustration of signal representation in time and frequency domains for a rectangular pulse.

3 Amplitude Modulation and demodulation: Generation and display the relevant signals and its spectrums.

4
Frequency Modulation and demodulation: Generation and display the relevant signals and its spectrums.

5
Sampling and reconstruction of low pass signals. Display the signals and its spectrum.

6
Time Division Multiplexing and demultiplexing.

7
PCM Illustration: Sampling, Quantization and Encoding

8
Generate a)NRZ, RZ and Raised cosine pulse, b) Generate and plot eye diagram

9
Generate the Probability density function of Gaussian distribution function.

10 Display the signal and its spectrum of an audio signal.

Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:
1. Understand the principles of analog communication systems and noise modelling.
2. Identify the schemes for analog modulation and demodulation and compare their performance.
3. Design of PCM systems through the processes sampling, quantization and encoding.
4. Describe the ideal condition, practical considerations of the signal representation for baseband transmission of
digital signals.
5. Identify and associate the random variables and random process in Communication system design.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a pass in the course if
he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation)
and SEE (Semester End Examination) taken together.

The IPCC means the practical portion integrated with the theory of the course. CIE marks for the theory component
are 25 marks and that for the practical component is 25 marks.
CIE for the theory component of the IPCC
• 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests (Two Tests, each
of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other assessment methods
mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the syllabus and the second test after
covering 85-90% of the syllabus.
• Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for the theory
component of IPCC (that is for 25 marks).
• The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of IPCC.

EC(ACT) 30042024 3
TEMPLATE for IPCC (26.04.2022) Annexure-III

CIE for the practical component of the IPCC

• 15 marks for the conduction of the experiment and preparation of laboratory record, and 10 marks for the test
to be conducted after the completion of all the laboratory sessions.
• On completion of every experiment/program in the laboratory, the students shall be evaluated including viva-
voce and marks shall be awarded on the same day.
• The CIE marks awarded in the case of the Practical component shall be based on the continuous evaluation of
the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of all experiments’ write-
ups are added and scaled down to 15 marks.
• The laboratory test (duration 02/03 hours) after completion of all the experiments shall be conducted for 50
marks and scaled down to 10 marks.
• Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory component of
IPCC for 25 marks.
• The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the IPCC.
SEE for IPCC
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for the
course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum of 3
sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by the student shall be proportionally scaled down to 50 Marks
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will have a CIE
component only. Questions mentioned in the SEE paper may include questions from the practical
component.
• The minimum marks to be secured in CIE to appear for SEE shall be 10 (40% of maximum marks-25) in the
theory component and 10 (40% of maximum marks -25) in the practical component. The laboratory
component of the IPCC shall be for CIE only. However, in SEE, the questions from the laboratory component
shall be included. The maximum of 04/05 sub-questions are to be set from the practical component of IPCC,
the total marks of all questions should not be more than 20 marks.
• SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to qualify for
the SEE. Marks secured will be scaled down to 50.

• The student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100)
in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken
together.
Suggested Learning Resources:
Books
1. Louis E Frenzel, Principles of Electronic Communication Systems, 3rd Edition, Mc Graw Hill Education
(India) Private Limited, 2016. ISBN: 978-0-07-066755-6.
2. Simon Haykin & Michael Moher, Communication Systems, 5th Edition, John Wiley, India Pvt. Ltd, 2010, ISBN:
978-81-265-2151-7.
Reference Books

EC(ACT) 30042024 4
TEMPLATE for IPCC (26.04.2022) Annexure-III

1. B P Lathi, Zhi Ding, “Modern Digital and Analog Communication Systems”, Oxford University Press., 4th
edition, 2010, ISBN: 97801980738002.
2. Herbert Taub, Donald L Schilling, Goutam Saha, “Principles of Communication systems”, 4th Edition, Mc
Graw Hill Education (India) Private Limited, 2016. ISBN: 978-1-25-902985-1

Web links and Video Lectures (e-Resources):

1. Principles of Communication Systems https://nptel.ac.in/courses/108104091

2. Communication Engineering https://nptel.ac.in/courses/117102059

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

1. Assignments and test – Knowledge level, Understand Level and Apply level
2. Experiential Learning by using free and open source software’s SCILAB or OCTAVE
3. Open ended questions by faculty, Open ended questions from students

EC(ACT) 30042024 5
03.10.2022

VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI

B.E: Electronics & Communication Engineering / B.E: Electronics & Telecommunication
Engineering NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS)
(Effective from the academic year 2023 – 24)

IV Semester

Control Systems
Course Code BEC403 CIE Marks 50
Teaching Hours/Week (L: T: P) (3:0:2) SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 12 Lab slots Total Marks 100
Credits 04 Exam Hours 03
Course objectives: This course will enable students to:
1. Understand basics of control systems and design mathematical models using block diagram
reduction, SFG, etc.
2. Understand Time domain and Frequency domain analysis.
3. Analyze the stability of a system from the transfer function
4. Familiarize with the State Space Model of the system.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teacher can use to accelerate the attainment of the various
course outcomes.
• Lecture method (L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
• Show Video/animation films to explain the different concepts of Linear Algebra & Signal
Processing.
• Encourage collaborative (Group) Learning in the class.
• Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes
critical thinking.
• Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather than
simply recall it.
• Topics will be introduced in a multiple representation.
• Show the different ways to solve the same problem and encourage the students to come up
withtheir own creative ways to solve them.
• Discuss how every concept can be applied to the real world - and when that's possible, it
helps improve the students' understanding.
• Adopt Flipped class technique by sharing the materials / Sample Videos prior to the class and
have discussions on the that topic in the succeeding classes.
• Give Programming Assignments.
Module-1
Introduction to Control Systems: Types of Control Systems, Effect of Feedback Systems,
Differential equation of Physical Systems -Mechanical Systems, Electrical Systems, Analogous
Systems. (Textbook 1: Chapter 1.1, 2.2)

Teaching- Chalk and Talk, YouTube videos

LearningProcess RBT Level: L1, L2, L3

EC(ACT) 30042024
 03.10.2022

Module-2
Block diagrams and signal flow graphs: Transfer functions, Block diagram algebra and Signal
Flow graphs. (Textbook 1: Chapter 2.4, 2.5, 2.6)
Teaching- Chalk and Talk, YouTube videos, Any software tool to implement block diagram
LearningProcess reduction techniques and Signal Flow graphs
RBT Level: L1, L2, L3
Module-3
Time Response of feedback control systems: Standard test signals, Unit step response of First
and Second order Systems. Time response specifications, Time response specifications of second
order systems, steady state errors and error constants. Introduction to PI, PD and PID Controllers
(excluding design). (Textbook 1: Chapter 5.3, 5.4, 5.5)
Teaching- Chalk and Talk, YouTube videos, Any software tool to show time
LearningProcess response for various transfer functions and PI, PD and PID controllers.
RBT Level: L1, L2, L3
Module-4
Stability analysis: Concepts of stability, Necessary conditions for Stability, Routh stability
criterion, Relative stability analysis: more on the Routh stability criterion.
Introduction to Root-Locus Techniques, The root locus concepts, Construction of root loci.
(Textbook 1: Chapter 6.1, 6.2, 6.4, 6.5, 7.1, 7.2, 7.3)
Teaching- Chalk and Talk, YouTube videos, Any software tool to plot Root locus for
LearningProcess various transfer functions
RBT Level: L1, L2, L3
Module-5
Frequency domain analysis and stability: Correlation between time and frequency response,
Bode Plots, Experimental determination of transfer function. (Textbook 1: Chapter 4: 8.1, 8.2, 8.4)
Mathematical preliminaries, Nyquist Stability criterion, (Stability criteria related to polar plots are
excluded) (Textbook 1: 9.2, 9.3)
State Variable Analysis: Introduction to state variable analysis: Concepts of state, state variable
and state models. State model for Linear continuous –Time systems, solution of state equations.
(Textbook 1: 12.2, 12.3, 12.6)
Teaching- Chalk and Talk, YouTube videos, Any software tool to draw Bode plot
LearningProcess for various transfer functions
RBT Level: L1, L2, L3

PRACTICAL COMPONENT OF IPCC

Using suitable simulation software (P-Spice/ MATLAB / Python / Scilab / OCTAVE / LabVIEW)
demonstrate the operation of the following circuits:
Sl.No Experiments
1 Implement Block diagram reduction technique to obtain transfer function a control system.
2 Implement Signal Flow graph to obtain transfer function a control system.
3 Simulation of poles and zeros of a transfer function.
4 Implement time response specification of a second order Under damped System, for different
damping factors.
5 Implement frequency response of a second order System.
6 Implement frequency response of a lead lag compensator.
7 Analyze the stability of the given system using Routh stability criterion.
8 Analyze the stability of the given system using Root locus.
9 Analyze the stability of the given system using Bode plots.
10 Analyze the stability of the given system using Nyquist plot.
11 Obtain the time response from state model of a system.
12 Implement PI and PD Controllers.
13 Implement a PID Controller and hence realize an Error Detector.
14 Demonstrate the effect of PI, PD and PID controller
EC(ACT) 30042024 on the system response.
03.10.2022

Course Outcomes

At the end of the course the student will be able to:

1. Deduce transfer function of a given physical system, from differential equation
representation or Block Diagram representation and SFG representation.
2. Calculate time response specifications and analyse the stability of the system.
3. Draw and analyse the effect of gain on system behaviour using root loci.
4. Perform frequency response Analysis and find the stability of the system.
5. Represent State model of the system and find the time response of the system.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam
(SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20
marks). A student shall be deemed to have satisfied the academic requirements and earned the
credits allotted to each subject/ course if the student secures not less than 35% (18 Marks out
of 50) in the semester-end examination (SEE), and a minimum of 40% (40 marks out of 100) in
the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination)
taken together

CIE for the theory component of IPCC

Two Tests each of 20 Marks (duration 01 hour)
• First test at the end of 5th week of the semester
• Second test at the end of the 10th week of the semester
Two assignments each of 10 Marks
• First assignment at the end of 4th week of the semester
• Second assignment at the end of 9th week of the semester
Scaled-down marks of two tests and two assignments added will be CIE marks for the theory
component of IPCC for 30 marks.

CIE for the practical component of IPCC

• On completion of every experiment/program in the laboratory, the students shall be
evaluated and marks shall be awarded on the same day. The 15 marks are for
conducting the experiment and preparation of the laboratory record, the other 05
marks shall be for the test conducted at the end of the semester.
• The CIE marks awarded in the case of the Practical component shall be based on the
continuous evaluation of the laboratory report. Each experiment report can be
evaluated for 10 marks. Marks of all experiments’ write-ups are added and scaled down
to 15 marks.
• The laboratory test (duration 03 hours) at the end of the 15th week of the semester
/after completion of all the experiments (whichever is early) shall be conducted for
50 marks and scaled down to 05 marks.
• Scaled-down marks of write-up evaluations and tests added will be CIE marks for the
laboratory component of IPCC for 20 marks.

EC(ACT) 30042024
03.10.2022

SEE for IPCC

Theory SEE will be conducted by University as per the scheduled timetable, with common
question papers for the course (duration 03 hours)
• The question paper will have ten questions. Each question is set for 20 marks.
• There will be 2 questions from each module. Each of the two questions under a
module (with a maximum of 3 sub-questions), should have a mix of topics under that
module.
• The students have to answer 5 full questions, selecting one full question from each
module.

The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical
portion will have a CIE component only. Questions mentioned in the SEE paper shall
include questions from the practical component.
• The minimum marks to be secured in CIE to appear for SEE shall be the 12 (40% of
maximum marks-30) in the theory component and 08 (40% of maximum marks -20) in
the practical component. The laboratory component of the IPCC shall be for CIE only.
However, in SEE, the questions from the laboratory component shall be included. The
maximum of 04/05 questions to be set from the practical component of IPCC, the total
marks of all questions should not be more than the 20 marks.

SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to
qualify inthe SEE. Marks secured out of 100 shall be reduced proportionally to 50.
Suggested Learning Resources:
Text Books
1. Control Systems Engineering, I J Nagrath, M. Gopal, New age international Publishers, Fifth
edition.

Web links and Video Lectures (e-Resources):

• https://nptel.ac.in/courses/108106098

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Programming Assignments / Mini Projects can be given to improve programming skills

EC(ACT) 30042024
Template for Practical Course and if AEC is a practical Course Annexure-V

Communication Laboratory Semester 4

Course Code BECL404 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 0:0:2 SEE Marks 50
Credits 01 Exam Hours 03
Examination type (SEE) Theory/Practical/Viva-Voce /Term-work/Others
Course objectives:
This laboratory course enables students to
• Understand the basic concepts of AM and FM modulation and demodulation.
• Design and analyse the electronic circuits used for AM and FM modulation and demodulation circuits.
• Understand the sampling theory and design circuits which enable sampling and reconstruction of analog signals.
• Design electronic circuits to perform pulse amplitude modulation, pulse position modulation and pulse width
modulation.

Experiments (Experiments to be conducted using hardware components)

1
Design and test a high-level collector Modulator circuit and Demodulation the signal using diode detector.

2
Test the Balanced Modulator / Lattice Modulator (Diode ring)

3
Design a Frequency modulator using VCO and FM demodulator using PLL (Use IC566 and IC565).

4
Design and plot the frequency response of Preemphesis and Deemphasis Circuits

5
Design and test BJT/FET Mixer

6
Design and test Pulse sampling, flat top sampling and reconstruction

7
Design and test Pulse amplitude modulation and demodulation.

8
Generation and Detection of Pulse position Modulation

9 Generation and Detection of Pulse Width Modulation

10 PLL Frequency Synthesizer

11 Data formatting and Line Code Generation

12 PCM Multiplexer and Demultiplexer

Course outcomes (Course Skill Set):

At the end of the course the student will be able to:
1. Illustrate the AM generation and detection using suitable electronic circuits.
2. Design of FM circuits for modulation, demodulation and noise suppression.
3. Design and test the sampling, Multiplexing and pulse modulation techniques using electronic hardware.
4. Design and Demonstrate the electronic circuits used for RF transmitters and receivers.

EC(ACT) 30042024
Template for Practical Course and if AEC is a practical Course Annexure-V

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation (CIE):

CIE marks for the practical course are 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
• Each experiment is to be evaluated for conduction with an observation sheet and record write-up. Rubrics for
the evaluation of the journal/write-up for hardware/software experiments are designed by the faculty who is
handling the laboratory session and are made known to students at the beginning of the practical session.
• Record should contain all the specified experiments in the syllabus and each experiment write-up will be
evaluated for 10 marks.
• Total marks scored by the students are scaled down to 30 marks (60% of maximum marks).
• Weightage to be given for neatness and submission of record/write-up on time.
• Department shall conduct a test of 100 marks after the completion of all the experiments listed in the
syllabus.
• In a test, test write-up, conduction of experiment, acceptable result, and procedural knowledge will carry a
weightage of 60% and the rest 40% for viva-voce.
• The suitable rubrics can be designed to evaluate each student’s performance and learning ability.
• The marks scored shall be scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and marks of a test is the total CIE marks scored
by the student.
Semester End Evaluation (SEE):
• SEE marks for the practical course are 50 Marks.
• SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed
by the Head of the Institute.
• The examination schedule and names of examiners are informed to the university before the conduction of
the examination. These practical examinations are to be conducted between the schedule mentioned in the
academic calendar of the University.
• All laboratory experiments are to be included for practical examination.
• (Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be strictly
adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be decided jointly
by examiners.
• Students can pick one question (experiment) from the questions lot prepared by the examiners jointly.
• Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by examiners.
• General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and result in -60%,
Viva-voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks and scored marks shall be
scaled down to 50 marks (however, based on course type, rubrics shall be decided by the examiners)
• Change of experiment is allowed only once and 15% of Marks allotted to the procedure part are to be made
zero.
The minimum duration of SEE is 02 hours

Suggested Learning Resources:

EC(ACT) 30042024
Template for Practical Course and if AEC is a practical Course Annexure-V

1. Louis E Frenzel, Principles of Electronic Communication Systems, 3rd Edition, Mc Graw Hill Education
(India) Private Limited, 2016. ISBN: 978-0-07-066755-6.

EC(ACT) 30042024
 13.09.2023

MICROCONTROLLERS Semester 4
Course Code BEC405A CIE Marks 50
Teaching Hours/Week(L:T:P) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 3
Examination type(SEE) Theory
Course objectives:
This course will enable students to:
• Understand the difference between Microprocessor and Microcontroller and embedded
microcontrollers.
• Analyze the basic architecture of 8051microcontroller.
• Program 8051 microcontroller using Assembly Language and C.
• Understand the operation and use of inbuilt Timers/Counters and Serial port of 8051
• Understand the interrupt structure of 8051 and Interfacing I/O devices using I/O ports of 8051.

Teaching-Learning Process(General Instructions)

The samples strategies, which the teacher can use to accelerate the attainment of the various
course outcomes are listed in the following:
1. Lecture method (L) does not mean only the traditional lecture method, but a
different type of teaching method may be adopted to develop the outcomes.
2. Show Video/animation films to explain the functioning of various techniques.
3. Encourage collaborative(Group)Learning in the class
4. Ask at least three HOTS(Higher-order Thinking) questions in the class, which
promotes critical thinking
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical kills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather
than simply recall it.
6. Show the different ways to solve the same problem and encourage the students to
come up with their own creative ways to solve them.
7. Discuss how every concept can be applied to the real world and when that's possible,
it helps improve the students' understanding.
Give Programming Assignments.

RBT
Level
Module-1 ( 8 Hrs )
Microcontroller: Microprocessor Vs Microcontroller, Micro L1,L2
controller & Embedded Processors, Processor Architectures-Harvard Vs
Princeton & RISC Vs CISC , 8051 Architecture- Registers, Pin diagram, I/O
ports functions, Internal Memory organization. External Memory (ROM &
RAM) interfacing. (Text book 1-1.1,Text book 2-1.0,1.1,3.0,3.1,3.2,3.3 Text
book 3-Pg 5-9)
Module-2 ( 8 Hrs )
Instruction Set: 8051 Addressing Modes, Data Transfer Instructions, L1,L2
Arithmetic instructions, Logical Instructions, Jump & Call Instructions
Stack & Subroutine Instructions of 8051 (with examples in assembly
Language). (Text book 2- Chapter 5,6,7,8, Additional reading Refer
Textbook 3, Chapter 3 for complete understanding of instructions with
flow diagrams)
EC(ACT) 30042024
 13.09.2023

Module-3 ( 8 Hrs )
Timers/Counters & Serial port programming: L1,L2,
L3
Basics of Timers & Counters, Data types & Time delay in the 8051 using
C, Programming 8051 Timers, Mode 1 & Mode 2 Programming, Counter
Programming (Assembly Language only). (Text book 2- 3.4, Text book 1-
7.1, 9.1,9.2)

Basics of Serial Communication, 8051 Connection to RS232,

Programming the 8051 to transfer data serially & to receive data serially
using C.( Text book 2- 3.5, Text book 1- 10.1,10.2,10.3 except assembly
language programs, 10.5)

Module-4 ( 8 Hrs )
Interrupt Programming: Basics of Interrupts, 8051 Interrupts, Programming L1,L2,
Timer Interrupts, Programming Serial Communication Interrupts, Interrupt L3
Priority in 8051(Assembly Language only) ( Text book 2- 3.6, Text book 1-
11.1,11.2,11.4, 11.5)

Module-5 ( 8 Hrs )
I/O Port Interfacing & Programming: I/O Programming in 8051 C, LCD L1, L2, L3
interfacing, DAC 0808 Interfacing, ADC 0804 interfacing, Stepper motor
interfacing, DC motor control & Pulse Width Modulation (PWM) using C
only. (Text book 1- 7.2, 12.1, 13.1, 13.2, 17.2, 17.3)

Course outcome (Course Skill Set)

At the end of the course, students will be able to:
1. Describe the difference between Microprocessor and Microcontroller, Types of
Processor Architectures and Architecture of 8051Microcontroller.
2. Discuss the types of 8051 Microcontroller Addressing modes & Instructions with
Assembly Language Programs.
3. Explain the programming operation of Timers/Counters and Serial port of
8051 Microcontroller.
4. Illustrate the Interrupt Structure of 8051 Microcontroller & its programming.
5. Develop C programs to interface I/O devices with 8051 Microcontroller.

EC(ACT) 30042024
 13.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE)is
50%.The minimum passing mark for the CIE is 40%of the maximum marks(20marks out of 50) and for
the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is
declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
There are 25marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
Each test shall be conducted for 25marks.The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of
the syllabus. The average of the two tests shall be scaled down to 25 marks
Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then
only one assignment for the courses hall be planned. The schedule for assignments shall be
planned properly by the course teacher. The teacher should not conduct two assignments at the end
of the semester if two assignments are planned. Each assignment shall be conducted for 25 marks.
(If two assignments are conducted then the sum of the two assignments shall be scaled down to 25
marks)
The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.
Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20marks.
2. There will be 2questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored shall be proportionally reduced to50 marks

Suggested Learning Resources:

TEXT BOOKS
1. The “8051 Microcontroller and Embedded Systems – Using Assembly and C”,
Muhammad Ali Mazidi and Janice Gillespie Mazidi and Rollind. Mckinlay; Phi,
2006 / Pearson, 2006.
2. “The 8051 Microcontroller”, Kenneth j. Ayala, 3rd edition, Thomson/Cengage
Learning.
3. “Programming And Customizing The 8051 Microcontroller”.,Myke Predko Tata
Mc Graw-Hill Edition 1999 (reprint 2003).
REFERENCEBOOKS:
1. “The 8051 Microcontroller Based Embedded Systems”, Manish K Patel,
McGraw Hill, 2014, ISBN: 978-93-329-0125-4.
2. “Microcontrollers: Architecture, Programming, Interfacing and System Design”, Raj
Kamal, Pearson Education, 2005.
Web links and Video Lectures(e-Resources):
https://youtu.be/pA6K5NgWTow?si=zQqqgXQq50dVL_-s

EC(ACT) 30042024
 Annexure-II 1

Industrial Electronics Semester IV

Course Code BEC405B CIE Marks 50
Teaching Hours/Week (L: T:P: S) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 hours Total Marks 100
Credits 03 Exam Hours 03
Examination type (SEE) Theory
Course objectives: This course will enable student to
 Explain broad types of industrial power devices, there structure, and its characteristics.
 Design and analyse the broad categories of power electronic circuits.
 Explain various types of MEMs devices, principle of operation and construction.
 Familiarize with soft core processors and computer architecture.
 Apply protective methods for devices and circuits.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Lecture method (L) does not mean only traditional lecture method, but different type of teaching
methods may be adopted to develop the outcomes.
2. Show Video/animation films to explain evolution of communication technologies.
3. Encourage collaborative (Group) Learning in the class.
4. Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes critical
thinking.
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking skills
such as the ability to evaluate, generalize, and analyze information rather than simply recall it.
6. Show the different ways to solve the same problem and encourage the students to come up with their
own creative ways to solve them.
7. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.

Module-1
Industrial Power Devices: General purpose power diodes, fast recovery power diodes, schottky power
diodes, silicon carbide power diodes (Text book 1: 2.5, 2.6), Power MOSFETs, Steady state characteristics,
switching characteristics, silicon carbide MOSFETs, COOLMOS, Junction field effect transistors, operation
and characteristics of JFETs, Silicon Carbide JFET structures, Bipolar Junction Transistors, Steady state
characteristics, switching characteristics, silicon carbide BJTs, IGBT, silicon carbide IGBTs (Text book 1:
4.3, 4.4, 4.6, 4.7
Module-2
Power Electronics Circuits: ), Thyristor, Thyristor characteristics, two transistor model (Text book 1:
9.2, 9.3, 9.4).Controlled Rectifiers – Single phase full converter with R and RL load, Single phase dual
converters, and Three phase full converter with RL load (Text book 1: 10.2, 10.3, 10.4).
Switching mode regulators – Buck Regulator, Boost regulator, Buck – Boost regulator, comparison of
regulators (Text book 1: 5.9.1, 5.9.2, 5.9.3, 5.10)

Module-3
Inverters – Principle of operation, Single phase bridge inverter, Three phase inverter with 180 and 120
degree conduction, Current source inverter (Text book 1: 6.3, 6.4, 6.5, 6.9).
AC voltage controllers – Single phase full wave controller with resistive load, single phase full wave
controller with inductive load (Text book 1: 11.3, 11.4).

EC(ACT) 30042024 1
 Annexure-II 2

Module-4
MEMS Devices: Sensing and Measuring Principles, Capacitive Sensing, Resistive Sensing, Piezoelectric
Sensing, Thermal Transducers, Optical Sensors, Magnetic Sensors, MEMS Actuation Principles, Electrostatic
Actuation, Thermal Actuation, Piezoelectric Actuation, Magnetic Actuation, MEMS Devices Inertial Sensors,
Pressure Sensors, Radio Frequency MEMS: Capacitive Switches and Phase Shifters, Microfluidic Components,
Optical Devices. (Text book 2: 13.1, 13.3, 13.4)
MEMS Applications: Introduction, Industrial, Automotive, Biomedical (Text book 2:15.1, 15.2,
15.3, 15.4)
Module-5
Protections of Devices and Circuits: Cooling and Heat sinks, Thermal Modeling of Power Switching Devices,
Electrical Equivalent Thermal model, Mathematical Thermal Equivalent Circuit, Coupling of Electrical and
Thermal Components, Snubber circuits, Voltage protection by Selenium Diodes and Metaloxide Varistors,
Current protection, Fusing, Fault current with AC source, Fault current with DC source, Electromagnetic
Interference, sources of EMI, Minimizing EMI Generation, EMI shielding, EMI standards (Text book 1: 17.2,
17.3, 17.4, 17.5, 17.6, 17.7, 17.8, 17.9).
Course outcome (Course Skill Set)
At the end of the course, the student will be able to :
1. Explain different types of industrial power devices such as MOSFET, BJT, IGBT etc, there
structure, and its operating characteristics.
2. Design and analyse the power electronic circuits such as switch mode regulators, inverters,
controlled rectifiers and ac voltage controllers.
3. Explain various types of MEMs devices used for sensing pressure, temperature, current,
voltage, humidity, vibration etc..
4. Familiarize with soft core processors such as ASIC and FPGA.
5. Familiarize with computer hardware, software, architecture, instruction set, memory
organization, multiprocessor architecture.
6. Apply protective methods for devices various industrial power devices based on thermal
requirements and develop protective methods for the circuits against various electrical
parameters.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a pass
in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment
Test component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of
the coverage of the syllabus, and the second test will be administered after 85-90% of the
coverage of the syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then
only one assignment for the course shall be planned. The schedule for assignments shall be
planned properly by the course teacher. The teacher should not conduct two assignments at the
end of the semester if two assignments are planned. Each assignment shall be conducted for 25
marks. (If two assignments are conducted then the sum of the two assignments shall be scaled
down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.

EC(ACT) 30042024 2
 Annexure-II 3

Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for
the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Text Books
1. Power Electronics: Devices, Circuits, and Applications, Muhammad H. Rashid, Pearson, 4 th International
edition.
2. Fundamentals of Industrial Electronics , Bogdan M. Wilamowski, J. David Irwin, CRC Press, 2011,

Reference Books

1. Thomas E. Kissell, Industrial Electronics: Applications for Programmable Controllers, Instrumentation

and Process Control, and Electrical Machines and Motor Controls, 3rd edition, 2003, Prentice Hall.
2. Ned Mohan, T.M. Undeland and W.P. Robbins, “Power Electronics: Converters, Applications and Design”,
Wiley India Ltd, 2008.

Web links and Video Lectures (e-Resources):

 https://archive.nptel.ac.in/courses/108/102/108102145/
 https://nptel.ac.in/courses/117105082
 https://www.youtube.com/channel/UCKg8GNii0Q-ieXE56AXosGg/featured
 https://www.ieee-ies.org/

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

 Quiz and Seminars

EC(ACT) 30042024 3
 13.09.2023

OPERATING SYSTEM Semester 4

Course Code BEC405C CIE Marks 50
Teaching Hours/Week(L:T:P) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 3
Examination type(SEE) Theory
Course objectives:
This course will enable students to:
 Understand the services provided by an operating system.
 Explain how processes are synchronized and scheduled.
 Understand different approaches of memory management and virtual memory
management. Describe the structure and organization of the file system
 Understand interprocess communication and deadlock situations.

Teaching-Learning Process(General Instructions)

The samples strategies, which the teacher can use to accelerate the attainment of the various
course outcomes are listed in the following:

1. Lecturer method (L) need not to be only traditional lecture method, but alternative effective
teaching methods could be adopted to attain the outcomes.
2. Use of Video/Animation to explain functioning of various concepts.
3. Encourage collaborative (Group Learning) Learning in the class.
4. Ask at least three HOT (Higher order Thinking) questions in the class, which promotes critical
thinking.
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
design thinking skills such as the ability to design, evaluate, generalize, and analyze information
rather than simply recall it.
6. Introduce Topics in manifold representations.
7. Show the different ways to solve the same problem and encourage the students to come up
with their own creative ways to solve them.
8. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
RBT
Level
Module-1
Introduction to Operating Systems: OS, Goals of an OS, Operation of an OS, L1,L2
Computational Structures, Resource allocation techniques, Efficiency, System
Performance and User Convenience, Classes operating System, Batch processing, Multi
programming, Time Sharing Systems, Real Time and distributed Operating Systems
(Topics from Sections 1.2, 1.3, 2.2 to 2.8 of Text).

Module-2
Process Management: OS View of Processes, PCB, Fundamental State Transitions of a L1,L2,
process, Threads, Kernel and User level Threads, Non-preemptive scheduling- FCFS and L3
SRN, Preemptive Scheduling- RR and LCN, Scheduling in Unix and Scheduling in Linux
(Topics from Sections 3.3, 3.3.1 to 3.3.4, 3.4, 3.4.1, 3.4.2 , Selected scheduling topics
from 4.2 and 4.3 , 4.6, 4.7 of Text).
EC(ACT) 30042024
 13.09.2023

Module-3
Memory Management: Contiguous Memory allocation, Non-Contiguous Memory L1,L2,
Allocation, Paging, Segmentation, Segmentation with paging, Virtual Memory L3
Management, Demand Paging, VM handler, FIFO, LRU page replacement policies,
Virtual memory in Unix and Linux
(Topics from Sections 5.5 to 5.9, 6.1 to 6.3 except Optimal policy and 6.3.1, 6.7,6.8
of Text)

Module-4
L1,L2
File Systems: File systems and IOCS, File Operations, File Organizations, Directory
structures, File Protection, Interface between File system and IOCS, Allocation of disk
space, Implementing file access
(Topics from Sections 7.1 to 7.8 of Text).

Module5
Message Passing and Deadlocks: Overview of Message Passing, Implementing L1, L2
message passing, Mailboxes, Deadlocks, Deadlocks in resource allocation, Handling
deadlocks, Deadlock detection algorithm, Deadlock Prevention
(Topics from Sections 10.1 to 10.3, 11.1 to 11.5 of Text).

Course outcome (Course Skill Set)

At the end of the course, students will be able to:
1. Explain the goals, structure, operation and types of operating systems.
2. Apply scheduling techniques to find performance factors.
3. Explain organization of file systems and IOCS.
4. Apply suitable techniques for contiguous and non-contiguous memory allocation.
5. Describe message passing, deadlock detection and prevention methods.

EC(ACT) 30042024
 13.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE)is
50%.The minimum passing mark for the CIE is 40%of the maximum marks(20marks out of 50) and for
the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is
declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
There are 25marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
Each test shall be conducted for 25marks.The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the courses hall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.
Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20marks.
2. There will be 2questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored shall be proportionally reduced to50 marks

Suggested Learning Resources:

TEXT BOOKS
Operating Systems – A concept based approach, by Dhamdhere, TMH, 2nd edition.
REFERENCEBOOKS:
1. Operating systems concepts, Silberschatz and Galvin, John Wiley India Pvt. Ltd, 5th
edition,2001.
2. Operating system–internals and design system, William Stalling, Pearson Education, 4th ed,
2006.
3. Design of operating systems, Tannanbhaum, TMH, 2001.
Web links and Video Lectures(e-Resources):
 https://archive.nptel.ac.in/courses/106/105/106105214/
 https://onlinecourses.nptel.ac.in/noc20_cs04/preview
 https://onlinecourses.nptel.ac.in/noc21_cs72/preview
 https://nptel.ac.in/courses/106106144 EC(ACT) 30042024
 1

Data Structures Using C Semester IV

Course Code BEC405D CIE Marks 50
Teaching Hours/Week (L: T:P: S) 3:0:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 03
Examination nature (SEE) Theory
COURSE OVERVIEW:

COURSE OBJECTIVES:
The objectives of this course are to:
1. Develop proficiency in designing and implementing fundamental data structures.
2. Learn various sorting and searching algorithms and analyze their time complexity.
3. Understand algorithmic problem-solving techniques, including recursion.
4. Explore advanced data structures like trees, graphs, and hash tables.
5. Apply data structures and algorithms knowledge to solve real-world programming challenges
efficiently.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teachers can use to accelerate the attainment of the
various course outcomes.
1. The lecturer's approach (L) does not have to be limited to traditional methods of teaching. It
is possible to incorporate alternative and effective teaching methods to achieve the desired
outcomes.
2. Utilize videos and animations to illustrate the functioning of different techniques used in the
manufacturing of smart materials.
3. Foster collaborative learning exercises within the classroom to encourage group participation
and engagement.
4. Pose a minimum of three Higher Order Thinking (HOT) questions during class discussions
to stimulate critical thinking among students.
5. Implement Problem-Based Learning (PBL) as an approach that enhances students' analytical
skills and nurtures their ability to design, evaluate, generalize, and analyze
information, rather than solely relying on rote memorization.
Module-1
Arrays:1D,2D and multidimensional.
Pointers: Definition and Concepts, Array of pointers, Structures and unions. Array of structures,
pointer arrays, pointer to structures. Passing pointer variable as parameter in functions
Dynamic memory allocation: malloc(), calloc(), realloc() and free function.
Introduction to data structures and algorithms
Text book 1 -Chapter-1.1-1.3 except Rational Numbers.
Text Book 2, chapter-2

EC(ACT) 30042024 1
 2

Module-2
The Stack – Definition and examples, primitive operations, Example. Representing Stacks in C,
Example:Infix,Postfix and Prefix,converting an Expression from Infix to Prefix and Program.
Text Book -1-Chapter – 2.1-2.3
Recursion – Recursive Definition and Processes, Recursion in C, Writing Recursive Programs.
Recursions - Text Book -1-Chapter – 3.1-3.3

Module-3
Queues and Lists – The Queue and its sequential representation, Linked Lists, Lists in C.
Other Lists structures – Circular Lists, Stacks, Queues as circular list. The Josephus problem ,doubly
linked lists.
Linked lists and Queues - Text Book -1-Chapter – 4.1-4.3,4.5

Module-4

Trees – Binary Trees, binary tree representations, Huffman algorithm, Trees and their applications.
Searching – Basic searching Techniques, Tree Searching.
Trees - Text Book -1-Chapter – 5.1-5.3,5.5,7.1,7.2

Module-5
Hashing – Introduction, Static Hashing, Dynamic Hashing
Text Book 3 -8.1 – 8.3
Graphs - Graph representation, Elementary graph operations, Minimum cost spanning Trees –
Kruskal’s Algorithm, Prim’s algorithm
Text Book 3 - 6.1,6.2,6.3.1,6.3.2
Course Outcomes (COs) (Course Skill Set)
At the end of the course, the student will be able to:
1. Master the implementation and application of key data structures in programming.
2. Demonstrate the ability to analyze algorithm efficiency and optimize code.
3. Solve complex problems by applying algorithmic strategies and techniques.
4. Design and implement algorithms for tasks involving searching, sorting, and graph traversal.
5. Utilize data structures and algorithms to enhance software performance and scalability

EC(ACT) 30042024 2
 3

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the
SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). A student shallbe deemed
to have satisfied the academic requirements and earned the credits allotted to each subject/ course if the
student secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal
Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

• For the Assignment component of the CIE, there are 25 marks and for the InternalAssessment
Test component, there are 25 marks.
• The first test will be administered after 40-50% of the syllabus has been covered, and the
second test will be administered after 85-90% of the syllabus has been covered
• Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-basedthen
only one assignment for the course shall be planned. The teacher should not conduct two
assignments at the end of the semester if two assignments are planned.
• For the course, CIE marks will be based on a scaled-down sum of two tests and other
methods of assessment.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.
Semester-End Examination (SEE):
Theory SEE will be conducted by University as per the scheduled timetable, with commonquestion
papers for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (witha
maximum of 3 sub-questions), should have a mix of topics under that module.

Suggested Learning Resources:

TEXT BOOKS:
1. Data Structures using C and C++, Yedidyah, Augenstein, Tannenbaum, 2nd Edition, Pearson
Education, 2007.
2. Data Structures using C, Reema Thareja, 2nd Edition, Oxford University Press, 2011
3. Fundamentals of Data structures in C, 2nd Edition, Horowitz, Sahni, Anderson freed
Universities Press,2008

REFERENCEBOOKS:
1. Reema Thareja, Computer fundamentals and programming in C, second edition, Oxford
University Press.
2. Gilberg and Forouzan, Data Structures: A Pseudo-code approach with C, 2ndEd,
CengageLearning,2014.

EC(ACT) 30042024 3
 4

Web links and Video Lectures (e-Resources):

• https://archive.nptel.ac.in/courses/106/102/106102064/
• https://archive.nptel.ac.in/courses/106/106/106106127/
• https://nptel.ac.in/courses/106102064
• http://elearning.vtu.ac.in/econtent/courses/video/CSE/06CS35.html
• https://nptel.ac.in/courses/106/105/106105171/
• http://www.nptelvideos.in/2012/11/data-structures-and-algorithms.html
• http://elearning.vtu.ac.in/econtent/courses/video/CSE/06CS43.html
• https://nptel.ac.in/courses/106/101/106101060/

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Real world problem solving using group discussion.
• Back/Forward stacks on browsers.
• Undo/Redo stacks in Excel or Word.
• Linked list representation of real-world queues -Music player, image viewer
• Real world problem solving and puzzles using group discussion. E.g., Fake coin identification, Peasant,
wolf, goat, cabbage puzzle, Konigsberg bridge puzzle etc.,
• Demonstration of solution to a problem through programming.

EC(ACT) 30042024 4
EC(ACT) 30042024
Assessment Details(both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The minimum
passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each course. The student has to secure not less than 35% (18
Marks out of 50) in the semester-end examination (SEE).
Continuous Internal Evaluation(CIE):
CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/journal and test are in the ratio 60:40.
• Each experiment to be evaluated for conduction with observation sheet and record write-up. Rubrics for the
evaluation of the journal/write-up for hardware/software experiments designed by the faculty who is handling the
laboratory session and is made known to students at the beginning of the practical session.
• Record should contain all the specified experiments in the syllabus and each experiment write-up will
beevaluatedfor10marks.
• Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
• Weightage to be given for neatness and submission of record/write-upon time.
• Department shall conduct 02 tests for 100 marks, the first test shall be conducted after the 8 th week of the
semester and these test shall be conducted after the 14thweek of the semester.
• In each test, write-up, conduction of experiment, acceptable result, and procedural knowledge will carry a
weightage of 60% and the rest 40% for viva-voce.
• The suitable rubrics can be designed to evaluate each student’s performance and learning ability. Rubrics
suggested in Annexure-II of Regulation book
• The average of 02 tests is scaled down to 20 marks (40%of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and average marks of two tests is the total CIE marks
scored by the student.
Semester End Evaluation(SEE):
SEE marks for the practical course is 50Marks.
SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed by the University
All laboratory experiments are to be included for practical examination.
(Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be strictly adhered
to by the examiners. OR based on the course requirement evaluation rubrics shall be decided jointly by examiners.
Students can pick one question (experiment) from the question slot prepared by the internal/external examiners jointly.
Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by examiners. General
rubrics suggested for SEE are mentioned here, write up-20%, Conduction procedure and result -60%, Viva-voce 20%
of maximum marks. SEEf or practical shall be evaluated for 100 marks and scored marks shall be scaled down to 50
marks (however, based on course type, rubrics shall be decided by the examiners)
Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made zero. The
duration of SEE is 03hours
Rubrics suggested in Annexure-II of Regulation book

Suggested Learning Resources:

Textbooks:
• Data Structures using C, Reema Thareja, 2nd Edition, Oxford University Press, 2011
• Introduction to the Design and Analysis of Algorithms, Anany Levitin: 2nd Edition, 2009.Pearson.

• Online Courses:
o Coursera: "Algorithms" by Princeton University (taught by Robert Sedgewick and Kevin Wayne).
o edX: "Algorithmic Design and Techniques" (offered by UC San Diego and Higher School of Economics).
• Websites and Online Resources:
o Geeks for Geeks: Offers a wide range of tutorials, practice problems, and coding challenges related to
data structures and algorithms.

o Leet Code: Provides coding challenges that are frequently asked in technical interviews and cover a

EC(ACT) 30042024
 variety of algorithmic concepts.
o Hacker Rank: Offers coding challenges and competitions with a focus on algorithms and data structures.
o Top Coder: Provides algorithmic challenges and competitions for practicing and improving problem-
solving skills.
• YouTube Channels:
o My code school: Offers video tutorials on various data structures and algorithms topics.
o The Coding Train: Provides interactive coding tutorials on algorithms and data structures.
• Coding Platforms:
o Code forces: Offers competitive programming challenges to improve algorithmic problem-solving skills.
Hackerearth: Provides coding competitions and challenges along with tutorials and practice problems.

EC(ACT) 30042024
 Microcontrollers Lab Semester 4
CourseCode BECL456A CIEMarks 50
TeachingHours/Week(L:T:P) 0:0:2 SEEMarks 50
Credits 01 TotalMarks 100
ExamHours 2
Examination type(SEE) Practical
Courseo bjectives: This course will enable students to:
� Understand the basic programming of Microcontrollers.
� Developthe8051 Microcontroller-basedprogramsforvariousapplicationsusing Assembly Language &
C Programming.
� Program8051MicrocontrollertocontrolanexternalhardwareusingsuitableI/Oports.
Note Execute the following experiments by using Keil Microvision Simulator (any 8051 Microcontroller
can be chosen as the target) and Hardware Interfacing Programs using 8051 Trainer Kit.
Sl.No I. Assembly Language Programming
Data Transfer Programs:
Write an ALP to move a block of n bytes of data from source (20h) to destination (40h) using
1
Internal-RAM.
2 Write an ALP to move a block of n bytes of data from source (2000h) to destination (2050h) using
External RAM.
3 Write an ALP To exchange the source block starting with address 20h, (Internal RAM) containing
N (05) bytes of data with destination block starting with address 40h (Internal RAM).
4 Write an ALP to exchange the source block starting with address 10h (Internal memory), containing
n (06) bytes of data with destination block starting at location 00h (External memory).
Arithmetic & Logical Operation Programs:
Write an ALP to add the byte in the RAM at 34h and 35h, store the result in the register R5 (LSB)
5 and R6 (MSB), using Indirect Addressing Mode.

6 Write an ALP to subtract the bytes in Internal RAM 34h &35h store the result in register R5 (LSB)
& R6 (MSB).
7 Write an ALP to multiply two 8-bit numbers stored at 30h and 31h and store16- bit result in 32h and
33h of Internal RAM.
8 Write an ALP to perform division operation on 8-bit number by 8-bit number.
9 Write an ALP to separate positive and negative in a given array.
10 Write an ALP to separate even or odd elements in a given array.
11 Write an ALP to arrange the numbers in Ascending & Descending order.
12 Write an ALP to find Largest & Smallest number from a given array starting from 20h & store it in
Internal Memory location 40h.
Counter Operation Programs:
13 Write an ALP for Decimal UP-Counter.
14 Write an ALP for Decimal DOWN-Counter.
15 Write an ALP for Hexadecimal UP-Counter.
16 Write an ALP for Hexadecimal DOWN-Counter.
II. C Programming
1 Write an 8051 C program to find the sum of first 10 Integer Numbers.
2 Write an 8051 C program to find Factorial of a given number.
3 Write an 8051 C program to find the Square of a number (1 to 10) using Look-Up Table.
4 Write an 8051 C program to count the number of Ones and Zeros in two consecutive memory
locations.
III. Hardware Interfacing Programs
1 Write an 8051 C Program to rotate stepper motor in Clock & Anti-Clockwise direction.
2 Write an 8051 C program to Generate Sine & Square waveforms using DAC interface.
EC(ACT) 30042024
Courseoutcomes(CourseSkillSet):Attheendofthecoursethestudentwillbeableto:
1. Write a Assembly
Language/Cprogramsin8051forsolvingsimpleproblemsthatmanipulateinputdatausingdifferentinstructi
ons.
2. Develop Testing and experimental procedures on 8051 Microcontroller, Analyze their operation
under different cases.
3. Developprogramsfor8051Microcontrollertoimplementreal worldproblems.
4. DevelopMicrocontrollerapplicationsusingexternalhardwareinterface.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%.Theminimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for
the SEE minimumpassing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be
deemed to have satisfied theacademic requirements and earned the credits allotted to each subject/ course
if the student secures a minimum of40% (40 marks out of 100) in the sum total of the CIE (Continuous
Internal Evaluation) and SEE (Semester EndExamination)takentogether.
ContinuousInternalEvaluation(CIE):
CIEmarksforthepracticalcourseare50Marks.
Thesplit-upofCIEmarksforrecord/journalandtestareintheratio60:40.
� Each experiment is to be evaluated for conduction with an observation sheet and record write-up.
Rubrics fortheevaluationofthejournal/write-
upforhardware/softwareexperimentsaredesignedbythefacultywhoishandlingthelaboratorysessionand
aremadeknowntostudentsatthebeginningofthepracticalsession.
� Record should contain all the specified experiments in the syllabus and each experiment write-
up will beevaluatedfor 10marks.
� Totalmarksscoredbythestudentsarescaleddownto 30marks(60%ofmaximummarks).
� Weightagetobegivenforneatnessandsubmissionofrecord/write-upontime.
� Departmentshallconductatestof100marksafterthecompletionofalltheexperimentslistedinthesy
llabus.
� Inatest,testwrite-
up,conductionofexperiment,acceptableresult,andproceduralknowledgewillcarryaweightageof
60%andthe rest40%forviva-voce.
� Thesuitablerubricscanbedesignedtoevaluateeachstudent’sperformanceandlearningability.
� Themarksscoredshallbescaleddownto20marks(40%ofthemaximummarks).
TheSumofscaled-downmarksscoredinthereportwrite-up/journalandmarksofatestisthetotalCIEmarksscored
bythe student.
SemesterEndEvaluation(SEE):
� SEEmarksforthepractical courseare50Marks.
� SEE shall be conducted jointly by the two examiners of the same institute, examiners are
appointedbytheHeadof theInstitute.
� The examination schedule and names of examiners are informed to the university before the conduction
ofthe examination. These practical examinations are to be conducted between the schedule mentioned in
theacademiccalendar of the University.
� Alllaboratoryexperimentsaretobeincludedforpracticalexamination.
� (Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to bestrictly
adhered to by the examiners.OR based on the course requirement evaluation rubrics shall
bedecidedjointlybyexaminers.
� Studentscanpickonequestion(experiment)fromthequestionslotpreparedbytheexaminersjointly.
� Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by
examiners.General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and
result in -60%,Viva-
voce20%ofmaximummarks.SEEforpracticalshallbeevaluatedfor100marksandscoredmarksshallbescaleddownto
50marks(however,basedoncoursetype,rubricsshallbedecidedby the examiners)
Changeofexperimentisallowedonlyonceand15%ofMarksallottedtotheprocedurepartaretobemadezero.Theminim
um durationofSEEis02hours
SuggestedLearningResources: EC(ACT) 30042024
“The 8051 Microcontroller: Hardware, Software and Applications” ,V Udayashankara and M S
st
Mallikarjuna Swamy, McGraw Hill Education,1 edition,2017.

EC(ACT) 30042024
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EC(ACT) 30042024
 Annexure-II 1

PROGRAMMABLE LOGIC CONTROLLER (PLC) Semester IV

Course Code BEC456B CIE Marks 50
Teaching Hours/Week (L: T:P: S) 1:0:0:0 SEE Marks 50
Total Hours of Pedagogy 14 to 16 hours Total Marks 100
Credits 01 Exam Hours 01
Examination type (SEE) Theory

Course objectives: This course will enable student to

• To understand the need for automation in the industry with basic controller mechanisms involved.
• To study programming concepts to achieve the desired goal or to define the various steps involved in
the automation.
• To understand programming involved with basic subroutine functions.
• To make use of the internal hardware circuits of automation circuit to control the devices during
various states by monitoring the timers and counters.
• To handle the data of the I/O devices to interface the data with the controller and auxiliary devices.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Lecture method (L) does not mean only traditional lecture method, but different type of teaching
methods may be adopted to develop the outcomes.
2. Show Video/animation films to explain evolution of communication technologies.
3. Encourage collaborative (Group) Learning in the class.
4. Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes critical
thinking.
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking skills
such as the ability to evaluate, generalize, and analyze information rather than simply recall it.
6. Show the different ways to solve the same problem and encourage the students to come up with their
own creative ways to solve them.
7. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.

Module-1
Introduction: Programmable logic controller (PLC), role in automation (SCADA), advantages and
disadvantages, hardware, internal architecture, sourcing and sinking (Textbook 1: 1.1 to 1.4)
I/O devices and Processing: list of input and output devices, examples of applications. I/O processing,
input/output units, signal conditioning, remote connections, networks, processing inputs I/O addresses.
(TextBook1: 2.1 to 2.3 and 4.1 to 4.7).
Module-2
Programming: Ladder programming- ladder diagrams, logic functions, latching, multiple outputs, entering
programs, functional blocks, program examples like location of stop and emergency switches. (TextBook1:
5.1 to 5.7).
Module-3
Programming Methods: Instruction Lists- Ladder programs and Instruction lists, Branch codes,
Programming Examples- Signal lamp-valve operation task. Sequential Function Charts- Branching and
convergence. (TextBook1: 6.1 to 6.3).

Module-4
Internal Relays: ladder programs, battery-backed relays, one-shot operation, set and reset, master control
relay (TextBook1: 7.1 to 7.6).
Timers and counters: Types of timers, ON and OFF- delay timers, pulse timers, forms of counter,
programming, up and down counters. (TexBook1: 9.1 to 9.6).

Module-5

EC(ACT) 30042024 1
 Annexure-II 2

Shift register and data handling: shift registers, ladder programs, registers and bits, data handling,
arithmetic functions. (TextBook1: 11.1 to 11.2 and 12.1 to 12.3)

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :
1. Describe the PLC and how to construct PLC ladder diagrams.
2. Illustrate an application with programming.
3. Describe characteristics of registers and conversion examples.
4. Apply PLC functions to timing and counting applications.
5. Analyse the analog operation of PLC and demonstrate the robot applications with PLC.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a pass in the
course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous
Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

• There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
• Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the coverage
of the syllabus, and the second test will be administered after 85-90% of the coverage of the syllabus. The
average of the two tests shall be scaled down to 25 marks
• Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only one
assignment for the course shall be planned.
• The schedule for assignments shall be planned properly by the course teacher. The teacher should not
conduct two assignments at the end of the semester if two assignments are planned. Each assignment shall
be conducted for 25 marks. (If two assignments are conducted then the sum of the two assignments shall
be scaled down to 25 marks)
• The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.

Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for
the course (duration 01 hours).
1. SEE paper shall be set for 50 questions, each of the 01 marks. The pattern of the question paper is MCQ
(multiple choice questions).
2. The time allotted for SEE is 01 hour. The student has to secure a minimum of 35% of the maximum
marks meant for SEE.
Suggested Learning Resources:

Textbooks:
1. Programmable Logic controllers-W Bolton, 5th edition/6th edition, Elsevier- newness, 2009/2015.
2. Programmable logic controllers - principles and applications”-John W. Webb, Ronald A Reiss, Pearson
education, 5th edition, 2007.

EC(ACT) 30042024 2
 Annexure-II 3

Reference Books:
1 Programmable Logic Controllers”- E. A Paar, 3rd Edition, An Engineers Guide. Newness, 2003.
2 “Introduction to Programmable Logic Controller”- Garry Dunning, 3rd Edition, Thomson Asia Pte Ltd.
Publication, 2006
3 “PLCs & SCADA - Theory and Practice”- Rajesh Mehra, Vikrant Vij, 2nd Edition, Laxmi publication, 2017
4 “PLC Programming for Industrial Automation”- Kevin Collins, 1st Edition, Kindle, 2016

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning.

• Quiz and Seminars

EC(ACT) 30042024 3
 Octave Programming
Course Code BECL456C CIE Marks 50
Teaching Hours/Week (L:T:P:S) 0:0:2 SEE Marks 50
Total Hours of Pedagogy 12 Sessions Total 100
Credits 01 Exam Hours 02
*Additional One hour may be considered for instructions if
required
Course objectives:
• Apply theoretical knowledge of Octave programming to practical programming tasks.
• Gain hands-on experience in implementing and debugging octave Programming through coding
exercises and projects.

Course Syllabus :
Basic data structures in Octave – Vectors, Matrices, Cell Arrays. Special vecors. Linear sampling and
logarithmic sampling. Accessing elements of vectors, matrices, and matrices. Mathematical operations on
vectors and matrices. Addition, Multiplication, Subtraction, Division, Power, Square-Root, trigonometric
operations. Dot Products and Cross Products of Vectors. Matrix multiplication, matrix inverse and matrix
transpose operations. Finding eigen values andvectors of a square matrix. Finding the solution of a system
of linear equations. Linear programming and integer linear programming using glpk. Plotting in Octave.
Subplots, Stem Plots, Semilog and Log-log plots. Packages in Matlab – symbolic, signal processing,
control. Applications of Octave to solve problems in Electrical engineering, Electronics engineering,
Control Systems, Signals and Systems/Signal Processing.
Sl..NO Experiments
(a) Define the following matrices using Octave
1
i. A 4x4 identity matrix
ii. A 4x4 matrix of zeros
iii. A 4x4 matrix of ones
iv. The matrix U4 defined below.

v. Matrix D4 defined below. It is also called the Hadamard matrix of dimension 4.

vi. Matrix H4 defined below

vii. A 4x4 magic square G4

viii. A 4x4 matrix of random numbers selected from the range {-1,0,1}.
ix. A 4x4 matrix of random numbers in the range 0 to 1.
(b)
(i) How can you generate a 4x4 matrix of all 2’s?
(ii) Find the transpose of U4.
(iii) Multiply D4 by its transpose and obtain the resulting matrix. How is
EC(ACT) 30042024
 related to the identify matrix?
(iv) Find the inverse of H4 and verify that it is the inverse.
(v) What is the determinant of D4?
(vi) Extract the diagonal elements of H4.
(vii) How can you reshape the elements of D4 into a 2x8 matrix?
(viii) What is the magic sum of a 4x4 matrix? How can you verify that G4 is
indeed a magic square?
(ix) The matrix D4 mentioned above is a 4x4 matrix. We wish to extract
the sub- matrix consisting of rows 1 and 4 and columns 1 and 4. [In
other words, the four corners of D4.) Show Octave code for generating
the submatrix SM.
(x) Check if the H4 and D4 are orthogonal matrices.

2 You will have learnt Kirchhoff’s current and voltage laws to solve the voltages and
currents in a DC circuit. Given a circuit with n loops, we can write down n equations in n
unknowns (loop currents). Alternately, given a circuit with n nodes, we can write down
n equations in n unknowns (node voltages). These linear equations can be solved using
Octave.

(a) Write down the KCL and KVL for the following circuit and solve the node
voltages and currents. Assume that Vs is 100V.

(b) Find the total power dissipated in the circuit.

(c) Find the total power supplied by the voltage source.
(d) Challenge – Instead of hardcoding the values of the resistors and the voltage
source, can you allow the user to input R1, R2, R3, R4, R5, and Vs? Develop a
complete Octave script which reads in the values of circuit parameters and prints
the node voltages, node currents, and power dissipation.
(e) Variations of the above exercises can be given to the students. For example, a
resistor can be included in series with Vs. Alternately, a different circuit from a
text book can be given. You can also change the problem by specifying the current
through one of the resistors and asking the user to solve for Vs.

(a) Consider the RC circuit shown in the figure below. Plot the voltage across C and the
3
charging current through C when the switch is turned on.
(b) What is the rise time of the capacitor voltage?

EC(ACT) 30042024
4

(a) The figure shows a diode-based rectifier. The diode conducts only when the input
voltage is positive. Assume that it is an ideal diode. Plot the half-wave rectified
waveform if the input to the rectifier is a 50- Hz sine wave of 200V RMS. Plot the
output waveform for four cycles of the input.
(b) Find the average of the Halfwave-rectified output in Octave and verify your answer
using the formula for the average output.
(c) Plot the output of a full-wave rectifier.
(d) Find the RMS value of the Fullwave-rectified output in Octave and verify your
answer using the formula for the RMS value.
(e) Assume that the input voltage is 2sin(500t) V and that the diode has a cut-in voltage
of 0.6V. Plot the half-wave and full-wave rectified waveforms and find their average
and RMS values.

You have studied that any periodic signal of frequency f can be decomposed into a sum of sine
5
and cosine waveforms whose frequencies ae integral multiples of f. The resulting series is called
the Fourier series. Consider the following equation.
𝒙(𝒕) = 𝟒/𝝅 × ∑_(𝒌 = 𝟏)^𝒏▒〖𝒔𝒊𝒏 (𝟐 𝝅𝒇 (𝟐𝒌 − 𝟏)𝒕) 〗

(a) Write an Octave program to read f and n and plot x(t). What does x(t) resemble?
(b) How can you modify x(t) to generate a square waveform of frequency f, but whose
amplitude goes from 0 to 2?
(c) Generate x(t) assuming that the square wave goes from -1 to 1 and has a frequency of 1
kHz. Take 100 samples in each period. Perform an FFT analysis of x(t).

6 (a) Given Z parameters, obtain the Y parameters using a function

called Z2Y() Given Y parameters, obtain the Z parameters using a
function called Y2Z()
(b) Find the Z and Y parameters for the T-network

EC(ACT) 30042024
 (c) Find the Z and Y parameters for the Delta. Assume that all resistors are 15 Ohms.

( d) Find the T-equivalent of the Delta network above.

( e) Find the T-equivalent of the Delta network above. Let the T network have the resistors
Zb, Zc, Za.
(a) Represent the number 65 as an unsigned integer using fewest number of bits
7
(b) Represent the number -65 as a signed magnitude integer using the fewest number of bits
(c) Represent the number -65 as a one’s complement number using fewest number of bits
(d) Represent the number -65 as a two’s complement number using the fewest number of bits
(e) Represent the number 1965 in hexadecimal
(f) Find the decimal equivalent of the hexadecimal number ABCDh
(g) Assume that "10010101" is a binary number. Interpret it as an unsigned number and
convert it to decimal.
(h) Memory is organized in terms of bytes. When a 32-bit number is read from a memory, 4
bytes have to be read. Suppose the bytes are stored as follows at location A in the memory.
In the little-endian representation, the bytes will be organized into a 32-bit register as
shown. Write a function which converts a 32-bit number from big-endian to little-endian
format.

MEM LOC M 00h 03 02 01 00

MEM LOC M+1 01h Little Endian
MEM LOC M+2 02h
MEM LOC M+3 03h 02 03
MEM LOC M+4 04h 00 01
… … Big Endian

A series circuit consists of resistance R, inductance L and capacitance C. A sinusoidal voltage of

8
V sin(wt) is applied to the series circuit. Assume V=100. Plot the current in the circuit and the
input voltage for the following cases.
(a) w=1000, R = 5 ohm, L = 1mH, C = 200uF; is the current leading or lagging? What
is the power dissipation in the circuit?
(b) w=10000, R=5 ohm, L = 1mH, C = 200 uF; is the current leading or lagging? What
is the power dissipation in the circuit?
(c) The resonant frequency w0, R = 5 ohm, L = 1mH, C = 200uF. What is the phase
difference between the voltage and current? What is the value of w? What is the power
dissipation?
EC(ACT) 30042024
 Write a function to plot the voltage and current. Take the inputs R, L, and C from the user.

(a) Consider the circuit shown below and determine the inductance L and capacitance C.
9
(b) Plot the impedance of the RLC circuit shown in the figure as the frequency is varied
from 0 to 10 kHz.
(c) Find the resonant frequency from the plot

10 Find the value of capacitor C to maximize the power transferred to the load. (The load includes

the inductance.)

Course outcomes (Course Skill Set):

At the end of the course the student will be able to:
⚫ Develop proficiency in octave coding and debugging complex program flow.
⚫ Understand the concepts of Matrices and apply the octave programming concepts to solve the Matrices.
⚫ Acquire practical knowledge and apply the octave programming skills to solve Electric circuits.
⚫ Develop a Octave program to analyze the continuous and discrete signals
⚫ Understand the concept memory and to represent data and address using Octave Programming.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall be deemed to have
satisfied the academic requirements and earned the credits allotted to each course. The student has to secure not
less than 35% (18 Marks out of 50) in the semester-end examination (SEE).
Continuous Internal Evaluation(CIE):
CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/journal and test are in the ratio 60:40.
• Each experiment to be evaluated for conduction with observation sheet and record write-up. Rubrics for
the evaluation of the journal/write-up for hardware/software experiments designed by the faculty who is
handling thelaboratory session and is made known to students at the beginning of the practical session.
• Record should contain all the specified experiments in the syllabus and each experiment
EC(ACT) 30042024
 write-up willbeevaluatedfor10marks.
• Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
• Weightage to be given for neatness and submission of record/write-upon time.
• Department shall conduct 02 tests for 100 marks, the first test shall be conducted after the 8 th
week of thesemester and these test shall be conducted after the 14thweek of the semester.
• In each test, write-up, conduction of experiment, acceptable result, and procedural knowledge will
carry aweightage of 60% and the rest 40% for viva-voce.
• The suitable rubrics can be designed to evaluate each student’s performance and learning ability.
Rubricssuggested in Annexure-II of Regulation book
• The average of 02 tests is scaled down to 20 marks (40%of the maximum marks).

The Sum of scaled-down marks scored in the report write-up/journal and average marks of two tests is the total
CIE marksscored by the student.
Semester End Evaluation(SEE):
SEE marks for the practical course is 50Marks.
SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed by the
UniversityAll laboratory experiments are to be included for practical examination.
(Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be strictly
adheredto by the examiners. OR based on the course requirement evaluation rubrics shall be decided jointly by
examiners.
Students can pick one question (experiment) from the question slot prepared by the internal/external examiners
jointly.Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by
examiners. General rubrics suggested for SEE are mentioned here, write up-20%, Conduction procedure and
result -60%, Viva-voce 20%of maximum marks. SEEf or practical shall be evaluated for 100 marks and
scored marks shall be scaled down to 50 marks (however, based on course type, rubrics shall be decided by
the examiners)
Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made
zero. Theduration of SEE is 03hours
Rubrics suggested in Annexure-II of Regulation book
Suggested Learning Resources:
Textbooks:
Dr. P.J.G. Long, Department of Engineering University of Cambridge, "Introduction to Octave,"
can be downloaded from octavetut.pdf (cam.ac.uk)

EC(ACT) 30042024
o

EC(ACT) 30042024
EC(ACT) 30042024
 Data Structures Lab using C
Course Code BECL456 CIE Marks 50
D
Teaching Hours/Week (L:T:P:S) 0:0:2 SEE Marks 50
Total Hours of Pedagogy 15 Total 10
Sessions 0
Credits 01 Exam Hours 03
*Additional One hour may be considered for instructions
if required
Course objectives:
• Apply theoretical knowledge of data structures and algorithms to practical programming tasks.
• Gain hands-on experience in implementing and debugging data structures and algorithms
through coding exercises and projects.
Sl..N Experiments
O
1 Write a C Program to create a Student record structure to store, N records, each record having
the structure shown below: USN, Student Name and Semester. Write necessary functions
a. To display all the records in the file. b. To search for a specific record based on the USN. In
case the record is not found, suitable message should be displayed. Both the options in this case
must be demonstrated. (Use pointer to structure for dynamic memory allocation)
2 Write a C Program to construct a stack of integers and to perform the following operations on it:
a. Push b. Pop c. Display The program should print appropriate messages for stack overflow,
stack underflow, and stack empty.
3 Write a C Program to convert and print a given valid parenthesized infix arithmetic expression
to postfix expression. The expression consists of single character operands and the binary
operators + (plus), - (minus), * (multiply) and / (divide).
4 Write a C Program to simulate the working of a queue of integers using an array. Provide the
following operations: a. Insert b. Delete c. Display
5 Write a C Program using dynamic variables and pointers to construct a stack of integers using
singly linked list and to perform the following operations: a. Push b. Pop c. Display The
program should print appropriate messages for stack overflow and stack empty.
6 Write a C Program to support the following operations on a doubly linked list where each node
consists of integers: a. Create a doubly linked list by adding each node at the front. b. Insert a
new node to the left of the node whose key value is read as an input c. Delete the node of a
given data, if it is found, otherwise display appropriate message. d. Display the contents of the
list. (Note: Only either (a,b and d) or (a, c and d) may be asked in the examination)
7 Write a C Program a. To construct a binary search tree of integers. b. To traverse the tree using
all the methods i.e., inorder, preorder and postorder. c. To display the elements in the tree.
8 Write recursive C Programs for a. Searching an element on a given list of integers using the
Binary Search method. b. Solving the Towers of Hanoi problem.
9 Write a program to traverse a graph using BFS method.
Write a program to check whether given graph is connected or not using DFS method.
10 Design and develop a program in C that uses Hash Function H:K->L as H(K)=K mod
m(reminder method) and implement hashing technique to map a given key K to the address
space L. Resolve the collision (if any) using linear probing
Note: The students must be encouraged to create Leetcode account and work on Leetcode platform to
improve the competency.

EC(ACT) 30042024
Course outcomes (Course Skill Set):
At the end of the course the student will be able to:
⚫ Develop proficiency in coding and debugging complex algorithms and data structures.
⚫ Acquire practical problem-solving skills by applying data structures and algorithms to real-world programming
challenges.
⚫ Develop a C program to perform arithmetic operation using data structure and operators.
⚫ Understand the concept of graph theory and develop a C program for searching an element.
⚫ Develop a C program to check the given graph is connected using different algorithms.

EC(ACT) 30042024
Assessment Details(both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The minimum
passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each course. The student has to secure not less than 35% (18
Marks out of 50) in the semester-end examination (SEE).
Continuous Internal Evaluation(CIE):
CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/journal and test are in the ratio 60:40.
• Each experiment to be evaluated for conduction with observation sheet and record write-up. Rubrics for the
evaluation of the journal/write-up for hardware/software experiments designed by the faculty who is handling the
laboratory session and is made known to students at the beginning of the practical session.
• Record should contain all the specified experiments in the syllabus and each experiment write-up will
beevaluatedfor10marks.
• Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
• Weightage to be given for neatness and submission of record/write-upon time.
• Department shall conduct 02 tests for 100 marks, the first test shall be conducted after the 8 th week of the
semester and these test shall be conducted after the 14thweek of the semester.
• In each test, write-up, conduction of experiment, acceptable result, and procedural knowledge will carry a
weightage of 60% and the rest 40% for viva-voce.
• The suitable rubrics can be designed to evaluate each student’s performance and learning ability. Rubrics
suggested in Annexure-II of Regulation book
• The average of 02 tests is scaled down to 20 marks (40%of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and average marks of two tests is the total CIE marks
scored by the student.
Semester End Evaluation(SEE):
SEE marks for the practical course is 50Marks.
SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed by the University
All laboratory experiments are to be included for practical examination.
(Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be strictly adhered
to by the examiners. OR based on the course requirement evaluation rubrics shall be decided jointly by examiners.
Students can pick one question (experiment) from the question slot prepared by the internal/external examiners jointly.
Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by examiners. General
rubrics suggested for SEE are mentioned here, write up-20%, Conduction procedure and result -60%, Viva-voce 20%
of maximum marks. SEEf or practical shall be evaluated for 100 marks and scored marks shall be scaled down to 50
marks (however, based on course type, rubrics shall be decided by the examiners)
Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made zero. The
duration of SEE is 03hours
Rubrics suggested in Annexure-II of Regulation book

Suggested Learning Resources:

Textbooks:
• Data Structures using C, Reema Thareja, 2nd Edition, Oxford University Press, 2011
• Introduction to the Design and Analysis of Algorithms, Anany Levitin: 2nd Edition, 2009.Pearson.

• Online Courses:
o Coursera: "Algorithms" by Princeton University (taught by Robert Sedgewick and Kevin Wayne).
o edX: "Algorithmic Design and Techniques" (offered by UC San Diego and Higher School of Economics).
• Websites and Online Resources:
o Geeks for Geeks: Offers a wide range of tutorials, practice problems, and coding challenges related to
data structures and algorithms.

o Leet Code: Provides coding challenges that are frequently asked in technical interviews and cover a

EC(ACT) 30042024
 variety of algorithmic concepts.
o Hacker Rank: Offers coding challenges and competitions with a focus on algorithms and data structures.
o Top Coder: Provides algorithmic challenges and competitions for practicing and improving problem-
solving skills.
• YouTube Channels:
o My code school: Offers video tutorials on various data structures and algorithms topics.
o The Coding Train: Provides interactive coding tutorials on algorithms and data structures.
• Coding Platforms:
o Code forces: Offers competitive programming challenges to improve algorithmic problem-solving skills.
Hackerearth: Provides coding competitions and challenges along with tutorials and practice problems.

EC(ACT) 30042024