PD - 95708D

IRFB3207PbF
IRFS3207PbF
IRFSL3207PbF
Applications
HEXFET® Power MOSFET
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply D
VDSS 75V
3.6m:
l High Speed Power Switching
l Hard Switched and High Frequency Circuits RDS(on) typ.
G
max. 4.5m:
Benefits S ID 170A
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free S S S
D D D
G G G

TO-220AB D2Pak TO-262

IRFB3207PbF IRFS3207PbF IRFSL3207PbF

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 170c A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 120c
IDM Pulsed Drain Current d 720
PD @TC = 25°C Maximum Power Dissipation 300 W
Linear Derating Factor 2.0 W/°C
VGS Gate-to-Source Voltage ± 20 V
dV/dt Peak Diode Recovery f 5.8 V/ns
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw x
10lb in (1.1N m)x
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy e 910 mJ
IAR Avalanche Current c See Fig. 14, 15, 16a, 16b, A
EAR Repetitive Avalanche Energy g mJ

Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case k ––– 0.50
RθCS Case-to-Sink, Flat Greased Surface , TO-220 0.50 ––– °C/W
RθJA Junction-to-Ambient, TO-220 k ––– 62
RθJA Junction-to-Ambient (PCB Mount) , D2Pak jk ––– 40

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IRF/B/S/SL3207PbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 75 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.069 ––– V/°C Reference to 25°C, ID = 1mA d
RDS(on) Static Drain-to-Source On-Resistance ––– 3.6 4.5 mΩ VGS = 10V, ID = 75A g
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 75V, VGS = 0V
––– ––– 250 VDS = 75V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
RG Gate Input Resistance ––– 1.2 ––– Ω f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 150 ––– ––– S VDS = 50V, ID = 75A
Qg Total Gate Charge ––– 180 260 nC ID = 75A
Qgs Gate-to-Source Charge ––– 48 ––– VDS = 60V
Qgd Gate-to-Drain ("Miller") Charge ––– 68 ––– VGS = 10V g
td(on) Turn-On Delay Time ––– 29 ––– ns VDD = 48V
tr Rise Time ––– 120 ––– ID = 75A
td(off) Turn-Off Delay Time ––– 68 ––– RG = 2.6Ω
tf Fall Time ––– 74 ––– VGS = 10V g
Ciss Input Capacitance ––– 7600 ––– pF VGS = 0V
Coss Output Capacitance ––– 710 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 390 ––– ƒ = 1.0MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related) i ––– 920 ––– VGS = 0V, VDS = 0V to 60V j, See Fig.11
Coss eff. (TR) Effective Output Capacitance (Time Related) h ––– 1010 ––– VGS = 0V, VDS = 0V to 60V h, See Fig. 5
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 170 c A MOSFET symbol D

(Body Diode) showing the

ISM Pulsed Source Current ––– ––– 720 integral reverse G

(Body Diode) di p-n junction diode.

S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 75A, VGS = 0V g
trr Reverse Recovery Time ––– 42 63 ns TJ = 25°C VR = 64V,
––– 49 74 TJ = 125°C IF = 75A
Qrr Reverse Recovery Charge ––– 65 98 nC TJ = 25°C di/dt = 100A/µs g
––– 92 140 TJ = 125°C
IRRM Reverse Recovery Current ––– 2.6 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Calculated continuous current based on maximum allowable junction † Coss eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Package limitation current is 75A. as Coss while VDS is rising from 0 to 80% VDSS.
‚ Repetitive rating; pulse width limited by max. junction ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
temperature. Coss while VDS is rising from 0 to 80% VDSS.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.33mH ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use footprint and soldering techniques refer to application note #AN-994.
above this value. ‰ Rθ is measured at TJ approximately 90°C.
„ ISD ≤ 75A, di/dt ≤ 500A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.

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 IRF/B/S/SL3207PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

8.0V 8.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
100 4.8V 4.8V
BOTTOM 4.5V BOTTOM 4.5V

100

10
4.5V

4.5V ≤ 60µs PULSE WIDTH

≤ 60µs PULSE WIDTH
Tj = 25°C Tj = 175°C
1 10
0.1 1 10 100 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000.0 2.5

RDS(on) , Drain-to-Source On Resistance

ID = 75A
VGS = 10V
TJ = 175°C
ID, Drain-to-Source Current(Α)

2.0
100.0 (Normalized)
TJ = 25°C

1.5

10.0

1.0
VDS = 50V
≤ 60µs PULSE WIDTH
1.0
0.5
4.0 5.0 6.0 7.0 8.0 9.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

12000 20
VGS = 0V, f = 1 MHZ
ID= 75A VDS = 60V
Ciss = Cgs + Cgd, Cds SHORTED
VGS, Gate-to-Source Voltage (V)

10000 Crss = Cgd VDS= 38V

16
Coss = Cds + Cgd
C, Capacitance (pF)

8000 Ciss
12

6000
8
4000

4
2000
Coss
Crss
0
0
0 40 80 120 160 200 240 280
1 10 100
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRF/B/S/SL3207PbF
1000.0 10000
OPERATION IN THIS AREA
LIMITED BY R DS (on)

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

TJ = 175°C 1000
100.0

100 100µsec
10.0

10

TJ = 25°C
1.0
1 1msec
Tc = 25°C
Tj = 175°C 10msec
VGS = 0V Single Pulse DC
0.1 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage

V(BR)DSS , Drain-to-Source Breakdown Voltage

200 100

Limited By Package

150
ID, Drain Current (A)

90

100

80

50

70
0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
25 50 75 100 125 150 175
T C , Case Temperature (°C) TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3.0 4000
EAS, Single Pulse Avalanche Energy (mJ)

I D
TOP 12A
2.5
16A
3000 BOTTOM 75A
2.0
Energy (µJ)

1.5 2000

1.0
1000

0.5

0.0 0
20 30 40 50 60 70 80 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting TJ, Junction Temperature (°C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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 IRF/B/S/SL3207PbF
1

D = 0.50
Thermal Response ( ZthJC )

0.1
0.20
0.10
0.05 R1 R2
R1 R2 Ri (°C/W) τi (sec)
0.01 0.02 τJ τC
τJ τ 0.2151 0.001175
0.01 τ1 τ2
τ1 τ2 0.2350 0.017994
Ci= τi/Ri
Ci= i/Ri
0.001
Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Duty Cycle = Single Pulse 0.01 Tstart =25°C (Single Pulse)
Avalanche Current (A)

0.05
10
0.10

Allowed avalanche Current vs avalanche

1
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.

0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth

1000 Notes on Repetitive Avalanche Curves , Figures 14, 15:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1% Duty Cycle 1. Avalanche failures assumption:
EAR , Avalanche Energy (mJ)

800 ID = 75A Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max)
is exceeded.
600
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
400 during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
200 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
0 ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
25 50 75 100 125 150 175
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Starting TJ , Junction Temperature (°C) Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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IRF/B/S/SL3207PbF
5.0 16

ID = 1.0A
VGS(th) Gate threshold Voltage (V)

4.5 14
ID = 1.0mA
ID = 250µA
4.0 12

IRRM - (A)
3.5 10

3.0 8

2.5 6 IF = 30A
VR = 64V
2.0 4 TJ = 125°C
TJ = 25°C
1.5 2
-75 -50 -25 0 25 50 75 100 125 150 175 100 200 300 400 500 600 700 800 900 1000

TJ , Temperature ( °C ) dif / dt - (A / µs)

Fig 16. Threshold Voltage Vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

16 400

14

300
12 QRR - (nC)
IRRM - (A)

10
200
8

6 IF = 45A IF = 30A
100
VR = 64V VR = 64V
4 TJ = 125°C TJ = 125°C
TJ = 25°C TJ = 25°C
2 0
100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / µs) dif / dt - (A / µs)

Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

400

300
QRR - (nC)

200

IF = 45A
100
VR = 64V
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRF/B/S/SL3207PbF
Driver Gate Drive
D.U.T P.W.
Period D=
P.W.
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚
-
„ +
Recovery
Current
Body Diode Forward
Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms

LD
VDS VDS
90%
+
VDD -

D.U.T 10%
VGS VGS
Pulse Width < 1µs
Duty Factor < 0.1% td(on) tr td(off) tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Id
Vds

Vgs

L
VCC
DUT Vgs(th)
0
1K

Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRF/B/S/SL3207PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

(;$03/( 7+,6,6$1,5)
/27&2'( ,17(51$7,21$/ 3$57180%(5
$66(0%/('21:: 5(&7,),(5
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$66(0%/<
LQGLFDWHV/HDG)UHH /27&2'( :((.
/,1(&

TO-220AB packages are not recommended for Surface Mount Application.

8 www.irf.com
 IRF/B/S/SL3207PbF

TO-262 Package Outline

Dimensions are shown in millimeters (inches)

TO-262 Part Marking Information

(;$03/( 7+,6,6$1,5//
/27&2'( 3$57180%(5
,17(51$7,21$/
$66(0%/('21::
5(&7,),(5
,17+($66(0%/</,1(& /2*2
'$7(&2'(
<($5 
$66(0%/<
/27&2'( :((.
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25
3$57180%(5
,17(51$7,21$/
5(&7,),(5
/2*2
'$7(&2'(
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$66(0%/<
/27&2'( 352'8&7 237,21$/
<($5 
:((.
$ $66(0%/<6,7(&2'(

www.irf.com 9
IRF/B/S/SL3207PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)

D2Pak (TO-263AB) Part Marking Information

7+,6,6$1,5)6:,7+ 3$57180%(5
/27&2'( ,17(51$7,21$/
$66(0%/('21:: 5(&7,),(5 )6
,17+($66(0%/</,1(/ /2*2
'$7(&2'(
$66(0%/< <($5 
/27&2'( :((.
/,1(/

25
3$57180%(5
,17(51$7,21$/
5(&7,),(5 )6
/2*2 '$7(&2'(
3 '(6,*1$7(6/($')5((
352'8&7 237,21$/
$66(0%/< <($5 
/27&2'(
:((.
$ $66(0%/<6,7(&2'(

10 www.irf.com
 IRF/B/S/SL3207PbF

D2Pak (TO-263AB) Tape & Reel Information

TRR

1.60 (.063)
1.50 (.059)
1.60 (.063)
4.10 (.161)
1.50 (.059) 0.368 (.0145)
3.90 (.153)
0.342 (.0135)

FEED DIRECTION 1.85 (.073) 11.60 (.457)

1.65 (.065) 11.40 (.449) 24.30 (.957)
15.42 (.609)
23.90 (.941)
15.22 (.601)
TRL
1.75 (.069)
10.90 (.429) 1.25 (.049)
10.70 (.421) 4.72 (.136)
16.10 (.634) 4.52 (.178)
15.90 (.626)

FEED DIRECTION

13.50 (.532) 27.40 (1.079)

12.80 (.504) 23.90 (.941)

330.00 60.00 (2.362)

(14.173) MIN.
MAX.

30.40 (1.197)
NOTES : MAX.
1. COMFORMS TO EIA-418. 26.40 (1.039) 4
2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)
3. DIMENSION MEASURED @ HUB.
3
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/06
www.irf.com 11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) . contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon WARNINGS
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applicable legal requirements, norms and Technologies, Infineon Technologies’ products may
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The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.