B.E/B.

TECH DEGREE EXAMINATION, MAY/JUNE 2016

EC 6504 – MICROPROCESSOR AND MICROCONTROLLER
PART – A (10x2=20 Marks)

1. List the flags of 8086.

2. Define stack.
3. Differentiate External verses Internal bus.
4. Compare closely coupled and loosely coupled configurations.
5. List the advantages and disadvantages of parallel communication over serial communication.
6. What is key bouncing?
7. What are the different ways of operand addressing in 8051?
8. Write an 8051 ALP to toggle P1 a total of 200 times. Use RAM location 32H to hold your
counter value instead of registers R0-R7.
9. Compare polling and interrupt.
10. Define baud rate of 8051.

PART – B (5x16=80 Marks)

11. (a) (i) Explain the Data transfer, arithmetic and branch instructions with examples. (9)
(ii) Write an 8086 ALP to find the sum of numbers in an array of 10 elements. (7)
OR
(b) Define interrupts and their types. Write in detail about interrupt service routine. (16)
12. (a) Explain in detail about the system bus timing of 8086. (16)
OR
(b) Explain the following:
(i) Multiprocessor system. (ii) Coprocessor (iii) Multiprogramming (iv) Semaphore
13. (a) Explain in detail about DMA controller with its diagram. (16)
OR
(b) Draw and explain the block diagram of alarm controller. (16)
14. (a) Explain the architecture of 8051 with its diagram. (16)
OR
(b) Write an 8051ALP to create a square wave of 66 % duty cycle on bit 3 of port 1. (16)

15. (a) Draw the diagram to interface a stepper motor with 8051 microcontroller and Write its
ALP to run the stepper motor in both forward and reverse direction with delay. (16)
OR
(b) Explain 8051 serial port programming with examples. (16)
 PART – A (10x2=20 Marks)

1. List the flags of 8086.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

U U U U OF DF IF TF SF ZF U AF U PF U CF

U: Undefined; CF : Carry flag - Set by carry out of MSB

PF: Parity flag- set if result has even parity; AF : Auxiliary carry flag - used for BCD
operation; ZF : Zero flag - set if result = 0; SF : Sign flag - set if result is –ve.

TF : Trap flag - set to enable single step execution mode. IF: Interrupt flag- set to enable
interrupt ;DF : Direction flag - set to enable auto decrement mode for string operation ;OF:
Overflow flag - used for signed arithmetic operation

2. Define stack.
A stack pointer is a small register that stores the address of the last program request in a stack.
A stack is a specialized buffer which stores data from the top down. As new requests come in,
they "push down" the older ones.

3. Differentiate External verses Internal bus.

The internal data bus is the one responsible for transferring the data between the data registers
and each other or between the data registers and the CPU. The external data bus transfers the
data between the internal registers and the external memory or directly to the output.

4. Compare closely coupled and loosely coupled configurations.

S.No Closely coupled Loosely coupled
1 It perform better and size is small when Less expensive
compared

2 More expensive Here single standalone processor is used connected

via interconnected network

3 It contains multiple CPUs Data rate is low.

4 Data rate is high Data rate is low.

5. List the advantages and disadvantages of parallel communication over serial

communication.
For transferring data between computers, laptops two methods are used, namely, Serial
Transmission and Parallel Transmission. There are some similarities and dissimilarities between
them. One of the primary differences is that; in Serial Transmission data is sent bit by bit
whereas, in Parallel Transmission a byte (8 bits) or character is sent.

6. What is key bouncing?

When a key is pressed the contact bounce back and forth and settle down only after a small time
delay (about 20ms). Even though a key is actuated once, it will appear to have been actuated
several times. This problem is called Key Bouncing.

7. What are the different ways of operand addressing in 8051?

Different ways of addressing modes are1) Immediate addressing mode 2) Direct addressing
mode 3) Register direct addressing mode 4) Register indirect addressing mode 5) Indexed
addressing mode.
8. Write an 8051 ALP to toggle P1 a total of 200 times. Use RAM location 32H to hold your
counter value instead of registers R0-R7.
MOV P1,#55H ;P1=55H
MOV 32H,#200 ;load counter value into RAM loc 32H
LOP1: CPL P1 ;toggle P1
ACALL DELAY
DJNZ 32H,LOP1 ;repeat 200 times

9. Compare polling and interrupt.

Interrupt is a signal to the microprocessor from a device that requires attention. The
microprocessor will respond by setting aside execution of its current task and deal with the
interrupting device. When the interrupting device has been dealt with, the microprocessor
continues with its original task as if it had never been interrupted.

In Polling the processor continuously polls or tests every device in turn as to whether it requires
attention (e.g. has data to be transferred). The polling is carried out by a polling program that
shares processing time with the currently running task.

10. Define baud rate of 8051.

In serial communication the data is rate known as the baud rate, which simply means the
number of bits transmitted per second. In the serial port modes that allow variable baud rates,
this baud rate is set by timer 1. The 8051 serial port is full duplex.

PART – B (5x16=80 Marks)

11. (a) (i) Explain the Data transfer, arithmetic and branch instructions with examples. (9)
Data copy or transfer instructions

MOV
This instruction copies a word or a byte of data from some source to a destination. This
destination can be a register or a memory location. The source can be a register, a memory
location or an immediate number.
Example
MOV AX,BX
MOV AX,500H
MOV AX,[SI]
MOV AX,[2000H]
MOV AX,50H[BX]
Direct loading of the segment registers with immediate data is not permitted.
PUSH : Push to stack
This instruction pushes the contents of the specified register/memory location on to the stack.
The stack pointer is decremented by 2, after each execution of this instruction.
Example
PUSH AX
PUSH DX
PUSH [5000H]
POP : Pop from stack
This instruction when executed, loads the specified register/memory location with the contents
of the memory location of which the address is formed using the current stack segment and
stack pointer. The stack pointer is incremented by 2.
Example
POP AX
POP DS
POP [5000H]
XCHG : Exchange byte or word
This instruction exchange the contentrs of a specified source and destination operands
Example`
XCHG [5000H], AX
XCHG BX,AX
XLAT
Translate byte using look up table
Example
LEA BX, TABLE1
MOV AL, 04H
XLAT

Simple input and output port transfer instructions

IN : Copy a byte or word from a specified port to accumulator.
Example
IN AL, 03H
IN AX, DX

OUT: Copy a byte or word from accumulator specified port.

Example
OUT 03H, AL
OUT DX, AX

LEA : Load effective address of the operands in specified register.

Eg.
LEA reg, offset

LDS : Load DS register with other specified register from memory

[reg] [mem]
[DS] [mem +2]
Eg.
LDS reg, mem

LES : Load ES register and other specified register from memory.

[reg] [mem]
[reg] [mem +2]
Eg.
LES reg, mem
ARITHMETIC INSTRUCTIONS
The 8086 provides many arithmetic operations : addition, subtraction, negation , multiplication
and comparing two values.
ADD :
The add instruction adds the contents of the source operand to the destination operand.
Eg.
ADD AX,0100H
ADD AX,BX
ADD AX,[SI]
ADD AX, [5000H]
ADD [5000H], 0100H
ADD 0100H
ADC :
Add with carry
This instruction performs the same operation as the add instruction, but adds the carry flag to
the result.
Eg.
ADC 0100H
ADC AX,BX
ADC AX,[SI]
ADC AX,[5000]
ADC [5000],0100H

SUB: Subtract
The subtract instructiion subtracts the source operand from the destination operand and the
result is left in the destination operand.
Eg.

SUB AX,0100H
SUB AX,BX
SUB AX,[SI]
SUB AX, [5000H]
SUB [5000H], 0100H

SBB : Subtract with borrow

The subtract with borrow instruction subtracts the source operand and the borrow flag (CF)
which may reflect the result of the previous calculations, from the destination operand.
Eg.

SBB AX,0100H
SBB AX,BX
SBB AX,[SI]
SBB AX, [5000H]
SBB [5000H], 0100H

INC : Increment
This instruction increases the contents of the specified register or memory location by 1.
Immediate data cannot be operand of this instruction.
Eg.
INC AX
INC [BX]
INC [5000H]

DEC : Decrement
The decrement instruction subtract 1 from the contents of the specified register or memory
location.
Eg.
DEC AX
DEC [5000h]

NEG : Negate
The negate instruction forms 2's complement of the specified destination in the instruction. The
destinatiopn can be a register or a memory location . This instruction can be implemented by
inverting each bit and adding 1 to it.
Eg
NEG AL
AL= 0011 0101 35H Replace number in AL with its 2's complement
AL = 1100 1011 = CBH

CMP : Compare
This instruction compares the source operand, which may be a register or a memory location,
with a destination operand that may be a memory location
Eg.
CMP BX,0100H
CMP AX, 0100H
CMP [5000H], 0100H
CMP BX, [SI]
CMP BX, CX

MUL : Unsigned multiplication byte or word

This instruction multiplies an unsigned byte or word by the contents of AL.
Eg.
MUL BH ; (AX) (AL) * (AX)
MUL CH ; (DX)(AX) (AX) * (CX)
MUL WORD PTR [SI] ; (DX) (AX) (AX) * ([SI[)

IMUL : Signed multiplication

This instruction multiplies a signed byte in source operand by a signed byte in AL or a signed
word in source operand by a signed word in AX.
Eg.
IMUL BH
IMUL CX
IMUL [SI]

CBW : Convert signed byte to word

This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be sign
extension of AL.
Eg.
CBW
AX = 0000 0000 1001 1000 Convert signed byte in AL signed word in AX
Result in AX = 1111 1111 1001 1000

CWD : Convert signed word to double word

This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be a
signed extension of AL
Eg,
CWD
Convert signed word in AX to signed double word in DX : AX
DX = 1111 1111 1111 1111
Result in AX = 1111 0000 1100 0001

DIV : Unsigned division

This instruction is used to divide the unsigned word by a byte or to divide an unsigned double
word by a word.
Eg
DIV CL ; word in AX / byte in CL ,quotient im AL , remainder in AH.
DIV CX ; Double word in DX and AX / word in CX and Quotient in AX , remainder in DX.

AAA : ASCII adjust after addition

The AAA instruction is executed after an ADD instruction that adds two ASCII coded operand
to give a byte of result in AL . The AAA instruction converts the resulting contents of AI to a
unpacked decimal digit.
Eg.
ADD CL,DL ; [CL] = 32H = ASCII for 2 , [DL] = 35H = ASCII for 5, Result [CL] = 67H

MOV AL, CL ; move ASCII result into AL since AAA adjust only [ AL]

AAA ; [AL] = 07, unpacked BCD for 7

AAS : ASCII adjust AL after subtraction

This instruction corrects the result in AL register after subtracting two unpacked ASCII
operands. The result is in unpacked decimal format. THE procedure is similar to AAA
instruction except for the subtraction of 06 from AL.

AAM : ASCII adjust after multiplication

This instruction after execution converts the product available in AL into unpacked BCD
format.
Eg.
MOV AL , 04H ; AL= 04H
MOV BL , 09 ; BL = 09
MUL BL ; AX = AL* BL ; AX= 24H
AAM ; AH= 03, AL=06

AAD : ASCII adjust before division

This instruction converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL. This adjustment must be done before dividing the two unpacked BCD digits in
AX by an unpacked BCD byte. IN the instruction sequence , this instruction appears before DIV
instruction.
Eg.
AX 05 08
AAD result in AL 00 3A; 58D= 3A h in AL

DAA : Decimal adjust accumulator

This instruction is used to convert the result of the addition of the two packed BCD numbers to
a valid BCD number. The result has to be only in AL
Eg.
AL = 53 CL = 29
ADD AL, CL ; AL (AL) + (CL)
AL 53 +29
AL 7C
DAA ;AL 7C + 06
;AL 82

DAS : Decimal adjust after subtraction

This instruction converts the result of the subtraction of two packed BCD numbers to a valid
BCD number. This subtraction has to be AL only
Eg.
AL = 75, BH= 46
SUB AL, BH ; AL 2F= (AL) - (BH)
AF= 1
DAS ; AL 29 (as F >9, F-6= 9)

BRANCH INSTRUCTIONS
Branch instruction transfers the flow of execution of the program to a new address specified in
the instruction directly or indirectly. When this type of instruction is executed, the CS and IP
registers get loaded with new values of CS and IP corresponding to the location to be
transferred.

The branch instruction are classified into two types

1. Unconditional branch instructions

2. Conditional branch instructions

Unconditional branch instruction :

In unconditional control transfer instructions, the execution control is transferred to the
specified location independent of any status or condition . The CS and IP are unconditionally
modified to the new CS and IP.

CALL : Unconditional call

This instruction is used to call a subroutine (procedure) from the main program. Address of
procedure may be specified directly or indirectly.
There are two types of procedures depending upon whether it is available in the same segment
or in another segment.

1. Near CALL i.e., +32K or -32K displacement

2. Far CALL i.e., anywhere outside the segment.
On execution this instruction stores the incremented IP and CS onto the stack and loads the CS
and IP registers with segment and offset address of the procedure to be called.

RET : Return from procedure

At the end of the procedure, the RET instruction must be executed. When it is executed, the
previously stored content of IP and CS along with flags are retrieved into the CS, IP and Flag
registers from the stack and execution of the main programs continues further.

INT N : Interrupt Type N

In the interrupt structure of the 8086, 256 interrupts are defined corresponding to the types from
00H to FFH. When INT N instruction is executed, the type byte N is multiplied by 4 and the
contents of the IP and CS of the interrupt service routine will be taken from memory block in
0000 segment.

INTO : Interrupt in overflow

This instruction is executed when the overflow flag ODF is set, This is equivalent to a Type4
interrupt instruction.

JMP : Conditional jump

This instruction unconditionally transfers the control of execution to the specified address using
an 8 bit ot 16 bit displacement. No flags are affected by this instruction.

IRET : Return from stack

When its is executed the values of IP ,CS and flags are retrieved from the stack to continue the
execution of the main program.

LOOP : LOOP unconditional

This instruction executes the part of the program from the Label or address specified in the
instruction up to the loop instruction CX number of times . At each iteration ,CX is decremented
automatically and JUMP OF NOT ZERO structure.
Conditonal branch instructions
When this instruction is executed, execution control is transferred to the address specified
relatively in the instruction, provided the condition implicit in the opcode is satisfied.
Otherwise execution continues sequentially.
JZ/JZE Label
Transfers execution control to address 'label' , if ZF = 1
JNZ/JNE Label
Transfers execution control to address 'label' , if ZF = 0
JS Label
Transfers execution control to address 'label' , if SF = 1
JNS Label
Transfers execution control to address 'label' , if SF = 0
JO Label
Transfers execution control to address 'label' , if OF = 1
JNO Label
Transfers execution control to address 'label' , if OF = 0
JNP Label
Transfers execution control to address 'label' , if PF = 0
JP Label
Transfers execution control to address 'label' , if PF = 1
JB Label
Transfers execution control to address 'label' , if CF = 1
JNB Label
Transfers execution control to address 'label' , if CF = 0
JNXZB Label
Transfers execution control to address 'label' , if CX = 0
Conditional loop instructions
LOOPZ/LOOPE Label
Loop through a sequence of instructions from label while ZF = 1 and CX = 0
LOOPNZ/LOOPENE Label
Loop through a sequence of instructions from label while ZF = 1 and CX = 0

(ii) Write an 8086 ALP to find the sum of numbers in an array of 10 elements. (7)
DATA SEGMENT
ARR DB 1,4,2,3,9,8,6,7,5,10
LEN DW $-ARR
LARGE DB ?
DATA ENDS
CODE SEGMENT
ASSUME DS:DATA CS:CODE
START:
MOV AX,DATA
MOV DS,AX
LEA SI,ARR
MOV AL,ARR[SI]
MOV LARGE,AL
MOV CX,LEN
REPEAT:
MOV AL,ARR[SI]
CMP LARGE,AL
JG NOCHANGE

MOV LARGE,AL
NOCHANGE:
INC SI
LOOP REPEAT
MOV AH,4CH
INT 21H
CODE ENDS
END START

OR
(b) Define interrupts and their types. Write in detail about interrupt service routine. (16)
A signal indicating that an event needing immediate attention has occurred

3 Types of Interrupts:

• External - generated outside CPU by other hardware

• Internal - generated within CPU as a result of an instruction or operation
• - x86 has internal interrupts: int, into, Divide Error and Single Step
• - Trap generally means any processor generated interrupt
• - in x86, Trap usually means the Single Step interruptx86 Interrupts:
1) Hardware Interrupt - External Uses INTR and NMI

2) Software Interrupt - Internal - from int or into

3) Processor Interrupt - Traps and 10 Software Interrupts (12 total)

Interrupt Vector Table:

256 different Interrupts Specified by vector, Type vector is pointer in to Interrupt vector table

Interrupt Acknowledge Cycle

The interrupt number for NMI is 2 so the location in the IVT for the NMI ISR address is 4+2 =
0X0008h. Upon receipt of interrupt cycle 8086 executes a two special bus cycle called Interrupt
Acknowledge Cycle. It is used to fetch the interrupt vector number from the interrupting device
via D&-D0 lines

The Operation of an Interrupt sequence on the 8086 Microprocessor:

 1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an
internal interrupt occurs.
2. The CPU finishes the present instruction (for a hardware interrupt) and sends
Interrupt Acknowledge (INTA) to hardware interface.
3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from
the hardware interface.
4. The contents of the flag registers are pushed onto the stack.
5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the
trap or single-step feature.
6. The contents of the code segment register (CS) are pushed onto the Stack.
7. The contents of the instruction pointer (IP) are pushed onto the Stack.
8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP and
from (4 x N +2) into the CS so that the next instruction executes at the interrupt service
procedure addressed by the interrupt vector.
9. While returning from the interrupt-service routine by the Interrupt Return (IRET)
instruction, the IP, CS and Flag registers are popped from the Stack and return to their state
prior to the interrupt.
Multiple Interrupts
If more than one device is connected to the interrupt line, the processor needs to know to which
device service routine it should branch to. The identification of the device requesting service can
be done in either hardware or software, or a combination of both.
The three main methods are:
Software Polling,
Hardware Polling, (Daisy Chain),
Hardware Identification (Vectored Interrupts).

12. (a) Explain in detail about the system bus timing of 8086. (16)

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX* pin to logic1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode system. The
remaining components in the system are latches, transreceivers, clock generator, memory and
I/O devices. Some type of chip selection logic may be required for selecting memory or I/O
devices, depending upon the address map of the system.

The latches are generally buffered output D-type flip-flops, like, 74LS373 or 8282. They are used
for separating the valid address from the multiplexed address/data signals and are controlled
by the ALE signal generated by 8086. Transreceivers are the bidirectional buffers and some
times they are called as data amplifiers. They are required
to separate the valid data from the time multiplexed address/data signal. They are controlled
by two signals, namely, DEN* and DT/R*. The DEN* signal indicates that the valid data is
available on the data bus, while DT/R indicates the direction of data, i.e. from or to the
processor. The system contains memory for the monitor and users program
storage. Usually, EPROMS are used for monitor storage, while RAMs for users program
storage. A system may contain I/O devices for communication with the processor as well as
some special purpose I/O devices. The clock generator generates the clock from the crystal
oscillator and then shapes it and divides to make it more precise so that it can be used as an
accurate timing reference for the system. The clock generator also synchronizes some external
signals with the system clock. The general system organization is shown in Fig. 1.1. Since it has
20 address lines and 16 data lines, the 8086 CPU requires three octal address latches and two
octal data buffers for the complete address and data separation.

The working of the minimum mode configuration system can be better described in terms of the
timing diagrams rather than qualitatively describing the operations. The opcode fetch and read
cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the
timing diagram for read cycle and the second is the timing
diagram for write cycle.

Fig 1.2 shows the read cycle timing diagram. The read cycle begins in T1 with the assertion of
the address latch enable (ALE) signal and also M/IO* signal. During the negative going edge of
this signal, the valid address is latched on the local bus. The BHE* and A0 signals address low,
high or both bytes. From Tl to T4, the M/IO* signal
indicates a memory or I/O operation. At T2 the address is removed from the local bus and is
sent to the output. The bus is then tristated. The read (RD*) control signal is also activated in
T2 .The read (RD) signal causes the addressed device to enable its data bus drivers. After RD*
goes low, the valid data is available on the data bus. The addressed device will drive the
READY line high, when the processor returns the read signal to high level, the addressed device
will again tristate its bus drivers.

Fig 1.3 shows the write cycle timing diagram. A write cycle also begins with the assertion of
ALE and the emission of the address. The M/IO* signal is again asserted to indicate a memory
or I/O operation. In T2 after sending the address in Tl the processor sends the data to be written
to the addressed location. The data remains on the bus until
middle of T4 state. The WR* becomes active at the beginning ofT2 (unlike RD* is somewhat
delayed in T2 to provide time for floating).
The BHE* and A0 signals are used to select the proper byte or bytes of memory or I/O word to
be read or written. The M/IO*, RD* and WR* signals indicate the types of data transfer as
specified in Table

HOLD Response Sequence

The HOLD pin is checked at the end of the each bus cycle. If it is received active by the
processor before T4 of the previous cycle or during T1 state of the current cycle, the CPU
activities HLDA in the next clock cycle and for the succeeding bus cycles, the bus will be given
to another requesting master The control control of the bus is not regained by the processor
until the requesting master does not drop the HOLD pin low.

OR
(b) Explain the following:
(i) Multiprocessor system. (4)
Multiprocessor means a multiple set of processors that executes instructions simultaneously.
There are three basic multiprocessor configurations.

 Coprocessor configuration
 Closely coupled configuration
 Loosely coupled configuration

(ii) Coprocessor (4)

A Coprocessor is a specially designed circuit on microprocessor chip which can perform the
same task very quickly, which the microprocessor performs. It reduces the work load of the
main processor. The coprocessor shares the same memory, IO system, bus, control logic and
clock generator. The coprocessor handles specialized tasks like mathematical calculations,
graphical display on screen, etc.

The 8086 and 8088 can perform most of the operations but their instruction set is not able to
perform complex mathematical operations, so in these cases the microprocessor requires the
math coprocessor like Intel 8087 math coprocessor, which can easily perform these operations
very quickly.

(iii) Multiprogramming (4)

Multiprogramming is a rudimentary form of parallel processing in which several programs are
run at the same time on a uniprocessor. Since there is only one processor, there can be no true
simultaneous execution of different programs. Instead, the operating system executes part of
one program, then part of another, and so on. To the user it appears that all programs are
executing at the same time.
If the machine has the capability of causing an interrupt after a specified time interval, then the
operating system will execute each program for a given length of time, regain control, and then
execute another program for a given length of time, and so on. In the absence of this
mechanism, the operating system has no choice but to begin to execute a program with the
expectation, but not the certainty, that the program will eventually return control to the
operating system.
(iv) Semaphore (4)
Semaphore is often used to synchronize operations for multiple processes to avoid starvation
and deadlock. Normally, the semaphore is initially set to the number of available resources. A
positive semaphore value indicates the resource is available. When the process gains the access
to the resource, the process decrements the semaphore. The system guarantee that the test and
decrement operation on the semaphore are atomic. If the semaphore value is zero, the
requesting process must wait. After the process finishes the operation on the resource, it
increments the semaphore value by 1, and other processes that have been waiting are notified
by the system. Semaphore that control access to a single resource is often called binary
semaphore (0 for in use, and 1 for available); for to multiple resources, called counting
semaphore.

13. (a) Explain in detail about DMA controller with its diagram. (16)
 It is a device to transfer the data directly between IO device and memory without
through the CPU. So it performs a high-speed data transfer between memory and I/O
device.

The features of 8257 is,

 The 8257 has four channels and so it can be used to provide DMA to four I/O devices

 Each channel can be independently programmable to transfer up to 64kb of data by

DMA.

 Each channel can be independently perform read transfer, write transfer and verify
transfer.

It is a 40 pin IC and the pin diagram is,

Functional Block Diagram of 8257:

 The functional blocks of 8257 are data bus buffer, read/write logic, control logic, priority
resolver and four numbers of DMA channels.

The functional block diagram of 8257 is shown in fig.

OPERATING MODES OF INTEL 8257
 Each channel of 8257 Block diagram has two programmable 16-bit registers named as
address register and count register.

 Address register is used to store the starting address of memory location for DMA data
transfer.

 The address in the address register is automatically incremented after every

read/write/verify transfer.

 The count register is used to count the number of byte or word transferred by DMA. The
format of count register is,

 14-bits B0-B13 is used to count value and a 2-bits is used for indicate the type of DMA
transfer (Read/Write/Veri1 transfer).

 In read transfer the data is transferred from memory to I/O device.

 In write transfer the data is transferred from I/O device to memory.

 Verification operations generate the DMA addresses without generating the DMA
memory and I/O control signals.
 The 8257 has two eight bit registers called mode set register and status register. The
format of mode set register is,

 The use of mode set register is,

1. Enable/disable a channel.
2. Fixed/rotating priority
3. Stop DMA on terminal count.
4.Extended/normal write time.
5. Auto reloading of channel-2.

 The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0, 1,
2 and 3 respectively. A one in these bit position will enable a particular channel and a
zero will disable it.

 If the bit B4 is set to one, then the channels will have rotating priority and if it zero then
the channels wilt have fixed priority.

1. In rotating priority after servicing a channel its priority is made as lowest.

2. In fixed priority the channel-0 has highest priority and channel-2 has lowest priority.

 If the bit B5 is set to one, then the timing of low write signals (MEMW and IOW) will be
extended.

 If the bit B6 is set to one then the DMA operation is stopped at the terminal count.

 The bit B7 is used to select the auto load feature for DMA channel-2.

 When bit B7 is set to one, then the content of channel-3 count and address registers are
loaded in channel-2 count and address registers respectively whenever the channel-2
reaches terminal count. When this mode is activated the number of channels available
for DMA reduces from four to three.

 The format of status register of 8257 is shown in fig.

  The bit B0, B1, B2, and B3 of status register indicates the terminal count status of
channel-0, 1,2 and 3 respectively. A one in these bit positions indicates that the particular
channel has reached terminal count.

 These status bits are cleared after a read operation by microprocessor.

 The bit B4 of status register is called update flag and a one in this bit position indicates
that the channel-2 register has been reloaded from channel-3 registers in the auto load
mode of operation.

 The internal addresses of the registers of 8257 are listed in table.

INTERFACING OF DMA 8257 WITH 8085

 A simple schematic for interfacing the 8257 with 8085 processor is shown.

 The 8257 can be either memory mapped or I/O mapped in the system.

 In the schematic shown in figure is I/O mapped in the system.

 Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

 The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-
0 to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257.

 The address line A7 and the control signal IO/M (low) are used as enable for decoder.

 The D0-D7 lines of 8257 are connected to data bus lines D0-D7 for data transfer with
processor during programming mode.

 These lines (D0-D7) are also used by 8257 to supply the memory address A8-A15 during
the DMA mode.

 The 8257 also supply two control signals ADSTB and AEN to latch the address supplied
by it during DMA mode on external latches.
 Two 8-bit latches are provided to hold the 16-bit memory address during DMA mode.
During DMA mode, the AEN signal is also used to disable the buffers and latches used
for address, data and control signals of the processor.

 The 8257 provide separate read and write control signals for memory and I/O devices
during DMA.

 Therefore the RD (low), WR (low) and IO/M (low) of the 8085 processor are decoded by
a suitable logic circuit to generate separate read and write control signals f memory and
I/O devices.

 The output clock of 8085 processor should be inverted and supplied to 8257 clock input
for proper operation.

 The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD
request to the processor.

 The HLDA output of 8085 is connected to HLDA input of 8257, in order to receive the
acknowledge signal from the processor once the HOLD request is accepted.

 The RESET OUT of 8085 processor is connected to RESET of 8257.

 The I/O addresses of the internal registers of 8257 are listed in table.
 OR
(b) Draw and explain the block diagram of alarm controller. (16)

pin diagram

The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing and
counting functions. They were primarily designed for the Intel 8080/8085-processors, but later
used in x86-systems.

The 8253 was used in IBM PC compatibles since their introduction in 1981.[1] In modern times,
this PIT is not included as a separate chip in an x86 PC. Rather, its functionality is included as
part of the motherboard's south bridge chipset. In some modern chipsets, this change may show
up as measurable timing differences in accessing a PIT using the x86 I/O address space. Reads
and writes to such a PIT's registers in the I/O address space may complete much faster.

Newer motherboards also include a counter through the Advanced Configuration and Power
Interface (ACPI), a counter on the Local Advanced Programmable Interrupt Controller (Local
APIC), and a High Precision Event Timer. The CPU itself also provides the Time Stamp Counter
(TSC) facility.
 Block diagram of Intel 8253

The timer has three counters, called channels. Each channel can be programmed to operate in
one of six modes. Once programmed, the channels can perform their tasks independently. The
timer is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical
function it performs and because so many devices depend on it.

Counters: There are 3 counters (or timers), which are labeled as Counter 0, Counter 1 and
Counter 2. Each counter has 2 input pins – CLK (clock input) and GATE – and 1-pin, OUT, for
data output. The 3 counters are 16-bit down counters independent of each other, and can be
easily read by the CPU.

In the original IBM PCs, the first counter (selected by setting A1=A0=0, see Control Word
Register below) is used to generate a timekeeping interrupt. The second counter (A1=0, A0=1)
is used to trigger the refresh of DRAM memory. The last counter (A1=1, A0=0) is used to
generate tones via the PC speaker.

Besides the counters, a typical Intel 8253 microchip also contains the following components:

Data/Bus BufferThis block contains the logic to buffer the data bus to / from the
microprocessor, and to the internal registers. It has 8 input pins, usually labelled as D7..D0,
where D7 is the MSB.

Read/Write Logic

The Read/Write Logic block has 5 pins, which are listed below. Notice that /X denotes an active
low signal.

 /RD: read signal

 /WR: write signal
 /CS: chip select signal
 A0, A1: address lines

Operation mode of the PIT is changed by setting the above hardware signals. For example, to
write to the Control Word Register, one needs to set /CS=0, /RD=1, /WR=0, A1=A0=1.

Control Word Register

Port 43h R/W

Port 53h R/W – second chip ...
This register contains the programmed information which will be sent (by the microprocessor)
to the device. It defines how the PIT logically works. Each access to these ports takes about 1 µs.

To initialize the counters, the microprocessor must write a control word (CW) in this register.
This can be done by setting proper values for the pins of the Read/Write Logic block and then
by sending the control word to the Data/Bus Buffer block.

The control word register contains 8 bits, labeled D7..D0 (D7 is the MSB).

Bit# D7 D6 D5 D4 D3 D2 D1 D0 Short Description

Name SC1 SC0 RW1 RW0 M2 M1 M0 BCD

0 0 x x x x x x Counter 0 at port 40h R/W

0 1 x x x x x x Counter 1 at port 41h R/W

1 0 x x x x x x Counter 2 at port 42h R/W

Counter Latch, value can be read out in the way

x x 0 0 x x x x RW1, RW0 was set before. The value is held
until it is read out or overwritten.

x x 0 1 x x x x Read/Write bits 0..7 of counter value

x x 1 0 x x x x Read/Write bits 8..15 of counter value

2xRead/2xWrite bits 0..7 then 8..15 of counter

x x 1 1 x x x x
value

x x x x 0 0 0 x Mode 0: Interrupt on Terminal Count

x x x x 0 0 1 x Mode 1: Hardware Retriggerable One-Shot

x x x x 0 1 0 x Mode 2: Rate Generator

x x x x 0 1 1 x Mode 3: Square Wave

x x x x 1 0 0 x Mode 4: Software Triggered Strobe

Mode 5: Hardware Triggered Strobe

x x x x 1 0 1 x
(Retriggerable)

Counter is a 16 bit binary

x x x x x x x 0
counter(0..65535,FFFFh)

Counter is a 16 bit decimal counter 4 x 4bit

x x x x x x x 1
decades(0..9999)

Name 1 1 _____ _____ C2 C1 C0 0

 count status
1 1 0 1 x x x 0 Counter(C0..C2) value(s) can be read out.

Counter's(C0..C2) state(s) can be read out.

1 1 1 0 x x x 0
see below Status Byte
1 1 0 0 x x x 0 error !

When setting the PIT, the microprocessor first sends a control message, then a count message to
the PIT. The counting process will start after the PIT has received these messages, and, in some
cases, if it detects the rising edge from the GATE input signal.

On PCs the address for timer0 (chip) is at port 40h..43h like described and the second timer1
(chip) is at 50h..53h.

Operation Modes

The D3, D2, and D1 bits of the Control Word set the operating mode of the timer. There are 6
modes in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases
for modes 2 and 3. Notice that, for modes 0, 2, 3 and 4, GATE must be set to HIGH to enable
counting. For mode 5, the rising edge of GATE starts the count. For details on each mode, see
the reference links.

Mode 0 (000): Interrupt on Terminal Count

Mode 0 is used for the generation of accurate time delay under software control. In this mode,
the counter will start counting from the initial COUNT value loaded into it, down to 0.
Counting rate is equal to the input clock frequency.

The OUT pin is set low after the Control Word is written, and counting starts one clock cycle
after the COUNT programmed. OUT remains low until the counter reaches 0, at which point
OUT will be set high until the counter is reloaded or the Control Word is written. The Gate
signal should remain active high for normal counting. If Gate goes low counting get terminated
and current count is latched till Gate pulse goes high again.

Mode 1 (001): Programmable One Shot

In this mode 8253 can be used as monostable multivibrator. GATE input is used as trigger
input.

OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the
one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and
remain high until the CLK pulse after the next trigger.

After writing the Control Word and initial count, the Counter is armed. A trigger results in
loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot
pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.

The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger.
The one-shot pulse can be repeated without rewriting the same count into the counter. GATE
has no effect on OUT. If a new count is written to the Counter during a oneshot pulse, the
current one-shot is not affected unless the counter is retriggered. In that case, the Counter is
loaded with the new count and the oneshot pulse continues until the new count expires.

Mode 2 (X10): Rate Generator

In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a
real-time clock interrupt.

Like other modes, counting process will start the next clock cycle after COUNT is sent. OUT
will then remain high until the counter reaches 1, and will go low for one clock pulse. OUT will
then go high again, and the whole process repeats itself.

The time between the high pulses depends on the preset count in the counter's register, and is
calculated using the following formula:

Value to be loaded into counter =

Note that the values in the COUNT register range from to 1; the register never reaches zero.

Mode 3 (X11): Square Wave Generator

This mode is similar to mode 2. However, the duration of the high and low clock pulses of the
output will be different from mode 2.

Suppose n is the number loaded into the counter (the COUNT message), the output will be

 high for counts, and low for counts, if n is even.

 high for counts, and low for counts, if n is odd.

Mode 4 (100): Software Triggered Strobe

After Control Word and COUNT is loaded, the output will remain high until the counter
reaches zero. The counter will then generate a low pulse for 1 clock cycle (a strobe) – after that
the output will become high again.

Mode 5 (101): Hardware Triggered Strobe

This mode is similar to mode 4. However, the counting process is triggered by the GATE input.

After receiving the Control Word and COUNT, the output will be set high. Once the device
detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the
output will go low for one clock cycle – after that it will become high again, to repeat the cycle
on the next rising edge of GATE.
14. (a) Explain the architecture of 8051 with its diagram. (16)

Central Processor Unit (CPU)

The CPU is the brain of any processing device of the microcontroller. It monitors and controls
all operations that are performed on the Microcontroller units. The User has no control over the
work of the CPU directly . It reads program written in ROM memory and executes them and do
the expected task of that application.

Interrupts
Interrupt is a subroutine call that interrupts of the microcontrollers main operations or work
and causes it to execute any other program, which is more important at the time of operation.
The feature of Interrupt is very useful as it helps in case of emergency operations. An Interrupts
gives us a mechanism to put on hold the ongoing operations, execute a subroutine and then
again resumes to another type of operations.

The Microcontroller 8051 can be configured in such a way that it temporarily terminates or
pause the main program at the occurrence of interrupts. When a subroutine is completed, Then
the execution of main program starts. Generally five interrupt sources are there in 8051
Microcontroller. There are 5 vectored interrupts are shown in below

INTO
TFO
INT1
TF1
R1/T1
Out of these, (INT0) ̅ and (INT1) ̅ are external interrupts that could be negative edge triggered
or low level triggered. When All these interrupts are activated, set the corresponding flogs
except for serial interrupt,.The interrupt flags are cleared when the processor branches to the
interrupt service routine (ISR). The external interrupt flags are cleared when the processor
branches to the interrupt service routine, provides the interrupt is a negative edge triggered
whereas the timers and serial port interrupts two of them are external interrupts, two of them
are timer interrupts and one serial port interrupt terminal in general.

Memory
Microcontroller requires a program which is a collection of instructions. This program tells
microcontroller to do specific tasks. These programs require a memory on which these can be
saved and read by Microcontroller to perform specific operations of a particular task. The
memory which is used to store the program of the microcontroller is known as code memory or
Program memory of applications. It is known as ROM memory of microcontroller also requires
a memory to store data or operands temporarily of the micro controller. The data memory of
the 8051 is used to store data temporarily for operation is known RAM memory. 8051
microcontroller has 4K of code memory or program memory,that has 4KB ROM and also 128
bytes of data memory of RAM.

BUS
Basically Bus is a collection of wires which work as a communication channel or medium for
transfer of Data. These buses consists of 8, 16 or more wires of the microcontroller. Thus, these
can carry 8 bits,16 bits simultaneously. Hire two types of buses that are shown in below

Address Bus
Data Bus
Address Bus: Microcontroller 8051 has a 16 bit address bus for transferring the data. It is used to
address memory locations and to transfer the address from CPU to Memory of the
microcontroller. It has four addressing modes that are

Immediate addressing modes.

Bank address (or) Register addressing mode.
Direct Addressing mode.
Register indirect addressing mode.
Data Bus: Microcontroller 8051 has 8 bits of the data bus, which is used to carry data of
particular applications.

Oscillator
Generally, we know that the microcontroller is a device, therefore it requires clock pulses for its
operation of microcontroller applications. For this purpose, microcontroller 8051 has an on-chip
oscillator which works as a clock source for Central Processing Unit of the microcontroller. The
output pulses of oscillator are stable. Therefore, it enables synchronized work of all parts of the
8051 Microcontroller.

Input/Output Port
Normally microcontroller is used in embedded systems to control the operation of machines in
the microcontroller. Therefore, to connect it to other machines, devices or peripherals we
require I/O interfacing ports in the microcontroller interface. For this purpose microcontroller
8051 has 4 input, output ports to connect it to the other peripherals

Timers/Counters
8051 microcontroller has two 16 bit timers and counters. These counters are again divided into a
8 bit register. The timers are used for measurement of intervals to determine the pulse width of
pulses.

OR
(b) Write an 8051ALP to create a square wave of 66 % duty cycle on bit 3 of port 1. (16)
15. (a) Draw the diagram to interface a stepper motor with 8051 microcontroller and Write its
ALP to run the stepper motor in both forward and reverse direction with delay. (16)
A stepper motor is a widely used device that translates electrical pulses into mechanical
movement. It is used for position control in applications such as disk drives, dot matrix printers
and robotics.

Stepper motors commonly have a permanent magnet rotor (shaft) surrounded by a stator as
shown in Figure 17-7.
The most common stepper motors have four stator windings that are paired with a center-
tapped common as shown in Figure 17-8. This type of stepper motor is commonly referred to as
a four-phase or unipolar stepper motor.

The center tap allows a change of current direction in each of two coils when a winding is
grounded, thereby resulting in a polarity change of the stator. When a conventional motor shaft
runs freely, the stepper motor shaft moves to a precise position based on magnetic theory where
poles of the same polarity repel and opposite poles attract. The direction of the rotation is
dictated by the stator poles. The stator poles are determined by the current sent through the
wire coils. As the direction of the current is changed, the polarity is also changed causing the
reverse motion of the rotor.
The 8051 connection to the stepper motor is shown in Figure 17-9. The four leads of the stator
windings are controlled by four bits of the 8051 port (P1.0 – P1.3). Since the 8051 lacks
sufficient current to drive the stepper motor windings, a driver such as ULN2003 is used to
energize the stator. The ULN2003 has an internal diode to take care of back EMF.
8051 assembly language program to run the stepper motor in both forward and reverse
direction with delay.
LOOK UP TABLE:
Clockwise Direction Anti-Clockwise Direction
Memory A1 A2 B1 B2 HEX A1 A2 B1 B2 HEX
Location Code Code
4500 1 0 0 1 09 1 0 1 0 0A
4501 0 1 0 1 05 0 1 1 0 06
4502 0 1 1 0 06 0 1 0 1 05
4503 1 0 1 0 0A 1 0 0 1 09
FLOWCHART:

Start

Initialize Counter (DPTR) for Look Up Table

Get the First Data from the Accumulator

Move Data into the Accumulator

Drive the Motor Circuitry

Delay

Decrement Counter (R2)

Y
Is R2 = 0?
N

Get the Data From Look Up Table

PROGRAM:
LABEL MNEMONICKS
START: MOV DPTR, #4500
MOV R2, #04
MOV R0, DPL
MOV R1, DPH
LOOP: MOVX A, @DPTR
MOV DPTR, #FF10
MOVX @DPTR, A
INC R0
MOV DPL, R0
MOV DPH, R1
CALL DELAY
DJNZ R2, LOOP
SJMP START
DELAY: MOV R4, #55
L3: MOV R5, #55
L2: DJNZ R5, L2
DJNZ R4, L3
RET
OR
(b) Explain 8051 serial port programming with examples. (16)
One of the microcontroller features making it so powerful is an integrated UART, better known
as a serial port. It is a full-duplex port, thus being able to transmit and receive data
simultaneously and at different baud rates. Without it, serial data send and receive would be an
enormously complicated part of the program in which the pin state is constantly changed and
checked at regular intervals. When using UART, all the programmer has to do is to simply
select serial port mode and baud rate. When it's done, serial data transmit is nothing but writing
to the SBUF register, while data receive represents reading the same register. The
microcontroller takes care of not making any error during data transmission.

Serial port must be configured prior to being used. In other words, it is necessary to determine
how many bits is contained in one serial “word”, baud rate and synchronization clock source.
The whole process is in control of the bits of the SCON register (Serial Control).
Serial Port Control (SCON) Register

SM0 - Serial port mode bit 0 is used for serial port mode selection.
SM1 - Serial port mode bit 1.
SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit.
When set, it enables multiprocessor communication in mode 2 and 3, and eventually mode 1. It
should be cleared in mode 0.
REN - Reception Enable bit enables serial reception when set. When cleared, serial
reception is disabled.
TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem of
transmiting the 9th bit in modes 2 and 3. It is set to transmit a logic 1 in the 9th bit.
RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if 9th
bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.
TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte is
sent. It's a signal to the processor that the line is available for a new byte transmite. It must be
cleared from within the software.
RI - Receive Interrupt flag is automatically set upon one byte receive. It signals that byte
is received and should be read quickly prior to being replaced by a new data. This bit is
also cleared from within the software.
Serial port mode is selected by combining the SM0 and SM2 bits:

SM0 SM1 Mode Description Baud Rate

0 0 0 8-bit Shift Register 1/12 the quartz frequency

0 1 1 8-bit UART Determined by the timer 1

1/32 the quartz frequency (1/64 the quartz

1 0 2 9-bit UART frequency)
 1 1 3 9-bit UART Determined by the timer 1

In mode 0, serial data are transmitted and received through the RXD pin, while the
TXD pin output clocks. The bout rate is fixed at 1/12 the oscillator frequency. On transmit, the
least significant bit (LSB bit) is sent/received first.

TRANSMIT - Data transmit is initiated by writing data to the SBUF register. In fact, this
process starts after any instruction being performed upon this register. When all 8 bits have
been sent, the TI bit of the SCON register is automatically set.

RECEIVE - Data receive through the RXD pin starts upon the two following conditions are met:
bit REN=1 and RI=0 (both of them are stored in the SCON register). When all 8 bits have been
received, the RI bit of the SCON register is automatically set indicating that one byte receive is
complete.

Since there are no START and STOP bits or any other bit except data sent from the SBUF
register in the pulse sequence, this mode is mainly used when the distance between devices is
short, noise is minimized and operating speed is of importance. A typical example is I/O port
expansion by adding a cheap IC (shift registers 74HC595, 74HC597 and similar).
Mode 1
In mode 1, 10 bits are transmitted through the TXD pin or received through the RXD pin in the
following manner: a START bit (always 0), 8 data bits (LSB first) and a STOP bit (always 1). The
START bit is only used to initiate data receive, while the STOP bit is automatically written to the
RB8 bit of the SCON register.
TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data
transmission is indicated by setting the TI bit of the SCON register.

RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The following
two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the SCON
register. The RI bit is automatically set upon data reception is complete.

The Baud rate in this mode is determined by the timer 1 overflow.

When Timer 1 operates at mode 2 (Auto reload mode)

When timer 1 is not run in mode 2

Mode 2

In mode 2, 11 bits are transmitted through the TXD pin or received through the RXD pin: a
START bit (always 0), 8 data bits (LSB first), a programmable 9th data bit and a STOP bit
(always 1). On transmit, the 9th data bit is actually the TB8 bit of the SCON register. This bit
usually has a function of parity bit. On receive, the 9th data bit goes into the RB8 bit of the same
register (SCON).The baud rate is either 1/32 or 1/64 the oscillator frequency.
TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data
transmission is indicated by setting the TI bit of the SCON register.
RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The following
two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the SCON
register. The RI bit is automatically set upon data reception is complete.

The Baud rate in this mode is determined by

Mode 3
Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is
variable.
When Timer 1 operates at mode 2 (Auto reload mode)

When timer 1 is not run in mode 2

Baud Rate
Baud Rate is a number of sent/received bits per second. In case the UART is used, baud rate
depends on: selected mode, oscillator frequency and in some cases on the state of the SMOD bit
of the SCON register.