Verilog Training for

APSSDC

Anand S Moghe

* ANAND S MOGHE 1
 VERILOG – A Hardware Description Language (HDL)
• Importance of Verilog in VLSI design and verification
Background:
• Verilog introduced by Philip Moorby in 1985
• Dominant standard for advanced electronic designs, because
of its clarity, simplicity, power, range of tools available, higher
simulation speeds and efficacy, vast libraries, and because
ASICs are signed off by vendors running Verilog
• Verilog commands a higher share (than VHDL) in the market
today
• Average density of largest ICs and medial clock frequency of
designs using Verilog were both nearly twice as that of
designs using VHDL

* ANAND S MOGHE 2
 VERILOG – A Hardware Description Language (HDL)
Background (contd):
• Best language for building digital systems.
• Verilog led VHDL by 5-10 years (a few years ago) with its goal
of making digital designers the most productive.
• Verilog has evolved because of its open standard. A standard
must be open so that others can use it and build on it and
compete with it to make it better.
• Verilog – it is a language, a simulator and an environment. For
all these contexts, the term Verilog is used without causing
any confusion in the mind of the participant.

* ANAND S MOGHE 3
 VERILOG – A Hardware Description Language (HDL)
Use of an HDL
1. Simulation: By allowing you to simulate your design, you
can see if the design works before you build it, which gives
you a chance to try out different ideas.
2. Documentation: This feature lets you maintain and reuse
your design ideas more easily. Verilog’s intrinsic hierarchical
modularity enables you to easily reuse portions of your
design as “intellectual property” or macro cells.
3. Synthesis: You can design using HDL and let other tools do
the tedious and detailed job of hooking up the gates.

* ANAND S MOGHE 4
 VERILOG – A Hardware Description Language (HDL)
History of Verilog
• It was introduced by Philip Moorby in 1985.. It was
originally developed by Philip Moorby and later he became
the chief designer of Verilog-XL. This work was originated at
Automated Integrated Design Systems (AIDS) , which was
later renamed as Gateway Design Automation.
• IEEE working group under the Design Automation
sub-committee developed the first standard named as “IEEE
1364-1995 Verilog”. Subsequently upgraded to “IEEE
1364-2000 Verilog.

* ANAND S MOGHE 5
 VERILOG – A means of describing hardware
Assumes knowledge of basic logic design and of basic software programming.
• Hardware described using Verilog is a collection of modules, just as a C program
is a collection of functions.
• module – It is a unit of functionality, and has some inputs and some outputs.
These inputs/outputs are called as ports. These are the pins through which the
module interacts/communicates with other modules (blocks).

in1 out1
some_func out2
in2
( logic blk ) out3
in3
out4

• The above is a module that has 3 pins where the inputs can be connected to the
logic block and 4 pins from where the logic outputs can be taken. (the words
input and output are reserved words in Verilog and hence cannot be used as
names; hence the use of in1/2/3 and out1/2/3/4)

* ANAND S MOGHE 6
 VERILOG – A means of describing hardware
• Structure of a module:
module some_func(out1, out2, out3, out4, in1, in2, in3);
output out1, out2, out3, out4;
input in1, in2, in3;
. . . . . . . .
. . . . . . . . (behavioral description goes here)
endmodule
//(module and endmodule form a pair of keywords)
• In the above example, a module is defined. A definition of a module gives its
form and structure only. No actual piece of logic is created when a module is
defined; some_func is the module type.
• Here in1 – in3 and out1 – out4 are called the ports of the module. A module
interfaces/communicates with other modules through its ports only.
• Instantiation:- this is when the actual logic gets created/connected as per the
module structure and form.
some_func MOD1 (a1, a2, a3, a4, p, q, r); → is an instance of a the module type some_func.
• A module can be instantiated several times, but each instance must have a
distinct name.

* ANAND S MOGHE 7
 VERILOG – A means of describing hardware…
• Execution of this statement
some_func MOD1 (a1, a2, a3, a4, p, q, r);
causes the logic described in the module to get executed as per the form and
structure of the module.

• The signals a1, a2, a3, a4 in the above instantiation get connected to the ports
out1 to out4 respectively of MOD1. Similarly, the signals p, q, r get connected to
the ports in1, in2 and in3 respectively, of MOD1. This is by virtue of position of
a1-a4 and p, q, r in the instantiation.

• A better way of instantiating a module is:

some_func MOD1 (.out1(a1), .out2(a2), .out3(a3), .out4(a4), .in1(p), .in2(q), .in3(r) );
(note: the order or position is not important in this type of instantiation)

• A module cannot be defined in another module. (Nesting of definition not

allowed). It can only be instantiated (called) in another module. This gives rise
to the concept of hierarchy. (see next slide for an illustration)

* ANAND S MOGHE 8
 VERILOG – A means of describing hardware…
• Instantiation of a module should be done preferably in the following way.
• One port per line…. for ease of reading….
some_func MOD1 (
.out1(a1), // comments can be written for each port if required….
.out2(a2),
module type .out3(a3),
.out4(a4),
Instance name – it has
.in1(p), to be unique
.in2(q),
.in3(r) // last port does not have a comma in the end
);

* ANAND S MOGHE 9
 VERILOG – A means of describing hardware…
Nesting of modules – illustration:

module some_func(ou1, out2, out3, out4, in1, in2);

……
…….
……
module
…..
This is a nested definition and is not allowed in Verilog.
…..
endmodule

endmodule

* ANAND S MOGHE 10
 Details of a Verilog module…
Functional objective:
To add 2 numbers in1 and in2 and produce an output called “sum”.

Intended logic: Adder

Verilog module to achieve the above functionality:
module two_ip_add(sum, in1, in2);
output [8:0] sum; // by default this is of data-type wire
input [7:0] in1;
two_ip_add
input [7:0] in2;
in1
sum
// the below statement provides the functionality to the module... in2
assign sum = in1 + in2;

endmodule

This module has defined a two – input adder functionality. No hardware has been
created at this point. Only the template of the adder has been defined. in1 and in2
are the input ports of this module and sum is the output port of this module.

assign statement → evaluates when either in1 or in2 changes. (How it will change, we will
see later).
Hence at all times, the value of sum is the addition of in1 and in2.

* ANAND S MOGHE 11
 Details of a Verilog module…
Another way of writing the Verilog module to achieve the above functionality:
module two_ip_add(sum, in1, in2);
output [7:0] sum; two_ip_add
in1
input [7:0] in1; sum
input [7:0] in2; in2
reg [7:0] sum;
// the below statement provides the functionality to the module...
always @(in1 or in2) begin // procedural block
sum = in1 + in2;
end
endmodule

Concept of simulation time – how execution of Verilog code is different from that of
normal C code, for example.

Concept of reg and wire variables – when to declare a variable as reg and when to
declare it as a wire. (The data types wire and reg have merged as ‘logic’ in
system Verilog).

* ANAND S MOGHE 12
 Verilog vs. C
Difference between execution of Verilog code and C code:
– Verilog code represents hardware and hence it (Verilog code) will
not execute once and finish execution like the C code.
– Verilog code starts executing at simulation time t=0 and
continues to execute till the signal / logic inputs are available.
– C code execution starts at the beginning of the file and flows
through depending on the control , and completes the execution
and stops.
– Verilog code executes concurrently with respect to simulation
time.
– In Verilog, it does not matter at which point in the file we write a
piece of ‘valid code’. Even if we change the position of this code,
it does not matter to the result. This is due to the nature of
execution of the Verilog code.
– In C, it matters at which point in the file we write a piece of valid
code. If the position of this code is incorrect, then the program
will not execute correctly.
* ANAND S MOGHE 13
 Details of a Verilog module…
• Test bench to verify the module functionality:

(i) Test bench is a Verilog module just like any other Verilog module.
(ii) Test bench has no input or output ports – it is the topmost level module in a
hierarchy.
(iii) The module to be verified is instantiated in the test bench.

two_ip_add
a
in1 DUT
b
sum
in2 (instantiated) y

Values
generation
code
Test bench

• In the test bench, declare some variables a, b as reg type variables, as they have
to hold the values given to them by the test bench writer (verification engineer).
Also declare an internal variable y as wire.
• a, b, and y are of width 8 bits ( [7:0] ) and are internal to the test bench.

* ANAND S MOGHE 14
 Details of a Verilog module…
• Write a test bench to verify the functionality of the adder…
module tb_two_ip_add; // notice that there are no ports for this module
reg [7:0] a; // local variable of type reg
reg [7:0] b; // local variable of type reg
wire [8:0] y; // local variable of type wire
// instantiate the two-input adder in the test bench….
two_ip_add ADD2_NO1 (.in1(a), .in2(b), .sum(y) );

// apply inputs to a and b….

initial begin two_ip_add
a
a = 8’h0b; in1
b = 8’h1e; b
sum
in2 (instantiated) y
#5
a = 8’ha7; Values
b = 8’hb2; generator

#10 Test bench

$stop();
end
initial begin
$monitor ($time, “y = %5d a = %5d b = %5d “, y, a, b);
end
endmodule

* ANAND S MOGHE 15
 Details of a Verilog module…
• Note that the inputs are applied to a and b – not to in1 and in2. The module
two_ip_add has been instantiated in the test bench
• The input line a gets connected to the input port in1 and the input line b gets
connected to the input port in2.
• $monitor is a Verilog system function that prints the values whenever there is
change in the values of a or b or both .
• $finish is a system function that causes the simulation to end. Without this, the
simulation will not end.
• Name the file as two_ip_add.v and write the module and test bench in the same
file. Simulate the file by using the command (cadence simulator):
ncverilog +access+rw two_ip_add.v
and observe the output. Verify manually.

• There can be several always blocks a two_ip_add

in a Verilog module in1
b
sum
in2 (instantiated) y
• Similarly, there can be several initial
blocks in a Verilog module Values
generator
Test bench

* ANAND S MOGHE 16
 Hierarchy in a Verilog description…
Objective:
• To construct a 3-input adder from a 2-input adder used in the previous
example. Specification of the 3-input adder is:- y = a + b + c

three_ip_add
two_ip_add
a in1 ps
sum
b in2 1

two_ip_add
in1 y
sum
c
in2
2

• Figure above shows a 3-input adder constructed from a two-input adder. The
ports of the 3-input adder are a,b,c (input) and y (output).
• We say that the 3-input adder has a lower level of hierarchy below it. The lower
level is the 2-input adder.

* ANAND S MOGHE 17
 Hierarchy in a Verilog description…
module three_ip_add (y, a, b, c);
output [7:0] y;
input [7:0] a;
input [7:0] b;
input [7:0] c;

wire [7:0] ps;

// instantiate 2 nos. of two_ip_add and connect them as shown in the figure …

two_ip_add ADD2_NO1 (.sum(ps), .in1(a), .in2(b) );
two_ip_add ADD2_NO2 (.sum(y), .in2(c), .in1(ps) );
endmodule

There are other ways in which the module for the three_ip_add can be written:
module three_ip_add (y, a, b, c);
output [7:0] y;
input [7:0] a;
input [7:0] b;
input [7:0] c;

wire [7:0] ps;

assign ps = a + b;
two_ip_add ADD2_NO2 (.sum(y), .in1(c), .in2(ps) );
endmodule

* ANAND S MOGHE 18
 Hierarchy in a Verilog description…
• The previous example shows a mix of behavioral and structural ways of writing code to
express the same functionality (of the adder).
• The test bench for this will look something like this :
Test bench

three_ip_add
p two_ip_add
a in1 ps
sum
q b in2 1

two_ip_add
in1 y Output
r sum check
c
in2
2

Values generator

• Note that the test bench instantiates the three_ip_add and the three_ip_add
instantiates the two_ip_add. There are 3 levels of hierarchy here.
* ANAND S MOGHE 19
 Hierarchy in a Verilog description…
• The three_ip_add module can be used to construct a six_ip_add module which adds 6
nos of 8-bit inputs. Specifications : y = a + b + c + d + e + f.
Test bench
six_ip_add
three_ip_add
a a

b b ps1
y two_ip_add

c c
in1
y
sum
three_ip_add

d in2
a

ps2
e b y

f c

• In this case, if the test bench is considered as the top level module, there are 4
levels of hierarchy.

* ANAND S MOGHE 20
 Hierarchy in a Verilog description…
• The module for the 6-input adder can be written in one of several different ways:

module six_ip_add (y, a, b, c, d, e, f);

output [7:0] y;
input [7:0] a, b, c, d, e, f;
wire [7:0] ps1, ps2;

// instantiate the adders…..

three_ip_add THREE_IP_ADD1 (.a(a), .b(b), .c(c), .y(ps1));
three_ip_add THREE_IP_ADD2 (.a(d), .b(e), .c(f), .y(ps2));
two_ip_add TWO_IP_ADD1 (.in1(ps1), .in2(ps2), .sum(y));

endmodule

The above is a purely structural way of writing. A mix of all forms is also possible:
module six_ip_add (y, a, b, c, d, e, f);
output [7:0] y;
input [7:0] a, b, c, d, e, f;
wire [7:0] ps1, ps2;

reg [7:0] y;

assign ps1 = a + b + c;
three_ip_add THREE_IP_ADD2 (.a(d), .b(e), .c(f), .y(ps2));
always @(ps1 or ps2)
y = ps1 + ps2;

endmodule

* ANAND S MOGHE 21