VLSI Testing

積體電路測試

Advanced Topics

Professor James Chien-Mo Li 李建模

Lab. of Dependable Systems
Graduate Institute of Electronics Engineering
National Taiwan University

1 VLSI Test 18.1 © National Taiwan University

 Why Am I Learning This?
• Your manager asks you
 “We already apply test patterns of 100% fault coverage, why can’t
we achieve 0 DPM?”
 “We are entering the automobile market, how to reduce test
escapes?”

“When you have faults,

do not fear to abandon them.”
過則勿憚改
( Confucius)

2 VLSI Test 18.1 © National Taiwan University

 Outline
• Introduction
 Defect Categories
• Defect-based Testing
• Advanced ATPG
• Conclusion

3 VLSI Test 18.1 © National Taiwan University

 100% FC  0 DPM
• In theory, DL =1-Y(1-FC)
 but fault coverage does NOT represent defect coverage
• Experimental results [Stanford CRC]
 Total 5.5K chips tested by many kinds of test sets
 116 defective chips, up to 6 escaped 100% SSF test sets
• Example of test escapes
 High impedance bridging defect
 Cause abnormal static current
 May not detectable by Boolean testing

Must Understand Defects Better to Test Them

4 VLSI Test 18.1 © National Taiwan University
 Defects
• Defect
 Unintended physical difference between hardware
implementation and its intended design
 Example: unwanted wire (short to ground)
• Failure Mechanism
 Physical or chemical process that cause defects
defect
causes
 Examples: Dust particle falling on wafer
• Failure Mode
 Causes or possible ways a device can fail
 Examples:
defect
behavior
 Opens, Shorts
 Parametric
− Vt shift

− Transistor transconductance (Ron , Roff) changed

− Contact resistance, wire resistance increased

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 Different Levels of Terminology
error signal Error
1
1/0
1

SA 0 Fault
logic circuit Fault

Fault modeling

Open Metal Wire

open/short/parametric Failure mode

defects

physical/chemical Failure mechanism

Particle on Mask

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 Quiz
Q: Which of following is failure mechanism?

A: a metal wire is open

B: a particle dust falling on mask

C: a transistor Ron is too high

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 Outline
• Introduction
 Defect Categories
 Oxidation
 Metallization
 Wire Bonding / Packaging
 Overstress
 Others: Reliability
• Defect-based Testing
• Advanced ATPG
• Conclusion

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 Defect Categories
• Classified by occurrence
 Random defects
 Caused by random factors such as particles
 Systematic defects
 Caused by deterministic factors such masks

• Classified by process
 Oxidation (front end process)
 Metallization (back end process)
 Wire Bonding / Packaging
 Overstress
 Others: Reliability

Briefly Introduce CMOS Process Defects

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 Oxidation Related Defects
• Thin oxide (gate oxide)
 Hot electron injection ➔ Vt shift, Transconductance change
 Oxide breakdown ➔ gate oxide shorts
 Ionic contamination ➔ Vt shift

• Thick oxide (field oxide)

 Ionic contamination

Failure Mechanism ➔ Failure Mode

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 Hot Electron Injection aka Hot Carrier Injection
• Failure mechanism
Carriers (like electrons) gain high energy from source-drain
potential drop
 Some electrons gain such high energy (called hot electrons) that
they are able to cross the energy barrier of Si-Oxide interface and
trapped in oxide
• More evident in nMOS

oxide
e-

oxide
e-
− 
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 Hot Electron Injection 2/2
• Results (Failure modes) of HEI
 Vt shift
 Transconductance change

• Example

VG = 5V Before HEI
Current
After HEI
VG = 3V

VG = 2V

Drain Voltage
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 Oxide Breakdown
• What is Oxide breakdown?
 Sudden increase in oxide conductance
 High current pass through and Joul heating cause oxide damage
• Three frequent failure mechanisms
1. Pinholes or thin spots in oxide
 Point defects in thin oxide where atom missing from lattice
site
2. Tunneling effect
 Electrons injected into oxide by tunneling and break bonds by
collision
 Can be serious problem in future ultra-thin oxide technology
3. Electrical overstress
 Wrong design or careless handling
• Results (Failure mode) of oxide breakdown
 Gate oxide shorts

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 Gate Oxide Shorts
• What are gate oxide shorts ?
Low impedance path between gate and Si surface
• One of the most frequent failure modes in CMOS technology
• Gate oxide shorts can exist between
 Gate-drain
 Gate-source
 Gate-substrate

• Models
 if nMOS
 Simply resistor, 4.7Kohm [Hawkins 85]
 The number is process dependent
 If pMOS
 Complex model with diodes, resistors [Syrzycki 89]

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 Ionic Contamination
• Failure Mechanism
Presence of mobile ions (e.g. Na+) near surface of oxide can
invert the intended doping concentration near surface
 Can accumulate over time
• Failure modes
 Vt Shift
 Leakage current increased
• One major problems in early CMOS process (1930)
 Took ~10 years to figure out the culprit was ion

  

Na+
Na+

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 Outline
• Introduction
Defect Categories
 Oxidation
 Metallization
 Wire Bonding / Packaging
 Overstress
 Others: Reliability
• Defect-based Testing
• Advanced ATPG
• Conclusion

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 Metallization Related Defects
• Poor lithography patterning ➔ open or short
 mask problem, misalignment, poor step coverage etc
• Bad Chemical Mechanical Polishing (CMP) ➔ open or short
• Particle ➔ open or short
• Bad Via or contact ➔ open or increased resistance
• Melting ➔ open
 Excess current density melt wires
 can be caused by design error, scratch, mask problem
• Alloy ➔ open or short
 Si dissolved into Al or Al dissolved into Si
• Scratch ➔ open
 Caused by careless handling

Failure Mechanism ➔ Failure Mode

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 Particles Can Cause Shorts
• Aluminum process steps
 1. Al deposition
 2. Photoresist deposition
 3. Expose
 4. Etch off photoresist between wires
 Particles fall on die
 5. Etch off Al between wires
 Particles cause shorts

“What is an Etch System”

https://www.hitachi-hightech.com/

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 Particles Also Cause Opens
• Copper Process (Damascene process)
 1. Oxide deposition
 2. Photoresist deposition
 Expose
 Etching
 3. Copper Seed layer
 Particles fall on die
 4. Copper deposition
 Particle cause opens N. Kobayashi, “Damascene Concept and Process
Steps,” Advanced Nanoscale ULSI Interconnects,
 5. Chemical Mechanical Polishing 2009

Defects are Process Dependent

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 Metallization Defects
• Vias / contact related defects
 Failure Mechanism
 Incomplete etching
 Mask problems
 Particles
 Failure modes
 Open D. Payne (Synopsys), “Catching IC
Manufacturing Defects With Slack-Based
 Increased resistance Transition Delay Testing”, SemiWikli.com, 2014

• CMP related defects

 Failure mechanism
 Insufficient polishing
 Failure mode K.M. Robinson, K. DeVriendt, and D.R. Evans,
“Integration Issues of CMP,” Chemical-Mechanical
 shorts Planarization of Semiconductor Materials, Springer 2004

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 Wire Bonding Related Defects
• Poor pad ➔ open or short
Al interact with Si at high temperature, penetrating each other
• Purple plague ➔ open
 Bonding Au wire to Al pad in the presence of Si forms AuAl2
compound, a purple intermetallic compound which is brittle
• Poor pad-wire contact ➔ open or short
 Caused by insufficient or excessive pressure/temperature

Bond wire
pin

die pad

21 package
VLSI Test 18.1 © National Taiwan University
 Package Related Defects
• Moisture penetration
• Mechanical problem
• Poor die-attach
 Die cannot sit in the package substrate properly
 Caused by :Solder quantity, temperature, pressure

E. Spaan, E. Ooms, “Wire bonding the future:

a combined experimental and numerical
approach to improve the Cu-wire bonding
quality,” EuroSimE, 2010

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 Overstress
• Electrical overstress

Due to design mistake
• Electrostatic discharge (ESD)
 Due to careless handling
 Can be minimized by ESD protection circuitry

Vdd

(A) ESD Protection Diode

Bond
Buffer

Pin Bond Pad

ESD Protection Diode Edvard, “Never underestimate
(B) electrostatic discharge (ESD) while
working with data networking
Gnd equipment, “ EE Portal 2017

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 Outline
• Introduction
Defect Categories
 Oxidation (front end process)
 Metallization (backend process)
 Wire Bonding / Packaging
 Overstress
 Others: Reliability
• Defect-based Testing
• Advanced ATPG
• Conclusion

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 Review: Reliability Curve (CH1)
• IC’s failure rate* resembles a bathtub
 Infant mortality: fail early in life, due to reliability defects

Infant Normal Wear-out

mortality lifetime period
period
Failure rate

*Failure Rate =
percentage of failures
in a period of time

Time
~ 20 weeks 5 – 25 yrs
Burn-in ALT

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 Reliability Defects
• Devices
 Negative bias temperature instability (NBTI) → Vt shift in PMOS
 Time-dependent gate oxide breakdown (TDDB) → Vt shift,
increase leakage current
 Hot electron injection → Vt shift

• Wiring
 Eletronmigration ➔ open, short
 Stress-induced voiding ➔ open
 Corrosion ➔ open

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 Electromigration
• Atom moved by electron wind when current density J too high
 Aluminum J > 105 A/cm2 and T > 100ºC
 Copper is more resistant to electromigration

• Two possible failure modes:

 Voids ➔ open
 hillocks ➔short

hillocks ➔ Short Voids ➔ Open

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 Example Defect Pareto
defect pareto
40%

35%

30%

25%

20%

15%

10%

5%

0%
metalization oxidation packaging overstree others

Defects are Process Dependent

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 Quiz
Q: Which of following is NOT correct?

A: particle can cause both opens and shorts

B: reliability defects worsen with time

C: SSF can model all kinds of open defects

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 Conclusion
• 100% FC  0 DPM
• Failure mechanism: cause of defect
Physical or chemical process that cause defects
• Failure mode: behavior of defect
 Causes or possible ways a device can fail
• Defect Categories (process dependent)
 Oxidation (front end process)
 Metallization (backend process)
 Wire Bonding / Packaging
 Overstress
 Others: Reliability

Impossible To Model All Defects

by a Single Fault Model
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31 VLSI Test 18.1 © National Taiwan University
 Corrosion
• Residue of solvents used during process or traces of chemicals in
packaging
 Corrosion in Al in presence of H2O
• Plastic package particularly poor
 Moisture can penetrate

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 Test Escape vs. Yield Loss
• True pass and true reject are correct decision
• Test escapes = defective chips that pass test
also known as (aka.) under-testing
• Yield loss = good chips that fail the tests
 aka. overkill, over-testing
• Goal of DBT: reduce both test escape and yield loss
 Side effects of DBT
 Sometimes inevitably increases yield loss
 Trade off between yield loss and test quality

Good IC Defective IC
Pass tests True PASS Test Escapes
(less is better)
Fail tests Yield Loss True Reject
(less is better)

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 Definitions
• Defect
Unintended physical difference between hardware
implementation and its intended design
 Example: unwanted wire (short to ground)
• Fault
 Representation of defects at abstracted logic level
 Example: b stuck at zero fault
• Error 1
1/0
 Wrong output signal value 1
 Example: output = 0, when a=b=1
good / error
• Failure
 Deviation from expected behavior
 Example: computer crash

Defect → Fault → Error → Failure

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 Introduction
• What is Defect Based Testing (DBT)
 Testing without specific fault model involved

• Why Defect Based Testing?

 reduce DPM
 100% fault coverage is not good enough
 Defects do not always behave as faults

• Experimental results [Stanford CRC]

 Total 5.5K chips tested by many kinds of test sets
 116 defective found
 2 to 6 chips escaped 100% SSF test sets
 Example : High impedance bridging defect
 Cause abnormal static current
 May not detectable by Boolean testing
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 Example

Failure Mechanism: Particle on Mask Failure Mode: Open Metal Line

A 1 0
1

Fault Model: Stuck-at-1 Fault

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 Fail. Mech → Fail. Mode → Fault

Higher level system behavior Failure

I/O signal Error

logic circuit Fault

defects
open/short/ Failure mode
device model

Lower level physical/chemical Failure mechanism

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 Failure Mode Analysis

[Vallet IBM 1997]

[Nigh IBM 1998]

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 D. Payne, “Catching IC Manufacturing Defects With Slack-Based Transition Delay Testing”

C.Wuab,Syaoa,B.Corinne, “Leakage current study and relevant defect localization in inte

circuit failure analysis,”
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