VHDL Language

VHSIC Hardware Description language

School of Aerospace & Automotive Engineering Prof. BELKASMI Merouan

International University of Rabat
2023-2024
 Why using VHDL ?
•Executable specification

Simulate early and fast

Automatic synthesis and test generation

•Explore design alternatives

•Portable design data (Protect investment)

 Introduction, VHDL Basics
01

Concurrent structures
02

Sequential structures
03

Testbenches
04
 Introduction
• Classical digital design flow
 Introduction
• Classical digital design flow
 Introduction
Modern digital design flow
 Introduction
Modern digital design flow
 Introduction
Integrated Circuits
▪ An integrated circuit (IC) is a collection of a set of electronic components (transistors, resistors,capacitors, diodes, etc.)
integrated in one small flat piece (called chip) of semiconductor material such as silicon.

Integrated Circuits

Standard Logic Programmable programmable architecture Circuits with important

Circuits integrated circuit circuit short development time development time

Microcontroller
74HC… Microprocessor PLD,CPLD, FPGA… ASIC
 Introduction
FPGA : Field Programmable Grid Array
• Hardware integration of additional components
• RAM: called LUT (Look-Up Table)
• Mutiplexers
• PLL
• DSP
Introduction
Specifications
FPGA
• Cyclone II EP2C35F672C6 FPGA and
EPCS16 serial configuration device
I/O Devices
• Built-in USB Blaster for FPGA configuration
• 10/100 Ethernet, RS-232, Infrared port
• Video Out (VGA 10-bit DAC)
• Video In (NTSC/PAL/Multi-format)
• USB 2.0 (type A and type B)
• PS/2 mouse or keyboard port
• Line-in, Line-out, microphone-in
(24-bit audio CODEC)
• Expansion headers (76 signal pins)
Memory
• 8-MB SDRAM, 512-KB SRAM, 4-MB Flash
• SD memory card slot
Switches, LEDs, Displays, and Clocks
• 18 toggle switches
• 4 debounced pushbutton switches
• 18 red LEDs, 9 green LEDs
• Eight 7-segment displays
• 16 x 2 LCD display
• 27-MHz and 50-MHz oscillators, external SMA clock input
VHDL basics
The Anatomy of a VHDL File

Package
(IEEE standard package is inherent. additional
packages are optional)

Entity
(description of inputs/outputs of the system)

Architecture
(description of the behavior of the system)
 VHDL basics
Entity declaration
Describes the name, the parameters and the interface
(input/output signals) of the component

Ports types
Entity name
Ports names
Semicolon
ENTITY and2_op IS
PORT(
Without semicolon
a, b: IN STD_LOGIC;
z : OUT STD_LOGIC
);
END and2_op;

Reserved words Ports modes (data flow directions)

 VHDL basics
Architecture description
Architecture - describes component implementation by a
• Data flow description model
• Structural description model
• Behavioral description model

Architecture name Entity name

ARCHITECTURE data_flow OF and2_op IS

BEGIN
Output signal
z <= a AND b;
assignment
END data_flow;

Reserved words delimiting

the architecture
 VHDL basics
Entity and architecture declaration
Complete description of the logic structure

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY and2_op IS
PORT(
a, b: IN STD_LOGIC;
z : OUT STD_LOGIC);
END and2_op;

ARCHITECTURE data_flow OF and2_op IS

BEGIN
z <= a AND b;
END data_flow;
 VHDL basics
Port mode IN
Signal of the port
in mode IN Entity

The signal is generated Ex. :

outside of the entity C <= A;

Internal signal Input

• IN: input port – data coming to this port can be read inside the component, the name of the port can be
situated only on the right side of the assignment expression
 VHDL basics
Port mode OUT
Entity

Signal of the port in mode OUT

Int_sig B

Output Internal signal

C
B <= Int_sig;
The signal is generated C <= B;
inside the entity
Internal signal
Output signal
Problem: the signal in the mode OUT cannot be read (referenced)
inside the entity (C cannot read B in mode OUT)
 VHDL basics
Port mode BUFFER
Entity

Signal of the port in mode BUFFER

Int_sig B

The signal can be referenced

C inside the entity

B <= Int_sig;
The signal is generated
C <= B;
inside the entity

Problem: the output signal in the mode BUFFER cannot be connected to a port in the mode
OUT in the higher hierarchical level
 VHDL basics
Port mode BUFFER (cont)
Superior entity
Entity
Signal of the port Signal of the port
in mode BUFFER in mode OUT

B D

C
D <= B;

Solution: see the next slide

 VHDL basics
Port mode OUT with an internal signal
Entity

Additional internal signal

Signal of the port in

Int B mode OUT
Int_sig

The signal Int can be referenced

C inside the entity

Int <= Int_sig;

The signal is generated
Inside the entity B <= Int;
C <= Int;
 VHDL basics
Port mode INOUT (bi-directional)
Signal of the port Entity

The signal can be referenced

The signal can be generated inside the entity
inside or outside of the entity
 VHDL basics
Port modes - summary
Modes of the ports specify the direction of the data
transfer (when looking from the component side
• IN: input port – data coming to this port can be read inside the
component, the name of the port can be situated only on the right
side of the assignment expression
• OUT: output port – output data can only be updated (and not read)
inside the component, the name of the port can be situated only on
the left side of the assignment expression
• INOUT: input/output port – data can be updated and read inside
the component, the name of the port can be situated on the left or
on the right side of the assignment expression
• BUFFER: output port – output data can be read inside the
component, the name of the port can be situated on the left or on
the right side of the assignment expression
 VHDL basics
Data Types
Pre-defined types (library STD)
scalar types sim syn composite types (arrays) sim syn
character (enum) ✓ ✓ string ✓ ✓
bit (enum) ✓ ✓ bit_vector ✓ ✓
boolean (enum) ✓ ✓
real (float) ✓
integer (integer) ✓ ✓

Types defined in the IEEE library

scalar types sim syn composite types (arrays) sim syn
std_logic (signals) ✓ ✓ std_logic_vector (signal vectors) ✓ ✓
 VHDL basics
Type STD_LOGIC (multi-value, multi-source signals)
Value Meaning Simul. Synth.

‘U’ Unknown – non initialized ✓

‘X’ Forcing unknown – unknown level, strong forcing ✓

‘0’ Forcing 0 – level 0, strong forcing ✓ ✓

‘1’ Forcing 1 – level 1, strong forcing ✓ ✓

‘Z’ High Impedance – high impedance ✓ ✓

‘W’ Weak Unknown – unknown level, weak forcing ✓

‘L’ Weak 0 – level 0, weak forcing ✓

‘H’ Weak 1 – level 1, weak forcing ✓

‘-’ Don't Care – any level ✓ ✓

 VHDL basics
Meaning of the STD_LOGIC levels
'U'
• Default signal value at the beginning of the simulation
• Value of signals, which are not generated (updated) during the
simulation

'X'

'1' Logic contention

'X'
on the bus!
'0'
 VHDL basics
Meaning of the STD_LOGIC levels (cont.)
Conflict resolving – tri-state logic - maximum one signal can be in
a low impedance state, others has to be in high impedance

Bus A B Bus Comment

A Z Z Z Without conflict
'Z' Z 1 1 Without conflict
'1'
Z 0 0 Without conflict
1 Z 1 Without conflict
'0' 0 Z 0 Without conflict
1 1 1 Weak (electr.) conflict
B '0'
'0' 0 0 0 Weak (electr.) conflict
0 1 X Conflict on the bus!
1 0 X Conflict on the bus!
 VHDL basics
Meaning of the STD_LOGIC levels (cont.))
Other STD_LOGIC levels: 1', '0', 'H', 'L', 'W', 'Z'

VDD
VDD

'1' 'H'
'W' 'Z'

(not connected)
'0' 'L'
 VHDL basics
Meaning of the STD_LOGIC levels

‘-’
• Any level
• Can be assigned to the output if the corresponding signal does not
depend on input signals (synthesis results can be significantly
improved, logic area can be reduced)
 VHDL basics
Signals and constants
Signal – simple wire interconnection
Two signal types
• std_logic
• std_logic_vector
Internal signals declaration examples:
SIGNAL dff, reset : std_logic;
SIGNAL internal_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL zero, carry_out : std_logic;

List of signals separated by a comma Signal types

Constant – associates a fixed value to a signal

Assignment of a value: operator :=
Constant declaration examples :
CONSTANT Aero: std_logic_vector(1 DOWNTO 0):= "00";
 VHDL basics
Operators
• Simple signal assignment <=
- signal <= expression (with signals);
For the case of vactor that could be :
- binary, example : Vector <= "1001"
- HEXA, example : Vector <= X"9"
- OCTAL, example : Vector <= O"11"
• Logical operators
• AND, OR, NAND, NOR, XOR, NOT
• Arithmetic operators
• + - * /
• Relational operators
• = < <= > >=
• Concatenation of two vectors &
• "Aero" & "Auto" => "AeroAuto"
 VHDL basics
Priority of operators
not
= /= < <= > >=
and or nand nor xor xnor

❑ Arithmetic operators have higher precedence than relational operators.

❑ Relational operators have higher precedence than logical operators.

– example:
Intended function:
Example : A * B + C < D or E > F
Results -- Evaluation order:
-- 1. A * B (Multiplication)
-- 2. C (Addition with Result of 1)
-- 3. (Result of 2) < D (Relational)
-- 4. E (Relational with F)
-- 5. (Result of 3) or (Result of 4)
 VHDL basics
VHDL design models

VHDL design models

data flow structural behavioral

Concurrent Components and Sequential

statements interconnections statements
• Registers
• State machines
Most appropriate • Testbenches
for the synthesis
 VHDL basics
Example : XOR3

U1
a U2

b result
c

ENTITY xor3 IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
result : OUT STD_LOGIC
);
END xor3;
 VHDL basics
Dataflow architecture
U1
a u1_out U2

b result
c

Architecture name Entity name

ARCHITECTURE xor3_dataflow OF xor3 IS

SIGNAL u1_out: STD_LOGIC; Internal signal
BEGIN declaration
u1_out <= a XOR b;
result <= u1_out XOR c;
END xor3_dataflow;
 VHDL basics
Dataflow architecture (cont.)

• Dataflow model describes relations between

data inside the module.
• It uses concurrent statements to realize the
logic. Statements are evaluated
simultaneously (in parallel), their order is
therefore not important!
• It is the most useful, if the logic can be
represented using Boolean statements
(combinatorial logic).
 VHDL basics
Data flow architecture (Application) LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SystemX IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
d : OUT STD_LOGIC
);
END SystemX;

ARCHITECTURE data_flow OF SystemX IS

BEGIN
F= ((a.b + c’).a)’ d <= ( NOT(c) OR (a AND b)) NAND a;
END data_flow;
 VHDL basics
Structural model of the architecture
ARCHITECTURE xor3_struct OF xor3 IS Internal signal declaration
SIGNAL u1_out: STD_LOGIC;
Component declaration
COMPONENT xor2
PORT(
i1 : IN STD_LOGIC; Component
i2 : IN STD_LOGIC; instantiation
y : OUT STD_LOGIC i1
); y
END COMPONENT; i2
BEGIN XOR2
u1: xor2 PORT MAP (i1 => a,
i2 => b,
y => u1_out);
a u1_out
result
u2: xor2 PORT MAP (i1 => u1_out,
i2 => C, c
Y => result);
b
u1 u2
END xor3_struct;
XOR3
 VHDL basics
Structural model of the architecture (cont.)

• It is easy to understand. It is close to schematics design: it uses

simple blocks to create higher-level logic functions
• Components can be interconnected in a hierarchical manner
• In the structural model we can connect simple logic ports or
complex (and abstract) components
• The structural model of the architecture is useful if the blocks
can be interconnected in a natural way
 VHDL basics
Component declaration and instantiation
Assignment of interconnections by their Assignment of connections by their
names - recommended positions - not recommended!

COMPONENT xor2 IS COMPONENT xor2 IS

PORT( PORT(
i1 : IN STD_LOGIC; Component declaration i1 : IN STD_LOGIC;
i2 : IN STD_LOGIC; (in the "declarations" i2 : IN STD_LOGIC;
y : OUT STD_LOGIC part of the architecture) y : OUT STD_LOGIC
); );
END COMPONENT; END COMPONENT;
Connection indicator

u1: xor2 PORT MAP (i1 => a, u1: xor2 PORT MAP (a, b, u1_out);
Component instantiation
i2 => b,
(in the architecture body)
y => u1_out);

Instantiation name Component name

 VHDL basics
Structural model of architecture (Application)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY AND_S IS ENTITY OR_S IS ENTITY NAND_S IS

PORT( PORT( PORT(
x1 : IN STD_LOGIC; i1 : IN STD_LOGIC; e1 : IN STD_LOGIC;
x2 : IN STD_LOGIC; i2 : IN STD_LOGIC; e2 : IN STD_LOGIC;
y : OUT STD_LOGIC O : OUT STD_LOGIC s : OUT STD_LOGIC
); ); );
END AND_S; END OR_S; END NAND_S;
ARCHITECTURE Struc1 OF AND_S IS ARCHITECTURE Struc2 OF OR_S IS ARCHITECTURE Struc3 OF NAND_S IS
BEGIN BEGIN BEGIN
y <= x1 AND x2; O <= NOT(i1) OR i2; s <= e1 NAND e2);
END Struc1; END Struc2; END Struc3;
 VHDL basics
Structural model of the architecture (App cont.)
LIBRARY ieee; COMPONENT OR_S IS
USE ieee.std_logic_1164.ALL; PORT(
ENTITY SystemX IS i1 : IN STD_LOGIC;
PORT( i2 : IN STD_LOGIC;
a : IN STD_LOGIC; O : OUT STD_LOGIC
b : IN STD_LOGIC; );
c : IN STD_LOGIC; END COMPONENT;
COMPONENT NAND_S IS
d : OUT STD_LOGIC PORT(
); e1 : IN STD_LOGIC;
END SystemX; e2 : IN STD_LOGIC;
ARCHITECTURE System_struct OF SystemX IS s : OUT STD_LOGIC
SIGNAL int_S1,int_S2 : STD_LOGIC; );
END COMPONENT;
COMPONENT AND_S IS BEGIN
PORT( u1: AND_S PORT MAP (x1 => a,x2 => b, y => int_S1);
x1 : IN STD_LOGIC; u2: OR_S PORT MAP (i1 => c,i2 => int_S1,
x2 : IN STD_LOGIC; O => int_S2);
y : OUT STD_LOGIC u3: NAND_S PORT MAP (e1 => a,e2 => int_S2, s => d);
);
END COMPONENT; END System_struct;
 VHDL basics
Behavioral model of the architecture
ARCHITECTURE xor3_behav OF xor3 IS
BEGIN
xor3_proc: PROCESS (a, b, c)
BEGIN
IF ((a XOR b XOR c) = '1') THEN
result <= '1';
ELSE
result <= '0';
END IF;
END PROCESS xor3_proc;
END xor3_behav;

Behavioral model describes what happens at the output of

the module (depending on input) without specification of
the internal structure of the block (black-box approach)
It uses a VHDL structure called Process
It is not recommended for combinatorial structures
 VHDL basics
Testbench

The Testbench applies the stimuli to the input of the

component (Device Under Test – DUT) and (eventually) verifies
the simulation results
The results can be observed in the simulator waveform
window or they can be written to a file
Since the Testbench is written in VHDL, it is not restricted to
the use of a specific simulation tool (portability notion)
The same Testbench can be easily adapted to test different
implementations (e. g. different architectures) of the same
project
 VHDL basics
Testbench (cont.)
Verification flow in the Testbench
Testbench -
Testbench - User interface management
Device management
Print simulation output
- Device instantiation values to the terminal
- Stimuli generation
Print simulation output
waveforms to the simulator
DUT window
(Design under test)

Simulation verification
(comparison with expected
values specified in a file)
 VHDL basics
Testbench – example
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; Testbench does not
ENTITY tb_xor3 IS have ports!
END tb_xor3;
ARCHITECTURE structure OF tb_xor3 IS
COMPONENT xor3
PORT(
a: IN std_logic;
b: IN std_logic;
c: IN std_logic; DUT declaration
d: OUT std_logic
);
END COMPONENT;
SIGNAL x1, x2, x3 : std_logic; Declaration of
SIGNAL y : std_logic; internal signals
BEGIN
u_xor3: xor3
port map (
a => x1, DUT instantiation
b => x2,
c => x3,
d => y
); see next page … 1
 VHDL basics
Testbench – example (cont.)
stimuli: PROCESS Stimuli generation
BEGIN
x1 <= '0';
x2 <= '0';
x3 <= '0';
WAIT FOR 10 ns;
x1 <= '1';
x2 <= '0';
x3 <= '0';
WAIT FOR 10 ns;
x1 <= '0';
x2 <= '1';
x3 <= '0';
WAIT FOR 10 ns;
x1 <= '1';
x2 <= '1';
x3 <= '0';
WAIT FOR 10 ns;
x1 <= '0';
x2 <= '0';
x3 <= '1';
WAIT FOR 10 ns;

WAIT FOR 30 ns;

END PROCESS stimuli;
END structure; 2
 VHDL basics
Testbench – example (cont)
 Concurrent structures
Concurrent instructions (cont.)
▪ Concurrent instructions ▪ Component instantiation
• Unconditional signal assignment ▪ Multiple assignments
• signal <= expression (using signals); • label: FOR loop_variable IN interval GENERATE
• Conditional signal assignment {concurrent instruction(s)}
• signal <= expression1 WHEN condition ELSE END GENERATE label;
expression2 WHEN condition ELSE
expression3;
• Selective signal assignment
• WITH selector SELECT
signal <= expression1 WHEN selector_value1,
expression1 WHEN selector_value2 ,
------
expression by default WHEN OTHERS ;
 Concurrent structures
Concurrent instructions (cont.)
Conditional assignment
target_signal <= value1 WHEN condition1 ELSE
value2 WHEN condition2 ELSE
. . .
valueN-1 WHEN conditionN-1 ELSE
valueN;

valueN ... target_signal

valueN-1

value2
value1
conditionN-1
condition2
condition1

Conclusion : caution – priority encoding!

 Concurrent structures
Concurrent instructions (cont.)
-- conditional assignment
y <= a WHEN sel1 = '1' ELSE
b WHEN sel2 = '1‘ ELSE
Obtained logic c;
sel1
sel2
a
Selection of signal a by
b y the signal sel1 has
priority before b and c!
c

q = (sel1 AND a)
OR ((NOT sel1) AND sel2 AND b)
OR ((NOT sel1) AND (NOT sel2) AND c)
 Concurrent structures
Concurrent instructions (cont.)
Selective assignment
WITH selector SELECT
target_signal <= value1 WHEN selector_value,
value2 WHEN selector_ value,
...
valueN WHEN OTHERS;

Application example: multiplexer

value1
target_signal
value2
value3 MUX
value4

selector
 Concurrent structures
Concurrent instructions (cont.)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; If we change a,b,c and d by a: IN
ENTITY multiplexer IS std_logic vector(3 DOWNTO 0);
PORT (a, b, c, d : IN std_logic;
sel : IN std_logic_vector(1 DOWNTO 0);
y : OUT std_logic);
END multiplexer;
ARCHITECTURE rtl OF multiplexer IS a(0) WHEN "00",
BEGIN a(1) WHEN "01",
-- selective assignment a(2) WHEN "10",
WITH sel SELECT a(3) WHEN OTHERS;
y <= a WHEN "00",
b WHEN "01", Selection without priority!
c WHEN "10",
d WHEN OTHERS;
END rtl; Address of vector

y = (a AND (NOT sel(1)) AND (NOT sel(0)))

OR (b AND (NOT sel(1)) AND sel(0))
OR (c AND sel(1) AND (NOT sel(0)))
OR (d AND sel(1) AND sel(0))
 Concurrent structures
Concurrent instructions (application : decoder)

LIBRARY ieee; WITH (ABC) SELECT

F <= "00000001" WHEN "000",
USE ieee.std_logic_1164.ALL;
"00000010" WHEN "001",
ENTITY decoder IS "00000100" WHEN "010",
PORT( ABC :IN STD_LOGIC_VECTOR(2 DOWNTO 0); "00001000" WHEN "011",
F : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); "00010000" WHEN "100",
END decoder; "00100000" WHEN "101",
ARCHITECTURE decoder_arch OF decoder IS "01000000" WHEN "110",
BEGIN "10000000" WHEN "111";
END decoder_arch;
 Concurrent structures
Concurrent instructions (cont.)
Structure GENERATE for concurrent instructions
label: FOR loop_variable IN interval GENERATE
[declarations]
BEGIN Optional
{concurrent assignment(s)}
END GENERATE label;

Application example: parity generator

par_in(0)

par_in(1) par_out
par_in(2)
par_in(3)
par_in(4)
par_in(5)
par_in(6)
par_in(7)
 Concurrent structures
Concurrent instructions (cont.)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY parity IS
PORT (par_in : IN std_logic_vector(7 DOWNTO 0);
y : OUT std_logic);
END parity;
ARCHITECTURE rtl OF parity IS
SIGNAL par_int : std_logic_vector(7 DOWNTO 0);
BEGIN We can use the signal par_int(7)
par_int(0) <= par_in(0); before a value is assigned to it
y <= par_int(7);
Calc_parity: (concurrent structure)
FOR i IN 1 TO 7 GENERATE
par_int(i) <= par_in(i) XOR par_int(i-1);
END GENERATE Calc_parity;
END rtl;

y = par_in(0) XOR par_in(1) XOR par_in(2) XOR par_in(3)

XOR par_in(4) XOR par_in(5) XOR par_in(6) XOR par_in(7)
 Concurrent structures
Applications of concurrent structures
Implementation of combinatorial logic functions (CLF)

Combinatorial functional blocks

Application examples:
• Simple combinatorial structures
• Multiplexers
• Parity generators
• Coders/decoders
• Comparators, arithmetic and logic unit
• …
 sequential structures
Basic sequential structures
Used only inside the PROCESS, FUNCTION and PROCEDURE!
Four basic structures:
Rules of Variables:
• Unconditional assignment of a signal or variable
signal <= expression (with signals); • Variables can only be used inside processes

variable := expression (with variables); • Any variable that is created in one process cannot be
used in another process
• Conditional structure
• Variables need to be defined after the
IFcondition THEN keyword process but before the keyword begin
{sequential instruction(s)} • Variables that are assigned immediately take the value
[ELSIF condition THEN of the assignment
{sequential instruction(s)}]
Optional
[ELSE parts
{sequential instruction(s)}]
...
END IF;
 sequential structures
Basic sequential structures (cont.)
• Selective structure ‘‘WHEN value’’ can take up three forms:
CASE selector IS WHEN value -- single value
WHEN value1 to value2 -- range, for enumerated data types -- only
WHEN selector_value1 =>
WHEN value1 | value2 |... -- value1 or value2 or ...
{sequential instruction(s)}
WHEN selector_value2 =>
{sequential instruction(s)} ✓ keyword NULL (the counterpart of UNAFFECTED), can
be used when no action is to take place. Example:
WHEN selector_value3 =>
WHEN OTHERS => NULL;
{sequential instruction(s)}
...
❑ Example:
[WHEN OTHERS =>
{sequential instruction(s)}]
CASE control IS
WHEN "00" => x<=a; y<=b;
END CASE; WHEN "01" | “10" => x<=b; y<=c;
Optional, but WHEN OTHERS => NULL;
recommended part END CASE;
 sequential structures
Basic sequential structures (cont.)

• Loop structures • 1- Simple loop (infinite)

• Three basic types Syntax:
1- Simple loops (without iteration scheme) [label:] LOOP
2- FOR loops {sequential instruction(s)}
3- WHILE loops END LOOP [label] ;
• Used mostly in testbenches Optional

• Exit from the loop by

EXIT [WHEN condition] ; exit from the loop
NEXT [WHEN condition] ; jump to the next iteration
 sequential structures
Basic sequential structures (cont.)
• Conditional EXIT • Conditional NEXT
Student : LOOP Student : LOOP
EXIT Student WHEN value = 10 ; Statements following the NEXT - Count := Count+1;
Count := Count+1; statement are ignored if value = 3. NEXT Student WHEN value = 3 ;
value := Count; value := Count;
END LOOP Student ; END LOOP Student ;

• Unconditional EXIT • Unconditional NEXT

Loops are left with the EXIT -
LOOP statement if value = 10 LOOP
IF value = 10 THEN Count := Count+1;
EXIT; IF value = 3 THEN
END IF ; NEXT;
Count := Count+1; END IF ;
value := Count; value := Count;
END LOOP ; END LOOP ;
;

sequential structures
Basic sequential structures (cont.)
• Loop FOR ❑ Example of Loop FOR:
[label :] FOR loop_variable IN interval LOOP lbl : FOR i IN 0 TO 5 LOOP
{sequential instruction(s)} var := var + 5 ;
END LOOP [label] ; END LOOP lbl ;
Optional

• Loop variable does not need to be declared!

❑ Example of Loop WHILE:

• Loop WHILE
[label :] WHILE condition LOOP WHILE value < 10 LOOP
{sequential instruction(s)} Value := Value + 1;
END LOOP [label] ; END LOOP ;
Optional

• Loops while the condition is true.

 sequential structures
Basic sequential structures (cont.)
Series of VHDL instructions with a sequential behavior
Instruction order - important!
Three phases of the PROCESS:
• Standby, Activation, Execution
Syntax:
[label:] PROCESS [(sensitivity list)]
[declarative part ] Optional

BEGIN
{sequential instruction(s)}
END PROCESS [label ];

Optional
 sequential structures
Two PROCESS interpretations
• Compiler infers a combinatorial structure
– Sensitive to all signals used in the
combinatorial logic a
Example
c
b
PROCESS(a, b, sel)

sensitivity list contains all signals

sel
referenced in the process

• Compiler infers a sequential structure D Q q

d
– Sensitive to the clock signal and to
asynchr. control signals (reset, preset) clk
Example ENA
PROCESS(clr, clk) CLRN

clr
sensitivity list does not contain input D,
only clock and asynchronous control signals
 sequential structures
Implementation of several PROCESSes
An architecture can contain several PROCESSes
They are executed in parallel, because they are situated in the
concurrent part of the architecture
Inside the PROCESS, the instructions are executed
sequentially, the PROCESS is a sequential structure
Reduction of the number of processes increases readability

Architecture
Process 1
Concurrent . Order is not
Signals . important
structures .
Process 2
 sequential structures
Two structures that give the same result after the synthesis, but not in the functional simulation
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_1164.all;
ENTITY simp IS ENTITY simp_prc IS
PORT(a, b : IN std_logic; PORT(a,b : IN std_logic;
x : OUT std_logic); x : OUT std_logic);
END simp; END simp_prc;
ARCHITECTURE exam OF simp IS ARCHITECTURE exam OF simp_prc IS
SIGNAL c : std_logic; SIGNAL c : STD_LOGIC;
BEGIN BEGIN
c <= a AND b; A PROCESS(a, b)
B
x <= c; BEGIN
END exam; simulation before and c <= a and b;
after the synthesis of A x <= c;
END PROCESS;
a END exam; functional
b
c simulation of B
x
a
b
post-synthesis simulation of B c
x
 sequential structures
Basic sequential structures (cont.)

Conclusions :

• Do not use PROCESS to implement combinatorial logic, if not, caution!

• Signal values are updated at the end of a process execution: the old
current value of a signal is overwritten by the future value
• Use the PROCESS to implement sequential logic (containing storage
elements)
• Latches
• Registers
• State machines
• Use the PROCESS freely to realize testbenches
 sequential structures
Basic sequential structures (cont.)
Sequential logic function - definition
• The next output value of the function depends on the current
inputs AND on the current state – this needs implicitely the use
of a memory element

Two main types

• Asynchronous logic – state can change any time
• Synchronous logic – state can change only in pre-defined time
intervals – rising or falling edge of clock signals

Basis sequential functions

• Asynchronous flip-flops – RS, D latch
• Synchronous flip-flops - D, T, RS, JK
• Synchronous and asynchronous counters
• Registers and shift registers
• State machines
Basic sequential blocks
D Latch
D
Q
Ena
_ Truth table
Q
Ena D Q+ nQ+
0 0 -Q -nQ

Ena 0 1 -Q -nQ

D 1 0 0 1
1 1 1 0
Q

Locked Transpar. Locked Transpar.

 Basic sequential blocks
D latch using a behavioral description – VERY easy to read
and understand its behavior
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY d_latch IS
PORT ( d : IN std_logic;
ena : IN std_logic;
q : OUT std_logic
);
END d_latch;
ARCHITECTURE behavior OF d_latch IS
BEGIN
PROCESS (ena, d) Sensitivity list contains both
BEGIN inputs
IF ena = '1' THEN
q <= d;
END IF; If ena = '0'? => Implicit memory!
END PROCESS;
END behavior;
 Basic sequential blocks
Synchronous D flip-flop – the value present at the D input
during the rising (or falling) edge of the clock signal is
stored in the flip-flop until the next rising (or falling)

D Q
Truth table
clk _
Q
clk D Q+ nQ+
0 x -Q -nQ
Sensitivity on the rising edge
1 x -Q -nQ

clk  x -Q -nQ

 0 0 1
D
 1 1 0

Q
 Basic sequential blocks
Synchronous D flip-flop (cont.) ---- Solution 2: OK -------------------
2 LIBRARY ieee;
---- Solution 1: doesn’t Work-------- 3 USE ieee.std_logic_1164.all;
2 LIBRARY ieee; 4 ---------------------------------------
3 USE ieee.std_logic_1164.all; 5 ENTITY dff IS
4 --------------------------------------- 6 PORT ( d, clk: IN STD_LOGIC;
5 ENTITY dff IS 7 q: BUFFER STD_LOGIC;
6 PORT ( d, clk: IN STD_LOGIC; 8 qbar: OUT STD_LOGIC);
7 q: BUFFER STD_LOGIC; LINE 19
9 END dff;
8 qbar: OUT STD_LOGIC); I’m describing a 10 ---------------------------------------
9 END dff; 11 ARCHITECTURE ok OF dff IS
10 ---------------------------------------
logic operation =>
write it outside of 12 BEGIN
11 ARCHITECTURE not_ok OF dff IS 13 PROCESS (clk)
12 BEGIN PROCESS!!!
14 BEGIN
13 PROCESS (clk) 15 IF (clk'EVENT AND clk='1') THEN
14 BEGIN 16 q <= d;
15 IF (clk'EVENT AND clk='1') THEN 17 END IF;
16 q <= d; LINE 17
18 END PROCESS;
17 qbar <= NOT q; q will be updated at the end of 19 qbar <= NOT q;
18 END IF; 20 END ok;
the process execution
19 END PROCESS; 21 ---------------------------------------
20 END not_ok; 70
 Basic sequential blocks
Synchronous D flip-flop (cont.) ---- Solution 3: OK NOT RECOMENDED---------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ---------------------------------------
5 ENTITY dff IS
6 PORT ( d, clk: IN STD_LOGIC;
7 q: OUT STD_LOGIC;
8 qbar: OUT STD_LOGIC);
9 END dff;
10 ---------------------------------------
11 ARCHITECTURE ok OF dff IS
12 BEGIN
13 PROCESS (clk)
14 BEGIN
15 IF (clk'EVENT AND clk='1') THEN
16 q <= d;
17 qbar <= NOT d;
18 END IF;
19 END PROCESS;
20 END ok;
21 ---------------------------------------
 Basic sequential blocks
Testbench of Synchronous D flip-flop (cont.) process
begin
library ieee; T_clk <= '0';
use ieee.std_logic_1164.all; wait for clk_period/2;
entity Dflipflop_test is T_clk <= '1';
end Dflipflop_test; wait for clk_period/2;
------------------------------------------ end process;
architecture testbench of Dflipflop_test is process
begin
component dff --case1
port (d, clk: IN STD_LOGIC; T_d <= '0';
q: BUFFER STD_LOGIC; wait for clk_period*2;
qbar: OUT STD_LOGIC); --case2
end component; T_d <= '1';
wait for clk_period*1.5;
signal T_d: std_logic; --case3
signal T_clk: std_logic; T_d <= '0';
signal T_q: std_logic; wait for clk_period*0.5;
signal T_qbar : std_logic; --case4
T_d <= '1';
constant clk_period : time := 50 ns; wait for clk_period*2;
begin end process;
uut: dff port map (T_d,T_clk,T_q,T_qbar); end testbench;
 Basic sequential blocks
JK synchronous flip-flop – behaviour similar to that of the RS
flip-flop (J input works as S and K input as R), except for the
case when J and K were equal to one, in this case the output
is inverted
J Q
Truth table
clk _ clk J K Q+ nQ+ Next state
Q -Q
K 0 x x -nQ Previous state

1 x x -Q -nQ Previous state

sensitivity on the rising edge
 x x -Q -nQ Previous state

 0 0 -Q -nQ Previous state

sensitivity on the falling edge
 1 0 1 0 Set

 0 1 0 1 Reset

 1 1 -nQ -Q Inversion
Basic sequential blocks
Synchronous JK flip-flop - behavioral description
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY jk_ff IS
PORT ( j, k, clk : IN std_logic;
q : OUT std_logic
);
END jk_ff;
ARCHITECTURE behavior OF jk_ff IS
SIGNAL sel : std_logic_vector(1 DOWNTO 0);
SIGNAL q_int : std_logic;
BEGIN
sel <= j & k;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN set
CASE sel IS
WHEN "10" => q_int <= '1'; reset
WHEN "01" => q_int <= '0';
WHEN "11" => q_int <= NOT q_int; inversion
WHEN OTHERS => q_int <= q_int;
END CASE; storing
END IF;
END PROCESS;
q <= q_int;
END behavior;
 Basic sequential blocks
Up/down counter using a signal
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL; updn q
USE ieee.numeric_std.ALL;
ENTITY count_a IS clk
PORT (clk, rst, updn : IN std_logic;
q : OUT std_logic_vector(15 DOWNTO 0)); rst
END count_a; CMPT
ARCHITECTURE logic OF count_a IS
SIGNAL int_q : std_logic_vector(15 DOWNTO 0);
BEGIN
PROCESS(rst, clk) Internal signal declaration
BEGIN (an output signal cannot be
IF rst = '0' THEN
int_q <= (OTHERS => '0'); referenced in the right-side
ELSIF rising_edge(clk) THEN expression)
IF updn = '1' THEN
int_q <= int_q + 1;
ELSE
int_q <= int_q - 1; The signal value is stored until the
END IF; next rising edge of the clock signal
END IF;
END PROCESS;
q <= int_q;
END logic; Output signal assignment
 Basic sequential blocks
Up/down counter using a variable
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL; updn q
USE ieee.numeric_std.ALL;
ENTITY count_a IS clk
PORT (clk, rst, updn : IN std_logic;
q : OUT std_logic_vector(7 DOWNTO 0));
END count_a; rst
CMPT
ARCHITECTURE logic OF count_a IS
BEGIN
PROCESS(rst, clk)
VARIABLE tmp_q : std_logic_vector(7 DOWNTO 0);
BEGIN
IF rst = '0' THEN
q <= (OTHERS => '0'); Arithmetic expressions
ELSIF rising_edge(clk) THEN assigned to a variable
IF updn = '1' THEN
tmp_q := tmp_q + 1;
ELSE
tmp_q := tmp_q - 1;
END IF;
q <= tmp_q; Output signal assignment
END IF;
END PROCESS;
END logic;
 Basic sequential blocks
Concurrent and sequential structures - summary
Concurrent Sequential
structures structures
Unconditional assignment Unconditional assignment
… <= … … <= …
Conditional assignment Conditional structure
… <= … WHEN … ELSE … IF … THEN … ELSE … END IF
Selective assignment Selective structure
WITH … SELECT CASE … IS
… <= … WHEN … WHEN … => …
END CASE
Structures GENERATE Structures LOOP
FOR … GENERATE … FOR … LOOP …
END GENERATE END LOOP
 Finite State machine structure
Two types of finite state machines (FSM) : Mealy and moore

Mealy Outputs z = f(x,y)

Next State Y = f(x,y)

Moore Outputs z = f(y)

 Basic sequential blocks
State’s diagram of Moore and Mealy machine

State diagram of Moore machine

State diagram of Mealy machine