A B C D E

1 1

Compal confidential 2

Schematics Document
AMD K8 with
3

ATI RS480M+ATI SB400 3

2005-08-29
REV:0.8

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 1 of 53
A B C D E
 A B C D E

Compal confidential
File Name : LA-2771

Memory BUS(DDR)
DDR-SO-DIMM-0
1 Thermal Sensor Mobile BANK 0, 1, 2, 3 page 8,10
1

ADM1032
page 4
AMD Athlon 64 2. 5V DDR- 400

754 pin DDR-SO-DIMM-1

page 4, 5, 6, 7 BANK 0, 1, 2, 3 page 9,10
Clock Generator
Fan Control ICS 951412
page 4 2. 5V DDR- 400

HT 16x16 1000MHZ page 16

1 x PCIE
New Card
LVDS Panel ATI-RS480M Connector
page 27
Interface page 17
705 BGA
2 CRT & TV OUT page 11, 12, 13, 14 TV tuner 2

page 34
page 18 A-Link Express
2 x PCIE
USB conn X3
USB2.0 page 34
Side Port(VRAM)
16M x 16 page 15 BT Conn
ATI-SB400 AC-LINK
page 34
ATA-100
Primary IDE
3.3V 33 MHz PCI BUS 564 BGA Audio CKT MODEM
page 19, 20, 21, 22 AMOM page 31 AMOM page 32

LAN CardBus Controller PATA HDD AMP & Audio Jack

MINI PCI RTL 8100CL TI PCI7411/PCI1510 Connector page 33
LPC BUS page 24
page 30 page 29 page 25,26,27
3 3

CDROM
RTC CKT. Connector
page 19 RJ45 CONN Slot 0 1394 Card reader page 24
page 29 page 27 page 25 page 26
ENE KB910/L
page 37, 38

Power OK CKT. SPR CONN.

page 42 *RJ45 CONN
Touch Pad Int.KBD *MIC IN JACK
page 35 page 35
*LINE OUT JACK
*1394 CONN
Power On/Off CKT. BIOS *SPDIF CONN
page 35 page 39 *DC JACK
*TVOUT CONN
*USB CONN x1
*CIR x1
4
DC/DC Interface CKT. 4
page 40
page 41

Power Circuit DC/DC Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
page 43~49 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 2 of 53
A B C D E
 A

Voltage Rails BOM STATUS :

+5VS VRAM@ ,VRAMIC@, SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,17_EXP@

+3VS ,15_EXO@,CIR@ ,D@, C@, 15.4@, DOCK@, WL_LED@
power
plane +2.5VS
+12VALW +5V
+1.8VS
+5VALW +2.5V
+1.5VS
+3VALW +1.25V
+2.5VDDA 45@ ( for 45 level RTC battery )
State +1.8VALW
+CPU_CORE
+1.2V_HT
HAL10 17" VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,17_EXP@ ,CIR@
S0 O O O ,D@ ,DOCK@,WL_LED@

S1
O O O HAL20 FF 15.4" VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,15_EXP@ ,CIR@
S3 ,C@ ,DOCK@,WL_LED@, 15.4@(LED)
O O X
S5 S4/AC
O X X HAL20 DF 15.4" EXP@, C@ ,DOCK@ ,15.4@(LED), CIR@, WLAN@, 15_EXP@
S5 S4/AC don't exist
X X X
O MEANS ON
X MEANS OFF

PCI Devices
1 1

INTERNAL
DEVICE IDSEL # REQ/GNT # PIRQ
SM BUS
IDE A
LPC I/F
PCI to PCI
AC97 AUDIO B
A C97 MODEM B
OHCI#1 USB D
OHCI#1 USB D
EHCI USB D
SAT A#1 A
SAT A#2 A

EXTERNAL
Wire less LAN AD18 3 F

LAN AD22 1 G

CARD BUS & 1394 AD20 2 E ,H

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 3 of 53
A
 A B C D E

ZZZ1

L A -2771 REV 0

H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADOP[0..15] <11>
H_CADIN[0..15] H_CADON[0..15]
<11> H_CADIN[0..15] H_CADON[0..15] <11>
Fan Control Circuit
4 JP1A 4

+5VS
Claw Hammer-DTR
H_CADIP15 T25 N26 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15 B+
R25 N27 1 2
H_CADIP14 L0_CADIN_L15 L0_CADOUT_L15 H_CADOP14
U27 L25
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14 C2 C1
U26 M25
H_CADIP13 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP13 0.1U_0402_16V4Z 10U_1206_16V4Z
V25 L26
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 +3VS
U25 L27 2 1
L0_CADIN_L13 L0_CADOUT_L13

1
2
5
6
H_CADIP12 W27 J25 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12 D
W26 K25

P
L0_CADIN_L12 L0_CADOUT_L12

2
HTT Interface
H_CADIP11 AA27 G25 H_CADOP11 3 G Q1
L0_CADIN_H11 L0_CADOUT_H11 <37,38> EN_FAN1 +IN
H_CADIN11 AA26 H25 H_CADON11 1 FAN1_ON 3 SI3456DV-T1_TSOP6 R1
H_CADIP10 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP10 OUT S
AB25 L0_CADIN_H10 L0_CADOUT_H10 G26 2 -IN 10K_0402_5%
H_CADIN10 AA25 G27 H_CADON10 U1A

4
L0_CADIN_L10 L0_CADOUT_L10

G
H_CADIP9 AC27 E25 H_CADOP9 LM358A_SO8

1
H _CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
AC26 F25

4
H_CADIP8 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP8
AD25 L0_CADIN_H8 L0_CADOUT_H8 E26
H _CADIN8 AC25 E27 H_CADON8 JP2
H_CADIP7 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP7 FAN1
T27 L0_CADIN_H7 L0_CADOUT_H7 N29 1 2 1
H _CADIN7 T28 P29 H_CADON7 R2
L0_CADIN_L7 L0_CADOUT_L7 2

1000P_0402_50V7K

C4 10U_0805_10V4Z
H_CADIP6 V29 M28 H_CADOP6 100K_0402_5%
L0_CADIN_H6 L0_CADOUT_H6 3

1
H _CADIN6 U29 M27 H_CADON6 1 1
H_CADIP5 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP5 R3 ACES_85205-0300
V27 L0_CADIN_H5 L0_CADOUT_H5 L29
H _CADIN5 V28 M29 H_CADON5 150K_0402_5%
H_CADIP4 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP4 D1 @
Y29 L0_CADIN_H4 L0_CADOUT_H4 K28
H _CADIN4 W29 K27 H_CADON4 1N4148_SOT23 2 2

2
H_CADIP3 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP3
AB29 L0_CADIN_H3 L0_CADOUT_H3 H28

C3
H _CADIN3 AA29 H27 H_CADON3
H_CADIP2 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP2
AB27 G29

2
H _CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
AB28 L0_CADIN_L2 L0_CADOUT_L2 H29
3 H_CADIP1 H_CADOP1 3
AD29 L0_CADIN_H1 L0_CADOUT_H1 F28
H _CADIN1 AC29 F27 H_CADON1
H_CADIP0 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP0
AD27 L0_CADIN_H0 L0_CADOUT_H0 E29 <37,38> FAN_SPEED1
H _CADIN0 AD28 F29 H_CADON0 1
L0_CADIN_L0 L0_CADOUT_L0
@ C5
1000P_0402_50V7K
H_CLKIP1 Y25 J26 H_CLKOP1 2
<11> H_CLKIP1 H_CLKIN1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKON1 H_CLKOP1 <11>
<11> H_CLKIN1 W25 J27 H_CLKON1 <11>
H_CLKIP0 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKOP0
<11> H_CLKIP0 Y27 J29 H_CLKOP0 <11>
+1.2V_HT H_CLKIN0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKON0
<11> H_CLKIN0 Y28 K29 H_CLKON0 <11>
L0_CLKIN_L0 L0_CLKOUT_L0
R4 49.9_0402_1% 2 1 R27 N25
R5 49.9_0402_1% 2 L0_CTLIN_H1 L0_CTLOUT_H1
1 R26 P25
H_CTLIP0 L0_CTLIN_L1 L0_CTLOUT_L1 H_CTLOP0
<11> H_CTLIP0 T29 P28 H_CTLOP0 <11>
+1.2V_HT H_CTLIN0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLON0
<11> H_CTLIN0 R29 P27 H_CTLON0 <11>
L0_CTLIN_L0 L0_CTLOUT_L0
R6 44.2_0603_1% 2 1 LVREF1 AF27 AJ27 LDTSTOP#
L0_REF1 LDTSTOP_L LDTSTOP# <13,19>
R7 44.2_0603_1% 1 2 LVREF0 AE26
L0_REF0
1 2 +2.5VS
FOX_PZ75403-2941-42 R8
680_0402_5%

Thermal Sensor THERMDA_CPU

THERMDA_CPU <6>
ADM1032 THERMDC_CPU
THERMDC_CPU <6>
+3VS
2 W =1 5mil 2
U2 2
EC_SMC_2 8 1 C6
<37,38> EC_SMC_2 SCLK VDD
1
EC_SMD_2 7 2 THERMDA_CPU C7 0.1U_0402_16V4Z
<37,38> EC_SMD_2 SDATA D+ 1
6 3 THERMDC_CPU 2200P_0402_50V7K
ALERT# D- 2
5 4
GND THERM#

ADM1032AR_SOP8

1 1

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Claw Harmmer & Fan
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 4 of 53
A B C D E
 A B C D E

50 mil width/20 mil space

+1.25VREF_CPU
JP1B
+2.5V AG12 MEMVREF1
34.8_0603_1% 1 R10 MEMZN
34.8_0603_1%
2
2 1 R11 MEMZP
D14
C14
MEMZN Claw Hammer-DTR
1 MEMZP 1
<8> DDR_SDQ[0..63]
DDR_SDQ63 A16 AE8 DDR_CKE0
DDR_SDQ62 MEMDATA63 MEMCKEA DDR_CKE1 DDR_CKE0 <8>
B15 AE7 DDR_CKE1 <9>
DDR_SDQ61 MEMDATA62 MEMCKEB
A12
DDR_SDQ60 MEMDATA61 DDR_CLK7
B11 D10 DDR_CLK7 <8>
DDR_SDQ59 MEMDATA60 MEMCLK_H7 DDR_CLK7# DDR_CLK7 R12 120_0402_5% DDR_CLK7#
A17 C10 DDR_CLK7# <8> 1 2
DDR_SDQ58 MEMDATA59 MEMCLK_L7 DDR_CLK6
A15 E12 DDR_CLK6 <9>
DDR_SDQ57 MEMDATA58 MEMCLK_H6 DDR_CLK6# DDR_CLK6 R13 120_0402_5% DDR_CLK6#
C13 E11 DDR_CLK6# <9> 1 2
DDR_SDQ56 MEMDATA57 MEMCLK_L6 DDR_CLK5
A11 AF8 DDR_CLK5 <8>
DDR_SDQ55 MEMDATA56 MEMCLK_H5 DDR_CLK5# DDR_CLK5 R14 120_0402_5% DDR_CLK5#
A10 AG8 DDR_CLK5# <8> 1 2
DDR_SDQ54 MEMDATA55 MEMCLK_L5 DDR_CLK4
B9 AF10 DDR_CLK4 <9>
DDR_SDQ53 MEMDATA54 MEMCLK_H4 DDR_CLK4# DDR_CLK4 R15 120_0402_5% DDR_CLK4#
C7 MEMDATA53 MEMCLK_L4 AE10 DDR_CLK4# <9> 1 2
DDR_SDQ52 A6 V3
DDR_SDQ51 MEMDATA52 MEMCLK_H3
C11 MEMDATA51 MEMCLK_L3 V4
DDR_SDQ50 A9 K5
DDR_SDQ49 MEMDATA50 MEMCLK_H2
A5 MEMDATA49 MEMCLK_L2 K4
DDR_SDQ48 B5 R5
DDR_SDQ47 MEMDATA48 MEMCLK_H1
C5 MEMDATA47 MEMCLK_L1 P5
DDR_SDQ46 A4 P3
DDR_SDQ45 MEMDATA46 MEMCLK_H0
E2 MEMDATA45 MEMCLK_L0 P4
DDR_SDQ44 E1
DDR_SDQ43 MEMDATA44
A3 MEMDATA43 MEMCS_L7 D8
DDR_SDQ42 B3 C8
DDR_SDQ41 MEMDATA42 MEMCS_L6
E3 MEMDATA41 MEMCS_L5 E8
DDR_SDQ40 F1 E7
DDR_SDQ39 MEMDATA40 MEMCS_L4 DDR_SCS#3
G2 MEMDATA39 MEMCS_L3 D6 DDR_SCS#3 <9>
DDR_SDQ38 G1 E6 DDR_SCS#2
DDR_SDQ37 MEMDATA38 MEMCS_L2 DDR_SCS#1 DDR_SCS#2 <9>

DDR Memory
L3 MEMDATA37 MEMCS_L1 C4 DDR_SCS#1 <8>
DDR_SDQ36 L1 E5 DDR_SCS#0
MEMDATA36 MEMCS_L0 DDR_SCS#0 <8>
DDR_SDQ35 G3
DDR_SDQ34 MEMDATA35 DDR_SRASA#
J2 MEMDATA34 MEMRASA_L H5 DDR_SRASA# <8>
DDR_SDQ33 L2 D4 DDR_SCASA#
2 DDR_SDQ32 MEMDATA33 MEMCASA_L DDR_SWEA# DDR_SCASA# <8> 2
M1 MEMDATA32 MEMWEA_L G5 DDR_SWEA# <8>

A CHANGEL ADDRESS
DDR_SDQ31 W1 +2.5V
DDR_SDQ30 MEMDATA31 DDR_SBSA1
W3 MEMDATA30 MEMBANKA1 K3 DDR_SBSA1 <8>
DDR_SDQ29 AC1 H3 DDR_SBSA0
MEMDATA29 MEMBANKA0 DDR_SBSA0 <8>

1
DDR_SDQ28 AC3 R16
DDR_SDQ27 MEMDATA28
W2 MEMDATA27 DDR_SMAA[0..13] <8>
DDR_SDQ26 Y1 E10 DDR_SMAA13 1K_0402_1%
DDR_SDQ25 MEMDATA26 MEMADDA13 DDR_SMAA12 +1.25VREF_CPU
AC2 AE6
DDR_SDQ24 MEMDATA25 MEMADDA12 DDR_SMAA11
AD1 AF3

2
DDR_SDQ23 MEMDATA24 MEMADDA11 DDR_SMAA10
AE1 M5
DDR_SDQ22 MEMDATA23 MEMADDA10 DDR_SMAA9
AE3 AE5
MEMDATA22 MEMADDA9

1
DDR_SDQ21 AG3 AB5 DDR_SMAA8 R17 1 1
DDR_SDQ20 MEMDATA21 MEMADDA8 DDR_SMAA7 C8 C9
AJ4 AD3
DDR_SDQ19 MEMDATA20 MEMADDA7 DDR_SMAA6 1K_0402_1%
AE2 Y5
DDR_SDQ18 MEMDATA19 MEMADDA6 DDR_SMAA5 1000P_0402_50V7K
AF1 AB4
DDR_SDQ17 MEMDATA18 MEMADDA5 DDR_SMAA4 2 2
AH3 Y3

2
DDR_SDQ16 MEMDATA17 MEMADDA4 DDR_SMAA3
AJ3 V5
DDR_SDQ15 MEMDATA16 MEMADDA3 DDR_SMAA2 0.1U_0402_16V4Z
AJ5 T5
DDR_SDQ14 MEMDATA15 MEMADDA2 DDR_SMAA1
AJ6 T3
DDR_SDQ13 MEMDATA14 MEMADDA1 DDR_SMAA0
AJ7 N5
DDR_SDQ12 MEMDATA13 MEMADDA0
AH9
DDR_SDQ11 MEMDATA12 DDR_SRASB#
AG5 H4 DDR_SRASB# <9>
DDR_SDQ10 MEMDATA11 MEMRASB_L DDR_SCASB#
AH5 F5 DDR_SCASB# <9>
DDR_SDQ9 MEMDATA10 MEMCASB_L DDR_SWEB#
AJ9 F4 DDR_SWEB# <9>
DDR_SDQ8 MEMDATA9 MEMWEB_L

B CHANGEL ADDRESS
AJ10
DDR_SDQ7 MEMDATA8 DDR_SBSB1
AH11 L5 DDR_SBSB1 <9>
DDR_SDQ6 MEMDATA7 MEMBANKB1 DDR_SSB0
AJ11 J5 DDR_SBSB0 <9>
DDR_SDQ5 MEMDATA6 MEMBANKB0
AH15 DDR_SMAB[0..13] <9>
DDR_SDQ4 MEMDATA5 DDR_SMAB13
AJ15 E9
DDR_SDQ3 MEMDATA4 MEMADDB_B13 DDR_SMAB12
AG11 AF6
DDR_SDQ2 MEMDATA3 MEMADDB_B12 DDR_SMAB11
AJ12 AF4
DDR_SDQ1 MEMDATA2 MEMADDB_B11 DDR_SMAB10
AJ14 M4
3 DDR_SDQ0 MEMDATA1 MEMADDB_B10 DDR_SMAB9 3
AJ16 AD5
MEMDATA0 MEMADDB_B9 DDR_SMAB8
AC5
MEMADDB_B8 DDR_SMAB7
<8> DDR_SDM[0..7] R1 AD4
DDR_SDM7 MEMDQS17 MEMADDB_B7 DDR_SMAB6
A13 AA5
DDR_SDM6 MEMDQS16 MEMADDB_B6 DDR_SMAB5
A7 AB3
DDR_SDM5 MEMDQS15 MEMADDB_B5 DDR_SMAB4
C2 Y4
DDR_SDM4 MEMDQS14 MEMADDB_B4 DDR_SMAB3
H1 W5
DDR_SDM3 MEMDQS13 MEMADDB_B3 DDR_SMAB2
AA1 U5
DDR_SDM2 MEMDQS12 MEMADDB_B2 DDR_SMAB1
AG1 T4
DDR_SDM1 MEMDQS11 MEMADDB_B1 DDR_SMAB0
AH7 M3
DDR_SDM0 MEMDQS10 MEMADDB_B0
AH13
MEMDQS9
<8> DDR_SDQS[0..7] T1
DDR_SDQS7 MEMDQS8
A14 N3
DDR_SDQS6 MEMDQS7 MEMCHECK7
A8 N1
DDR_SDQS5 MEMDQS6 MEMCHECK6
D1 U3
DDR_SDQS4 MEMDQS5 MEMCHECK5
J1 V1
DDR_SDQS3 MEMDQS4 MEMCHECK4
AB1 N2
DDR_SDQS2 MEMDQS3 MEMCHECK3
AJ2 P1
DDR_SDQS1 MEMDQS2 MEMCHECK2
AJ8 U1
DDR_SDQS0 MEMDQS1 MEMCHECK1
AJ13 U2
MEMDQS0 MEMCHECK0

FOX_PZ75403-2941-42

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Claw Harmmer/DDR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 5 of 53
A B C D E
 A B C D E

+1.25V Near Power Supply

+2.5VS
1 1

1
+2.5VS +3VALW + C10 + C11
R18
1K_0402_5% 220U_D2_2.5VM

1
2 2
R19 R20 220U_D2_2.5VM

2
10K_0402_5%
680_0402_5% +1.25V

2
4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K

2
Q2 1 1 1 1 1 1 1 1 1
1 H_THERMTRIP_S# 1
3 1H_THERMTRIP# H_THERMTRIP# <20>
C12 C13 C14 C15 C16 C17 C18 C19 C20
MMBT3904_SOT23
JP1C
2 2 2 2 2 2 2 2 2
TP_M_RESET# T1 PAD 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K
Claw Hammer-DTR NC
AG10
E14
H_THERMTRIP_S# NC +1.25V
A20 D12
THERMTRIP_L NC 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
Miscellaneous NC
E13
H_RST_CPU# AF20 C12 1 1 1 1 1 1 1 1 1
<19> H_RST# RESET_L NC
@ C21 1 2 0.001U_0402_50V7M D22 TP_K8_D22 T2 PAD C22 C23 C24 C25 C26 C27 C28 C29 C30
H_PWRGD NC TP_K8_C22 T3 PAD
<19> H_PWRGD AE18 C22
C31 3900P_0402_50V7K PWROK NC
NC B13
2 1 C LKIN AJ21 B7 2 2 2 2 2 2 2 2 2
<16> CPUCLK0_H CLKIN_H NC

1
CLKIN# AH21 C3 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
R22 FBCLKOUT CLKIN_L NC
1 2 AH19 FBCLKOUT_H
Clock NC K1
169_0402_1% 80.6_0402_1% R23 FBCLKOUT# AJ19 R2
FBCLKOUT_L NC
NC AA3
2 1 Place within 0.5" from CPU F3
<16> CPUCLK0_L

2
Route as 80 Ohm DIFF impedence 8/5/20 NC
NC C23
C32 3900P_0402_50V7K AG7
Place 169 Ohm within 0.5" from CPU CPU_COREFB NC
<48> CPU_COREFB A23 COREFB_H NC AE22
Route as DIF 5/5/5/20 R o u te a s D I F F p a ir 10/5/10 CPU_COREFB# A24 C24
<48> CPU_COREFB# COREFB_L NC
B23 A25 R24
CORE_SENSE NC 0_0805_5%
NC C9
PAD T4 VDDIOFB_H AE12 AE23 CLAW_ANALOG3 T5 PAD +2.5VS 1 2
PAD T6 VDDIOFB_L VDDIOFB_H NC CLAW_ANALOG2 T7 PAD
AF12 VDDIOFB_L NC AF23
L1 PAD T8 VDDIO_SENSE AE11 AF22 CLAW_ANALOG1 T9 PAD
LQG21F4R7N00_0805 VDDIO_SENSE NC CLAW_ANALOG0 T10 PAD
NC AF21
+2.5VDDA 3300P_0402_50V7K +VDDA 50 mil/20 mil U3
1 2 AH25 VDDA1 NC C1
1 AJ25 J3 +3VS 1 5 +2.5VDDA
VDDA2 NC IN OUT
1 1 1 NC R3 2 2
C33 + C34 C35 C36 VID4 AG13 AA2 C37 2
2 <48> VID4 VID3 VID4 NC GND 2
100U_6.3V_M AF14 D3 C38
<48> VID3 VID2 VID3 NC
AG14 AG2 @ 1U_0603_10V4Z 3 4 1U_0603_10V4Z
2 2 2 2 <48> VID2 VID1 VID2 NC 1 SHDN BYP 1
<48> VID1 AF15 VID1 NC B18 1
0.22U_0603_10V7K VID0 AE15 AH1 @ G914E_SOT23-5
<48> VID0 VID0 NC
AE21 C39
NC @ 0.01U_0402_16V7K
NC C20
4.7U_0805_6.3V6K D B RDY AH17 AG4 2
DBREQ# DBRDY NC
AE19
DBREQ_L
Debug NC
C6
07/11 change for reduce H_RST# glitch NC
AG6
+2.5V
AE9
NC +2.5V
AG9
+2.5VS NC
AF18
NC BPSCLK R25
NC
AJ23 1 2 820_0402_5%
2 1 H_RST# AH23 BPSCLK# R27 1 2 820_0402_5%
R26 680_0402_5% THERMDA_CPU NC TP_K8_AE24 T11 PAD
<4> THERMDA_CPU A26 AE24
THERMDA NC
2 1 H_PWRGD <4> THERMDC_CPU
THERMDC_CPU A27 AF24 TP_K8_AF24 T12 PAD
THERMDC NC
1

R28 680_0402_5% D TP_K8_C15 T13 PAD

C15
NC
2 SUSP NC
AG18 TP_CPU_BP3 T14 PAD
G SUSP <41,47> AH18 TP_CPU_BP2 T15 PAD
Q61 NC BP1 R29 680_0402_5%
S AG17 1 2
3

H_RST# 2N7002_SOT23 NC BP0 R30 680_0402_5%

AJ18 1 2
NC
1

TDO A22 C18 SIN CHN R31 1 2 680_0402_5%

TDO NC +2.5VS
TMS E20 A19 BRN# R33 1 2 680_0402_5% RP1
@ R32 TCK TMS NC SCANCLK1 SCANCLK2
E17 D20 4 5
100_0402_5% TRST# TCK NC SCANCLK2 SCANCLK1
B21
TRST_L JTAG NC
C21 3 6
TDI A21 D18 SCANEN SCANEN 2 7
2 2

TDI NC SCANSHENB SCANSHENB

C19 1 8
J1 NC SCANSHENA R34
B19 1 2 680_0402_5%
0.22U_0603_10V7K 4.7U_0805_6.3V6K NC 680_1206_8P4R_5%
JOPEN D29 AH29 +1.2V_HT
1

VLDT0_A VLDT0_B
D27 AH27
VLDT0_A VLDT0_B
1 1 1 D25 AG28
3 C40 C41 C42 VLDT0_A VLDT0_B 3
C28 AG26
VLDT0_A VLDT0_B
C26 AF29
VLDT0_A VLDT0_B
B29 AE28
2 2 2 VLDT0_A VLDT0_B
B27 AF25
0.22U_0603_10V7K VLDT0_A VLDT0_B

+1.25V D17 AG15 +1.25V

VTT_A VTT_B
A18 AF16
VTT_A VTT_B
B17 AG16
VTT_A VTT_B
C17 AH16
VTT_A VTT_B
C16 AJ17
VTT_A VTT_B VTT_SENSE T16 PAD
AE13
PAD T17 TP_K8_A28 VTT_SENSE
A28
PAD T18 TP_K8_AJ28 KEY1
AJ28
KEY0
FOX_PZ75403-2941-42

+2.5VS
+1.2V_HT
R35 R36 R37 R38 R39 R40 R41
0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
1 250 mil
@ 560_0402_5%

@ 560_0402_5%

@ 560_0402_5%

@ 560_0402_5%

@ 560_0402_5%

@ 560_0402_5%

@ 560_0402_5%

1 1 1 1 1 1
1

+ C43 C44 C45 C46 C47 C48 C49

+2.5VS 0.22U_0603_10V7K
JP3 2 2 2 2 2 2 2
100U_D2_10VM 0.22U_0603_10V7K 0.22U_0603_10V7K
2

1 2
3 4
DBREQ# 5 6
4 D B RDY 7 8 4
TCK 9 10
TMS 11 12
TDI 13 14
TRST# 15 16
TDO 17 18
19 20
21 22
23 24 Security Classification Compal Secret Data
26
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title

SAMTEC_ASP-68200-07
Claw Harmmer(MISC)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 6 of 53
A B C D E
 A B C D E

+CPU_CORE +2.5V
JP1E JP1D
B2 L28 L7 E4 +CPU_CORE
VSS VSS VDD VDDIO
AH20 VSS VSS R28 AC15 VDD VDDIO G4
AB21 W28 H18 J4 820U_E9_2_5V_M_R7 330U_D_2VM_R15 @ 330U_D_2VM_R15
VSS VSS VDD VDDIO
W22 VSS VSS AC28 B20 VDD VDDIO L4
M23 VSS VSS AF28 E21 VDD VDDIO N4 1 1 1 1 1 1
L24 VSS VSS AH28 H22 VDD VDDIO U4
AG25 C29 J23 W4 + C50 + C51 + C52 + C53 + C54 + C55
VSS VSS VDD VDDIO
AG27 VSS VSS F2 H24 VDD VDDIO AA4
D2 VSS VSS H2 F26 VDD VDDIO AC4
AF2 K2 N7 AE4 2 2 2 2 2 2
VSS VSS VDD VDDIO
W6 M2 L9 D5
VSS VSS VDD VDDIO 820U_E9_2_5V_M_R7 @ 330U_D_2VM_R15 330U_D_2VM_R15
Y7 P2 V10 AF5
1 VSS VSS VDD VDDIO 1
AA8 T2 G13 F6
VSS VSS VDD VDDIO
AB9 V2 K14 H6
VSS VSS VDD VDDIO
AA10 Y2 Y14 K6
VSS VSS VDD VDDIO
J12 AB2 AB14 M6
VSS VSS VDD VDDIO +CPU_CORE +CPU_CORE
B14 AD2 G15 P6
VSS VSS VDD VDDIO
Y15 AH2 J15 T6
VSS VSS VDD VDDIO 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
AE16 B4 AA15 V6
VSS VSS VDD VDDIO
J18 AH4 H16 Y6
VSS VSS VDD VDDIO
G20 B6 K16 AB6 1 1 1 1 1 1 1 1
VSS VSS VDD VDDIO C56 C57 C58 C59 C60 C61 C62 C63
R20 G6 Y16 AD6
VSS VSS VDD VDDIO
U20 J6 AB16 D7
VSS VSS VDD VDDIO
W20 VSS VSS L6 G17 VDD VDDIO G7
AA20 N6 J17 J7 2 2 2 2 2 2 2 2
VSS VSS VDD VDDIO
AC20 VSS VSS R6 AA17 VDD VDDIO AA7
AE20 U6 AC17 AC7 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 1000P_0402_50V7K
VSS VSS VDD VDDIO
AG20 VSS VSS AA6 AE17 VDD VDDIO AF7
AJ20 VSS VSS AC6 F18 VDD VDDIO F8 4 in Socket Cavity
D21 AH6 K18 H8
F21
VSS VSS
F7 Y18
VDD VDDIO
AB8
2 on backside under Socket
VSS VSS VDD VDDIO
H21 VSS VSS H7 AB18 VDD VDDIO AD8
K21 VSS VSS K7 AD18 VDD VDDIO D9
M21 M7 AG19 G9 +CPU_CORE
VSS VSS VDD VDDIO
P21 VSS VSS P7 E19 VDD VDDIO AC9
T21 T7 G19 AF9 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K
VSS VSS VDD VDDIO
V21 VSS VSS V7 AC19 VDD VDDIO F10
Y21 VSS VSS AB7 AA19 VDD VDDIO AD10 1 1 1 1 1 1 1
AD21 AD7 J19 D11 C64 C65 C66 C67 C68 C69 C70
VSS VSS VDD VDDIO 4.7U_0805_6.3V6K
AG21 VSS VSS B8 F20 VDD VDDIO AF11
B22 VSS VSS G8 H20 VDD VDDIO F12
E22 J8 K20 AD12 2 2 2 2 2 2 2
VSS VSS VDD VDDIO
POWER

G22 VSS VSS L8 M20 VDD VDDIO D13

J22 N8 P20 AF13 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K
2 VSS VSS VDD VDDIO 2
L22 VSS VSS R8 T20 VDD VDDIO F14
N22 VSS VSS U8 V20 VDD VDDIO AD14 Close to socket

POWER
R22 W8 Y20 F16
U22
VSS
VSS
VSS
VSS AC8 AB20
VDD
VDD
VDDIO
VDDIO AD16 CPU Decouping Capacitor
AG29 AH8 AD20 D15 +CPU_CORE
VSS VSS VDD VDDIO
AA22 VSS VSS F9 G21 VDD VDDIO R4 Loop Bandwidth Bulk Cappacitance Total
AC22 H9 J21 +CPU_CORE 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
VSS VSS VDD KHz uF ESR
AG22 K9 L21 N28
VSS VSS VDD VDD
AH22
VSS VSS
M9 N21
VDD VDD
U28 1 1 1 1 1 1 2.5m ohm
AJ22 P9 R21 AA28 C75 C76
D23
VSS
VSS
VSS
VSS
T9 U21
VDD
VDD
VDD
VDD
AE27 C71 C72 C73 C74 20 23000 (AMD)
F23 V9 W21 R7
VSS VSS VDD VDD 2 2 2 2 2 2
H23
VSS VSS
Y9 AA21
VDD VDD
U7
50 9000 0.9m ohm
K23 AD9 AC21 W7
VSS VSS VDD VDD 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
P23 B10 F22 K8
VSS VSS VDD VDD
T23
VSS VSS
G10 K22
VDD VDD
M8
* 300 1500 2.5m ohm
V23 J10 M22 P8
VSS VSS VDD VDD
Y23
VSS VSS
L10 P22
VDD VDD
T8 In Socket Cavity
AB23 N10 T22 V8
VSS VSS VDD VDD
AD23 R10 V22 Y8
VSS VSS VDD VDD
AG23 U10 Y22 J9
VSS VSS VDD VDD
E24 W10 AB22 N9
VSS VSS VDD VDD
G24 AC10 AD22 R9
VSS VSS VDD VDD
J24 AH10 E23 U9
VSS VSS VDD VDD
N24 F11 G23 W9
VSS VSS VDD VDD
R24 H11 L23 AA9
VSS VSS VDD VDD +2.5V
U24 K11 N23 H10
VSS VSS VDD VDD +2.5V
W24 Y11 R23 K10
VSS VSS VDD VDD 4.7U_0805_6.3V6K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
AA24 AB11 U23 M10
VSS VSS VDD VDD
AC24 AD11 W23 P10
VSS VSS VDD VDD
AG24 B12 AA23 T10 1 1 1 1 1 1 1 1
VSS VSS VDD VDD C77 C78 C79 C80 C81 C82 C83 C84
AJ24 G12 AC23 Y10
3 VSS VSS VDD VDD 3
B25 AA12 B24 AB10
VSS VSS VDD VDD
C25 AC12 D24 G11
VSS VSS VDD VDD 2 2 2 2 2 2 2 2
B26 AH12 F24 J11
VSS VSS VDD VDD
D26 F13 K24 AA11
VSS VSS VDD VDD 4.7U_0805_6.3V6K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
H26 H13 M24 AC11
VSS VSS VDD VDD
M26 K13 P24 H12
VSS VSS VDD VDD
T26
VSS VSS
Y13 T24
VDD VDD
K12 Near Socket
Y26 AB13 V24 Y12
VSS VSS VDD VDD
AD26 AD13 Y24 AB12
VSS VSS VDD VDD
AF26 AF17 AB24 J13
VSS VSS VDD VDD
AH26 G14 AD24 AA13
VSS VSS VDD VDD
C27 J14 AH24 AC13
VSS VSS VDD VDD
B28 AA14 AE25 H14
VSS VSS VDD VDD
D28
G28
VSS VSS
AC14
AE14
K26
P26
VDD VDD
AB26
E28
For EMI require
VSS VSS VDD VDD
F15 D16 V26 J28
VSS VSS VDD VDD +CPU_CORE
H15 E15
VSS VSS 1000P_0402_50V7K 1000P_0402_50V7K
AB17 K15
VSS VSS
AD17 AB15
VSS VSS FOX_PZ75403-2941-42
B16 AD15 1 1 1 1
VSS VSS
G18 AH14
VSS VSS @C721
AA18
VSS VSS
E16 @ C722 @ C723 @C724
AC18 G16
VSS VSS 2 2 2 2
D19 J16
VSS VSS
F19 AA16
VSS VSS 1000P_0402_50V7K 1000P_0402_50V7K
H19 AC16
VSS VSS
K19 AE29
VSS VSS
Y19 AJ26
VSS VSS
AB19 E18
VSS VSS
AD19 F17
VSS VSS
AF19 H17
VSS VSS
J20 VSS VSS K17
4 4
L20 VSS VSS Y17
N20 VSS
FOX_PZ75403-2941-42

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Claw Harmmer(Power)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 7 of 53
A B C D E
 A B C D E F G H

DD R_SDQS[0..7] DDR _DQ[0..63]

<5> DDR_SDQS[0..7] DDR_DQ[0..63] <9> +2.5V
DD R_SDQ[0..63] DDR _DQS[0..7]
<5> DDR_SDQ[0..63] DDR_DQS[0..7] <9> +2.5V
DDR_SDM[0..7] D DR_DM[0..7] JP4
<5> DDR_SDM[0..7] DDR_DM[0..7] <9> 40mil
1 VREF VREF 2 +1.25VREF_MEM
DDR_SMAA[0..13] 3 4 1
<5> DDR_SMAA[0..13] DDR_DQ0 VSS VSS DDR_DQ4
5 6 C85
DDR_DQ5 DQ0 DQ4 DDR_DQ1
7 8
DQ1 DQ5 0.1U_0402_16V4Z
9 10
DDR_DQS0 VDD VDD DDR_DM0 2
11 12
1 DDR_DQ3 DQS0 DM0 DDR_DQ2 1
13 14
DQ2 DQ6
15 16
DDR_DQ7 VSS VSS DDR_DQ6
17 18
DDR_DQ9 DQ3 DQ7 DDR_DQ8
19 20
DQ8 DQ12
21 22
DDR_DQ12 VDD VDD DDR_DQ13
23 24
RP24 RP25 DDR_DQS1 DQ9 DQ13 DDR_DM1
25 26
DQS1 DM1
27 28
DDR_SDQ26 DDR_DQ26 DDR_SDQ62 DDR_DQ62 DDR_DQ14 VSS VSS DDR_DQ10
1 8 1 8 29
DQ10 DQ14
30
DDR_SDQ31 2 7 DDR_DQ31 DDR_SDQ58 2 7 DDR_DQ58 DDR_DQ15 31 32 DDR_DQ11
DDR_SDQ30 DDR_DQ30 DDR_SDQ63 DDR_DQ63 DQ11 DQ15
3 6 3 6 33
VDD VDD
34
DDR_SDQ27 4 5 DDR_DQ27 DDR_SDQ59 4 5 DDR_DQ59 35 36
<5> DDR_CLK5 CK0 VDD
<5> DDR_CLK5# 37 CK0# VSS 38
10_0804_8P4R_5% 10_0804_8P4R_5% 39 40
VSS VSS
RP22 RP23
DDR_DQ20 41 42 DDR_DQ16 RP6 +1.25V
DDR_SDQ29 DDR_DQ29 DDR_SDQ61 DDR_DQ61 DDR_DQ17 DQ16 DQ20 DDR_DQ21 47_0804_8P4R_5%
1 8 1 8 43 44
DDR_SDQ24 DDR_DQ24 DDR_SDQ57 DDR_DQ57 DQ17 DQ21 DDR_SMAA12 8
2 7 2 7 45 VDD VDD 46 1
DDR_SDQS3 3 6 DDR_DQS3 DDR_SDM7 3 6 DDR_DM7 DDR_DQS2 47 48 DDR_DM2 DDR_SMAA9 7 2
DDR_SDM3 DDR_DM3 DDR_SDQS7 DDR_DQS7 DDR_DQ18 DQS2 DM2 DDR_DQ22 DDR_SMAA7 6
4 5 4 5 49 DQ18 DQ22 50 3
51 52 DDR_SMAA5 5 4
10_0804_8P4R_5% 10_0804_8P4R_5% DDR_DQ19 VSS VSS DDR_DQ23
53 DQ19 DQ23 54
DDR_DQ28 55 56 DDR_DQ25
RP20 RP21 DQ24 DQ28 RP9
57 VDD VDD 58
DDR_DQ24 59 60 DDR_DQ29 47_0804_8P4R_5%
DDR_SDQ23 DDR_DQ23 DDR_SDQ55 DDR_DQ55 DDR_DQS3 DQ25 DQ29 DDR_DM3 DDR_SMAA3 8
1 8 1 8 61 62 1
DDR_SDQ22 DDR_DQ22 DDR_SDQ51 DDR_DQ51 DQS3 DM3 DDR_SMAA1 7
2 7 2 7 63 VSS VSS 64 2
DDR_SDQ28 3 6 DDR_DQ28 DDR_SDQ56 3 6 DDR_DQ56 DDR_DQ26 65 66 DDR_DQ30 DDR_SMAA10 6 3
DDR_SDQ25 DDR_DQ25 DDR_SDQ60 DDR_DQ60 DDR_DQ27 DQ26 DQ30 DDR_DQ31 DDR_SBSA0 5
4 5 4 5 67 DQ27 DQ31 68 4
69 VDD VDD 70
10_0804_8P4R_5% 10_0804_8P4R_5% 71 72
2 CB0 CB4 RP10 2
Note: 73 CB1 CB5 74
RP18 RP19 75 76 47_0804_8P4R_5%
DDR_SMAA13 Recommend for AMD VSS VSS DDR_SMAA11 8
77 DQS8 DM8 78 1
DDR_SDQS2 1 8 DDR_DQS2 DDR_SDQS6 1 8 DDR_DQS6 79 80 DDR_SMAA8 7 2
DDR_SDM2 DDR_DM2 DDR_SDM6 DDR_DM6 CB2 CB6 DDR_SMAA6 6
2 7 2 7 81 VDD VDD 82 3
DDR_SDQ18 3 6 DDR_DQ18 DDR_SDQ54 3 6 DDR_DQ54 83 84 DDR_SMAA4 5 4
DDR_SDQ19 DDR_DQ19 DDR_SDQ50 DDR_DQ50 CB3 CB7
4 5 4 5 85 DU DU/RESET# 86
87 88
10_0804_8P4R_5% 10_0804_8P4R_5% VSS VSS RP13
89 90
CK2 VSS 47_0804_8P4R_5%
91 92
CK2# VDD DDR_SMAA2 8
93 94 1
RP16 RP17 DDR_CKE0 VDD VDD DDR_CKE0 DDR_SMAA0 7
<5> DDR_CKE0 95 96 2
CKE1 CKE0 DDR_SBSA1 6
97 98 3
DDR_SDQ16 DDR_DQ16 DDR_SDQ53 DDR_DQ53 DDR_SMAA12 DU/A13 DU/BA2 DDR_SMAA11 DDR_SRASA# 5
1 8 1 8 99 100 4
DDR_SDQ20 DDR_DQ20 DDR_SDQ48 DDR_DQ48 DDR_SMAA9 A12 A11 DDR_SMAA8
2 7 2 7 101
A9 A8
102
DDR_SDQ17 3 6 DDR_DQ17 DDR_SDQ49 3 6 DDR_DQ49 103 104
DDR_SDQ21 DDR_DQ21 DDR_SDQ52 DDR_DQ52 DDR_SMAA7 VSS VSS DDR_SMAA6
4 5 4 5 105 106
DDR_SMAA5 A7 A6 DDR_SMAA4
107 108
10_0804_8P4R_5% 10_0804_8P4R_5% DDR_SMAA3 A5 A4 DDR_SMAA2 DDR_SMAA13 1
109 110 2
DDR_SMAA1 A3 A2 DDR_SMAA0 47_0402_5% R42
111 112
A1 A0 DDR_SWEA# 1
113 114 2
RP14 RP15 DDR_SMAA10 VDD VDD DDR_SBSA1 47_0402_5% R43
115 116 DDR_SBSA1 <5>
DDR_SBSA0 A10/AP BA1 DDR_SRASA# DDR_SCASA# 1
<5> DDR_SBSA0 117 118 DDR_SRASA# <5> 2
DDR_SDQ14 DDR_DQ14 DDR_SDQ42 DDR_DQ42 DDR_SWEA# BA0 RAS# DDR_SCASA# 47_0402_5% R44
1 8 1 8 <5> DDR_SWEA# 119 120 DDR_SCASA# <5>
DDR_SDQ15 DDR_DQ15 DDR_SDQ47 DDR_DQ47 DDR_SCS#0 WE# CAS# DDR_SCS#1
2 7 2 7 <5> DDR_SCS#0 121 122 DDR_SCS#1 <5>
DDR_SDQ10 DDR_DQ10 DDR_SDQ43 DDR_DQ43 DDR_SMAA13 S0# S1#
3 6 3 6 123 124
DDR_SDQ11 DDR_DQ11 DDR_SDQ46 DDR_DQ46 DU DU DDR_SCS#0 1
4 5 4 5 125
VSS VSS
126 2
DDR_DQ32 127 128 DDR_DQ37 68_0402_5% R45
10_0804_8P4R_5% 10_0804_8P4R_5% DDR_DQ36 DQ32 DQ36 DDR_DQ33 DDR_SCS#1 1
129 130 2
DQ33 DQ37 68_0402_5% R46
131 132
DDR_DQS4 VDD VDD DDR_DM4 DDR_CKE0 1
133 134 2
RP11 RP12 DDR_DQ34 DQS4 DM4 DDR_DQ35 68_0402_5% R47
135 136
3 DQ34 DQ38 3
137 138
DDR_SDQ12 DDR_DQ12 DDR_SDQ44 DDR_DQ44 DDR_DQ38 VSS VSS DDR_DQ39
1 8 1 8 139
DQ35 DQ39
140
DDR_SDQS1 2 7 DDR_DQS1 DDR_SDQ45 2 7 DDR_DQ45 DDR_DQ40 141 142 DDR_DQ41
DDR_SDM1 DDR_DM1 DDR_SDM5 DDR_DM5 DQ40 DQ44
3 6 3 6 143
VDD VDD
144
DDR_SDQ13 4 5 DDR_DQ13 DDR_SDQS5 4 5 DDR_DQS5 DDR_DQ44 145 146 DDR_DQ45
DDR_DQS5 DQ41 DQ45 DDR_DM5
147 148
10_0804_8P4R_5% 10_0804_8P4R_5% DQS5 DM5
149 150
DDR_DQ47 VSS VSS DDR_DQ42
Layout note 151
DQ42 DQ46
152
DDR_DQ46 153 154 DDR_DQ43
RP7 RP8 DQ43 DQ47
155 156
VDD VDD
Place these resistors 157
VDD CK1#
158 DDR_CLK7# <5>
DDR_SDQ6 1 8 DDR_DQ6 DDR_SDQ35 1 8 DDR_DQ35 159 160
DDR_SDQ7 2 7 DDR_DQ7 DDR_SDQ39 2 7 DDR_DQ39 close to DIMM0, 161
VSS CK1
162
DDR_CLK7 <5>
+2.5V
DDR_SDQ8 DDR_DQ8 DDR_SDQ40 DDR_DQ40 all trace length<500 mil DDR_DQ48 VSS VSS DDR_DQ53
3 6 3 6 163 164
DDR_SDQ9 DDR_DQ9 DDR_SDQ41 DDR_DQ41 DDR_DQ49 DQ48 DQ52 DDR_DQ52
4 5 4 5 165
DQ49 DQ53
166

1
167 168
10_0804_8P4R_5% 10_0804_8P4R_5% DDR_DQS6 VDD VDD DDR_DM6 R48
169 170
DDR_DQ50 DQS6 DM6 DDR_DQ54
171 172
DQ50 DQ54 1K_0402_1% +1.25VREF_MEM
173 174
RP4 RP5 DDR_DQ55 VSS VSS DDR_DQ51
175 176

1 2
DDR_DQ56 DQ51 DQ55 DDR_DQ60
177 178
DDR_SDQS0 DDR_DQS0 DDR_SDQS4 DDR_DQS4 DQ56 DQ60
1 8 1 8 179
VDD VDD
180 1 1
DDR_SDM0 2 7 DDR_DM0 DDR_SDM4 2 7 DDR_DM4 DDR_DQ61 181 182 DDR_DQ57 R49 C86 C87
DDR_SDQ2 DDR_DQ2 DDR_SDQ34 DDR_DQ34 DDR_DQS7 DQ57 DQ61 DDR_DM7
3 6 3 6 183
DQS7 DM7
184
DDR_SDQ3 4 5 DDR_DQ3 DDR_SDQ38 4 5 DDR_DQ38 185 186 1K_0402_1% 0.1U_0402_16V4Z 1000P_0402_50V7K
DDR_DQ58 VSS VSS DDR_DQ62 2 2
187 188

2
10_0804_8P4R_5% 10_0804_8P4R_5% DDR_DQ59 DQ58 DQ62 DDR_DQ63
189 190
DQ59 DQ63
191 192
VDD VDD
<9,16,20,28> SB_SDAT 193 194
RP2 RP3 SDA SA0
<9,16,20,28> SB_SCLK 195 196
SCL SA1
197 198
DDR_SDQ0 DDR_DQ0 DDR_SDQ32 DDR_DQ32 +3VS VDD_SPD SA2
1 8 1 8 199 VDD_ID DU 200
4 DDR_SDQ4 DDR_DQ4 DDR_SDQ33 DDR_DQ33 4
2 7 2 7
DDR_SDQ5 3 6 DDR_DQ5 DDR_SDQ36 3 6 DDR_DQ36
DDR_SDQ1 4 5 DDR_DQ1 DDR_SDQ37 4 5 DDR_DQ37 AMP_1565918-1

10_0804_8P4R_5% 10_0804_8P4R_5% SO-DIMM0

Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
DDR-SODIMM0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 8 of 53
A B C D E F G H
 A B C D E

DDR _DQS[0..7]
<8> DDR_DQS[0..7] +2.5V
+2.5V
DDR _DQ[0..63] +1.25VREF_MEM
<8> DDR_DQ[0..63]
JP5
D DR_DM[0..7] 1 2 20 mil width
<8> DDR_DM[0..7] VREF VREF
3 VSS VSS 4 1
DDR_SMAB[0..13] DDR_DQ0 5 6 DDR_DQ4 C88
<5> DDR_SMAB[0..13] DDR_DQ5 DQ0 DQ4 DDR_DQ1
7 DQ1 DQ5 8
9 10 0.1U_0402_16V4Z
DDR_DQS0 VDD VDD DDR_DM0 2
11 12
DDR_DQ3 DQS0 DM0 DDR_DQ2
13 14
1 DQ2 DQ6 1
15 16
DDR_DQ7 VSS VSS DDR_DQ6
17 18
DDR_DQ9 DQ3 DQ7 DDR_DQ8
19 20
DQ8 DQ12
21 22
+1.25V +1.25V DDR_DQ12 VDD VDD DDR_DQ13
23 24
DDR_DQS1 DQ9 DQ13 DDR_DM1
25 26
RP26 RP27 DQS1 DM1
27 28
68_0804_8P4R_5% 68_0804_8P4R_5% DDR_DQ14 VSS VSS DDR_DQ10
29 30
DDR_DQ2 1 DDR_DQ3 1 DDR_DQ15 DQ10 DQ14 DDR_DQ11
8 8 31
DQ11 DQ15
32
DDR_DM0 2 7 DDR_DQS0 2 7 33 34
DDR_DQ1 3 DDR_DQ5 3 VDD VDD
6 6 <5> DDR_CLK4 35
CK0 VDD
36
DDR_DQ4 4 5 DDR_DQ0 4 5 37 38
<5> DDR_CLK4# CK0# VSS +1.25V
39 40 RP28
VSS VSS 47_0804_8P4R_5%
DDR_SMAB5 1 8
RP29 RP30 DDR_DQ20 41 42 DDR_DQ16 DDR_SMAB7 2 7
68_0804_8P4R_5% 68_0804_8P4R_5% DDR_DQ17 DQ16 DQ20 DDR_DQ21 DDR_SMAB9 3
43 DQ17 DQ21 44 6
DDR_DM1 1 8 DDR_DQS1 1 8 45 46 DDR_SMAB12 4 5
DDR_DQ13 2 DDR_DQ12 2 DDR_DQS2 VDD VDD DDR_DM2
7 7 47 DQS2 DM2 48
DDR_DQ8 3 6 DDR_DQ9 3 6 DDR_DQ18 49 50 DDR_DQ22
DDR_DQ6 4 DDR_DQ7 4 DQ18 DQ22 RP31
5 5 51 VSS VSS 52
DDR_DQ19 53 54 DDR_DQ23 47_0804_8P4R_5%
DDR_DQ28 DQ19 DQ23 DDR_DQ25 DDR_SBSB0 1
55 DQ24 DQ28 56 8
57 58 DDR_SMAB10 2 7
RP32 RP33 DDR_DQ24 VDD VDD DDR_DQ29 DDR_SMAB1 3
59 DQ25 DQ29 60 6
68_0804_8P4R_5% 68_0804_8P4R_5% DDR_DQS3 61 62 DDR_DM3 DDR_SMAB3 4 5
DDR_DQ21 1 DDR_DQ17 1 DQS3 DM3
8 8 63 64
DDR_DQ16 2 DDR_DQ20 2 DDR_DQ26 VSS VSS DDR_DQ30
7 7 65 DQ26 DQ30 66
DDR_DQ11 3 6 DDR_DQ15 3 6 DDR_DQ27 67 68 DDR_DQ31 RP34
DDR_DQ10 4 DDR_DQ14 4 DQ27 DQ31 47_0804_8P4R_5%
5 5 69 VDD VDD 70
71 72 DDR_SMAB4 1 8
CB0 CB4 DDR_SMAB6 2
73 CB1 CB5 74 7
2 RP35 RP36 DDR_SMAB8 3 2
75 VSS VSS 76 6
68_0804_8P4R_5% 68_0804_8P4R_5% Note: 77 78 DDR_SMAB11 4 5
DDR_DQ25 1 DDR_DQ28 1 DQS8 DM8
8 8 79 CB2 CB6 80
DDR_DQ23 2 7 DDR_DQ19 2 7 DDR_SMAA13 Recommend for AMD 81 82
DDR_DQ22 3 DDR_DQ18 3 VDD VDD RP37
6 6 83 CB3 CB7 84
DDR_DM2 4 5 DDR_DQS2 4 5 85 86 47_0804_8P4R_5%
DU DU/RESET# DDR_SRASB# 1
87 VSS VSS 88 8
89 90 DDR_SBSB1 2 7
CK2 VSS DDR_SMAB0 3
91 92 6
CK2# VDD DDR_SMAB2 4
93 94 5
RP38 RP39 DDR_CKE1 VDD VDD DDR_CKE1
<5> DDR_CKE1 95 96
68_0804_8P4R_5% 68_0804_8P4R_5% CKE1 CKE0
97 98
DDR_DQ31 1 DDR_DQ27 1 DDR_SMAB12 DU/A13 DU/BA2 DDR_SMAB11
8 8 99
A12 A11
100
DDR_DQ30 2 7 DDR_DQ26 2 7 DDR_SMAB9 101 102 DDR_SMAB8
DDR_DM3 3 DDR_DQS3 3 A9 A8 DDR_SMAB13 1
6 6 103
VSS VSS
104 2
DDR_DQ29 4 5 DDR_DQ24 4 5 DDR_SMAB7 105 106 DDR_SMAB6 47_0402_5% R50
DDR_SMAB5 A7 A6 DDR_SMAB4 DDR_SWEB# 1
107 108 2
DDR_SMAB3 A5 A4 DDR_SMAB2 47_0402_5% R51
109 110
RP40 RP41 DDR_SMAB1 A3 A2 DDR_SMAB0 DDR_SCASB# 1
111 112 2
68_0804_8P4R_5% 68_0804_8P4R_5% A1 A0 47_0402_5% R52
113 114
DDR_DQ35 1 DDR_DQ34 1 DDR_SMAB10 VDD VDD DDR_SBSB1
8 8 115 116 DDR_SBSB1 <5>
DDR_DM4 2 DDR_DQS4 2 DDR_SBSB0 A10/AP BA1 DDR_SRASB#
7 7 <5> DDR_SBSB0 117 118 DDR_SRASB# <5>
DDR_DQ33 3 DDR_DQ36 3 DDR_SWEB# BA0 RAS# DDR_SCASB#
6 6 <5> DDR_SWEB# 119 120 DDR_SCASB# <5>
DDR_DQ37 4 DDR_DQ32 4 DDR_SCS#2 WE# CAS# DDR_SCS#3 DDR_SCS#2 1
5 5 <5> DDR_SCS#2 121 122 DDR_SCS#3 <5> 2
DDR_SMAB13 S0# S1# 68_0402_5% R53
123 124
DU DU DDR_CKE1
125 126 1 2
DDR_DQ32 VSS VSS DDR_DQ37 68_0402_5% R54
127 128
RP42 RP43 DDR_DQ36 DQ32 DQ36 DDR_DQ33 DDR_SCS#3 1
129 130 2
68_0804_8P4R_5% 68_0804_8P4R_5% DQ33 DQ37 68_0402_5% R55
131 132
DDR_DM5 1 DDR_DQS5 1 DDR_DQS4 VDD VDD DDR_DM4
8 8 133 134
DDR_DQ45 2 DDR_DQ44 2 DDR_DQ34 DQS4 DM4 DDR_DQ35
7 7 135 136
DDR_DQ41 3 DDR_DQ40 3 DQ34 DQ38
6 6 137 138
3 DDR_DQ39 4 DDR_DQ38 4 DDR_DQ38 VSS VSS DDR_DQ39 3
5 5 139
DQ35 DQ39
140
DDR_DQ40 141 142 DDR_DQ41
DQ40 DQ44
143 144
DDR_DQ44 VDD VDD DDR_DQ45
Layout note 145
DQ41 DQ45
146
RP44 RP45 DDR_DQS5 147 148 DDR_DM5
68_0804_8P4R_5% 68_0804_8P4R_5% DQS5 DM5
Place these resistor 149
VSS VSS
150
DDR_DQ52 1 8 DDR_DQ49 1 8 DDR_DQ47 151 152 DDR_DQ42 Layout note
DDR_DQ53 2 7 DDR_DQ48 2 7
closely DIMM1, DDR_DQ46 153
DQ42 DQ46
154 DDR_DQ43
DDR_DQ43 3 DDR_DQ46 3 all trace DQ43 DQ47
6 6 155
VDD VDD
156 Place these resistor
DDR_DQ42 4 5 DDR_DQ47 4 5 length<=800mil 157 158
VDD CK1# DDR_CLK6# <5> close by DIMM1,
159 160 DDR_CLK6 <5>
VSS CK1 all trace length
161 162
DDR_DQ48 VSS VSS DDR_DQ53
163 164 Max=0.8"
RP46 RP47 DDR_DQ49 DQ48 DQ52 DDR_DQ52
165 166
68_0804_8P4R_5% 68_0804_8P4R_5% DQ49 DQ53
167 168
DDR_DQ60 1 DDR_DQ56 1 DDR_DQS6 VDD VDD DDR_DM6
8 8 169 170
DDR_DQ51 2 DDR_DQ55 2 DDR_DQ50 DQS6 DM6 DDR_DQ54
7 7 171 172
DDR_DQ54 3 DDR_DQ50 3 DQ50 DQ54
6 6 173 174
DDR_DM6 4 DDR_DQS6 4 DDR_DQ55 VSS VSS DDR_DQ51
5 5 175 176
DDR_DQ56 DQ51 DQ55 DDR_DQ60
177 178
DQ56 DQ60
179 180
DDR_DQ61 VDD VDD DDR_DQ57
181 182
RP48 RP49 DDR_DQS7 DQ57 DQ61 DDR_DM7
183 184
68_0804_8P4R_5% 68_0804_8P4R_5% DQS7 DM7
185 186
DDR_DQ63 1 DDR_DQ59 1 DDR_DQ58 VSS VSS DDR_DQ62
8 8 187 188
DDR_DQ62 2 DDR_DQ58 2 DDR_DQ59 DQ58 DQ62 DDR_DQ63
7 7 189 190
DDR_DM7 3 DDR_DQS7 3 DQ59 DQ63
6 6 191
VDD VDD
192
DDR_DQ57 4 5 DDR_DQ61 4 5 193 194
<8,16,20,28> SB_SDAT SDA SA0 +3VS
<8,16,20,28> SB_SCLK 195 196
SCL SA1
197 198
+3VS VDD_SPD SA2
199 200
VDD_ID DU
4 4
TYCO_1470804-2

DIMM1
Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
DDR-SODIMM1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 9 of 53
A B C D E
 A B C D E

+2.5V +1.25V
330U_6.3V_M 4.7U_0805_6.3V6K 10U_0805_10V4Z

1
1 1 1
1 1 1 1
+ C89 + C90 C91 C92
C93 C94

2 2 2 2 2 2

Layout note : 330U_6.3V_M 4.7U_0805_6.3V6K 10U_0805_10V4Z

Near DIMMs
Place one cap close to every 2 pull up resistors termination to
+1.25V

+1.25V
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1
C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106

2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+1.25V
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1
C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118
2 2

2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+1.25V
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1
C119 C120 C121 C122 C123 C124 C125 C126 C127 C128

2 2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+1.25V
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
3 3
1 1 1 1 1 1 1 1 1 1 1 1
C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140

2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+2.5V
+1.25V
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1
C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152

2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+2.5V

+1.25V
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1
C153 C154 C155 C156 C157 C158 C159 C160 C161 C162

2 2 2 2 2 2 2 2 2 2

4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4

+2.5V

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
DDR Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 10 of 53
A B C D E
 5 4 3 2 1

NMAA[0..14]
H_CADIP[0..15] <15> NMAA[0..14]
<4> H_CADIP[0..15]
H_CADIN[0..15] NMDA[0..63]
<4> H_CADIN[0..15] <15> NMDA[0..63]
H_CADOP[0..15]
<4> H_CADOP[0..15] NDQMA[0..7]
H_CADON[0..15] <15> NDQMA[0..7]
<4> H_CADON[0..15]
D ND QSA[0..7] D
<15> NDQSA[0..7]

U4B
NMAA0 AF17 AF28 NMDA0
U4A NMAA1 MEM_A0 MEM_DQ0 NMDA1
AK17 AF27
NMAA2 MEM_A1 MEM_DQ1 NMDA2
AH16 AG28
H_CADOP15 H_CADIP15 NMAA3 MEM_A2 MEM_DQ2 NMDA3
T26 R24 AF16 AF26
H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15 NMAA4 MEM_A3 MEM_DQ3 NMDA4
R26 R25 AJ22 AE25
H_CADOP14 HT_RXCAD15N HT_TXCAD15N H_CADIP14 NMAA5 MEM_A4 MEM_DQ4 NMDA5
U25 N26 AJ21 AE24
H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14 NMAA6 MEM_A5 MEM_DQ5 NMDA6
U24 P26 AH20 AF24
H_CADOP13 HT_RXCAD14N HT_TXCAD14N H_CADIP13 NMAA7 MEM_A6 MEM_DQ6 NMDA7
V26 HT_RXCAD13P HT_TXCAD13P N24 AH21 MEM_A7 MEM_DQ7 AG23
H_CADON13 U26 N25 H_CADIN13 NMAA8 AK19 AE29 NMDA8
H_CADOP12 HT_RXCAD13N HT_TXCAD13N H_CADIP12 NMAA9 MEM_A8 MEM_DQ8 NMDA9
W25 HT_RXCAD12P HT_TXCAD12P L26 AH19 MEM_A9 MEM_DQ9 AF29
H_CADON12 W24 M26 H_CADIN12 NMAA10 AJ17 AG30 NMDA10
H_CADOP11 HT_RXCAD12N HT_TXCAD12N H_CADIP11 NMAA11 MEM_A10 MEM_DQ10 NMDA11
AA25 HT_RXCAD11P HT_TXCAD11P J26 AG16 MEM_A11 MEM_DQ11 AG29
H_CADON11 AA24 K26 H_CADIN11 NMAA12 AG17 AH28 NMDA12
H_CADOP10 HT_RXCAD11N HT_TXCAD11N H_CADIP10 NMAA13 MEM_A12 MEM_DQ12 NMDA13
AB26 HT_RXCAD10P HT_TXCAD10P J24 AH17 MEM_A13 MEM_DQ13 AJ28
H_CADON10 AA26 J25 H_CADIN10 NMAA14 AJ18 AH27 NMDA14

HYPER TRANSPORT CPU

H_CADOP9 HT_RXCAD10N HT_TXCAD10N H_CADIP9 MEM_A14 MEM_DQ14 NMDA15
AC25 HT_RXCAD9P HT_TXCAD9P G26 MEM_DQ15 AJ27
H_CADON9 AC24 H26 H _CADIN9 NDQMA0 AG26 AE23 NMDA16
H_CADOP8 HT_RXCAD9N HT_TXCAD9N H_CADIP8 NDQMA1 MEM_DM0 MEM_DQ16 NMDA17
AD26 HT_RXCAD8P HT_TXCAD8P G24 AJ29 MEM_DM1 MEM_DQ17 AG22
H_CADON8 AC26 G25 H _CADIN8 NDQMA2 AE21 AF23 NMDA18
HT_RXCAD8N HT_TXCAD8N NDQMA3 MEM_DM2 MEM_DQ18 NMDA19
AH24 MEM_DM3 MEM_DQ19 AF22
H_CADOP7 R29 L30 H_CADIP7 NDQMA4 AH12 AE20 NMDA20
H_CADON7 HT_RXCAD7P HT_TXCAD7P H _CADIN7 NDQMA5 MEM_DM4 MEM_DQ20 NMDA21
R28 HT_RXCAD7N HT_TXCAD7N M30 AG13 MEM_DM5 MEM_DQ21 AG19
H_CADOP6 T30 L28 H_CADIP6 NDQMA6 AH8 AF20 NMDA22
H_CADON6 HT_RXCAD6P HT_TXCAD6P H _CADIN6 NDQMA7 MEM_DM6 MEM_DQ22 NMDA23
R30 HT_RXCAD6N HT_TXCAD6N L29 AE8 MEM_DM7 MEM_DQ23 AF19
H_CADOP5 T28 J29 H_CADIP5 AH26 NMDA24
H_CADON5 HT_RXCAD5P HT_TXCAD5P H _CADIN5 NDQSA0 MEM_DQ24 NMDA25
T29 HT_RXCAD5N HT_TXCAD5N K29 AF25 MEM_DQS0P MEM_DQ25 AJ26
H_CADOP4 V29 H30 H_CADIP4 NDQSA1 AH30 AK26 NMDA26
HT_RXCAD4P HT_TXCAD4P MEM_DQS1P MEM_DQ26

MEM_A I/F
H_CADON4 U29 H29 H _CADIN4 NDQSA2 AG20 AH25 NMDA27
C H_CADOP3 HT_RXCAD4N HT_TXCAD4N H_CADIP3 NDQSA3 MEM_DQS2P MEM_DQ27 NMDA28 C
Y30 HT_RXCAD3P HT_TXCAD3P E29 AJ25 MEM_DQS3P MEM_DQ28 AJ24
H_CADON3 W30 E28 H _CADIN3 NDQSA4 AH13 AH23 NMDA29
H_CADOP2 HT_RXCAD3N HT_TXCAD3N H_CADIP2 NDQSA5 MEM_DQS4P MEM_DQ29 NMDA30
Y28 HT_RXCAD2P HT_TXCAD2P D30 AF14 MEM_DQS5P MEM_DQ30 AJ23
H_CADON2 Y29 E30 H _CADIN2 NDQSA6 AJ7 AH22 NMDA31
H_CADOP1 HT_RXCAD2N HT_TXCAD2N H_CADIP1 NDQSA7 MEM_DQS6P MEM_DQ31 NMDA32
AB29 HT_RXCAD1P HT_TXCAD1P D28 AG8 MEM_DQS7P MEM_DQ32 AK14
H_CADON1 AA29 D29 H _CADIN1 AH14 NMDA33
H_CADOP0 HT_RXCAD1N HT_TXCAD1N H_CADIP0 MEM_DQ33 NMDA34
AC29 HT_RXCAD0P HT_TXCAD0P B29 AG25 MEM_DQS0N MEM_DQ34 AK13
H_CADON0 AC28 C29 H _CADIN0 AH29 AJ13 NMDA35
HT_RXCAD0N HT_TXCAD0N MEM_DQS1N MEM_DQ35 NMDA36
AF21 AJ11
I/F

H_CLKOP1 H_CLKIP1 MEM_DQS2N MEM_DQ36 NMDA37

<4> H_CLKOP1 Y26 L24 H_CLKIP1 <4> AK25 AH11
H_CLKON1 HT_RXCLK1P HT_TXCLK1P H_CLKIN1 MEM_DQS3N MEM_DQ37 NMDA38
<4> H_CLKON1 W26 L25 H_CLKIN1 <4> AJ12 AJ10
HT_RXCLK1N HT_TXCLK1N MEM_DQS4N MEM_DQ38 NMDA39
AF13 AH10
H_CLKOP0 H_CLKIP0 MEM_DQS5N MEM_DQ39 NMDA40
<4> H_CLKOP0 W29 F29 H_CLKIP0 <4> AK7 AE15
H_CLKON0 HT_RXCLK0P HT_TXCLK0P H_CLKIN0 MEM_DQS6N MEM_DQ40 NMDA41
<4> H_CLKON0 W28 G29 H_CLKIN0 <4> AF9 AF15
HT_RXCLK0N HT_TXCLK0N MEM_DQS7N MEM_DQ41 NMDA42
AG14
H_CTLOP0 H_CTLIP0 NMRASA# MEM_DQ42 NMDA43
<4> H_CTLOP0 P29 M29 H_CTLIP0 <4> <15> NMRASA# AE17 AE14
H_CTLON0 HT_RXCTLP HT_TXCTLP H_CTLIN0 NMCASA# MEM_RAS# MEM_DQ43 NMDA44
<4> H_CTLON0 N29 M28 H_CTLIN0 <4> <15> NMCASA# AH18 AE12
HT_RXCTLN HT_TXCTLN NMWEA# MEM_CAS# MEM_DQ44 NMDA45
<15> NMWEA# AE18 AF12
R56 NMCSA0# MEM_WE# MEM_DQ45 NMDA46
+1.2V_HT 1 2 49.9_0402_1% D27 B28 R57 1 2 100_0402_1% <15> NMCSA0# AJ19 AG11
R58 HT_RXCALN HT_TXCALP NMCKEA MEM_CS# MEM_DQ46 NMDA47
1 2 49.9_0402_1% E27
HT_RXCALP HT_TXCALN
A28 <15> NMCKEA AF18
MEM_CKE MEM_DQ47
AE11
AJ9 NMDA48
NMCLKA0 MEM_DQ48 NMDA49
<15> NMCLKA0 AK16 AH9
216RS480M_BGA706 NMCLKA0# MEM_CKP MEM_DQ49 NMDA50
<15> NMCLKA0# AJ16 AJ8
MEM_CKN MEM_DQ50 NMDA51
AK8
MEM_DQ51 NMDA52
AH7
+2.5VS MEM_DQ52 NMDA53
AJ6
MEM_DQ53 NMDA54
AH6
C163 1 MEM_DQ54 NMDA55
2 0.47U_0603_16V7K AE28 AJ5
C164 1 MEM_CAP1 MEM_DQ55 NMDA56
2 0.47U_0603_16V7K AJ4 AG10
MEM_CAP2 MEM_DQ56 NMDA57
AF11
MEM_DQ57

1
1 AF10 NMDA58
C165 R59 MEM_DQ58 NMDA59
AE9
B 0.1U_0402_16V4Z R60 MEM_DQ59 NMDA60 B
1 2 1K_0402_5% AJ20
MEM_VMODE MEM_DQ60
AG7
1K_0402_1% AF8 NMDA61
2 MEM_DQ61 NMDA62
AF7

2
MEM_VREF MEM_DQ62 NMDA63
AK20 AE7
MEM_VREF MEM_DQ63

1
1 1 2 MPVDD AJ15 AH5 R62 1 2 61.9_0402_1%
+1.8VS MPVDD MEM_COMPP
C166 R63 R61 AJ14 AD30 R64 1 2 61.9_0402_1% +2.5VS
0.1U_0402_16V4Z 0_0805_5% MPVSS MEM_COMPN
1K_0402_1% C167 216RS480M_BGA706
2 1 2

2 1U_0603_10V4Z

MEM_VREF , MPVDD (20mils)

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
RS480M-HT/VMEM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 11 of 53
5 4 3 2 1
 5 4 3 2 1

D D

U4C

D8 A7
GFX_RX0P GFX_TX0P
D7 B7
GFX_RX0N GFX_TX0N
D5 B6
GFX_RX1P GFX_TX1P
D4 GFX_RX1N GFX_TX1N B5
E4 GFX_RX2P GFX_TX2P A5
F4 GFX_RX2N GFX_TX2N A4
G5 GFX_RX3P GFX_TX3P B3
G4 GFX_RX3N GFX_TX3N B2
H4 GFX_RX4P GFX_TX4P C1
J4 GFX_RX4N GFX_TX4N D1

PCIE I/F TO VIDEO

H5 GFX_RX5P GFX_TX5P D2
H6 GFX_RX5N GFX_TX5N E2
G1 GFX_RX6P GFX_TX6P F2
G2 GFX_RX6N GFX_TX6N F1
K5 GFX_RX7P GFX_TX7P H2
K4 GFX_RX7N GFX_TX7N J2
L4 GFX_RX8P GFX_TX8P J1
M4 GFX_RX8N GFX_TX8N K1
N5 GFX_RX9P GFX_TX9P K2
N4 GFX_RX9N GFX_TX9N L2
P4 GFX_RX10P GFX_TX10P M2
R4 GFX_RX10N GFX_TX10N M1
P5 GFX_RX11P GFX_TX11P N1
P6 GFX_RX11N GFX_TX11N N2
C C
P2 GFX_RX12P GFX_TX12P R1
R2 GFX_RX12N GFX_TX12N T1
T5 GFX_RX13P GFX_TX13P T2
T4 GFX_RX13N GFX_TX13N U2
U4 GFX_RX14P GFX_TX14P V2
V4 GFX_RX14N GFX_TX14N V1
W1 GFX_RX15P GFX_TX15P Y2
W2 AA2
GFX_RX15N GFX_TX15N

AE1 AD2
GPP_RX0P GPP_TX0P
AE2 AD1
GPP_RX0N GPP_TX0N
AB2 AA1
GPP_RX1P GPP_TX1P
AC2 AB1
GPP_RX1N GPP_TX1N 17_EXP@
PCIE_RX0P
PCIE I/F TO SLOT PCIE_TX0P_C C168 1 PCIE_TX0P
<28> PCIE_RX0P AB5 Y5 2 0.1U_0402_16V4Z PCIE_TX0P <28>
PCIE_RX0N GPP_RX2P GPP_TX2P PCIE_TX0N_C C169 1 PCIE_TX0N
<28> PCIE_RX0N AB4
GPP_RX2N GPP_TX2N
Y6 2 0.1U_0402_16V4Z PCIE_TX0N <28>
17_EXP@ 15_EXP@
PCIE_RX1P Y4 W5 PCIE_TX1P_C C691 1 2 0.1U_0402_16V4Z PCIE_TX1P
<28> PCIE_RX1P PCIE_RX1N GPP_RX3P GPP_TX3P PCIE_TX1N_C C692 1 PCIE_TX1N PCIE_TX1P <28>
<28> PCIE_RX1N AA4 W4 2 0.1U_0402_16V4Z PCIE_TX1N <28>
GPP_RX3N GPP_TX3N 15_EXP@

SB_RX0P AG1 AF2 SB_TX0P_C C170 1 2 0.1U_0402_16V4Z SB_TX0P

<19> SB_RX0P SB_RX0N SB_RX0P SB_TX0P SB_TX0N_C C171 1 SB_TX0P <19>
<19> SB_RX0N AH1 AG2 2 0.1U_0402_16V4Z SB_TX0N SB_TX0N <19>
SB_RX0N SB_TX0N
SB_RX1P
PCIE I/F TO SB SB_TX1P_C C172 1
<19> SB_RX1P AC5
SB_RX1P SB_TX1P
AC4 2 0.1U_0402_16V4Z SB_TX1P SB_TX1P <19>
SB_RX1N AC6 AD4 SB_TX1N_C C173 1 2 0.1U_0402_16V4Z SB_TX1N
<19> SB_RX1N SB_RX1N SB_TX1N SB_TX1N <19>
R65 1 2 10K_0402_1% AH3
R66 1 PCE_ISET
2 8.25K_0402_1% AJ3 AH2 R67 1 2 150_0402_1%
PCE_TXISET PCE_PCAL R68
AJ2 1 2 82.5_0402_1% +1.2V_HT
B PCE_NCAL B
216RS480M_BGA706

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
RS480M PCIE/DVI Controller
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 12 of 53
5 4 3 2 1
 AVDD , AVDDI , AVDDQ , +NB_PLLVDD , +NB_HTPVDD
+NB_VDDR3 , LPVDD , LVDDR18D , LVDDR18A (20mils)
+3VS
L2
1 2 AVDD
FBML10160808121LMT_0603 1
C174
0.1U_0402_16V4Z
2
+1.8VS
U4D
AVDDI B27
+1.8VS AVDD1 LVDSB0+
1 C27 D18 LVDSB0+ <17>
L3 1U_0603_10V4Z C175 AVDD2 TXOUT_U0P LVDSB0-
D26 C18 LVDSB0- <17>
0.1U_0402_16V4Z AVSSN1 TXOUT_U0N LVDSB1+
1 2 D25 AVSSN2 TXOUT_U1P B19 LVDSB1+ <17>
FBML10160808121LMT_0603 1 1 C24 A19 LVDSB1-
2 AVDDDI TXOUT_U1N LVDSB1- <17>
C177 B24 D19 LVDSB2+
AVSSDI TXOUT_U2P LVDSB2- LVDSB2+ <17>
C176 C19
AVDDQ TXOUT_U2N LVDSB2- <17>
10U_0805_10V4Z E24 D20
2 2 AVDDQ TXOUT_U3P
D24 AVSSQ TXOUT_U3N C20

CRT/TVOUT
TV_CRMA B25 B16 LVDSA0+
<18,40> TV_CRMA TV_LUMA C TXOUT_L0P LVDSA0- LVDSA0+ <17>
<18,40> TV_LUMA A25 Y TXOUT_L0N A16 LVDSA0- <17>
TV_COMPS A24 D16 LVDSA1+
<18,40> TV_COMPS COMP TXOUT_L1P LVDSA1- LVDSA1+ <17>
TXOUT_L1N C16 LVDSA1- <17>
CRT_R C25 B17 LVDSA2+
<18> CRT_R CRT_G RED TXOUT_L2P LVDSA2- LVDSA2+ <17>
<18> CRT_G A26 GREEN TXOUT_L2N A17 LVDSA2- <17>
CRT_B B26 E17 +1.8VS
<18> CRT_B BLUE TXOUT_L3P
D17 0.1U_0402_16V4Z L4
CRT_VSYNC TXOUT_L3N
<18> CRT_VSYNC A11 DAC_VSYNC
1 2
R69 CR T_HSYNC LVDSBC+ FBML10160808121LMT_0603

LVDS
<18> CRT_HSYNC B11 DAC_HSYNC TXCLK_UP B20 LVDSBC+ <17> 1 1
1 2 715_0402_1% C26 A20 LVDSBC-
RSET TXCLK_UN LVDSBC- <17>
3VDDCCL E11 B18 LVDSAC+ C178 C179
+1.8VS <18> 3VDDCCL 3VDDCDA DAC_SCL TXCLK_LP LVDSAC- LVDSAC+ <17>
F11 C17 1U_0603_10V4Z
<18> 3VDDCDA DAC_SDA TXCLK_LN LVDSAC- <17> 2 2
L5
1 2 1U_0603_10V4Z E18 LPVDD
FBML10160808121LMT_0603 LPVDD L6
1 1 LPVSS F17
+NB_PLLVDD A14 E19 LVDDR18D 0.1U_0402_16V4Z 1 2 +1.8VS

PLL PWR
C180 C181 PLLVDD LVDDR18D L7 FBML10160808121LMT_0603
B14 PLLVSS LVDDR18A_1 G20 1 1
+2.5VS 10U_0805_10V4Z H20 LVDDR18A 0.1U_0402_16V4Z 1 2
+1.8VS 2 2 LVDDR18A_2 +1.8VS
+NB_HTPVDD M23 1 1 FBML10160808121LMT_0603 C182 C183
HTPVDD 1U_0603_10V4Z
L23 HTPVSS LVSSR1 G19
R554 1 2 1U_0603_10V4Z E20 C184 C185 2 2
LVSSR2
1

1 1 F20 1U_0603_10V4Z
R70 150_0603_1% LVSSR3 2 2
H18
C186 C187 NB_RST# LVSSR4
2.2K_0402_5% <19,24,28,35> NB_RST# D14 G18
10U_0805_10V4Z NB_PWRGD SYSRESET# LVSSR5
<42> NB_PWRGD B15 F19
2 2 LDTSTOP# POWERGOOD LVSSR6
B12 H19
2

<4,19> LDTSTOP# ALLOW_LDTSTOP LDTSTOP# LVSSR7

<19> ALLOW_LDTSTOP C12 F18
SUS_STAT# ALLOW_LDTSTOP LVSSR8
<20> SUS_STAT# AH4

PM
SUS_STAT# ENVDD
E14 ENVDD <17>
LVDS_DIGON ENABLT
F14 ENABLT <17,37,38>
LVDS_BLON
2

L9 1 2 +NB_VDDR3 H13 F13

+3VS VDDR3_1 LVDS_BLEN

1
1K_0402_5%

1K_0402_5%
R71 FBML10160808121LMT_0603 C188 1 2 H12
1U_0603_10V4Z VDDR3_2
5.6K_0402_5% B8
GFX_CLKP

R453
NB_REFCLK A13 A8
<16> NB_REFCLK OSCIN GFX_CLKN

R72
B13
1

OSCOUT
P23 R74 10K_0402_5% 1 2 @

2
HTTSTCLK HTREFCLK
N23
CLOCKs HTREFCLK
E8 SBLINKCLK
HTREFCLK <16>

SB_CLKP SBLINKCLK <16>

R75 2 1 10K_0402_5% B9 E7 SBLINKCLK#
TVCLKIN SB_CLKN SBLINKCLK# <16>
NB STRAPS(Internal pull up)
R76 1 2 3K_0402_5% F12 C13
DEF_GPIO0:SIDE PORT EN# E13
DFT_GPIO0/RSV DFT_GPIO3/RSV
C14
PAD T20 DFT_GPIO1/RSV DFT_GPIO4/RSV
High, SIDE PORT MEMORY DISABLE D13
DFT_GPIO2/RSV DFT_GPIO5/RSV
C15

Low, SIDE PORT MEMORY ENABLE BMREQ# TMDS_HPD

A10
<19> BMREQ# F10
EDID_CLK_LCD BMREQb T21 PAD
C10 E10
DEF_GPIO1:LOAD ROM STRAPS #
<17> EDID_CLK_LCD
C11
AF4
I2C_CLK
I2C_DATA
MIS. STRP_DATA
B10 EDID_DAT_LCD
THERMALDIODE_P DDC_DATA EDID_DAT_LCD <17>
High, LOAD ROM STRAP DISABLE AE4
THERMALDIODE_N
E12 R80 4.7K_0402_5% 1 2
+3VS TESTMODE
Low, LOAD ROM STRAP ENABLE
216RS480M_BGA706
2

R81 R82
4.7K_0402_5% 4.7K_0402_5%
1

EDID_CLK_LCD

EDID_DAT_LCD

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
RS480M VIDEO_IF/CLOCK GEN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 13 of 53
 5 4 3 2 1

U4F
G10 VSS1 VSSA1 R5
G12 VSS2 VSSA2 AE5
AD29 VSS3 VSSA3 V5
AD27 VSS4 VSSA4 N3
AC27 VSS5 VSSA5 F7
G15 F5 +1.2V_HT
VSS6 VSSA6 +1.2V_HT U4E
G14 VSS7 VSSA7 R3
Y24 VSS8 VSSA8 AA6 VDDA12_14 H9
G13 T3 N27 AA7 C190 1 2 22U_1206_10V4Z
VSS9 VSSA9 22U_1206_10V4Z C191 VDD_HT1 VDDA12_1
E9 VSS10 VSSA10 M6 2 1 U27 VDD_HT2 VDDA12_2 G9
D15 C5 V27 U8 C192 1 2 1U_0603_10V4Z
VSS11 VSSA11 0.1U_0402_16V4Z C230 VDD_HT3 VDDA12_3
D9 F8 2 1 G27 N7
VSS12 VSSA12 1U_0402_6.3V6K C232 VDD_HT4 VDDA12_4 C195 0.1U_0402_16V4Z
AD9 M8 2 1 V24 N8 1 2
VSS13 VSSA13 0.1U_0402_16V4Z C240 VDD_HT5 VDDA12_5 C198 0.1U_0402_16V4Z
D
G11
VSS14 VSSA14
Y8 2005.08.11 for ATI Suggestion 2 1 H27
VDD_HT6 VDDA12_6
U7 1 2
D
F16 V3 1U_0402_6.3V6K 2 1 C242 K24 F9 C202 1 2 1U_0402_6.3V6K
VSS15 VSSA15 1U_0402_6.3V6K C200 VDD_HT7 VDDA12_7 C201 0.1U_0402_16V4Z
G30 C3 2 1 AB24 AA8 1 2
VSS16 VSSA16 0.1U_0402_16V4Z C243 VDD_HT8 VDDA12_8
AB28 W3 2 1 P27 G8
VSS17 VSSA17 0.1U_0402_16V4Z C244 VDD_HT9 VDDA12_9
AB25
VSS18 VSSA18
K8 2 1 J27
VDD_HT10 VDDA12_10
G7 2005.08.11 for ATI Suggestion
D12 D3 0.1U_0402_16V4Z 2 1 C238 AA27 J8
VSS19 VSSA19 0.1U_0402_16V4Z C205 VDD_HT11 VDDA12_11
AD24 C6 2 1 K27 J7
VSS20 VSSA20 0.1U_0402_16V4Z C234 VDD_HT12 VDDA12_12 VDDA12_13
AA28 AA3 2 1 P24 B1
VSS21 VSSA21 VSSA22 0.1U_0402_16V4Z C207 VDD_HT13 VDDA12_13
G17 A2 2 1 AB27 AG4
VSS22 VSSA22 0.1U_0402_16V4Z C236 VDD_HT14 VDDA18_1 R84
Y23 AB3 2 1 AB23 R8
VSS23 VSSA23 0.1U_0402_16V4Z C252 VDD_HT15 VDDA18_2 0_0805_5%
AC9 P8 2 1 V23 AC8
VSS24 VSSA24 VDD_HT16 VDDA18_3 VDDA18
R19 J6 G23 AC7 2 1 +1.8VS
VSS25 VSSA25 VDD_HT17 VDDA18_4
Y27 VSS26 VSSA26 C8 E23 VDD_HT18 VDDA18_5 AF6
C28 AD3 W23 AE6 C210 1 2 1U_0603_10V4Z
VSS27 VSSA27 VDD_HT19 VDDA18_6 C211 0.1U_0402_16V4Z
G16 VSS28 VSSA28 V8 K23 VDD_HT20 VDDA18_7 L8 1 2
F25 F3 J23 W8 C212 1 2 0.1U_0402_16V4Z
VSS30 VSS29 VSSA29 VDD_HT21 VDDA18_8 C213 0.1U_0402_16V4Z
B30 VSS30 VSSA30 AE3 H23 VDD_HT22 VDDA18_9 W7 1 2
T24 AF3 U23 L7 C214 1 2 0.1U_0402_16V4Z
VSS31 VSSA31 VDD_HT23 VDDA18_10
F26 VSS32 VSSA32 M5 AA23 VDD_HT24 VDDA18_11 R7
W27 AB7 +2.5VS D23 AF5
VSS33 VSSA33 VDD_HT25 VDDA18_12 VDDA18_13
D11 VSS34 VSSA34 G3 F23 VDD_HT26 VDDA18_13 AK2
H11 VSS35 VSSA35 B4 C23 VDD_HT27 VDD_CORE1 N16
AD25 P7 22U_1206_10V4Z 2 1 C215 B23 M13
VSS36 VSSA36 VDD_HT28 VDD_CORE2

POWER
H17 VSS37 VSSA37 AA5 A23 VDD_HT29 VDD_CORE3 M15
H10 C9 0.1U_0402_16V4Z 2 1 C216 VDDHT30 A29 W16
VSS38 VSSA38 0.1U_0402_16V4Z C217 VDDHT31 AC30 VDD_HT30 VDD_CORE4
H16 VSS39 VSSA39 C7 2 1
VDD_HT31 VDD_CORE5 N18
H14 J5 0.1U_0402_16V4Z 2 1 C218 P19 +1.2V_HT
VSS40 VSSA40 0.1U_0402_16V4Z C219 VDD_CORE6
E16 VSS41 VSSA41 R6 2 1 AK23 VDD_MEM1 VDD_CORE7 N12
D10 J3 0.1U_0402_16V4Z 2 1 C220 AK28 P15
VSS42 VSSA42 0.1U_0402_16V4Z C221 VDD_MEM2 VDD_CORE8 C702 1 2 @ 100U_D2_6.3M_R45

+
E15 VSS43 VSSA43 AD5 2 1 AK11 VDD_MEM3 VDD_CORE9 N14
F15 D6 0.1U_0402_16V4Z 2 1 C222 AK4 M17
VSS44 VSSA44 0.1U_0402_16V4Z C223 VDD_MEM4 VDD_CORE10
VSSA45 C4 2 1 AE30 VDD_MEM5 VDD_CORE11 T19
K3 0.1U_0402_16V4Z 2 1 C224 AC14 G22 C225 1 2 22U_1206_10V4Z
C VSSA46 0.1U_0402_16V4Z C226 VDD_MEM6 VDD_CORE12 C227 1 C
U15 VSS45 VSSA47 AB8 2 1 AD12 VDD_MEM7 VDD_CORE13 R12 2 22U_1206_10V4Z
V14 T7 0.1U_0402_16V4Z 2 1 C228 AC18 P13
VSS46 VSSA48 0.1U_0402_16V4Z C229 VDD_MEM8 VDD_CORE14 C197 1U_0402_6.3V4Z
R15 VSS47 VSSA49 Y7 2 1 AC20 VDD_MEM9 VDD_CORE15 R14 1 2
T14 AD6 0.1U_0402_16V4Z 2 1 C231 AD10 V19 C199 1 2 0.1U_0402_16V4Z
VSS48 VSSA50 0.1U_0402_16V4Z C233 VDD_MEM10 VDD_CORE16 C193 0.1U_0402_16V4Z
N15 VSS49 VSSA51 K7 2 1 AD14 VDD_MEM11 VDD_CORE17 R18 1 2
V12 H7 0.1U_0402_16V4Z 2 1 C235 AD15 U16 C194 1 2 0.1U_0402_16V4Z
VSS50 VSSA52 0.1U_0402_16V4Z C237 VDD_MEM12 VDD_CORE18 C196 0.1U_0402_16V4Z
N13 M3 2 1 AD20 U12 1 2
GROUND

VSS51 VSSA53 0.1U_0402_16V4Z C239 VDD_MEM13 VDD_CORE19 C203 0.1U_0402_16V4Z

P14 V6 2 1 AC10 T13 1 2
VSS52 VSSA54 0.1U_0402_16V4Z C241 VDD_MEM14 VDD_CORE20 C204 0.1U_0402_16V4Z
U17 H8 2 1 AD18 U14 1 2
VSS53 VSSA55 VDD_MEM15 VDD_CORE21 C206 0.1U_0402_16V4Z
T16 C2 AC12 T17 1 2
VSS54 VSSA56 VDD_MEM16 VDD_CORE22 C208 0.1U_0402_16V4Z
R17 AG3 AD22 U18 1 2
VSS55 VSSA57 L10 VDD_MEM17 VDD_CORE23 C245 0.1U_0402_16V4Z
P12 L6 AC22 E22 1 2
VSS56 VSSA58 VSSA59 FBML10160808121LMT_0603 VDD_MEM18 VDD_CORE24 C246 0.1U_0402_16V4Z
T12 AJ1 AH15 R16 1 2
VSS57 VSSA59 VDD18 VDD_MEMCK VDD_CORE25 C247 0.1U_0402_16V4Z
R13 M7 +1.8VS 1 2 V13 1 2
VSS58 VSSA60 VDD_CORE26 C248 1U_0402_6.3V4Z
W13 V7 H15 T15 1 2
VSS59 VSSA61 VDD18_1 VDD_CORE27 C249 0.1U_0402_16V4Z
W17 F6 AC17 P17 1 2
VSS60 VSSA62 1U_0603_10V4Z C250 VDD18_2 VDD_CORE28 C251 1U_0402_6.3V4Z
P18 E6 2 1 AC15 W18 1 2
VSS61 VSSA63 VDD18_3 VDD_CORE29 C209 1U_0402_6.3V4Z
V18 U5 D22 1 2
VSS62 VSSA64 0.1U_0402_16V4Z C253 VDD_CORE30 C254 1U_0402_6.3V4Z
M18 U6 2 1 B21 W12 1 2
VSS63 VSSA65 0.1U_0402_16V4Z C255 VDD_CORE47 VDD_CORE31 C256 1U_0402_6.3V4Z
U13 E5 2 1 C21 V15 1 2
VSS64 VSSA66 0.1U_0402_16V4Z C257 VDD_CORE46 VDD_CORE32 C258 1U_0402_6.3V4Z
N17 L5 2 1 A22 W14 1 2
VSS65 VSSA67 0.1U_0402_16V4Z C259 VDD_CORE45 VDD_CORE33 C260 0.1U_0402_16V4Z
W15 T8 2 1 B22 V17 1 2
VSS66 VSSA68 VDDA12_13 VDD_CORE44 VDD_CORE34
V16 C22 M19
VSS67 VDD_CORE43 VDD_CORE35
T18 F21 H22
VSS68 VDD_CORE42 VDD_CORE36
M14 1 F22 H21
VSS69 C261 VDD_CORE41 VDD_CORE37
M12 E21 D21
VSS70 VDD_CORE40 VDD_CORE38
M16
VSS71 VSS113
F28 G21
VDD_CORE39 07/04 for +1.2V_HT ripple
P16 H28 4.7U_0805_6.3V6K
VSS72 VSS114 2 216RS480M_BGA706
M24
VSS115 VSSA22
J28
VSS116
U19 N19
VSS73 VSS117
AC16 K28
B VSS74 VSS118 VDDA18_13 B
AG18 T23
VSS75 VSS119
AC23 L27
VSS76 VSS120
AD8 1
VSS77 C262
AD11 M27
VSS78 VSS122
AD13 H24
VSS79 VSS123 4.7U_0805_6.3V6K
AD16 N28
VSS80 VSS124 2
AD19 P25
VSS81 VSS125 VSSA59
AD23 P28
VSS82 VSS126
AG5 E26
VSS83 VSS127
AG6 K25
VSS84 VSS128
AG21 U28
VSS85 VSS129 VDDHT30
AD17 V25
VSS86 VSS130
AG15 V28
VSS87 VSS131
AG12 R23 1
VSS89 VSS88 VSS132 C263
AF30
VSS89
AG24
VSS90 4.7U_0805_6.3V6K
AG9
VSS91 2
AC19
VSS92 VSS30
AG27
VSS93
AC11
VSS94
AD7
VSS95 VDDHT31
AJ30
VSS96
AC21
VSS97
AK5 1
VSS98 C264
AK10
VSS99
AC13
VSS100 4.7U_0805_6.3V6K
AD21
VSS101 2
AK22
VSS102 VSS89
AK29
VSS103
W19
VSS104
AE26
VSS105
AE27 VSS106
A A

T27 VSS107
R27 VSS108
AD28 VSS109
F24 VSS110
F27 VSS111
G28 VSS112 Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title

216RS480M_BGA706
RS480M Power/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 14 of 53
5 4 3 2 1
 5 4 3 2 1

+2.5VS VRAM@ VRAM@ VRAM@ VRAM@ VRAM@ +2.5VS VRAM@ VRAM@ VRAM@ VRAM@ VRAM@
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VRAM@ C265 C266 C267 C268 C269 C270 C271 C272 C273 C274 VRAM@ C275 C276 C277 C278 C279 C280 C281 C282 C283 C284
10U_0805_10V4Z 10U_0805_10V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

VRAM@ VRAM@ VRAM@ VRAM@ VRAM@ VRAM@ VRAM@ VRAM@

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

D D

U6 +2.5VS
U7 +2.5VS NMAA[0..14] NDQSA5 16 1
NDQSA3 <11> NMAA[0..14] NDQMA5 LDQS0 VDD0
16 1 20 18
NDQMA3 LDQS0 VDD0 NMDA40 LDM1 VDD1
20 18 2 33
NMDA24 LDM1 VDD1 NMDA[0..63] NMDA41 DQ0 VDD2
2 33 <11> NMDA[0..63] 4 3
NMDA25 DQ0 VDD2 NMDA42 DQ1 VDDQ0
4 DQ1 VDDQ0 3 5 DQ2 VDDQ1 9
NMDA26 5 9 NMDA43 7 15
NMDA27 DQ2 VDDQ1 NDQMA[0..7] NMDA44 DQ3 VDDQ2
7 DQ3 VDDQ2 15 <11> NDQMA[0..7] 8 DQ4 VDDQ3 55
NMDA28 8 55 NMDA45 10 61
NMDA29 DQ4 VDDQ3 NMDA46 DQ5 VDDQ4
10 DQ5 VDDQ4 61 11 DQ6
NMDA30 11 ND QSA[0..7] NMDA47 13 14
NMDA31 DQ6 <11> NDQSA[0..7] DQ7 NC0
13 DQ7 NC0 14 NC1 17
17 NDQSA4 51 19
NDQSA2 NC1 +2.5VS NDQMA4 UDQS0 NC2
51 UDQS0 NC2 19 47 UDM1 NC3 25
+2.5VS NDQMA2 47 25 NMDA32 54 43
NMDA16 UDM1 NC3 NMDA33 DQ8 NC4
54 DQ8 NC4 43 56 DQ9 NC5 50

1
NMDA17 56 50 NMDA34 57 53
DQ9 NC5 DQ10 NC6
1

NMDA18 57 53 NMDA35 59
NMDA19 DQ10 NC6 R85 VRAM@ NMDA36 DQ11 NMCLKA0
59 DQ11 60 DQ12 CK 45
R86 VRAM@ NMDA20 60 45 NMCLKA0 1K_0402_1% NMDA37 62 46 NMCLKA0#
1K_0402_1% NMDA21 DQ12 CK NMCLKA0# NMDA38 DQ13 CK# NMCKEA
62 46 63 44

2
NMDA22 DQ13 CK# NMCKEA NMDA39 DQ14 CKE
63 44 65
2

NMDA23 DQ14 CKE NMCKEA <11> DQ15 NMAA13

65 26
DQ15
26 NMAA13 (20mil) VREF_2 49
BA0
27 NMAA14
(20mil) VREF_1 49 VREF
BA0
BA1 27 NMAA14 VREF BA1

1
1 NMAA0 29 24 NMCSA0#
A0 CS#
1

C NMAA0 NMCSA0# NMAA1 NMRASA# C

1 29 A0 CS# 24 NMCSA0# <11> 30 A1 RAS# 23
NMAA1 30 23 NMRASA# R87 VRAM@ C285 VRAM@ NMAA2 31 22 NMCASA#
NMAA2 A1 RAS# NMCASA# NMRASA# <11> NMAA3 A2 CAS# NMWEA#
R88 VRAM@ C286 VRAM@ 31 22 1K_0402_1% 0.1U_0402_16V4Z 32 21
NMAA3 A2 CAS# NMWEA# NMCASA# <11> 2 NMAA4 A3 WE#
1K_0402_1% 0.1U_0402_16V4Z 32 21 35

2
2 NMAA4 A3 WE# NMWEA# <11> NMAA5 A4
35 36 6
2

NMAA5 A4 NMAA6 A5 VSSQ0

36 A5 VSSQ0 6 37 A6 VSSQ1 12
NMAA6 37 12 NMAA7 38 52
NMAA7 A6 VSSQ1 NMAA8 A7 VSSQ2
38 52 39 58
NMAA8 A7 VSSQ2 NMAA9 A8 VSSQ3
39 58 40 64
NMAA9 A8 VSSQ3 NMAA10 A9 VSSQ4
40 64 28 34
NMAA10 A9 VSSQ4 NMAA11 AP/A10 VSS0
28 34 41 48
NMAA11 AP/A10 VSS0 NMAA12 A11 VSS1
41 48 42 66
NMAA12 A11 VSS1 A12 VSS2
42 66
A12 VSS2 @ HY5DU561622CT-4_TSOPII66
@ HY5DU561622CT-4_TSOPII66

U8 +2.5VS U9 +2.5VS
NDQSA1 16 1 NDQSA6 16 1
NDQMA1 LDQS0 VDD0 NDQMA6 LDQS0 VDD0
20 18 20 18
NMDA8 LDM1 VDD1 NMDA48 LDM1 VDD1
2 33 2 33
NMDA9 DQ0 VDD2 NMDA49 DQ0 VDD2
4 3 4 3
NMDA10 DQ1 VDDQ0 NMDA50 DQ1 VDDQ0
5 9 5 9
NMDA11 DQ2 VDDQ1 NMDA51 DQ2 VDDQ1
7 15 7 15
NMDA12 DQ3 VDDQ2 NMDA52 DQ3 VDDQ2
8 55 8 55
NMDA13 DQ4 VDDQ3 NMDA53 DQ4 VDDQ3
10 61 10 61
NMDA14 DQ5 VDDQ4 NMDA54 DQ5 VDDQ4
11 11
NMDA15 DQ6 NMDA55 DQ6
13 14 13 14
DQ7 NC0 DQ7 NC0
17 17
NDQSA0 NC1 NDQSA7 NC1
51 19 51 19
NDQMA0 UDQS0 NC2 NDQMA7 UDQS0 NC2
47 25 47 25
B NMDA0 UDM1 NC3 NMCLKA0 NMDA56 UDM1 NC3 B
54 43 NMCLKA0 <11> 54 43
NMDA1 DQ8 NC4 NMDA57 DQ8 NC4
56 50 56 50
NMDA2 DQ9 NC5 NMDA58 DQ9 NC5
57 53 57 53
DQ10 NC6 DQ10 NC6
1

NMDA3 59 NMDA59 59
NMDA4 DQ11 NMCLKA0 R89 VRAM@ NMDA60 DQ11 NMCLKA0
60 45 60 45
NMDA5 DQ12 CK NMCLKA0# 56_0402_5% NMDA61 DQ12 CK NMCLKA0#
62 46 62 46
NMDA6 DQ13 CK# NMCKEA NMDA62 DQ13 CK# NMCKEA
63 44 63 44
NMDA7 DQ14 CKE C287 VRAM@ NMDA63 DQ14 CKE
65 65
2

DQ15 NMAA13 0.01U_0402_16V7K DQ15 NMAA13

26 26
VREF_1 BA0 NMAA14 VREF_2 BA0 NMAA14
49 27 1 2 49 27
VREF BA1 VREF BA1
1 NMAA0 29 24 NMCSA0# 1 NMAA0 29 24 NMCSA0#
A0 CS# A0 CS#
1

NMAA1 30 23 NMRASA# NMAA1 30 23 NMRASA#

C288 VRAM@ NMAA2 A1 RAS# NMCASA# C289 VRAM@ NMAA2 A1 RAS# NMCASA#
31 22 31 22
0.1U_0402_16V4Z NMAA3 A2 CAS# NMWEA# R90 VRAM@ 0.1U_0402_16V4Z NMAA3 A2 CAS# NMWEA#
32 21 32 21
2 NMAA4 A3 WE# 56_0402_5% 2 NMAA4 A3 WE#
35 35
NMAA5 A4 NMAA5 A4
36 6 36 6
2

NMAA6 A5 VSSQ0 NMAA6 A5 VSSQ0

37 12 37 12
NMAA7 A6 VSSQ1 NMCLKA0# NMAA7 A6 VSSQ1
38 52 NMCLKA0# <11> 38 52
NMAA8 A7 VSSQ2 NMAA8 A7 VSSQ2
39 58 39 58
NMAA9 A8 VSSQ3 NMAA9 A8 VSSQ3
40 64 40 64
NMAA10 A9 VSSQ4 +2.5VS +2.5VS NMAA10 A9 VSSQ4
28 34 28 34
NMAA11 AP/A10 VSS0 VRAM@ NMAA11 AP/A10 VSS0
41 48 41 48
NMAA12 A11 VSS1 VRAM@ VRAM@ NMAA12 A11 VSS1
42 66 42 66
A12 VSS2 220P_0402_50V8J 1000P_0402_50V7K 220P_0402_50V8J 1000P_0402_50V7K A12 VSS2
@ HY5DU561622CT-4_TSOPII66 @ HY5DU561622CT-4_TSOPII66
2 2 1 1
2 2 1 1
C737 C740 VRAM@
C738 C739 C741 C742 C743 C744
Z ZZ Z ZZ VRAM@ 1 1 2 2
1 1 2 2 VRAM@
A 220P_0402_50V8J 1000P_0402_50V7K A

VRAM@ 220P_0402_50V8J 1000P_0402_50V7K

X 7 6 V R AM X 7 6 V R AM VRAM@

07/04 For EMI

Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
SAMSUNG@ SAMSUNG X76 VRAM HYNIX@ HYNIX X76 VRAM VGA DDR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 15 of 53
5 4 3 2 1
 A B C D E F G H

+3V_CLK (40 mils) +3V_VDD (20mils)

+3V_VDD +3VS
+3VS +3V_CLK L12
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CHB2012U121_0805
1 2 +3V_VDD 2 1
L11 1 1

0.1U_0402_16V4Z

10U_0805_10V4Z
1 CHB2012U121_0805 1
1 1 1 1 1 1 1
C292 C293 C294 C295 C296 C297 C298

C290

C291
2 2
2 2 2 2 2 2 2

10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.1U_0402_16V4Z

U10
+3VS
43 VDDCPU VDDA 39
14 VDDSRC GNDA 38

1
21 VDDSRC
L13 35
CHB2012U121_0805 VDDSRC CPUCLK0H R91
32 45 1 2 15_0402_1% CPUCLK0_H <6>
VDDATI CPUCLK8T0 CPUCLK0L R92
51 VDD_PCI CPUCLK8C0 44 1 2 15_0402_1% CPUCLK0_L <6>
48 VDDHTT CPUCLK8T1 41
C299 56 40

2
2.2U_0805_10V4Z VDDREF CPUCLK8C1
1 2 3 17_EXP@ 17_EXP@
C300 VDD48 17_EXP@ 17_EXP@
22P_0402_50V8J 12 PCIECLK0_R R93 1 2 33_0402_5% PCIECLK0 R94 1 2 49.9_0402_1% PCIECLK0
SRCCLKT7 PCIECLK0 <28>
1 2 14.31818MHz_20P_1BX14318BE1A XTALIN_CLK 1 13 PCIECLK0#_R R95 1 2 33_0402_5% PCIECLK0# R96 1 2 49.9_0402_1% PCIECLK0#
XTALOUT_CLK 2
X1 SRCCLKC7
16 PCIECLK1_R R469 1 2 33_0402_5% PCIECLK1 R470 1 2 49.9_0402_1%
PCIECLK0# <28> Express Card(17)
X2 SRCCLKT6
1

Y1 17 PCIECLK1#_R R471 1 2 33_0402_5% PCIECLK1# R472 1 2 49.9_0402_1%

SRCCLKC6 15_EXP@ 15_EXP@
6 NC SRCCLKT5 18
19 15_EXP@ 15_EXP@
SRCCLKC5 PCIECLK1
22 PCIECLK1 <28>
2

SB_SCLK SRCCLKT4 PCIECLK1#

1 2 7 23
<8,9,20,28> SB_SCLK
<8,9,20,28> SB_SDAT
SB_SDAT 8
SCLK
SDATA
SRCCLKC4
SRCCLKT3 24 SBSRCCLK_R R97 1 2 33_0402_5% SBSRCCLK R98 1 2 49.9_0402_1%
PCIECLK1# <28> Express Card(15.4)
C301 25 SBSRCCLK#_R R99 1 2 33_0402_5% SBSRCCLK# R100 1 2 49.9_0402_1%
2 22P_0402_50V8J SRCCLKC3 2
ATIGCLKT1 27
R101 1 2 33_0402_5% 52 28
<13> NB_REFCLK REF2 ATIGCLKC1 SBSRCCLK
ATIGCLKT0 30 SBSRCCLK <19>
29 SBSRCCLK#
R106 1 2 475_0402_1% 37 IREF
ATIGCLKC0
SRCCLKT0 34 SBLINKCLK_R R107 1 2 33_0402_5% SBLINKCLK R108 1 2 49.9_0402_1%
SBSRCCLK# <19> A link Express
33 SBLINKCLK#_R R109 1 2 33_0402_5% SBLINKCLK# R110 1 2 49.9_0402_1%
SRCCLKC0
@ R111
10K_0402_5% SBLINKCLK
SBLINKCLK <13>
1 2 NC_CLKSEL1# 11 50 SBLINKCLK#
<28> NC_CLKSEL0#
NC_CLKSEL0# 10
CLKREQB#
CLKREQA#
PCICLK0 SBLINKCLK# <13> A link Express

5 54 FS0 R112 1 2 33_0402_5%

GND FS0/REF0 SB_OSC_INT <20>
55 53 FS1
GND FS1/REF1 FS2
36 9
GNDSRC FS2
26
GNDSRC
20
GNDSRC R113 1
15
GNDSRC 2 33_0402_5% CLK_48M_CB <25>
31
GNDATI @ R114 1
49 4 2 33_0402_5% USBCLK_EXT <20>
GNDPCI USB_48MHz R115 1
46 47 2 33_0402_5% HTREFCLK <13>
GNDHTT HTTCLK0
42
GNDCPU

1
ICS951412AGLFT_TSSOP56 R116
51.1_0402_1%

2
3 3

+3V_CLK
EXT CLK FREQUENCY SELECT TABLE(MHZ)
1

1
FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT
R118 R119 R120 [2:1]

10K_0402_5% 10K_0402_5% 10K_0402_5% 0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved

2

FS0 0 0 1 X 100.00 X/3 X/6 48.00 Reserved

FS1
FS2 0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved
1

R121 R122 R123 1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved

1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved
@ 8.2K_0402_5% @ 8.2K_0402_5% @ 8.2K_0402_5%
2

1 1 1 200.00 100.00 66.66 33.33 48.00 Normal HAMMER operation

4
* 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Clock Generator
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 16 of 53
A B C D E F G H
 A B C D E F G H

+3VS
LCD Panel & inverter Connector

2
1 1
R124
JP6
41 42 4.7K_0402_5%
+LCDVDD GND GND D2
39 40

1
+LCDVDD 39 40 LVDSB2+ CH751H-40_SC76
37 38
37 38 LVDSB2- LVDSB2+ <13> DISPOFF#
1 35 36 1 2
C302 35 36 LVDSB2- <13> <37,38> BKOFF#
33 34
0.01U_0402_16V7K LVDSB1+ 33 34 LVDSB0+
<13> LVDSB1+ 31 32 LVDSB0+ <13>
LVDSB1- 31 32 LVDSB0- D3
<13> LVDSB1- 29 30 LVDSB0- <13>
2 29 30 CH751H-40_SC76
27 28
LVDSBC+ 27 28 LVDSA1+
<13> LVDSBC+ 25 25 26 26 LVDSA1+ <13> 1 2
LVDSBC- 23 24 LVDSA1- <13,37,38> ENABLT
<13> LVDSBC- 23 24 LVDSA1- <13>
WL_LED# 21 22
DISPOFF# 21 22 LVDSAC+
19 19 20 20 LVDSAC+ <13>
INVT_PWM 17 18 LVDSAC-
<37,38> INVT_PWM DAC_BRIG 17 18 LVDSAC- <13>
<37,38> DAC_BRIG 15 15 16 16
13 14 LVDSA2+
+5VS 13 14 LVDSA2+ <13>
EDID_CLK_LCD 11 12 LVDSA2-
<13> EDID_CLK_LCD EDID_DAT_LCD 11 12 LVDSA2- <13>
<13> EDID_DAT_LCD 9 9 10 10
7 8 LVDSA0+ B+ INVPWR_B+
INVPWR_B+ 7 8 LVDSA0- LVDSA0+ <13>
5 5 6 6
3 4 LVDSA0- <13> L14 1 2 0_0805_5%
3 4
1 1 2 2 +3VS
ACES_88242-4000 @ L15 1 2 0_0805_5%

2 2

WL_LED#

2
R581
150_0402_5%
WL_LED@

1
WL_LED@
R127
5/6 Add current limit resister

1
1K_0402_5%
WIRELESS_LED 1 2 2 Q4
<30,34,35> WIRELESS_LED
MMBT3904_SOT23

2
WL_LED@

3
R128
100K_0402_5%
WL_LED@

1
3 3
+LCDVDD +5VALW

+LCDVDD +3VS
1

Q5
2

R129 SI2301BDS_SOT23
R130
100_0402_1% 100K_0402_5% 1 3
S
D
1 2

D
G
2

2N7002_SOT23 0.047U_0402_16V4Z
2
Q6 G
S 1 1 1 1
3

C303 C304 C305

C306
1

4.7U_0805_10V4Z 4.7U_0805_10V4Z
Q7 2 2 2 2
DTC124EK_SC59
ENVDD 2 0.1U_0402_16V4Z
<13> ENVDD
3

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
LVDS Panel Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 17 of 53
A B C D E F G H
 A B C D E

+R_CRT_VCC , +CRTVDD (40mils)

+5VS +CRTVDD
+R_CRT_VCC
D6 F1
2 1 1 2
CRT CONNECTOR RB491D_SOT23 1.1A_6VDC_FUSE 1
C307
0.1U_0402_16V4Z
6/11 change D6 from RB411to RB491(higher 2
current rating)
1 JP8 1
SUYIN_070112FR015S222XU
L16 6
FCM2012C-800_0805 M_SEN# 11
CRT_R <37,38> M_SEN# CRTL_R
<13> CRT_R 1 2 1
L17 7
FCM2012C-800_0805 12 16
CRT_G 1 2 CRTL_G 2 17
<13> CRT_G
L18 8
FCM2012C-800_0805 13
CRT_B 1 2 CRTL_B 3
<13> CRT_B

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K

22P_0402_25V8K

22P_0402_25V8K

22P_0402_25V8K
+CRTVDD 9

2
75_0402_5%

75_0402_5%

75_0402_5%
1 1 1 1 1 1 14
4

33_0402_5%
+CRTVDD

R134 4.7K_0402_5%

R135 4.7K_0402_5%
10

33_0402_5%
R131

R132

R133
C314 15
2 2 2 2 2 2

C308

C309

C310

C311

C312

C313
1 2 5

1
Q8
5

0.1U_0402_16V4Z U11 2N7002_SOT23

OE#
P

CR T_HSYNC CR T_HSYNC_R CR T_HSYNCRFL 3VDDCDA

S
<13> CRT_HSYNC 2 A Y 4 1 2 1 2 1 3 3VDDCDA <13>
R136 L19
G

220P_0402_25V8K R552

R553
74AHCT1G125GW_SOT353-5 20_0402_5% FBM-L11-160808-800LMT_0603 Q9
2N7002_SOT23

G
3

2
1 2 1 2 C RT_VSYNCRFL
R137 L20 3VDDCCL

S
1 3 3VDDCCL <13>

10P_0402_50V8K

C317 10P_0402_50V8K
20_0402_5% FBM-L11-160808-800LMT_0603 1 1 1 1

C318 220P_0402_25V8K
R138 R139

G
2
5

U12 2 2 2 2

C315
4.7K_0402_5%
OE#
P

2 CRT_VSYNC CRT_VSYNC_R 2
<13> CRT_VSYNC 2 A Y 4
+3VS
G

C316
74AHCT1G125GW_SOT353-5
4.7K_0402_5%
3

TV-Out Connector
S-Video
L21
FLM1608081R8K_0603
TV_LUMA 1 2 LUMA_CL
<13,40> TV_LUMA
L22 JP9
FLM1608081R8K_0603 1
TV_CRMA CRMA_CL 1
<13,40> TV_CRMA 1 2 2
3 2 3
3
3
4
L23 4
5
FLM1608081R8K_0603 5
6 8
TV_COMPS COMPS_CL 6 GND
1 2 7 9
<13,40> TV_COMPS 7 GND
270P_0402_50V7K

270P_0402_50V7K

270P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K
SUYIN_030006FR007T107ZL
1

1
75_0402_1%

75_0402_1%

75_0402_1%

1 1 1 1 1 1
R140

R141

R142

C319

C320

C321

C322

C323

C324
2 2 2 2 2 2
2

R143
1 2 TVGND

0_0805_5%

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
CRT Connector & TV-OUT CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 18 of 53
A B C D E
 5 4 3 2 1

8.2K_0402_5%
5/11 EMI change
R145 1 2 U14A
L4 PCICLK0_R R146 1 2 39_0402_5%
+3VS
A_RST# AH8 A_RST# SB400 PCICLK0
PCICLK1 L3
L2
PCICLK1_R @ R451
PCICLK2_R R147
1
1
2
2
39_0402_5%
39_0402_5%
CLK_PCI_PCM <25>
CLK_PCI_TPM <35>
CLK_PCI_LAN <23,29>
SBSRCCLK PCICLK2 PCICLK3_R R148 39_0402_5%
<16> SBSRCCLK L27 L1 1 2 CLK_PCI_MINI <23,30>
SBSRCCLK# M27 PCIE_RCLKP PCICLK3 PCICLK4_R R149 39_0402_5%
<16> SBSRCCLK# M4 1 2 CLK_PCI_EC <23,37,38>
PCIE_RCLKN PCICLK4 CLK_PCI_SIO_R

PC I CLKS
RP50 M3
D PCICLK5 CLK_PCI_SIO_R <23,35> D
1 8 PCI_PIRQA# SB_RX0P C325 1 2 0.01U_0402_16V7K SB_RX0P_C M30 M2 CLK_PCI6
PCI_PIRQB# <12> SB_RX0P SB_RX0N SB_RX0N_C PCIE_TX0P PCICLK6 CLK_PCI7 CLK_PCI6 <23>
2 7 C326 1 2 0.01U_0402_16V7K N30 M1
PCI_PIRQC# <12> SB_RX0N SB_RX1P SB_RX1P_C PCIE_TX0N PCICLK7 CLK_PCI8 CLK_PCI7 <23>
3 6 C327 1 2 0.01U_0402_16V7K K30 N4
PCI_PIRQD# <12> SB_RX1P SB_RX1N SB_RX1N_C PCIE_TX1P PCICLK8 PCICLK9_R CLK_PCI8 <23>
4 5 C328 1 2 0.01U_0402_16V7K L30 N3 R150 1 2 22_0402_5%
<12> SB_RX1N PCIE_TX1N PCICLK9 PCICLKFB
H30 N2 C329 1 2 @ 0.1U_0402_16V4Z
8.2K_0804_8P4R_5% PCIE_TX2P PCICLK_FB
J30
PCIE_TX2N PCIRST# +3VALW
F30 AJ7
RP51 PCIE_TX3P PCIRST# PCI_AD0
G30 W3
PCI_PIRQF# PCIE_TX3N AD0/ROMA18 PCI_AD1
1 8 AD1/ROMA17
Y2
2 7 PCI_PIRQE# SB_TX0P M29 W4 PCI_AD2 C330 1 2 0.1U_0402_16V4Z
PCI_PIRQG# <12> SB_TX0P SB_TX0N PCIE_RX0P AD2/ROMA16 PCI_AD3
3 6 <12> SB_TX0N N29
PCIE_RX0N AD3/ROMA15
Y3
4 5 PCI_PIRQH# SB_TX1P M28 V1 PCI_AD4
<12> SB_TX1P PCIE_RX1P AD4/ROMA14

1
8.2K_0402_5%
SB_TX1N PCI_AD5

14
<12> SB_TX1N N28 PCIE_RX1N AD5/ROMA13 Y4

1
8.2K_0804_8P4R_5% R151 1 2 49.9_0402_1% SB_TX2P J29 V2 PCI_AD6
PCIE_RX2P AD6/ROMA12

R152
R153 1 2 49.9_0402_1% SB_TX2N K29 W2 PCI_AD7

OE#
P
SB_TX3P PCIE_RX2N AD7/ROMA11 PCI_AD8
RP52 R154 1 2 49.9_0402_1% J28 AA4 2 3 R155 1 2 33_0402_5% PCI_RST# PCI_RST# <25,27,29,30,35,37,38>
PCI_REQ#0 R156 49.9_0402_1% SB_TX3N PCIE_RX3P AD8/ROMA9 PCI_AD9 I O
1 8 1 2 K28 V4

2
PCIE_RX3N AD9/ROMA8

G
2 7 PCI_REQ#1 150_0402_1% AA3 PCI_AD10 U44A
PCI_REQ#2 L24 R157 AD10/ROMA7 PCI_AD11
3 6 2 1 G27 U1

7
PCI_REQ#3 PCIE_VDDR R158 PCIE_CALRP AD11/ROMA6 PCI_AD12
4 5 +1.8VS 2 1 2 1 H27 AA2
150_0402_1% PCIE_CALRN AD12/ROMA5 PCI_AD13
U2

PCI EXPRESS INTERFACE

8.2K_0804_8P4R_5% FBM-L11-321611-260-LMT_1206 AD13/ROMA4 PCI_AD14 SN74LVC125APWLE_TSSOP14
2 1 G28 AA1
R159 4.12K_0402_1% PCIE_CALI AD14/ROMA3 PCI_AD15
AD15/ROMA2 U3
RP53 C331 1 2 1U_0603_10V4Z PCIE_PVDD R30 T4 PCI_AD16
PCI_GNT#0 PCIE_PVDD AD16/ROMD0 PCI_AD17
1 8 AC1
PCI_GNT#1 C332 1 AD17/ROMD1 PCI_AD18
2 7 2 10U_0805_10V4Z F26 PCIE_VDDR_1 AD18/ROMD2 R2
3 6 PCI_GNT#2 R29 AD4 PCI_AD19 PC I_AD[0..31]
PCIE_VDDR_2 AD19/ROMD3 PCI_AD[0..31] <23,25,29,30>
4 5 PCI_GNT#3 C333 1 2 0.1U_0402_16V4Z G26 R3 PCI_AD20

PCI INTERFACE
L25 PCIE_VDDR_3 AD20/ROMD4 PCI_AD21
P26 PCIE_VDDR_4 AD21/ROMD5 AD3
8.2K_0804_8P4R_5% 2 1 K26 R4 PCI_AD22
+1.8VS PCIE_VDDR_5 AD22/ROMD6
L26 AD2 PCI_AD23
PCIE_VDDR_6 AD23/ROMD7

4
RP54 FBM-L11-321611-260-LMT_1206 P28 P2 PCI_AD24 U44B R144
C PCI_REQ#4 PCIE_VDDR_7 AD24 PCI_AD25 33_0402_5% C
1 8 N26 AE3

OE#
PCI_GNT#4 C335 1 PCIE_VDDR PCIE_VDDR_8 AD25 PCI_AD26 A_RST#
2 7 2 22U_1206_10V4Z P27 P3 5 6 1 2 NB_RST# <13,24,28,35>
PCI_REQ#5 PCIE_VDDR_9 AD26 PCI_AD27 I O
3 6 AD27 AE2
4 5 PCI_GNT#5 C336 1 2 0.1U_0402_16V4Z H28 P4 PCI_AD28
C337 0.1U_0402_16V4Z PCIE_VSS_1 AD28 PCI_AD29 SN74LVC125APWLE_TSSOP14
1 2 F29 PCIE_VSS_2 AD29 AF2
8.2K_0804_8P4R_5% C338 1 2 0.1U_0402_16V4Z H29 N1 PCI_AD30 +3VS
C339 0.1U_0402_16V4Z PCIE_VSS_3 AD30 PCI_AD31
1 2 H26 PCIE_VSS_4 AD31 AF1
1 2 PCI_REQ#6 C340 1 2 0.1U_0402_16V4Z F27 V3 PCI_CBE#0 PCI_CBE#0 <25,29,30>
R161 C341 0.1U_0402_16V4Z PCIE_VSS_5 CBE0#/ROMA10 PCI_CBE#1 SIRQ R163 1
1 2 G29
PCIE_VSS_6 CBE1#/ROMA1
AB4 PCI_CBE#1 <25,29,30> 2 10K_0402_5%
8.2K_0402_5% C342 1 2 0.1U_0402_16V4Z L29 AC2 PCI_CBE#2
PCIE_VSS_7 CBE2#/ROMWE# PCI_CBE#2 <25,29,30>
1 2 PCI_GNT#6 C343 1 2 0.1U_0402_16V4Z J26 AE4 PCI_CBE#3
PCIE_VSS_8 CBE3# PCI_CBE#3 <25,29,30>
R162 L28 T3 PCI_FRAME# LDRQ0# R164 1 2 10K_0402_5%
PCIE_VSS_9 FRAME# PCI_FRAME# <25,29,30>
8.2K_0402_5% J27 AC4 PCI_DEVSEL# LDRQ1# R165 1 2 10K_0402_5%
PCIE_VSS_10 DEVSEL#/ROMA0 PCI_DEVSEL# <25,29,30>
N27 AC3 PCI_IR DY# PCI_IRDY# <25,29,30>
RP55 PCIE_VSS_11 IRDY# PC I_TRDY#
M26 T2 PCI_TRDY# <25,29,30>
PCI_FRAME# PCIE_VSS_12 TRDY#/ROMOE# PCI_PAR LPC_AD0 R167 100K_0402_5%
1 8 K27 U4 1 2
2 7 PCI_IR DY# PCIE_PVDD (20mils) P29
PCIE_VSS_13 PAR/ROMA19
T1 PCI_STOP#
PCI_PAR <25,29,30>
PCI_STOP# <25,29,30> LPC_AD1 R168 1 2 100K_0402_5%
PC I_TRDY# PCIE_VSS_14 STOP# PCI_PERR# LPC_AD2 R170 100K_0402_5%
3 6 P30 AB2 1 2
4 5 PCI_STOP# PCIE_VDDR (40mils) PCIE_VSS_15 PERR#
SERR#
AB3 PCI_SERR#
PCI_PERR# <25,29,30>
PCI_SERR# <25,29,30>
LPC_AD3 R172 1 2 100K_0402_5%
AJ8 AF4 PCI_REQ#0
8.2K_0804_8P4R_5% CPU_STP#/DPSLP# REQ0# PCI_REQ#1
AK7 AF3 PCI_REQ#1 <29>
PCI_PIRQA# PCI_STP# REQ1# PCI_REQ#2
AG5 AG2 PCI_REQ#2 <25>
RP56 PCI_PIRQB# INTA# REQ2# PCI_REQ#3
AH5 AG3 PCI_REQ#3 <30>
PCI_SERR# PCI_PIRQC# INTB# REQ3#/PDMA_REQ0# PCI_REQ#4
1 8 AJ5 AH1
PCI_PAR PCI_PIRQD# INTC# REQ4#/PLL_BP33/PDMA_REQ1# PCI_REQ#5
2 7 AH6 AH2
PCI_DEVSEL# PCI_PIRQE# INTD# REQ5#/GPIO13 PCI_REQ#6
3 6 <25> PCI_PIRQE# AJ6 AH3
LOCK# PCI_PIRQF# INTE#/GPIO33 REQ6#/GPIO31 PCI_GNT#0
4 5 <30> PCI_PIRQF# AK6
INTF#/GPIO34 GNT0#
AJ2
<29> PCI_PIRQG# PCI_PIRQG# AG7 AK2 PCI_GNT#1 PCI_GNT#1 <29>
8.2K_0804_8P4R_5% PCI_PIRQH# INTG#/GPIO35 GNT1# PCI_GNT#2
<25> PCI_PIRQH# AH7 AJ3 PCI_GNT#2 <25>
C344 INTH#/GPIO36 GNT2# PCI_GNT#3
AK3 PCI_GNT#3 <30>
PCI_PERR# 18P_0402_50V8J GNT3#/PLL_BP66/PDMA_GNT0# PCI_GNT#4
2 1 AG4
R166 GNT4#/PLL_BP50/PDMA_GNT1# PCI_GNT#5
1 2 AH4
B 8.2K_0402_5% GNT5#/GPIO14 PCI_GNT#6 B
AJ4
GNT6#/GPIO32
20M_0603_5%

Y2 SB_32KHI B2 AG1 PCI_CLKRUN#

X1 CLKRUN# PCI_CLKRUN# <35>
2

2 1 PCI_CLKRUN# 4 3 AB1 LOCK#

R169 OUT NC LOCK#
10K_0402_5% 1 2 SB_32KH0 B1
IN NC X2
XTAL
R171

R173 AG25 LPC_AD0

1

LAD0 LPC_AD1 LPC_AD0 <35,37,38>

20M_0603_5% 32.768KHZ_12.5PF_6H03200468 AH25
LAD1 LPC_AD2 LPC_AD1 <35,37,38>
2 1 1 2 C29 AJ25 LPC_AD2 <35,37,38>
CPU_PG/LDT_PG LAD2 LPC_AD3
A28 AH24 LPC_AD3 <35,37,38>
C345 INTR/LINT0 LAD3 LPC_FRAME#
C28 AG24 LPC_FRAME# <35,37,38>
NMI/LINT1 LFRAME#
L PC

18P_0402_50V8J B29 AH26 LDRQ0# BATT1

INIT# LDRQ0# LDRQ1# LDRQ0# <35>
D29 AG26
LDTSTOP# SMI# LDRQ1#
<4,13> LDTSTOP# E4
SLP#/LDT_STP# SIRQ
B30 AK27 SIRQ <25,35,37,38>
IGNNE# SERIRQ
C PU

F28
A20M#
E28
ALLOW_LDTSTOP FERR#
<13> ALLOW_LDTSTOP E29
STPCLK#/ALLOW_LDTSTP CR2032 RTC BATTERY
H_PWRGD D25 C2 RTC_CLK
<6> H_PWRGD LDT_PG/SSMUXSEL/GPIO0 RTCCLK AUTO_ON# RTC_CLK <23>
E27 F3 AUTO_ON# <23>
BMREQ# DPRSLPVR RTC_IRQ#/ACPWR_STRAP
<13> BMREQ# D27
H_RST# BMREQ# JP10
<6> H_RST# D28 A2 +RTCVCC
LDT_RST# VBAT
A1
RTC_GND
2
RTC

CHS-215SB400-02_BGA564 C346 C347 W=20mils

+RTCVCC R174
1K_0402_5%
BATT1.1
+ -
1U_0603_10V4Z 1 2 1
+ -
2
1 W=20mils

2
0.1U_0402_16V4Z J2

JOPEN

1
A SUYIN_060003FA002TX00NL~D A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
SB400-PCI_EXP/PCI/LPC/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 19 of 53
5 4 3 2 1
 5 4 3 2 1

+3VALW

R177 1 2 10K_0402_5% NC_CP#

R178 1 2 4.7K_0402_5% SLP_S3#

R179 1 2 4.7K_0402_5% SLP_S5#

U14B
D R181 1 PCIE_PME# D
2 4.7K_0402_5%

R182 1 2 4.7K_0402_5% EC_FLASH#

<37,38> EC_THERM#
EC_THERM# C6
SB400
48M_X1/USBCLK
A15
B15
USBCLK_EXT <16>
EC_FLASH# TALERT#/TEMP_ALERT#/GPIO10 48M_X2 11.8K_0603_1% 1 R183
<39> EC_FLASH# D5 C15 2
R184 1 SYS_RESET# EC_SWI# BLINK/GPM6# USB_RCOMP USB_VREFOUT
2 10K_0402_5%

ACPI/WAKE UP EVENTS
<37,38> EC_SWI# C4 D16
NC_CP# PCI_PME#/GEVENT4# USB_VREFOUT T19 PAD
<28> NC_CP# D3 C16
R185 1 BT_ON# SLP_S3# RI#/EXTEVNT0# USB_ATEST1
2 10K_0402_5% <37,38> SLP_S3# B4 D15
SLP_S5# SLP_S3# USB_ATEST0 OVCUR#0
<37,38> SLP_S5# E3 B8 OVCUR#0 <34>
R186 1 BT_DET# PWRBTN_OUT# SLP_S5# USB_OC0#/GPM0# BT_DET#
2 10K_0402_5% <37,38> PWRBTN_OUT# B3
PWR_BTN# USB_OC1#/GPM1#
C8 BT_DET# <34>
SB_PWRGD C3 C7 LID_OUT#
S3_STATE <42> SB_PWRGD SUS_STAT# PWR_GOOD USB_OC2#/FANOUT1/GPM2# OVCUR#3 LID_OUT# <37,38>
R187 1 2 10K_0402_5% D4 B7
<13> SUS_STAT# SUS_STAT# USB_OC3#/GPM3# OVCUR#4 OVCUR#3 <34>
R188 1 2 10K_0402_5% F2 B6
KB_RST# TEST1 USB_OC4#/GPM4# EC_SCI# OVCUR#4 <35>
@ R556 1 2 10K_0402_5% R189 1 2 10K_0402_5% E2 A6
TEST0 USB_OC5#/GPM5# EC_SCI# <37,38>
EC_GA20 AJ26 B5 BT_ON# BT_ON# <34>
EC_RSMRST# <37,38> EC_GA20 KB_RST# GA20IN USB_OC6#/FAN_ALERT#/GEVENT6# EC_SMI#
@ R557 1 2 10K_0402_5% AJ27 A5
<37,38> KB_RST# KBRST# USB_OC7#/CASE_ALERT#/GEVENT7# EC_SMI# <37,38>
H_THERMTRIP# D6
<6> H_THERMTRIP# WL_ON SMBALERT#/THRMTRIP#/GEVENT2# USBP7+
<30> WL_ON 2 1 D7 C5 LPC_PME#/GEVENT3# USB_HSDP7+ A11 USBP7+ <28>
LPC_SMI# USBP7-

USB INTERFACE
A25 B11
S3_STATE CH751H-40_SC76 D8
LPC_SMI#/EXTEVNT1# USB_HSDM7- USBP7- <28> Express Card 15.4
+3VS SYS_RESET# VOLT_ALERT#/S3_STATE/GEVENT5# USBP6+
D7 SYS_RESET#/GPM7# USB_HSDP6+ A10 USBP6+ <34>
PCIE_PME# D2 B10 USBP6-
<28> PCIE_PME# WAKE#/GEVENT8# USB_HSDM6- USBP6- <34> Bluetooth
R190 1 2 2.2K_0402_5% SB_SCLK EC_RSMRST# D1 A14 USBP5+
<37,38> EC_RSMRST# RSMRST# USB_HSDP5+ USBP5- USBP5+ <35>

CLK / RST
B14
R191 1 2 2.2K_0402_5% SB_SDAT
<16> SB_OSC_INT
SB_OSC_INT A23
USB_HSDM5- USBP5- <35> Right side USB
14M_X1/OSC USBP4+
USB_HSDP4+ A13 USBP4+ <35>
R192 1 2 10K_0402_5% LPC_SMI# 14M_X2 B23 B13 USBP4-
14M_X2 USB_HSDM4- USBP4- <35> Right side USB
R193 1 2 10K_0402_5% AGP_STP# AK24 A18 USBP3+
SIO_CLK USB_HSDP3+ USBP3+ <34>
B18 USBP3-
R194 1 2 10K_0402_5% AGP_BUSY# R195 1 2 10K_0402_5% B25
USB_HSDM3- USBP3- <34> Left side USB
R196 1 ROM_CS#/GPIO1
2 10K_0402_5% C25 GHI#/GPIO6 USB_HSDP2+ A17
C R197 1 C
2 10K_0402_5% C23 VGATE/GPIO7 USB_HSDM2- B17
AGP_STP# D24
AGP_BUSY# AGP_STP#/GPIO4 USBP1+
D23 AGP_BUSY#/GPIO5 USB_HSDP1+ A21 USBP1+ <40>
EXP_RST# A27 B21 USBP1-
<28>
<31>
EXP_RST#
SB_SPKR
SB_SPKR C24
FANOUT0/GPIO3
SPKR/GPIO2
USB_HSDM1- USBP1- <40> Docking

GPIO
SB_SCLK A26 A20 USBP0+
<8,9,16,28> SB_SCLK SCL0/GPOC0# USB_HSDP0+ USBP0+ <34>
SB_SDAT B26 B20 USBP0-
+3VALW <8,9,16,28> SB_SDAT
R199 1 2 10K_0402_5% B27
SDA0/GPOC1# USB_HSDM0- USBP0- <34> Left side USB
R200 DDC1_SCL/GPIO9
1 2 10K_0402_5% C26
DDC1_SDA/GPIO8
R201 1 2@ 10K_0402_5% C27 C21 AVDDTX
R202 1 AC97_RST# DDC2_SCL/GPIO11 AVDDTX_0
2 10K_0402_5% R203 1 2 10K_0402_5% D26
DDC2_SDA/GPIO12 AVDDTX_1
C18
D13 L26 FBM-L11-321611-260-LMT_1206
R204 1 10K_0402_5% AVDDTX_2
2 AVDDTX_3
D10 2 1 +3VALW
R205 1 2 10K_0402_5% AC97_BITCLK +3VS R206 1 2@ 10K_0402_5% D20 AVDDRX
AVDDRX_0 AVDDTX C350 1
J2
NC1 AVDDRX_1
D17 2 10U_0805_10V4Z
R207 1 2 10K_0402_5% AC97_SDIN0 K3 C14
NC4 AVDDRX_2

(NOT USED)
J3 C11 C351 1 2 1U_0603_10V4Z
R208 1 2 10K_0402_5% AC97_SDIN1 check ATI for 2'nd hdd K2
NC3 AVDDRX_3
NC2 AVDDC C352 1
A16 2 0.1U_0402_16V4Z
R209 1 AC97_SDIN2 AVDDC
2 8.2K_0402_5% C353 1 2 0.1U_0402_16V4Z
B16 C354 1 2 0.1U_0402_16V4Z
R198 1 EXP_RST# AVSSC
2 10K_0402_5%
A9
AC97_BITCLK AVSS_USB_1
<31> AC97_BITCLK G1 A12
R210 1 AC_BITCLK AVSS_USB_2
<23,31> AC97_SDOUT 2 33_0402_5% G2 A19
AC97_SDIN0 AC_SDOUT AVSS_USB_3 L27 FBM-L11-321611-260-LMT_1206
<31> AC97_SDIN0 H4 A22
AC97_SDIN1 AC_SDIN0 AVSS_USB_4
G3 B9 2 1 +3VALW
AC97_SDIN2 AC_SDIN1 AVSS_USB_5
G4 B12
R211 1 AC_SDIN2 AVSS_USB_6 AVDDRX
2 33_0402_5% H1 B19 C355 1 2 10U_0805_10V4Z

USB PWR
AC 97
<31> AC97_SYNC AC97_RST# AC_SYNC AVSS_USB_7
<31> AC97_RST# H3 B22
SB_SPDIFO AC_RST# AVSS_USB_8 C356 1
<23,40> SB_SPDIFO H2 C9 2 1U_0603_10V4Z
C357 1 SB_OSC_INT SPDIF_OUT AVSS_USB_9
2@ 20P_0402_50V8J C10
B AVSS_USB_10 C358 1 B
AVSS_USB_11
C12 2 0.1U_0402_16V4Z
1

C13 C359 1 2 0.1U_0402_16V4Z

Y4 R212 AVSS_USB_12 C360 1
AVSS_USB_13
C17 2 0.1U_0402_16V4Z
@ 1M_0402_5% C19
@14.31818MHz_20P_1BX14318BE1A AVSS_USB_14
C20
2

AVSS_USB_15
C22
1

C361 1 14M_X2 AVSS_USB_16

2 @20P_0402_50V8J D9
AVSS_USB_17 L28 FBM-L11-321611-260-LMT_1206
D11
AVSS_USB_18 AVDDC
D12 2 1 +3VALW
AVSS_USB_19
D14
AVSS_USB_20 C362 1
AVSS_USB_21
D18 2 10U_0805_10V4Z
D19
AVSS_USB_22 C363 1
AVSS_USB_23
D21 2 1U_0603_10V4Z
D22
GPIO12 GPIO11 AVSS_USB_24 C364 1 2 0.1U_0402_16V4Z
HYNIX 128MB 0 1 CHS-215SB400-02_BGA564
*
SAMSUMG 128MB 1 1
AVDDC (20mils)
No VRAM 0 0 AVDDTX , AVDDRX (40mils)
Reserved 1 0

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
SB400-USB/ACPI/AC97/GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 20 of 53
5 4 3 2 1
 5 4 3 2 1

D U14C D

AK22
AJ22
SATA_TX0+
SATA_TX0- SB400 PIDE_IORDY
AD30
AE28
PD_IORDY
PD_IRQA PD_IORDY <24>
PD_IRQA <24>
PIDE_IRQ PD_A0
AK21 AD27 PD_A0 <24>
SATA_RX0- PIDE_A0 PD_A1
AJ21 AC27 PD_A1 <24>
SATA_RX0+ PIDE_A1 PD_A2
AD28 PD_A2 <24>
PIDE_A2 PD_DACK#
AK19 AD29 PD_DACK# <23,24>
SATA_TX1+ PIDE_DACK# PD_DREQ#
AJ19 AE27 PD_DREQ# <24>
SATA_TX1- PIDE_DRQ PD_IOR#
AE30 PD_IOR# <24>
PIDE_IOR# PD_IOW#
AK18 SATA_RX1- PIDE_IOW# AE29 PD_IOW# <24>
AJ18 AC28 PD_CS#1
SATA_RX1+ PIDE_CS1# PD_CS#1 <24>
AC29 PD_CS#3
PIDE_CS3# PD_CS#3 <24> PD _D[0..15]
AK14 SATA_TX2+ PD_D[0..15] <24>
AJ14 AF29 PD_D0
SATA_TX2- PIDE_D0 PD_D1
PIDE_D1 AF27
PD_D2

PRIMARY ATA 66/100

AK13 SATA_RX2- PIDE_D2 AG29
AJ13 AH30 PD_D3
SATA_RX2+ PIDE_D3 PD_D4

SERIAL ATA
PIDE_D4 AH28
AK11 AK29 PD_D5
SATA_TX3+ PIDE_D5 PD_D6
AJ11 SATA_TX3- PIDE_D6 AK28
AH27 PD_D7
PIDE_D7 PD_D8
AK10 SATA_RX3- PIDE_D8 AG27
AJ10 AJ28 PD_D9
SATA_RX3+ PIDE_D9 PD_D10
PIDE_D10 AJ29
AJ15 AH29 PD_D11
SATA_CAL PIDE_D11 PD_D12
PIDE_D12 AG28
AJ16 AG30 PD_D13
SATA_X1 PIDE_D13 PD_D14
PIDE_D14 AF30
AK16 AF28 PD_D15
SATA_X2 PIDE_D15
C SD_IORDY C
AK8 SATA_ACT# SIDE_IORDY V29 SD_IORDY <24>
T27 SD_IRQA
SIDE_IRQ SD_SBA0 SD_IRQA <24>
AH15 PLLVDD_SATA SIDE_A0 T28 SD_SBA0 <24>
U29 SD_SBA1
SIDE_A1 SD_SBA2 SD_SBA1 <24>
AH16 XTLVDD_SATA SIDE_A2 T29 SD_SBA2 <24>
V30 SD_DACK#
SIDE_DACK# SD_DACK# <24>
AG10 U28 SD_DREQ#
AVDD_SATA_1 SIDE_DRQ SD_DREQ# <24>
AG14 W29 SD_SIOR#
AVDD_SATA_2 SIDE_IOR# SD_SIOW# SD_SIOR# <24>
AH12 W30 SD_SIOW# <24>
AVDD_SATA_3 SIDE_IOW# SD_SCS1#
AG12 R27 SD_SCS1# <24>
AVDD_SATA_4 SIDE_CS1# SD_SCS3#
AG18 R28 SD_SCS3# <24>
AVDD_SATA_5 SIDE_CS3# SD _D[0..15]
AG21 SD_D[0..15] <24>
AVDD_SATA_6

SECONDARY ATA 66/100

AH18 V28 SD_D0
AVDD_SATA_7 SIDE_D0/GPIO15 SD_D1
AG20 W28
AVDD_SATA_8 SIDE_D1/GPIO16 SD_D2
Y30
SIDE_D2/GPIO17 SD_D3
AG9 AA30
AVSS_SATA_1 SIDE_D3/GPIO18 SD_D4
AF10 Y28
AVSS_SATA_2 SIDE_D4/GPIO19 SD_D5
AF11 AA28
AVSS_SATA_3 SIDE_D5/GPIO20 SD_D6
AF12 AB28
AVSS_SATA_4 SIDE_D6/GPIO21 SD_D7
AF13 AB27
AVSS_SATA_5 SIDE_D7/GPIO22

SERIAL ATA POWER

AF14 AB29 SD_D8
AVSS_SATA_6 SIDE_D8/GPIO23 SD_D9
AF15 AA27
AVSS_SATA_7 SIDE_D9/GPIO24 SD_D10
AF16 Y27
AVSS_SATA_8 SIDE_D10/GPIO25 SD_D11
AF17 AA29
AVSS_SATA_9 SIDE_D11/GPIO26 SD_D12
AF18 W27
AVSS_SATA_10 SIDE_D12/GPIO27 SD_D13
AF19 Y29
AVSS_SATA_11 SIDE_D13/GPIO28 SD_D14
AF20 V27
AVSS_SATA_12 SIDE_D14/GPIO29 SD_D15
AF21 U27
AVSS_SATA_13 SIDE_D15/GPIO30
AF22
AVSS_SATA_14
AH9
AVSS_SATA_15
AG11 AG13
AVSS_SATA_16 AVSS_SATA_33
AG15 AH22
B AVSS_SATA_17 AVSS_SATA_34 B
AG17 AK12
AVSS_SATA_18 AVSS_SATA_35
AG19 AH11
AVSS_SATA_19 AVSS_SATA_36
AG22 AJ17
AVSS_SATA_20 AVSS_SATA_37
AG23 AH14
AVSS_SATA_21 AVSS_SATA_38
AF9 AH19
AVSS_SATA_22 AVSS_SATA_39
AH17 AJ20
AVSS_SATA_23 AVSS_SATA_40
AH23 AH21
AVSS_SATA_24 AVSS_SATA_41
AH13 AJ9
AVSS_SATA_25 AVSS_SATA_42
AH20 AG16
AVSS_SATA_26 AVSS_SATA_43
AK9 AK15
AVSS_SATA_27 AVSS_SATA_44
AJ12 AK20
AVSS_SATA_28 AVSS_SATA_45
AK17
AVSS_SATA_29
AK23
AVSS_SATA_30
AH10
AVSS_SATA_31
AJ23
AVSS_SATA_32

CHS-215SB400-02_BGA564

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
SB400-IDE/SATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 21 of 53
5 4 3 2 1
 +3VS
U14D

C365 1 2 22U_1206_10V4Z A30 E19

C366 1 2 0.1U_0402_16V4Z
D30
E24
VDDQ_1
VDDQ_2 SB400 VSS_12
VSS_13
E22
E23
C367 0.1U_0402_16V4Z VDDQ_3 VSS_14
1 2 E25
VDDQ_4 VSS_15
E26
C368 1 2 0.1U_0402_16V4Z J5 E30
C369 0.1U_0402_16V4Z VDDQ_5 VSS_16
1 2 K1
VDDQ_6 VSS_17
F1
C370 1 2 0.1U_0402_16V4Z K5 F4
C371 0.1U_0402_16V4Z VDDQ_7 VSS_18
1 2 N5 G5
C372 0.1U_0402_16V4Z VDDQ_8 VSS_19
1 2 P5 H5
C373 0.1U_0402_16V4Z VDDQ_9 VSS_20
1 2 R1 J1
C374 0.1U_0402_16V4Z VDDQ_10 VSS_21
1 2 U5 J4
C375 0.1U_0402_16V4Z VDDQ_11 VSS_22
1 2 U26
VDDQ_12 VSS_23
K4
C376 1 2 0.1U_0402_16V4Z U30 L5
C377 0.1U_0402_16V4Z VDDQ_13 VSS_24
1 2 V5 M5
C378 0.1U_0402_16V4Z VDDQ_14 VSS_25
1 2 V26 P1
C379 0.1U_0402_16V4Z VDDQ_15 VSS_26
1 2 Y1 VDDQ_16 VSS_27 R5
C380 1 2 0.1U_0402_16V4Z Y26 R26
C381 0.1U_0402_16V4Z VDDQ_17 VSS_28
1 2 AA5 VDDQ_18 VSS_29 T5
C382 1 2 0.1U_0402_16V4Z AA26 T26
VDDQ_19 VSS_30
AB5 VDDQ_20 VSS_31 T30
AC30 VDDQ_21 VSS_32 W1
AD5 VDDQ_22 VSS_33 W5
AD26 VDDQ_23 VSS_34 W26
AE1 VDDQ_24 VSS_35 Y5
+1.8VS AE5 AB26
VDDQ_25 VSS_36
AE26 VDDQ_26 VSS_37 AB30
AF6 VDDQ_27 VSS_38 AC5
C383 1 2 22U_1206_10V4Z AF7 AC26
C384 1 VDDQ_28 VSS_39
2 22U_1206_10V4Z AF24 AD1
VDDQ_29 VSS_40
AF25 VDDQ_30 VSS_41 AF5
AK1 VDDQ_31 VSS_42 AF8
C385 1 2 0.1U_0402_16V4Z AK4 AF23
C386 0.1U_0402_16V4Z VDDQ_32 VSS_43
1 2 AK26 VDDQ_33 VSS_44 AF26
C387 1 2 0.1U_0402_16V4Z AK30 AG8
C388 0.1U_0402_16V4Z VDDQ_34 VSS_45
1 2 VSS_46 AJ1
C389 1 2 0.1U_0402_16V4Z M12 AJ24

POWER
C390 0.1U_0402_16V4Z VDD_1 VSS_47
1 2 M13 VDD_2 VSS_48 AJ30
C391 1 2 0.1U_0402_16V4Z M18 AK5
C392 0.1U_0402_16V4Z VDD_3 VSS_49
1 2 M19 VDD_4 VSS_50 AK25
C393 1 2 0.1U_0402_16V4Z N12 M14
C394 0.1U_0402_16V4Z VDD_5 VSS_51
1 2 N13 VDD_6 VSS_52 M15
C395 1 2 0.1U_0402_16V4Z N18 M16
C396 0.1U_0402_16V4Z VDD_7 VSS_53
1 2 N19 VDD_8 VSS_54 M17
V12 N14
VDD_9 VSS_55
V13 N15
VDD_10 VSS_56
V18 N16
VDD_11 VSS_57
V19 N17
+3VALW VDD_12 VSS_58
W12 P12
VDD_13 VSS_59
W13 P13
VDD_14 VSS_60
W18 P14
C397 1 VDD_15 VSS_61
2 22U_1206_10V4Z W19
VDD_16 VSS_62
P15
P16
C398 0.1U_0402_16V4Z VSS_63
1 2 A3 P17
C399 0.1U_0402_16V4Z S5_3.3V_1 VSS_64
1 2 A7
S5_3.3V_2 VSS_65
P18
C400 1 2 0.1U_0402_16V4Z E6 P19
C401 0.1U_0402_16V4Z S5_3.3V_3 VSS_66
1 2 E7
S5_3.3V_4 VSS_67
R12
C402 1 2 0.1U_0402_16V4Z E1 R13
S5_3.3V_5 VSS_68
F5 R14
S5_3.3V_6 VSS_69
R15
+1.8VALW VSS_70
E9 R16
S5_1.8V_1 VSS_71
E10 R17
C403 1 S5_1.8V_2 VSS_72
2 10U_0805_10V4Z E20 R18
S5_1.8V_3 VSS_73
E21 R19
C404 1 S5_1.8V_4 VSS_74
2 0.1U_0402_16V4Z T12
C405 1 VSS_75
2 0.1U_0402_16V4Z E13
USB_PHY_1.8V_1 VSS_76
T13
C406 1 2 0.1U_0402_16V4Z E14 T14
USB_PHY_1.8V_2 VSS_77
E16 T15
USB_PHY_1.8V_3 VSS_78
E17 T16
C407 2 USB_PHY_1.8V_4 VSS_79
1 0.1U_0402_16V4Z VSS_80
T17
+1.2V_HT C30 T18
C408 0.1U_0402_16V4Z CPU_PWR VSS_81
1 2 VSS_82
T19
C409 1 2 0.1U_0402_16V4Z AG6 U12
C410 0.1U_0402_16V4Z V5_VREF VSS_83
1 2 U13
C411 0.1U_0402_16V4Z AVDD_CK VSS_84
1 2 A24 U14
AVDDCK VSS_85
B24 U15
AVSSCK VSS_86
U16
VSS_87
A4 U17
VSS_1 VSS_88
A8 U18
R213 +1.8VS VSS_2 VSS_89
A29 U19
1K_0402_5% VSS_3 VSS_90
B28 V14
V5_VREF VSS_4 VSS_91
+5VS 1 2 C1
VSS_5 VSS_92
V15
1

2 2 E5 V16
VSS_6 VSS_93
E8 V17
D8 C412 C413 L29 VSS_7 VSS_94
E11 W14
CH751H-40_SC76 1U_0603_10V4Z VSS_8 VSS_95
0.1U_0402_16V4Z E12 W15
1 1 FBM-L11-321611-260-LMT_1206 VSS_9 VSS_96
+3VS 2 1 E15 W16
VSS_10 VSS_97
E18 W17
2

VSS_11 VSS_98
C414 1 2 10U_0805_10V4Z
CHS-215SB400-02_BGA564
C415 1 2 1U_0603_10V4Z

C416 1 2 0.1U_0402_16V4Z

V5_VREF (20mils)
AVDD_CK(40mils)

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
SB400-Power/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 22 of 53
 5 4 3 2 1

+3VALW +3VS +3VALW +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS

REQUIRED STRAPS

1
R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 R224
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @

2
AUTO_ON#
<19> AUTO_ON#
AC97_SDOUT
<20,31> AC97_SDOUT
RTC_CLK
D <19> RTC_CLK D
SB_SPDIFO
<20,40> SB_SPDIFO CLK_PCI_MINI
<19,30> CLK_PCI_MINI CLK_PCI_EC
<19,37,38> CLK_PCI_EC CLK_PCI_SIO_R
<19,35> CLK_PCI_SIO_R CLK_PCI6
<19> CLK_PCI6
CLK_PCI7
<19> CLK_PCI7 CLK_PCI8
<19> CLK_PCI8 CLK_PCI_LAN
<19,29> CLK_PCI_LAN

1
R225 R226 R227 R228 R229 R230 R231 R232 R233 R234
@ 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @ @ @ 10K_0402_5%

2
ACPWRON
PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5

AUTO_ON# AC97_SDOUT RTC_CLK SB_SPDIFO CLK_PCI_LAN CLK_PCI_MINI CLK_PCI_EC CLK_PCI_SIO CLK_PCI6 CLK_PCI7 PCI_CLK8

PULL MANUAL USE INTERNAL SIO 24MHz 48MHz OSC USB PHY INTERNAL PCIE_CM_SET CPU I/F = K8 ROM TYPE
HIGH PWR ON DEBUG RTC MODE PWRDOWN 4 8MHz LOW
STRAPS DISABLE H,H = PCI ROM
C C
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
H,L = PMC LPC ROM
PULL AUTO IGNORE EXTERNAL SIO 48MHz 48MHz XTAL USB PHY EXTERNAL PCIE_CM_SET CPU I/F = P4
PWR DEBUG RTC (NOT MODE PWRDOWN 4 8MHz High L,H = NORMAL LPC ROM
LOW DEFAULT
ON STRAPS SUPPORTED ENABLE
DEFAULT W/ IT8712 ) DEFAULT L,L = FWH ROM

+3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS

DEBUG STRAPS
1

1
R235 R236 R237 R238 R239 R240 R241 R242 R243 R244
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @ 10K_0402_5%
2

2
PD_DACK#
<21,24> PD_DACK#
PCI_AD31
<19,25,29,30> PCI_AD31
PCI_AD30
<19,25,29,30> PCI_AD30 PCI_AD29
<19,25,29,30> PCI_AD29 PCI_AD28
<19,25,29,30> PCI_AD28 PCI_AD27
<19,25,29,30> PCI_AD27 PCI_AD26
B <19,25,29,30> PCI_AD26 B
PCI_AD25
<19,25,29,30> PCI_AD25
PCI_AD24
<19,25,29,30> PCI_AD24 PCI_AD23
<19,25,29,30> PCI_AD23
1

1
R245 R246 R247 R248 R249 R250 R251 R252 R253 R254
1K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @ @ @
2

2
PD_DACK# PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

PULL USE RESERVED RESERVED RESERVED RESERVED BYPASS BYPASS BYPASS IDE USE EEPROM RESERVED
HIGH LONG PCI PLL ACPI PLL PCIE STRAPS
RESET BCLK
DEFAULT

PULL USE USE PCI USE USE IDE USE DEFAULT

LOW SHORT PLL ACPI PLL PCIE STRAPS
A RESET BCLK A
DEFAULT DEFAULT DEFAULT DEFAULT

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Hardware Trap
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 23 of 53
5 4 3 2 1
 5 4 3 2 1

Main HDD Second HDD

+5VS +5VS 2HDD@ 2HDD@
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z

1 1
1 1 1 1 1 1 1 1
@ C719 + @ C720 +
100U_C_4VM C417 C418 C419 C420 100U_C_4VM C421 C422 C423 C424
2 2 2 2 2 2 2 2 2 2

1U_0603_10V4Z 0.1U_0402_16V4Z 2HDD@ 2HDD@

D 1U_0603_10V4Z 0.1U_0402_16V4Z D

PD _D[0..15]
<21> PD_D[0..15]

JP11 JP12
NB_RST# 1 2 NB_RST# 1 2
<13,19,28,35> NB_RST# PD_D7 1 2 PD_D8 PD_D7 1 2 PD_D8
3 4 3 4
EMI PD_D6 5
3
5
4
6 6 PD_D9 PD_D6 5
3
5
4
6 6 PD_D9
PD_D5 7 8 PD_D10 PD_D5 7 8 PD_D10
PD_IOW# PD_IOR# PD_D4 7 8 PD_D11 PD_D4 7 8 PD_D11
9 9 10 10 9 9 10 10
PD_D3 11 12 PD_D12 PD_D3 11 12 PD_D12
11 12 11 12
1000P_0402_50V7K

1000P_0402_50V7K

PD_D2 13 14 PD_D13 PD_D2 13 14 PD_D13

PD_D1 13 14 PD_D14 PD_D1 13 14 PD_D14
1 1 15 15 16 16 15 15 16 16
PD_D0 17 18 PD_D15 PD_D0 17 18 PD_D15
17 18 17 18
19 19 20 20 19 19 20 20
PD_DREQ# 21 22 PD_DREQ# 21 22
2 2 <21> PD_DREQ# 21 22 21 22
@C725

@C726

PD_IOW# 23 24 R255 PD_IOW# 23 24 2HDD@ R256

<21> PD_IOW# PD_IOR# 23 24 PD_IOR# 23 24
25 26 470_0402_5% 25 26 10K_0402_5%
<21> PD_IOR# PD_IORDY 25 26 PCSEL PD_IORDY 25 26 PCSEL_S
<21> PD_IORDY 27 27 28 28 1 2 27 27 28 28 1 2 +5VS
PD_DACK# 29 30 PD_DACK# 29 30 @ R572
<21,23> PD_DACK# PD_IRQA 29 30 PD_IRQA 29 30
31 32 31 32 10K_0402_5%
<21> PD_IRQA PD_A1 31 32 PDIAG PD_A1 31 32 PDIAG
<21> PD_A1 33 33 34 34 33 33 34 34 1 2 +5VS
PD_A0 35 36 PD_A2 PD_A0 35 36 PD_A2
<21> PD_A0 PD_CS#1 35 36 PD_CS#3 PD_A2 <21> PD_CS#1 35 36 PD_CS#3
<21> PD_CS#1 37 37 38 38 PD_CS#3 <21> 37 37 38 38
1 2 HDD_LED# 39 40 HDD_LED# 39 40
+5VS 39 40 39 40
+5VS 41 41 42 42 +5VS +5VS 41 41 42 42 +5VS
@ R257 43 44 43 44
C 100K_0402_5% 43 44 43 44 C
45 GNDGND 46 45 GNDGND 46

SUYIN_200138FR044G213ZL SUYIN_200138FR044G213ZL

+5VS

+5VS
1

1U_0603_10V4Z 0.1U_0402_16V4Z

R258
100K_0402_5% 1 1 1 1
2

D9 C425 C426 C427 C428

CH751H-40_SC76 10U_0805_10V4Z
HDD_LED# ACT_LED# 2 2 2 2
1 2 ACT_LED <36>

D10 0.1U_0402_16V4Z
CH751H-40_SC76
CD_LED# 1 2

B B
SD _D[0..15]
<21> SD_D[0..15]

JP13

CDROM_L 1 2 CDROM_R
<31> CDROM_L CD_AGND 1 2 CDROM_R <31>
3 4
<31> CD_AGND
<13,19,28,35> NB_RST#
NB_RST# 5
3
5
4
6
6 SD_D8 Pin4 of CD_ROM connector is NC
SD_D7 7 8 SD_D9
SD_D6 9
7
9
8
10
10 SD_D10 if use Pioneer ODD(DVD Dual
SD_D5 11 12 SD_D11
SD_D4 13
11
13
12
14
14 SD_D12 DVR-K12TBC/DVR-K13TBC)
SD_D3 15 16 SD_D13
SD_D2 15 16 SD_D14
17 18
SD_D1 17 18 SD_D15
19 20
EMI SD_D0 21
19
21
20
22
22 SD_DREQ#
SD_DREQ# <21>
23 24 SD_SIOR#
SD_SIOW# SD_SIOR# SD_SIOW# 23 24 SD_SIOR# <21>
<21> SD_SIOW# 25 26
SD_IORDY 25 26 SD_DACK#
<21> SD_IORDY 27 28 SD_DACK# <21>
27 28
1000P_0402_50V7K

1000P_0402_50V7K

SD_IRQA 29 30
<21> SD_IRQA 29 30
1 1 SD_SBA1 31 32 PDIAG# R260 1 2 @ 100K_0402_5%
<21> SD_SBA1 31 32 +5VS
@ R261 SD_SBA0 33 34 SD_SBA2
<21> SD_SBA0 SD_SCS1# 33 34 SD_SCS3# SD_SBA2 <21>
100K_0402_5% 35 36
<21> SD_SCS1# CD_LED# 35 36 W=80mils SD_SCS3# <21>
+5VS 1 2 37 38 +5VS
2 2 37 38
@C727

@C728

+5VS 39 40 +5VS
39 40
+5VS 41 42 +5VS
R262 41 42
43 44 2 1
470_0402_5% 43 44
45 46
45 46
2 1 SEC_CSEL 47
47 48
48 C429
49 50 0.1U_0402_16V4Z
49 50
51 GND GND 52
A A
07/11 for defined by different ODD vender. 53 GND GND 54

SUYIN_800059MR050S119ZL

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HDD/CDROM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 24 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS
+VDDPLL
+3VS

0.1U_0402_16V4Z

7411@ C438 0.1U_0402_16V4Z

+3VS

0.01U_0402_16V7K

0.01U_0402_16V7K
7411@ C430

7411@ C431

C433

C434

C435
10U_0805_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_10V4Z
1 1 2 2 1 1
+3VS

7411@C432
2 2 1 1 2 2

7411@

7411@

7411@
1 1
PCI_CBE#[0..3] <19,29,30>

7411@
M19 C437
D D
+3VS 2 2
PCI_AD[0..31] <19,23,29,30>

VCCP W10
R13
R14
V17

V19
T18
1

VCCP W3
H1
7411@ R265 U17B
10K_0402_5%

VDPLL_33
VDPLL_15

VR_PORT
VR_PORT
AVDD
AVDD
AVDD
U2 PCI_AD31
AD31 PCI_AD30
V1

2
MC_PWRON# AD30 PCI_AD29
<26> MC_PWRON# F1 V2
MC_PWR_CTRL_0 AD29 PCI_AD28
F2 U3
MC_PWR_CTRL_1 AD28 PCI_AD27
W2
SD_CD# AD27 PCI_AD26
<26> SD_CD# E3 SD_CD# AD26 V3
MS_CD# F5 U4 PCI_AD25
<26> MS_CD# MS_CD# AD25
SM_CD# F6 V4 PCI_AD24
<26> SM_CD# SM_CD# AD24 PCI_AD23
AD23 V5
U5 PCI_AD22
MSCLK_SDCLK_SMELWP# AD22 PCI_AD21
<26> MSCLK_SDCLK_SMELWP# G5 MS_CLK/SD_CLK/SM_EL_WP# AD21 R6
MSBS_SDCMD_SMWE# F3 P6 PCI_AD20
<26> MSBS_SDCMD_SMWE# MSD3_SDD3_SMD3 MS_BS/SD_CMD/SM_WE# AD20 PCI_AD19
<26> MSD3_SDD3_SMD3 H5 MS_DATA3/SD_DAT3/SM_D3 AD19 W6
MSD2_SDD2_SMD2 G3 V6 PCI_AD18
<26> MSD2_SDD2_SMD2 MS_DATA2/SD_DAT2/SM_D2 AD18
MSD1_SDD1_SMD1 G2 U6 PCI_AD17
<26> MSD1_SDD1_SMD1 MSD0_SDD0_SMD0 MS_DATA1/SD_DAT1/SM_D1 AD17 PCI_AD16
<26> MSD0_SDD0_SMD0 G1 MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD16 R7
V9 PCI_AD15
AD15 PCI_AD14
AD14 U9
SDCLK_SMRE# J5 R9 PCI_AD13
<26> SDCLK_SMRE# SDCMD_SMALE SD_CLK/SM_RE#/SC_GPIO1 AD13 PCI_AD12
<26> SDCMD_SMALE J3 SD_CMD/SM_ALE/SC_GPIO2 AD12 N9
SDD0_SMD4 H3 V10 PCI_AD11
<26> SDD0_SMD4 SDD1_SMD5 SD_DAT0/SM_D4/SC_GPIO6 AD11 PCI_AD10
<26> SDD1_SMD5 J6 SD_DAT1/SM_D5/SC_GPIO5 AD10 U10
SDD2_SMD6 J1 R10 PCI_AD9
<26> SDD2_SMD6 SD_DAT2/SM_D6/SC_GPIO4 AD9
SDD3_SMD7 J2 N10 PCI_AD8
<26> SDD3_SMD7 SDWP#_SMCE# SD_DAT3/SM_D7/SC_GPIO3 AD8 PCI_AD7
<26> SDWP#_SMCE# H7 SD_WP/SM_CE# AD7 V11
U11 PCI_AD6
C AD6 PCI_AD5 C
AD5 R11
SMCLE J7 W12 PCI_AD4
<26> SMCLE SM_RB# SM_CLE/SC_GPIO0 AD4 PCI_AD3
<26> SM_RB# K1 SM_R/B AD3 V12
CLK_48M_CB K2 U12 PCI_AD2
SM_PHYS_WP#/SC_FCB AD2 PCI_AD1
AD1 N11
W13 PCI_AD0
AD0
1

L2 RSVD
7411@ R272 K5
@ R271 10K_0402_5% RSVD PCI_CBE#3
K3 W4
10_0402_5% RSVD C/BE3# PCI_CBE#2
+3VS 1 2 K7 W7
RSVD C/BE2# PCI_CBE#1
L1 W9
PCI7411
2

RSVD C/BE1# PCI_CBE#0

1 L3 W11
@ C440 RSVD C/BE0#
<27> VCCD1# L5
10P_0402_25V8K RSVD PCI_PAR
P9 PCI_PAR <19,29,30>
7411@ R273 1 PAR PCI_FRAME#
2 220_0402_5% P12
TEST0 FRAME#
V7 PCI_FRAME# <19,29,30>
2 @ R274 1 2 220_0402_5% W17 R8 PC I_TRDY#
NC TRDY# PCI_TRDY# <19,29,30>
T19 U7 PCI_IR DY#
RSVD IRDY# PCI_IRDY# <19,29,30>
7411@ R9 W8 PCI_STOP#
STOP# PCI_STOP# <19,29,30>
0_0402_5% PCI_DEVSEL# R275 7411@
CLOSE TO CHIP CLK_48M_CB1 2 M1
DEVSEL#
N8
W5
PCI_DEVSEL# <19,29,30>
1 2 PCI_AD20
<16> CLK_48M_CB CLK_48 IDSEL PCI_PERR#
V8 100_0402_5%
PERR# PCI_PERR# <19,29,30>
7411@ R276 U8 PCI_SERR#
SERR# PCI_SERR# <19,29,30>
1

1
7411@ R277

7411@ R278
56.2_0603_1%

56.2_0603_1%
1U_0603_10V4Z

+3VS 1 2 PHY_TEST R17 U1 PCI_REQ#2 R279 07/04 for EMI

PHY_TEST_MA REQ# PCI_REQ#2 <19>
7411@ C443

2 4.7K_0402_5% T2 PCI_GNT#2 10_0402_5%

GNT# PCI_GNT#2 <19>
7411@ R281 1 2 1 2
6.34K_0402_1% P5 CLK_PCI_PCM
PCICLK CLK_PCI_PCM <19>
1 2 U18 R3 PCI_RST# C442
2

1 R0 PCIRST# PCI_RST# <19,27,29,30,35,37,38>

U19 T1 10P_0402_25V8K
R1 GRST#
8
7
6
5

XTPBIAS0 U15 T3
XTPA0+ TPBIAS0 RI_OUT#/PME# 7411@
4 V15
GND4
GND3
GND2
GND1

4 XTPA0- TPA0P R282 1

3 W15 R2 2 4.7K_0402_5% +3VS
3 XTPB0+ TPA0N SUSPEND#
2 V14
B 2 XTPB0- TPB0P PCM_SPK B
1 W14 L7 PCM_SPK <31>
1 TPB0N SPKROUT
220P_0603_50V8J 56.2_0603_1%

5.1K_0603_1% 56.2_0603_1%

XTPBIAS1 U17
TPBIAS1
1

1
7411@ R283

7411@ R284

JP15 XTPA1+ V18 N3 PCI_PIRQE#

XTPA1- TPA1P MFUNC0 PCI_PIRQH# PCI_PIRQE# <19>
SUYIN_020204FR004S506ZL W18 M5
TPA1N MFUNC1 PCI_PIRQH# <19>
7411@ R285 XTPB1+ V16 P1
XTPB1- TPB1P MFUNC2 SIRQ SIRQ <19,35,37,38>
4.7K_0402_5% W16 P2 7411@
CPS TPB1N MFUNC3 R286 1
+3VS 1 2 M11 P3 2 4.7K_0402_5% +3VS
2

C NA CPS MFUNC4 CARD_LED

1 2 P15 N5 CARD_LED <26,36>
X_OUT CNA MFUNC5 R464 1
R19 R1 2 +3VS
XO MFUNC6
1

1 7411@ R287 X_IN R18 4.7K_0402_5% 7411@

XI
7411@ C444

7411@ R288

10K_0402_5% R12 M3 7411@1 R289 2 220_0402_5%

PC0(TEST1) SCL
U13 M2 1 2 220_0402_5%
PC1(TEST2) SDA
VSSPLL
VSSPLL

V13 7411@ R290

PC2(TEST3)
AGND
AGND
AGND

2 H2 R291 1 2 10K_0402_5%
2

VR_EN# 7411@
when VR_EN# is low, internal
PCI7411GHK_PBGA288
regulator is actived
N12
U14
U16

P14
T17

7411@ C445
1 2 +VDDPLL
0.1U_0402_16V4Z
1

1
56.2_0603_1%

56.2_0603_1%
7411@ C446

7411@ R292

7411@ R293
1U_0603_10V4Z

put C445 as close to

2 controller as possible
2

1 7411@ C447
XTPBIAS1 10P_0402_50V8J
XTPA1+ X_IN
<40> XTPA1+
XTPA1-
<40> XTPA1-
1

XTPB1+
<40> XTPB1+ XTPB1- 7411@ R296 X1
<40> XTPB1-
220P_0603_50V8J 56.2_0603_1%

5.1K_0603_1% 56.2_0603_1%

A 1M_0402_5% 7411@ A
1

1
7411@ C449 7411@ R294

7411@ R297 7411@ R295

X_OUT

7411@ C448 24.576MHZ_16P_XSL024576FG1H

10P_0402_50V8J
2

Security Classification Compal Secret Data

1

1
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
PCI7411(1/3)
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 25 of 53
5 4 3 2 1
 5 4 3 2 1

MC_PWRON#
<25> MC_PWRON#

1
D
CARD_LED 2 7411@ Q12
<25,36> CARD_LED
G 2N7002_SOT23
S

3
7411@ R456
D 0_0402_5% D
1 2 @ D30
CH751H-40_SC76
1 2 2 1 SD_CD#
+3VS SD_CD# <25>
@ R457
100K_0402_5% SM_CD#
2 1 SM_CD# <25> 8/23 Relocate Damping resistor to
@ D31
CH751H-40_SC76
solve Sandisk Card issue

JP14
MSD0_SDD0_SMD0 34 11 22_0402_5% 2 1 7411@ R459 MSD3_SDD3_SMD3
<25> MSD0_SDD0_SMD0 MSD1_SDD1_SMD1 SM-D0 SD-DAT3 MSD2_SDD2_SMD2
33 12 22_0402_5% 2 1 7411@ R460
<25> MSD1_SDD1_SMD1 SM-D1 / XD-D1 SD-DAT2
MSD2_SDD2_SMD2 32 6 22_0402_5% 2 1 7411@ R461 MSD1_SDD1_SMD1
<25> MSD2_SDD2_SMD2 MSD3_SDD3_SMD3 SM-D2 / XD-D2 SD-DAT1 MSD0_SDD0_SMD0
31 5 IN 1 CONN SD-DAT0 7 22_0402_5% 2 1 7411@ R462
<25> MSD3_SDD3_SMD3 SDD0_SMD4 SM-D3 / XD-D3 SDWP#_SMCE#
<25> SDD0_SMD4 21 SM-D4 / XD-D4 SD-WP-SW 5
SDD1_SMD5 22 10 22_0402_5% 2 1 7411@ R458 MSBS_SDCMD_SMWE#
<25> SDD1_SMD5 SDD2_SMD6 SM-D5 / XD-D5 SD-CMD MSCLK_SDCLK_SMELWP#
23 8 33_0402_5% 2 1 7411@ R266
<25> SDD2_SMD6 SM-D6 / XD-D6 SD_CLK
SDD3_SMD7 24 9 +VCC_5IN1
<25> SDD3_SMD7 SM-D7 / XD-D7 SD-VCC
NC 4
MSCLK_SDCLK_SMELWP# 35 42 SD_CD#
<25> MSCLK_SDCLK_SMELWP# SM_PHYS_WP# SM_WP-IN / XD_WP-IN SD-CD-SW
1 2 43 SM-WP-SW SD-CD-COM 41
R269 7411@ MSBS_SDCMD_SMWE# 36
<25> MSBS_SDCMD_SMWE# SDCMD_SMALE #SM_-WE / XD_-WE MSD0_SDD0_SMD0
330_0402_5% 37 15
<25> SDCMD_SMALE #SM-ALE / XD-ALE MS-DATA0 MSD1_SDD1_SMD1
MS-DATA1 14
+VCC_SM 25 16 MSD2_SDD2_SMD2
SM_CD# SM-LVD MS-DATA2 MSD3_SDD3_SMD3
3 SM-CD-SW MS-DATA3 18

0.1U_0402_16V4Z
07/11 change net name 29 19 MSCLK_SDCLK_SMELWP#
SM_-VCC / XD_-VCC MS-SCLK

C439
SM_RB# 26 17 MS_CD#
SDCLK_SMRE# #SM_R/-B / XD_R/-B MS-INS MSBS_SDCMD_SMWE#
1 <25> SDCLK_SMRE# 27 #SM_-RE / XD_-RE MS-BS 13
C +3VS +VCC_5IN1 SDWP#_SMCE# 28 20 C
<25> SDWP#_SMCE# #SM_-CE / XD_-CE MS-VCC +VCC_5IN1
@ U51 30 #SM_-CD

7411@
5 IN OUT 1 2 SM-CD-COM XD-VCC 40 +VCC_SM
2 SMCLE 38 39 SM_CD#
MC_PWRON# <25> SMCLE SM-CLE / XD-CLE XD-CD
ON# 4 GND 1
3 SET GND 44
GND 2
2

TAITN_R007-N3P-15-S
@ R573 AATI4610AIGV-T1_SOT23-5

10K_0402_1%
1

07/11 change net name

+VCC_5IN1 +VCC_SM
07/11 change net name

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
7411@ C687

7411@ C688

7411@ C689

7411@ C690
+3VS Q50 7411@ +VCC_5IN1 Q11 7411@ +VCC_SM
2 2 2 2
SI2301BDS_SOT23 SI2301BDS_SOT23
B B
S

S
D

3 1 3 1
1 1 1 1
1

1
G

1 1
2

2
100K_0402_5%

100K_0402_5%
R546 7411@
R544 7411@

MC_PWRON# 7411@ C698 7411@ R551 7411@ C436 7411@ R264

10U_0805_10V4Z 47K_0603_5% 10U_0805_10V4Z 47K_0603_5%
2 2
2

07/11 change net name

SM_CTRL#
D32 7411@ +VCC_SM
CH751H-40_SC76
SD_CD# 1 2 R549
10K_0402_5%
1

D SDWP#_SMCE#
<25> SDWP#_SMCE# 1 2
MS_CD# 1 2 2 Q51 7411@
<25> MS_CD#
G 2N7002_SOT23 R550
D33 7411@ S 10K_0402_5%
3

CH751H-40_SC76 SM_RB# 1 2
<25> SM_RB#

07/25 for XD log

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
PCI7411(2/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 26 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS 7411@ C451 7411@ C453 +3VS 7411@ C456 7411@ C458
0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z CardBus Power Switch
2 1 1 1 1 2 1 1 1 1 U18

7411@ C450 7411@ C455 TPS_DATA 3 20

1U_0603_10V4Z 1U_0603_10V4Z TPS_CLK DATA 12V
4 CLOCK 12V 7
1 2 2 2 2 1 2 2 2 2 TPS_LATCH 5
7411@ C452 7411@ C454 7411@ C457 7411@ C459 PCI_RST# LATCH +3VS C460 7411@
<19,25,29,30,35,37,38> PCI_RST# 12 RESET#
0.1U_0402_16V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 15 14 0.1U_0402_16V4Z
OC# NC3
21 SHDN# 3.3V 13 1 2
C462 7411@ +S1_VPP
+S1_VCC 0.1U_0402_16V4Z +5VS 1 2
1 2 8
AVPP NC4
24
D C461 7411@ D
19 2
+S1_VCC NC0 5V 4.7U_0805_10V4Z
1 1 1
5V
1 2
7411@ C464 7411@ C465 9 11 C466 7411@
0.1U_0402_16V4Z 0.1U_0402_16V4Z C463 7411@ AVCC GND 0.1U_0402_16V4Z
10
2 2 4.7U_0805_10V4Z AVCC
1 2
17 23
C468 7411@ NC1 NC5
18 22 1 2
+S1_VCC +3VS 0.1U_0402_16V4Z NC2 NC6
16
NC7 C467 7411@
1 2 6
NC8 4.7U_0805_10V4Z

1 2 7411@ SNP1X21DBR SSOP-24

M10
M12
H10
H11
H12

D19
A11

K12

K19
J12
M7

M9
H8
H9

N7
C469 7411@

A5

K8
J8
U17A 4.7U_0805_10V4Z

VCCA
VCCA

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
S1_D10 D1
S1_D9 A_CAD31/A_D10 +S1_VCC
C1
S1_D1 D3
A_CAD30/A_D9
N1 TPS_DATA close to card bus conn U47
S1_D8 A_CAD29/A_D1 DATA TPS_CLK
C2 A_CAD28/A_D8 CLOCK L6 VCC 13
S1_D0 B1 N2 TPS_LATCH 12
S1_A0 A_CAD27/A_D0 LATCH VCC
B4 A_CAD26/A_A0 9 12V VCC 11
S1_A1 A4
S1_A2 A_CAD25/A_A1
E6 A_CAD24/A_A2
S1_A3 B5 +S1_VPP
S1_A4 A_CAD23/A_A3
C6 A_CAD22/A_A4 RSVD B15
S1_A5 B6 A16 JP16 +5VS 10
S1_A6 A_CAD21/A_A5 RSVD VPP
G9 A_CAD20/A_A6 RSVD B16 GND 1
S1_A25 C7 A17 35 5
S1_A7 A_CAD19/A_A25 RSVD GND S1_D3 5V
B7 A_CAD18/A_A7 RSVD C16 DATA3 2 6 5V
S1_A24 A7 D17 36 S1_CD1#
C S1_A17 A_CAD17/A_A24 RSVD CD1# S1_D4 TPS_CLK C
A10 A_CAD16/A_A17 RSVD C19 DATA4 3 VCCD0 1
S1_IOWR# E11 D18 37 S1_D11 2 VCCD1#
S1_A9 A_CAD15/A_IOWR# RSVD DATA11 S1_D5 VCCD1 TPS_LATCH VCCD1# <25>
G11 A_CAD14/A_A9 RSVD E17 DATA5 4 VPPD0 15
S1_IORD# C11 E19 38 S1_D12 +3VS 14 TPS_DATA
S1_A11 A_CAD13/A_IORD# RSVD DATA12 S1_D6 VPPD1
B11 A_CAD12/A_A11 RSVD G15 DATA6 5
S1_OE# C12 F18 39 S1_D13 3
S1_CE2# A_CAD11/A_OE# RSVD DATA13 S1_D7 3.3V
B12 A_CAD10/A_CE2# RSVD H14 DATA7 6 4 3.3V OC 8

SHDN
S1_A10 A12 H15 40 S1_D14

GND
S1_D15 A_CAD9/A_A10 RSVD DATA14 S1_CE1#
E12 G17 7
A_CAD8/A_D15 RSVD CE1#

2
S1_D7 C13 K17 41 S1_D15
S1_D13 A_CAD7/A_D7 RSVD DATA15 S1_A10 @ R454 @
F12 L13 8

16
S1_D6 A_CAD6/A_D13 RSVD ADD10 S1_CE2# TPS2211AIDBR_SSOP16
A13 K18 42 10K_0402_5%
S1_D12 A_CAD5/A_D6 RSVD CE2# S1_OE#
C14 L15 9
S1_D5 A_CAD4/A_D12 RSVD OE# S1_VS1
E13 L17 43

1
S1_D11 A_CAD3/A_D5 RSVD VS1# S1_A11
A14 L18 10
S1_D4 A_CAD2/A_D11 RSVD ADD11 S1_IORD#
B14 L19 44
S1_D3 A_CAD1/A_D4 RSVD IORD# S1_A9
E14 M17 11
A_CAD0/A_D3 RSVD ADD9 S1_IOWR#
M14 45

S1_REG# C5
PCI 7411 RSVD
RSVD
M15
N19
IOWR#
ADD8
12
46
S1_A8
S1_A17
S1_A12 A_CC/BE3#/A_REG# RSVD ADD17 S1_A13
F9 N18 13
S1_A8 A_CC/BE2#/A_A12 RSVD ADD13 S1_A18
B10 N15 47
S1_CE1# A_CC/BE1#/A_A8 RSVD ADD18 S1_A14
G12 M13 14
A_CC/BE0#/A_CE1# RSVD ADD14 S1_A19
P18 48
S1_A13 RSVD ADD19 S1_WE#
G10 P17 15
S1_A23 A_CPAR/A_A13 RSVD WE# S1_A20
C8 P19 49
S1_A22 A_CFRAME#/A_A23 RSVD ADD20 S1_RDY#
A8 F15 16
S1_A15 A_CTRDY#/A_A22 RSVD READY S1_A21
B8 G18 50
S1_A20 A_CIRDY#/A_A15 RSVD ADD21 +S1_VCC
A9 K14 17 +S1_VCC
S1_A21 A_CSTOP#/A_A20 RSVD VCC
C9 M18 51
S1_A19 A_CDEVSEL#/A_A21 RSVD VCC
E10 K13 18
S1_A14 A_CBLOCK#/A_A19 RSVD VPP +S1_VPP
F10 G19 52
B S1_WAIT# A_CPERR#/A_A14 RSVD VPP S1_A16 +S1_VPP B
B3 H17 19
S1_INPACK# A_CSERR#/A_WAIT# RSVD ADD16 S1_A22
E7 J13 53
S1_WE# A_CREQ#/A_INPACK# RSVD ADD22 S1_A15
B9 J17 20
7411@ R299 S1_BVD1 A_CGNT#/A_WE# RSVD ADD15 S1_A23
B2 H19 54
33_0402_5% S1_WP A_CSTSCHG/A_BVD1(STSCHG/RI) RSVD ADD23 S1_A12
C3 J19 21
S1_A16 S1_CLK A_CCLKRUN#/A_WP(IOIS16) RSVD ADD12 S1_A24
1 2 E9 J18 55
S1_RDY# A_CCLK/A_A16 RSVD ADD24 S1_A7
C4 B18 22
A_CINT#/A_READY(IREQ) RSVD ADD7 S1_A25
E18 56
S1_RST RSVD ADD25 S1_A6
A6 J15 23
A_CRST#/A_RESET RSVD ADD6 S1_VS2
F14 57
S1_BVD2 RSVD VS2# S1_A5
A2 A18 24
A_CAUDIO/A_BVD2(SPKR#) RSVD ADD5 S1_RST
H18 58
S1_CD1# RSVD RESET S1_A4
C15 B19 25
S1_CD2# A_CCD1#/A_CD1# RSVD ADD4 S1_WAIT#
E5 F17 59
S1_VS1 A_CCD2#/A_CD2# RSVD WAIT# S1_A3
A3 C17 26
S1_VS2 A_CVS1/A_VS1# RSVD ADD3 S1_INPACK#
E8 N13 60
A_CVS2/A_VS2# RSVD INPACK# S1_A2
B17 27
S1_D14 RSVD ADD2 S1_REG#
B13 C18 61
S1_D2 A_CRSVD/A_D14 RSVD REG# S1_A1
D2 F19 28
S1_A18 A_CRSVD/A_D2 RSVD ADD1 S1_BVD2
C10 N17 62
A_CRSVD/A_A18 RSVD BVD2 S1_A0
A15 29
RSVD ADD0 S1_BVD1
E2 K15 63
A_USB_EN# RSVD BVD1 S1_D0
E1 30
B_USB_EN# DATA0 S1_D8
64
DATA8 S1_D1
31
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

DATA1 S1_D9
69 65
GND DATA9 S1_D2
70 32
PCI7411GHK_PBGA288 GND DATA2 S1_D10
66
G7
G8
G13
H13
J9
J10
J11
K9
K10
K11
L8
L9
L10
L11
L12
M8

DATA10 S1_WP
7411@ 33
S1_CD1# S1_CD2# WP S1_CD2#
67
CD2#
34
GND
GND 68
A A
7411@ C470 7411@ C471 SANTA_130609-1_LT
10P_0402_50V8J 10P_0402_50V8J

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
PCI7411(3/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 27 of 53
5 4 3 2 1
 A B C D E

Express Card Power Switch

EXP@ C472 U20 +3VS_PEC

+3VS
0.1U_0402_16V4Z
2 1 5 3.3Vin1 3.3Vout1 7
6 3.3Vin2 3.3Vout2 8

EXP@ C474 +3V_PEC

+3VALW +3VS
0.1U_0402_16V4Z
2 1 21
3.3Vaux_in Aux_out
20
+1.5VS

2
1 EXP@ C476 +1.5VS_PEC 1
2 1 18 16 EXP@ R302
1.5Vin1 1.5Vout1
19 17 10K_0402_5%
0.1U_0402_16V4Z 1.5Vin2 1.5Vout2

1
NC_CP# 14 NC_CLKSEL0#
<20> NC_CP# CPUSB# NC_CLKSEL0# <16>
15 23
CPPE# OC#

1
SUSP# D
<37,38,39,41> SUSP# 4
SYSON STBY# RCLKEN @ Q14
<37,38,41,46> SYSON 3 22 2
NB_RST# SHDN# RCLKEN PERST# G 2N7002_SOT23
<13,19,24,35> NB_RST# 2 9
SYSRST# PERST#
S

3
GND

NC1
NC2
NC3
NC4
NC5

1
D
EXP@ <20> EXP_RST# 2 EXP@ Q55

11

1
10
12
13
24
TPS2231PWPR_PWP24 G 2N7002_SOT23
S

3
close to JP36 JP17

17_EXP@ 0_0402_5% 1
<20> USBP7-
USBP7- R473 1 2 USB7- 2
GND
USB_D-
Near to Express Card slot. 17
USBP7+ R474 1 2 USB7+ 3
<20> USBP7+ NC_CP# USB_D+
4 CPUSB#
2 17_EXP@ 0_0402_5% 5 +3VS_PEC +3V_PEC 2
RSV 4.7U_0805_10V4Z
6 RSV
SB_SCLK 7
<8,9,16,20> SB_SCLK SB_SDAT SMB_CLK
<8,9,16,20> SB_SDAT 8 SMB_DATA
+1.5VS_PEC 9 +1.5V 1 1 1 1
+1.5VS_PEC 10 +1.5V
<20> PCIE_PME# R306 1 2 PCIE_PME#_R 11 17_EXP@ C479 C480 17_EXP@ 17_EXP@ C717 C478 17_EXP@
WAKE# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
12
EXP@ +3V_PEC PERST# +3.3VAUX 2 2 2 2
13
0_0402_5% PERST#
+3VS_PEC 14
+3.3V
15
NC_CLKSEL0# +3.3V
16
NC_CP# CLKREQ#
17
PCIECLK0# CPPE# +1.5VS_PEC
<16> PCIECLK0# 18
PCIECLK0 REFCLK- 4.7U_0805_10V4Z
<16> PCIECLK0 19
REFCLK+
20
PCIE_RX0N GND
<12> PCIE_RX0N 21 1 1
PCIE_RX0P PERn0
<12> PCIE_RX0P 22
PERp0 17_EXP@ C481 C482 17_EXP@
23
PCIE_TX0N GND 0.1U_0402_16V4Z
<12> PCIE_TX0N 24
PCIE_TX0P PETn0 2 2
<12> PCIE_TX0P 25
PETp0
26
GND
27
GND
28
GND
FOX_1CH4110C

3 3
JP36

1
USBP7- 2
GND Near to Express Card slot. 15.4
USBP7+ USB_D-
3
NC_CP# USB_D+
4
CPUSB# +3VS_PEC +3V_PEC
5
RSV 4.7U_0805_10V4Z
6
SB_SCLK RSV
<8,9,16,20> SB_SCLK 7
SB_SDAT SMB_CLK
<8,9,16,20> SB_SDAT 8
SMB_DATA
+1.5VS_PEC 9 1 1 1 1
+1.5V
+1.5VS_PEC 10
PCIE_PME#_R +1.5V 15_EXP@ C694 C695 15_EXP@ 15_EXP@ C718 C693 15_EXP@
11
WAKE# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
12
+3V_PEC PERST# +3.3VAUX 2 2 2 2
13
PERST#
+3VS_PEC 14
+3.3V
15
NC_CLKSEL0# +3.3V
16
NC_CP# CLKREQ#
17
PCIECLK1# CPPE# +1.5VS_PEC
<16> PCIECLK1# 18
PCIECLK1 REFCLK- 4.7U_0805_10V4Z
<16> PCIECLK1 19
REFCLK+
20
PCIE_RX1N GND
<12> PCIE_RX1N 21 1 1
PCIE_RX1P PERn0
<12> PCIE_RX1P 22
PERp0 15_EXP@ C696 C697 15_EXP@
23
PCIE_TX1N GND 0.1U_0402_16V4Z
<12> PCIE_TX1N 24
PCIE_TX1P PETn0 2 2
<12> PCIE_TX1P 25
PETp0
26
GND
27
GND
28 GND
4 4
FOX_1CH4110C

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Express Card
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 28 of 53
A B C D E
 5 4 3 2 1

+3VALW
C483 R307
1U_0603_10V4Z 300_0603_5% JP18
2 1 ACTIVITY# 1 2 12 Amber LED-

3
+3VALW 11 Amber LED+
Q15 16
CTRL25 2SB1188_SC62 SHLD4
1 8 PR4-
SHLD3 15
V2.5_LAN 7 PR4+

2
07/11 Swap net for HP request MDO1- 6
PR2-
D
1 D
5
C484 PR3-
4.7U_0805_10V4Z 4
2 PR3+
MDO1+ 3
PC I_AD[0..31] R308 PR2+
<19,23,25,30> PCI_AD[0..31] 3.6K_0402_5% MDO0- 2
PR1-
1 2 +3VALW SHLD2
14
R309 MDO0+ 1
U21 U22 300_0603_5% PR1+
13
PCI_AD0 LAN_EEDO LINK_100# SHLD1
104 108 4 5 1 1 2 10
PCI_AD1 AD0 EEDO LAN_EEDI DO GND Green LED-
103 AD1 AUX/EEDI 109 3 DI NC 6
PCI_AD2 102 111 LAN_EECLK 2 7 C485 0.1U_0402_16V4Z 9
AD2 EESK SK NC +3VALW Green LED+
PCI_AD3 98 106 LAN_EECS 1 8 +3VALW
PCI_AD4 AD3 EECS CS VCC 2 SUYIN_100073FR012S100ZL
97 AD4
PCI_AD5 96 117 ACTIVITY# AT93C46-10SI-2.7_SO8
PCI_AD6 AD5 LED0 LINK_100#
95 AD6 LED1 115
PCI_AD7 93 114
PCI_AD8 AD7 LED2
90 AD8 NC/LED3 113
PCI_AD9 89
PCI_AD10 AD9 TXD+/MDI0+
87 AD10 TXD+/MDI0+ 1
PCI_AD11 86 2 TXD-/MDI0-
PCI_AD12 AD11 TXD-/MDI0- RXIN+/MDI1+
85 AD12 RXIN+/MDI1+ 5
PCI_AD13 83 6 RXIN-/MDI1-
PCI_AD14 AD13 RXIN-/MDI1-
82 AD14
PCI_AD15 79 14
PCI_AD16 AD15 NC/MDI2+
59 AD16 NC/MDI2- 15
PCI_AD17 58 18
PCI_AD18 AD17 NC/MDI3+ U23
57 AD18 NC/MDI3- 19
PCI_AD19 55
PCI_AD20 AD19 LAN_X1 TXD+/MDI0+ MDO0+ R310 C486
53 AD20 X1 121 8 TD- TX- 9 MDO0+ <40>
PCI_AD21 50 122 LAN_X2 TXD-/MDI0- 7 10 MDO0- 75_0402_5%
C PCI_AD22 AD21 X2 TD+ TX+ MCT0 MDO0- <40> RJ45_GND 2 C
49 AD22 6 CT CT 11 2 1 1
PCI I/F

PCI_AD23 47 105 R311 1 2 1K_0402_5% C487

PCI_AD24 AD23 LWAKE R312 +3VS
43 AD24 ISOLATE# 23 1 2 15K_0402_5% 0.1U_0402_16V4Z
PCI_AD25 42 127 R313 1 2 5.6K_0603_1% 1 2 3 14 MCT1 2 1 1000P_1206_2KV7K
PCI_AD26 AD25 RTSET RXIN+/MDI1+ CT CT MDO1+ R314
40 AD26 NC/SMBCLK 72 2 RD- RX- 15 MDO1+ <40>
PCI_AD27 39 74 R313 5.6K for 8100CL RXIN-/MDI1- 1 16 MDO1- 75_0402_5%
AD27 NC/SMBDATA RD+ RX+ MDO1- <40>
PCI_AD28 37
PCI_AD29 AD28
36 88
PCI_AD30 AD29 NC/M66EN NS0013_16P
34
PCI_AD31 AD30
33 10
AD31 NC/AVDDH
120
PCI_CBE#0 NC/HV
<19,25,30> PCI_CBE#0 92
PCI_CBE#1 C/BE#0
<19,25,30> PCI_CBE#1 77 11
PCI_CBE#2 C/BE#1 NC/HSDAC+
<19,25,30> PCI_CBE#2 60 123
PCI_CBE#3 C/BE#2 NC/HG
<19,25,30> PCI_CBE#3 44 124
C/BE#3 NC/LG2
126
PCI_AD22 LAN_IDSEL NC/LV2
1 2 46
R315 100_0402_5% IDSEL
LAN I/F

PCI_PAR 76
<19,25,30> PCI_PAR PCI_FRAME# PAR
<19,25,30> PCI_FRAME# 61 9
PCI_IR DY# FRAME# NC/VSS
<19,25,30> PCI_IRDY# 63 13
PC I_TRDY# IRDY# NC/VSS
<19,25,30> PCI_TRDY# 67
PCI_DEVSEL# TRDY#
<19,25,30> PCI_DEVSEL# 68
PCI_STOP# DEVSEL# Y5
69 22
<19,25,30> PCI_STOP# STOP# NC/GND
NC/GND
48 25MHZ_16P_XSL025000FK1H close to chip
PCI_PERR# 70 62 LAN_X1 2 1 LAN_X2
<19,25,30> PCI_PERR# PERR# NC/GND
PCI_SERR# 75 73 1 1 R316
<19,25,30> PCI_SERR# SERR# NC/GND
112 49.9_0402_1% C490
PCI_REQ#1 NC/GND C488 C489 TXD+/MDI0+ 0.01U_0402_16V7K
30 118 2 1
<19> PCI_REQ#1 PCI_GNT#1 REQ# NC/GND 27P_0402_50V8J 27P_0402_50V8J
29 2 1
<19> PCI_GNT#1 GNT# 2 2 TXD-/MDI0- 2 1
PCI_PIRQG# 25 R317
B <19> PCI_PIRQG# INTA# B
8 CTRL25 49.9_0402_1%
PME_EC# CTRL25
<30,37,38> PME_EC# 31
PME#
125
PCI_RST# RTT3/CRTL18
<19,25,27,30,35,37,38> PCI_RST# 27
RST#
26 +3VALW
CLK_PCI_LAN VDD33
28 41
<19,23> CLK_PCI_LAN
1 2 65
CLK VDD33
56
1 1 1 1 1 close to magnetic
R318 CLKRUN# VDD33 C491 C492 C493 C494 C495
71
10K_0402_5% VDD33 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R319
84
VDD33 2 2 2 2 2 49.9_0402_1% C496
94
VDD33 RXIN+/MDI1+ 0.01U_0402_16V7K
107 2 1
VDD33
4 2 1
GND/VSS RXIN-/MDI1-
17 2 1
GND/VSS R320
128
GND/VSS 49.9_0402_1%
3 +3VALW
AVDD33/AVDDL
7 1 1 1
AVDD33/AVDDL
21 20
GND/VSSPST AVDD33/AVDDL C497 C498 C499
38 16
GND/VSSPST NC/AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
51
GND/VSSPST 2 2 2
66
CLK_PCI_LAN GND/VSSPST
81 32 V2.5_LAN
GND/VSSPST VDD25/VDD18
91 54 1 1 1 1
GND/VSSPST VDD25/VDD18
1

101 78
R322 GND/VSSPST VDD25/VDD18 C500 C501 C502 C503
119 99
10_0402_5% GND/VSSPST VDD25/VDD18 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
Power

35 24
2

GND NC/VDD18
1 52 45
C504 GND NC/VDD18
80 64
10P_0402_50V8K GND NC/VDD18
100 110
GND NC/VDD18
116
2 NC/VDD18 R323
A 0_0402_5% A
07/04 for EMI
12 V_12P 1 2
AVDD25/HSDAC- V2.5_LAN
1
RTL8100CL_LQFP128 C505

0.1U_0402_16V4Z
2

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
LAN-8100CL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 29 of 53
5 4 3 2 1
 A B C D E

D11

3
LAN RESERVED LAN RESERVED
1 JP19
<17,34,35> WIRELESS_LED TIP RING
1 2
1 2
2 KEY KEY
1 1
3 4
3 4
5 6
5 6
7 8
1N4148_SOT23 7 8
9 10
MINI_LED 9 10
11 12
WL_ON 11 12
<20> WL_ON 13 14
13 14
15 16
1000P_0402_50V7K PCI_PIRQF# 15 16 W = 30 mils
<19> PCI_PIRQF# 17 18 +5VS
W = 40 mils 17 18 PCI_PIRQF#
+3VS 19 20
19 20
1 1 1 21 22
C506 C507 C508 21 22 W = 40 mils
23 24 +3VALW
0.1U_0402_16V4Z CLK_PCI_MINI 23 24 PCI_RST# 1000P_0402_50V7K
<19,23> CLK_PCI_MINI 25 25 26 26 PCI_RST# <19,25,27,29,35,37,38>
27 28 W = 40 mils
2 2 2 27 28 +3VS
PCI_REQ#3 29 30 PCI_GNT#3 1 1 1
<19> PCI_REQ#3 29 30 PCI_GNT#3 <19>
4.7U_0805_10V4Z 31 32
PCI_AD31 31 32 PME_EC# C509 C510 C511
<19,23,25,29> PCI_AD31 33 33 34 34 PME_EC# <29,37,38>
PCI_AD29 35 36 CH_CLK 0.1U_0402_16V4Z
<19,23,25,29> PCI_AD29 35 36 PCI_AD30 CH_CLK <34> 2 2 2
37 37 38 38
PCI_AD27 PCI_AD30 <19,23,25,29> 4.7U_0805_10V4Z
<19,23,25,29> PCI_AD27 39 39 40 40
PCI_AD25 41 42 PCI_AD28
<19,23,25,29> PCI_AD25 41 42 PCI_AD28 <19,23,25,29>
CH_DATA 43 44 PCI_AD26
<34> CH_DATA PCI_CBE#3 43 44 PCI_AD24 PCI_AD26 <19,23,25,29>
<19,25,29> PCI_CBE#3 45 45 46 46
PCI_AD23 PCI_AD24 <19,23,25,29> PCI_AD18
<19,23,25,29> PCI_AD23 47 47 48 48 1 2 IDSEL : AD18
49 50 R324 100_0402_5%
PCI_AD21 49 50 PCI_AD22
<19,25,29> PCI_AD21 51 51 52 52
CLK_PCI_MINI PCI_AD19 PCI_AD20 PCI_AD22 <19,25,29>
<19,25,29> PCI_AD19 53 53 54 54 PCI_AD20 <19,25,29>
55 56 PCI_PAR
55 56 PCI_PAR <19,25,29>
1

PCI_AD17 57 58 PCI_AD18
<19,25,29> PCI_AD17 PCI_CBE#2 57 58 PCI_AD16 PCI_AD18 <19,25,29>
07/04 for EMI <19,25,29> PCI_CBE#2 59 59 60 60 PCI_AD16 <19,25,29>
R325 PCI_IR DY# 61 62
<19,25,29> PCI_IRDY# 61 62 PCI_FRAME#
10_0402_5% 63 64
63 64 PC I_TRDY# PCI_FRAME# <19,25,29>
R326 1 2 10K_0402_5% 65 66
2

2 PCI_SERR# 65 66 PCI_STOP# PCI_TRDY# <19,25,29> 2

1 <19,25,29> PCI_SERR# 67 67 68 68 PCI_STOP# <19,25,29>
69 69 70 70
C512 PCI_PERR# 71 72 PCI_DEVSEL# +5VS
<19,25,29> PCI_PERR# PCI_CBE#1 71 72 PCI_DEVSEL# <19,25,29>
10P_0402_50V8K 73 74 0.1U_0402_16V4Z
2 <19,25,29> PCI_CBE#1 PCI_AD14 73 74 PCI_AD15
<19,25,29> PCI_AD14 75 75 76 76 PCI_AD15 <19,25,29>
77 78 PCI_AD13 1 1 1
77 78 PCI_AD13 <19,25,29>
PCI_AD12 79 80 PCI_AD11
<19,25,29> PCI_AD12 79 80 PCI_AD11 <19,25,29>
PCI_AD10 81 82 C513 C514 C515 1000P_0402_50V7K
<19,25,29> PCI_AD10 81 82 PCI_AD9
83 84 PCI_AD9 <19,25,29>
PCI_AD8 83 84 PCI_CBE#0 2 2 2
85 86 PCI_CBE#0 <19,25,29>
<19,25,29> PCI_AD8 PCI_AD7 85 86 4.7U_0805_10V4Z
87 88
<19,25,29> PCI_AD7 87 88 PCI_AD6
89 90 PCI_AD6 <19,25,29>
PCI_AD5 89 90 PCI_AD4
91 92 PCI_AD4 <19,25,29>
<19,25,29> PCI_AD5 91 92 PCI_AD2
93 94 PCI_AD2 <19,25,29>
PCI_AD3 93 94 PCI_AD0
95 96 PCI_AD0 <19,25,29>
<19,25,29> PCI_AD3 W = 30 mils 95 96
+5VS 97 98
PCI_AD1 97 98
99 100
<19,25,29> PCI_AD1 99 100
101 102
101 102 @ R327 +3VALW
103 104
103 104 10K_0402_5% @ 1000P_0402_50V7K
105 106
105 106
107 108 1 2
107 108
109 110 1 1 1
109 110
111 112
111 112 @ C516 C517 C518
113 114
113 114 4.7U_0805_10V4Z
115 116
115 116 R328 2 2 2
117 118
117 118 10K_0402_5%
119 120
119 120 0.1U_0402_16V4Z
121 122 1 2 +3VS
121 122

127
128
W = 30 mils 123 124 W=40mils
+5VS 123 124 +3VALW
QTC_C102A-052B11

127
128
3 3

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Mini PCI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 30 of 53
A B C D E
 A B C D E

+3VAMP_CODEC

1
R329
10K_0402_1%
+VDDA_CODEC
W=40Mil U24 (3.33V)
250mA

2
R330 C519 +5VS 4 5
0_0402_5% 1U_0603_10V4Z VIN VOUT

1
0.1U_0402_16V4Z
10U_0805_10V4Z
MONO_IN 1 2 MONO_IN1 1 2 MONO_INR 1 1 2 6 1 2 1 1
DELAY SENSE or ADJ R331 C522 @ C523

1
C520

C521
1 R334 R332 7 47K_0603_1% 1U_0603_10V4Z 0.1U_0402_16V4Z 1
1
2.4K_0402_5% ERROR CNOISE
2 2 1 2 2
1 2 8 3 R333

2
SD GND C524 27K_0603_1%
10K_0402_5% SI9182DH-AD_MSOP8

2
R335 R336 2
8/23 Change to DGND
1

1
560_0402_5% Q16 Q17 560_0402_5%
<25> PCM_SPK 1 2 2 MMBT3904_SOT23 2 1 2 SB_SPKR <20> 0.01U_0402_16V7K
MMBT3904_SOT23
3

8/23 Change to DGND

GPIO4 GPIO5

For Layout: 0 0 disable HP-out

Place decoupling caps near the
power pins of SmartAMC 0 1 disable EQ/HP-out(sys HP only)
device.
1 0 enable HP-out
R339 +3VDD_CODEC +3VAMP_CODEC R340
0_0805_5% 0_0805_5% 1 1 disable EQ/HP-0ut(sys HP only)
+3VALW 1 2 1 2 +VDDA_CODEC
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
10U_0805_10V4Z

1U_0603_10V4Z
2 2

249K_0402_1%
1 1 1 1 1 1 1 1

1
2 2 2 2 2 2 2 2
C528

C529

C530

C531

C532

R341

C533

C534

C535
+CODEC_REF C662
0.1U_0402_16V4Z

18
10

23

33

44
2

5
U25 1 2
RCOSC1

VDD5

VDDC18
VDDC10

AVDD33

AVDD44
VDD_CLK

1
R342
1 3K_0402_5%
RCOSC1
2
R343 1 2 0_0402_5% 3

2
<32> DIB_DATAN DIB_DATAN MIC_IN
C536 29 C537 1 2 10U_0805_10V4Z
MIC_IN MIC <35>
150P_0402_50V8J R344 1 2 0_0402_5% 4
1 <32> DIB_DATAP DIB_DATAP
32 CDROM_RC_R C538 2 1 2.2U_0603_6.3V4Z CDROM_R_R R345 1 2 4.7K_0402_5%
CD_IN_R CDROM_R <24>
R346 1 2 0_0402_5% 7 31 C DGNDA C539 2 1 2.2U_0603_6.3V4Z CD_GNA R347 1 2 2.7K_0402_5%
<32> PWRCLKP PWRCLKP CD_IN_GND CD_AGND <24>
30 CDROM_RC_L C540 2 1 2.2U_0603_6.3V4Z CDROM_R_L R348 1 2 4.7K_0402_5%
CD_IN_L CDROM_L <24>
R349 1 2 0_0402_5% 8
<32> PWRCLKN PWRCLKN

1
4.7K_0402_5%

2.7K_0402_5%

4.7K_0402_5%
27 @ R555 0_0402_5%
AC97_SDOUT LINE_IN_L
2 <20,23> AC97_SDOUT 15 28 1 2
AC97_SYNC SDATA_OUT LINE_IN_R
<20> AC97_SYNC 16
C541 AC97_RST# SYNC LINE_OUTL
<20> AC97_RST# 17 39 LINE_OUTL <33>
AC_RESET# LINE_OUT_L

R350

R351

R352
150P_0402_50V8J 40 LINE_OUTR

2
1 LINE_OUT_R DOCK_L+ LINE_OUTR <33>
20 42
AC_ONLY HP_OUT_L DOCK_R+
43
R353 1 HP_OUT_R
<20> AC97_SDIN0 2 33_0402_5% 21
SDATA_IN0 REF_FLT
38
R354 1 REF_FLT VC_SCA
<20> AC97_BITCLK 2 33_0402_5% 22 37
BIT_CLK VC_SCA VREF_SCA
36
VREF_SCA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1U_0603_10V4Z
11
3 ID0# @ R355 2 3
MBIAS/AVDD
34 +CODEC_REF 1 4.7K_0402_5% 1 1 1 1
12
ID1#

C542

C543

C544

C545
46 SPDIFO D36
S_PDIF SPDIFO <35,40>
14 CH751H-40_SC76
<34,35,40> MUTE_LED EAPD 2 2 2 2
47 1 2 JACK_DET_D <33>
MONO_INR GPIO_4 @ R356 1
45 2 10K_0402_5%
PC_BEEP
48 1 2 HP_PLUG_D <33>
GPIO_5 @ R587 1
13 2 10K_0402_5%
DSPKOUT
AVSS_CLK

24 1 2 C546 1 2 15P_0402_50V8J D12

XTLO
GNDC19

AGND35
AGND41

CH751H-40_SC76
GNDC2

GNDC9

25
XTLI
2
GND8

R357
33_0402_5%
X2
5/13 HP requirement
CX20468-31_TQFP48 24.576MHZ_16P_XSL024576FG1H
2
6
9
19
26

35
41

@ C525 1 2
0.1U_0402_16V4Z
<37,38> MUTE_GATE
1 2 Q58 C547 15P_0402_50V8J
2

2N7002_SOT23
G

R588
@ C526
0_0402_5% +5VALW 1 2 1 3
1 2 1K_0402_5%
D

1
@ C700
@C527 close to dock side
0.1U_0402_16V4Z 1U_0603_10V4Z Q59
DOCK_LOUT_R <40>
2

2 2N7002_SOT23 cap. high 5.7mm

G

1 2

R337 DOCK_R+ C730 1 2 100U_6.3V_M R567 2 33_0805_5% DOCK_LOUT_R R568 1 2 1K_0402_5%

+

1 3 1
0_1206_5%
D

C731 1 2 100U_6.3V_M R569 2 33_0805_5% DOCK_LOUT_L R570 1 2 1K_0402_5%

+

1 2 1
8/23 reseve C700, slowly turn on Q59/Q60 Q60 1 2
2

@ R338 @ R589 0_0402_5%

G

4 0_1206_5% 2N7002_SOT23 4
DOCK_L+ DOCK_LOUT_L <40>
1 2 GNDA <33,35,40> 1 3
5/10 HP requirement
D

1 2

GND GNDA 0_0402_5%

@ R590
Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
AMOM_codec
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
07/25 Audio POP issue AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 31 of 53
A B C D E
 MTP28

1
MTP52

1
VDD MTP59
MTP26 BR908_CC
0.1U_0402_10V6K
1

1
MBR908A 1 1

6
BAV99DW-7_SOT363 MTP29 MC928
MC930 VDD MC978 C906 and C908 must be Y3 type
MTP22 2.2U_0805_10V6K 0.1U_0402_10V6K Capacitors for Nordic
2 2 1 1

1
1 2 MTP36 MTP37 Countries only
1
1 MTP35 1 MTP38
1

MR932 MC926 AGND_LSD MTP58 MFB902

1
15K_0402_5% 10P_0402_50V8J DGND_LSD R ING_2 MOD_RING

24
1 2
1 MTP39 1

2
MT902 1 2 CLK2 1 2 CLK MU902 MR902 MMZ1608D301BT_0603 MTP41

4
1 4 BR908_AC1 1M_0805_5% MC902

AVdd

DVdd
<31> PWRCLKN
1 MFB906 21 RAC1 1 2 RAC 1/RING 1 2 0.033U_1206_100V7K 1 MC906
RAC1

1
MTP23 1 2 MC904 470P_1808_3KV
MC962 1 MMZ1608D301BT_0603 26 20 TAC1 2 1 TAC1/TIP 1 2 0.033U_1206_100V7K MBR904
CLK TAC1

TB3100M-13-01_SMB
1

47P_0603_50V8J 1M_0805_5% MMBD3004S_SOT23

2 MBR908B MC970 MTP30 MTP34 MR904 TIP_2 2 MJ2
3
1 MTP40 1

MRV902
1
2 3 PCLK BAV99DW-7_SOT363 0.1U_0402_10V6K 19
<31> PWRCLKP PRI SEC 2 RAC2 TRDC 2
MTP24 MR906 1 2 6.8M_0805_5%

1
3

2
PWR+ 1
30U_82154R_1%_1:1.67 Check 0.047u or 10p cap 7 PWR+ TAC2 18 1
MTP27

2
MTP60 MTP33 E&T_3800-02
1

2
1

MTP72 AGND_LSD MR922 MC958 MC918 AGND_LSD 1 GND

2
1 1 0_0402_5% 1 EIC 1 MTP32
12 1 2 0.1U_0603_16V7K
MC922 DIB_P1 DIB_P2 TRDC 0.015U_0603_25V7K 2
<31> DIB_DATAP 1 2 10P_1808_3KV 1 2 27 MBR906 MC908
DIB_P MR910 MMBD3004S_SOT23 470P_1808_3KV
11
EIC 237K_0805_1% 2
AGND_LSD
MC924 1 2 10P_1808_3KV DIB_N1 1 2 DIB_N2 28 9 RXI 1 2 RXI-1

1
<31> DIB_DATAN DIB_N RXI 1 MTP71
0_0402_5% MFB904
MTP25 MTP73 MTP62 TIP_2 MOD_TIP
MR924 1 1 2
MT922 GPIO1 1 MTP70 1
AGND_LSD MMZ1608D301BT_0603 MTP42
1 1 1

1
MJ1 1 4 MTP61 5 R Bias 1 MR9542
RBias 59K_0402_1%
1 1 2 MC966
1 Vc_LSD MTP69 MC910 0.01U_0805_100V7M
2 3
2 Vc VZ 1 1 MR908 2 BRIDGE_CC
3 10 1 2
3 Vref_LSD VZ 348K_0805_1% 0.047U_1206_100V7K
4 4 AGND_LSD
4 VRef

1
5 MC940 MTP68 MTP67 C
5 1U_0603_6.3V6M MTP63 EIO 1 1 MQ902
6 2 3 17 2
6 PRI SEC EIO B PMBTA42_SOT23
7 1 1 1 1 8 Use 59K_0402_1% for MR954
1
7 NC1

2
4
8 @ 30U_82154R_1%_1:1.67 22 16 EIF E

3
8 MC974 MC944 MC976 NC2 EIF MQ904
25
NC3

1
@ HEADER8 @ 0.001U_0402_50V7M 14 C 1
2 22 2 TXO TXO MQ906
MJ1B 2
0.001U_0402_50V7M B PMBTA42_SOT23 FZT458TA_SOT223
1 1
29 13
0.1U_0402_10V6K PADDLE TXF E MTP66
2 2

DC_GND

1 3
TXF 1
3 3 AGND_LSD 1 MTP64

DGnd
AGnd
4 4
5 5

1
CX20493-58_QFN28 MR928
6 6

1
1 MTP65 MR938 27_0805_5%
7 7
6

15

23
110_0603_5%
8 8

2
MTP31
@ HEADER8 1 MTP49

2
GND AGND_LSD
DGND_LSD AGND_LSD AGND_LSD
AGND_LSD

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
AMOM_modem
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 32 of 53
 A B C D E

HEADPHONE OUT/LINE OUT

+5VAMP R362 +5VS
0.1U_0402_16V4Z 0_1206_5% Gain Settings
1 2

1 1 1
GAIN0 GAIN1 SE/BTL# Av(inv)
C548 C549 C550 6 dB
10U_0805_10V4Z 0 0 0
2 2 2
1 1
0 1 0 * 10 dB
0.1U_0402_16V4Z

1 0 0 15.6 dB

19

18
7
U26 21.6 dB
1 1 0

PVDD2
PVDD1
VDD
C551 1 2 0.047U_0603_16V7K LINE_C_OUTR 23 RLINEIN
<31> LINE_OUTR SPKL-
LOUT-
9 X X 1 4.1 dB
C552 1 2 0.47U_0603_16V7K HP_C_OUTR 20 4 SPKL+
RHPIN LOUT+ SPKR- SPKL+ <35>
ROUT- 16
C553 1 2 0.47U_0603_16V7K 8 21 SPKR+ 10 dB
RIN ROUT+ SPKR+ <35>
+5VS

1
C554 1 2 0.47U_0603_16V7K 10 15 SE
LIN SE/BTL# R363 @ R364
C555 1 2 0.47U_0603_16V7K HP_C_OUTL 6 17 100K_0402_5% 100K_0402_5%
LHPIN HP/LINE#
C556 1 2 0.047U_0603_16V7K LINE_C_OUTL 5

2
<31> LINE_OUTL LLINEIN
GAIN1 3
GAIN0 2
C557 1 2 0.47U_0603_16V7K 14 JP22
PC-BEEP SPKL+
BYPASS 11 1 1
EC_MUTE# 22 SPKL- 2
<37,38> EC_MUTE# SHUTDOWN# 2

1
2 SPKR+ 3 3

GND1
GND2
GND3
GND4
@ R365 R366 SPKR- 4
C558 100K_0402_5% 100K_0402_5% 4
0.47U_0603_10V7K ACES_85205-0400
1

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J
1
12
13
24

2
TPA0312PWP_TSSOP24 1 1 1 1

C559

C560

C561

C562
2 2

2 2 2 2
@ @ @ @

+5VS

1
C735
0.1U_0402_16V4Z
2
5

U52
JACK_DET 2
P

I0 SE
4
HP_PLUG O
1
I1
G

TC7SH32FU_SSOP5
3

5/13 HP requirement

3 +5VS 3
+5VS

+5VS +5VS
1

1
R368 +5VS +3VS R433 +5VS +3VS
1

1
100K_0402_5% 100K_0402_5%
2

2
1

1
R571 R434
100K_0402_5% HP_PLUG R586 100K_0402_5% JACK_DET R358 R359
R367
2

2
1

1
D 100K_0402_5% 100K_0402_5% D 100K_0402_5% 100K_0402_5%
HP_PLUG# 2 JACK_DET# 2
2

2
<35> HP_PLUG# <40> JACK_DET#
G Q54 G Q24
HP_PLUG_D <31> JACK_DET_D <31>
2

2
G

G
S 2N7002_SOT23 S 2N7002_SOT23
3

3
1

1
D D
3 1 2 3 1 2 Q57
Q53
S

D
G G 2N7002_SOT23
S 2N7002_SOT23 S
3

3
Q52 Q56
2N7002_SOT23 2N7002_SOT23

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
AMP & Audio jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 33 of 53
A B C D E
 +5V
+USB_VCCB
C565 U28
2 1 5 1
IN OUT
1 USB CONNECTOR 0/3 (Left side)

1
0.1U_0402_16V4Z 4 C566
ON# R369
3 SET
2 0.47U_0603_16V7K
GND

2
10K_0402_5% 2
R370 AATI4610AIGV-T1_SOT23-5

2
07/05 for EMI
4.7K_0402_1% OVCUR#2 07/05 for EMI
OVCUR#0 <20>
1

1
1
R371 C570 R563 R562 0_0402_5%
20K_0402_5% 1000P_0402_50V7K 0_0402_5% R561 0_0402_5% 1 2
1 2
2

2
OVCUR#3 L33 L34 WCM2012F2S-900T04_0805
OVCUR#3 <20> USBP0+ USBP0+_R JP23 USBP3+_R USBP3+
4 3 3 3
<20> USBP0+ 4 3 4 4 USBP3+ <20>
1 5
1 5
2 6
USBP0- USBP0-_R 2 6 USBP3-_R USBP3-
<20> USBP0- 1 2 3 7 2 1 USBP3- <20>
1 2 3 7 2 1
4 8
+5V WCM2012F2S-900T04_0805 4 8
+USB_VCCC 9 1 2
@ C573 @ U29 +USB_VCCB GND R560 0_0402_5%
1 2 10 GND
2 1 5 IN OUT 1 W=40mils R559 0_0402_5% 11 GND
1 12 GND

1
0.1U_0402_16V4Z 4 @ C574 @ 0_0603_5%
ON#

1000P_0402_50V7K
0.1U_0402_16V4Z
3 @ R372 1 1 1 1 2 R564 +USB_VCCC
SET 0.47U_0603_16V7K SUYIN_020122MR008S573ZR
GND 2
2

100U_6.3V_M
10K_0402_5% +
@ R373 AATI4610AIGV-T1_SOT23-5 +USB_VCCB

2
2 2
2

C567
4.7K_0402_1% OVCUR#3 W=40mils

C568

C569
1

1
1

0.1U_0402_16V4Z
1000P_0402_50V7K

100U_6.3V_M
@ R374 @ C578 1
1 1
20K_0402_5% 1000P_0402_50V7K +
2

C575
2

2 2 2

C577

C576
BT CONNECTOR
<20> BT_ON# 5/4 reserve +USB_VCCB
2
G

C581 D35
1U_0603_10V4Z USBP0+_R 1 4 USBP3+_R
D1+ D2+
+3VALW 3 1 +3V_BT 1 2
S

1 2 5
C582 GND VCC
1U_0603_10V4Z AO3413_SOT23 USBP3-_R 3 6 USBP0-_R
Q18 D2- D1-
D28 2 @ IP4220CZ6_SO6
JP25
3 1
1
2
USBP6+ 2
<17,30,35> WIRELESS_LED 1 <20> USBP6+ 3
USBP6- 3
<20> USBP6- 4
WIRELESS_LED_BT 4
2 5
R375 5
<30> CH_DATA 1 2 100_0402_5% 6
6
R376 1 2 100_0402_5% 7
<30> CH_CLK BT_DET# 7
<20> BT_DET# 8
1N4148_SOT23 8
ACES_87213-0800

0.1U_0402_16V4Z 2 1 C753
<35> ON/OFFBTN#
@
0.1U_0402_16V4Z 2 1 C754
<35,37,38> KSI0
@
0.1U_0402_16V4Z 2 1 C755
<35,37,38> KSI1
@
0.1U_0402_16V4Z 2 1 C756
<35,37,38> KSI3
@
0.1U_0402_16V4Z 2 1 C757
<35,37,38> KSI4
@
0.1U_0402_16V4Z 2 1 C758
<35,37,38> KSO17
@
0.1U_0402_16V4Z 2 1 C759
<17,30,35> WIRELESS_LED
@
0.1U_0402_16V4Z 2 1 C760
<35,37,38> VOL_UP#
@
0.1U_0402_16V4Z 2 1 C761
<35,37,38> VOL_DWN#
@
0.1U_0402_16V4Z 2 1 C762
<35,37,38> LID_SW#
@
0.1U_0402_16V4Z 2 1 C763
<35,37,38> NUMLED#
@
0.1U_0402_16V4Z 2 1 C764
<31,35,40> MUTE_LED
@
0.1U_0402_16V4Z 2 1 C765
<35,37,38> PWR_ACTIVE#
@
0.1U_0402_16V4Z 2 1 C766
<35,36,38> PA_LED_ALW
@
0.1U_0402_16V4Z 2 1 C767
<35,36> PR_LED_ALW
@
0.1U_0402_16V4Z 2 1 C768
<35,36> PA_LED
@
0.1U_0402_16V4Z 2 1 C769
<35,36> PR_LED
@
0.1U_0402_16V4Z 2 1 C770
<35,36> PA_LED_VS
@
0.1U_0402_16V4Z 2 1 C771
<35,36> PR_LED_VS
@
Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
Bluetooth & USB CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
2005.08.11 for EMI solution DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 34 of 53
 5 4 3 2 1

KSI7 C583 D@ 1 2 100P_0402_50V8J KSI1 C663 C@1 2 100P_0402_50V8J

Power BTN
KSI0 C584 D@ 1 2 100P_0402_50V8J KSI7 C664 C@1 2 100P_0402_50V8J
D13 R377 100K_0402_5%
5/3 change
KSI5 C585 D@ 1 2 100P_0402_50V8J KSI6 C665 C@1 2 100P_0402_50V8J DAN202U_SC70 1 2
INT_KBD CONN.( TYPE "D" KB) +3VL
KSI1 C586 D@ 1 2 100P_0402_50V8J KSO9 C666 C@1 2 100P_0402_50V8J 3 ON /OFF# ON/OFF# <37,38>

KSI4 C587 D@ 1 2 100P_0402_50V8J KSI4 C667 C@1 2 100P_0402_50V8J ON/OFFBTN# 1

KSI[0..7] KSI6 C588 D@ 1 2 100P_0402_50V8J KSI5 C668 C@1 2 100P_0402_50V8J 2
KSI[0..7] <34,37,38> EC_PWR_ON# <43>
KSI3 C589 D@ 1 2 100P_0402_50V8J KSO0 C669 C@1 2 100P_0402_50V8J 15.4 ( TYPE "C" KB)
KSO[0..17] JP20 +3VL
D KSO[0..17] <34,37,38>
KSI2 C590 D@ 1 2 100P_0402_50V8J KSI2 C670 C@1 2 100P_0402_50V8J KSI1 5/3 change D
KSI7 24
23

1
KSO1 C591 D@ 1 2 100P_0402_50V8J KSI3 C671 C@1 2 100P_0402_50V8J KSI6 1
KSO9 22 Q19 C595 D14

O
21

1
JP27 KSO2 C592 D@ 1 2 100P_0402_50V8J KSO5 C672 C@1 2 100P_0402_50V8J KSI4 DTC124EK_SC59
KSI7 KSI5 20 R378 RLZ20A_LL34
26
KSI0 26 KSO4 C593 D@ 1 KSO1 KSO0 19 2
25 2 100P_0402_50V8J C673 C@1 2 100P_0402_50V8J 4.7K_0402_5%

2
KSI5 25 KSI2 18
24
24 17

G
KSI1 KSO0 C594 D@ 1 2 100P_0402_50V8J KSI0 C674 C@1 2 100P_0402_50V8J KSI3

I
23

2
KSI4 23 KSO5 16
22

3
KSI6 22 KSO16 C596 D@ 1 KSO2 KSO1 15
21
21 2 100P_0402_50V8J C675 C@1 2 100P_0402_50V8J 14
1000P_0402_50V7K
KSI3 20 KSI0 EC_ON
KSI2 20 KSO5 KSO4 KSO2 13 <37,38,45> EC_ON
19 C597 D@ 1 2 100P_0402_50V8J C676 C@1 2 100P_0402_50V8J
KSO1 19 KSO4 12
18 18 11 WHEN R=0,Vbe=1.35V
KSO2 17 KSO6 C598 D@ 1 2 100P_0402_50V8J KSO7 C677 C@1 2 100P_0402_50V8J KSO7 WHEN R=33K,Vbe=0.8V
17 10

1
KSO4 KSO8 D
16 16 9
KSO0 15 KSO3 C599 D@ 1 2 100P_0402_50V8J KSO8 C678 C@1 2 100P_0402_50V8J KSO6 2
KSO16 15 KSO3 8 Q20 G
14 14 7
KSO5 13 KSO7 C600 D@ 1 2 100P_0402_50V8J KSO6 C679 C@1 2 100P_0402_50V8J KSO12 @ 2N7002_SOT23 S

3
KSO6 13 KSO13 6
12 12 5
KSO3 11 KSO8 C601 D@ 1 2 100P_0402_50V8J KSO3 C680 C@1 2 100P_0402_50V8J KSO14
KSO7 11 KSO11 4
10 10 3
KSO8 9 KSO9 C602 D@ 1 2 100P_0402_50V8J KSO12 C681 C@1 2 100P_0402_50V8J KSO10
KSO9 9 KSO15 2
8 8 1
KSO10 7 KSO10 C603 D@ 1 2 100P_0402_50V8J KSO13 C682 C@1 2 100P_0402_50V8J
KSO11 7
6 6
KSO12 5 KSO11 C604 D@ 1 2 100P_0402_50V8J KSO14 C683 C@1 2 100P_0402_50V8J ACES_85201-2405
KSO13 5
4 4
KSO14 3 KSO12 C605 D@ 1 2 100P_0402_50V8J KSO11 C684 C@1 2 100P_0402_50V8J LDO5
KSO15 3
2 2
KSO17 1 KSO13 C606 D@ 1 2 100P_0402_50V8J KSO10 C685 C@1 2 100P_0402_50V8J
1 TP to MB CONN Consumer IR

1
C ACES_85201-2605 KSO14 C607 D@ 1 KSO15 C686 C
2 100P_0402_50V8J C@1 2 100P_0402_50V8J CIR@ R379
100_0402_5%
KSO15 C660 D@ 1 2 100P_0402_50V8J
5/9 change

2
KSO17 C661 D@ 1 2 100P_0402_50V8J @ C701 1 2 0.1U_0402_10V6K JP35

+5V 1 1 1
TP_DATA 2 CIR@ C608 CIR@ C609
<37,38> TP_DATA TP_CLK 3 0.1U_0402_10V6K
<37,38> TP_CLK 4 4.7U_0805_6.3V6K
2 2 U30 CIR@
+3VS 5
3 1
6 CIR_IN Vs GND
<37,38,40> CIR_IN 4 2
7 OUT GND
8 TSOP6236TR_4P
TPM(reserve) 1
C610 @
1
C611 @
1
C612 @
1
C613 @
ACES_87152-0807
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2

+3VS
11
25

19
5

@ U31
1
VDD
VDD
VDD

VDDC

@ R452 @ R380
10K_0402_5% 10K_0402_5%
LPC_AD0 2 26 1 2 +3VS
<19,37,38> LPC_AD0 LPC_AD1 LAD0 LPCPD#
3 17
Switch board conn
2

<19,37,38> LPC_AD1 LPC_AD2 LAD1 TESTEN

<19,37,38> LPC_AD2 6 16
+3VS LPC_AD3 LAD2 TESTIO
7 21
<19,37,38> LPC_AD3 LAD3 PACCESS
22 JP28 Audio board conn
B PENABLE ON/OFFBTN# B
9 <34> ON/OFFBTN# 1
CLKOVD 1
1

TPM KSI0 2
<34,37,38> KSI0 2
1

CLK_PCI_TPM 8 SLD 9630 TT 1.1 KSI1 3 JP29

<19> CLK_PCI_TPM LPC_FRAME# LCLK <34,37,38> KSI1 KSI3 3
13 1 @ R381 @ R382 4 +5V 1
<19,37,38> LPC_FRAME# LFRAME# NC <34,37,38> KSI3 4 1
@ R383 NB_RST# 27 14 300_0402_5% 10K_0402_5% KSI4 5 2
<13,19,24,28> NB_RST# SIRQ LRESET# NC <34,37,38> KSI4 KSO17 5 USBP4+ 2
4.7K_0402_5% 12 15 6 3
2

<19,25,37,38> SIRQ PCI_CLKRUN# SERIRQ NC WIRELESS_LED 6 <20> USBP4+ USBP4- 3

23 28 7 4
2

<19> PCI_CLKRUN# CLKRUN# NC <17,30,34> WIRELESS_LED VOL_UP# 7 <20> USBP4- OVCUR#4 4

20 <34,37,38> VOL_UP# 8 <20> OVCUR#4 5
BADDR VOL_DWN# 8 5
<34,37,38> VOL_DWN# 9 6
9 6
1

LID_SW# 10 USBP5+ 7
GND
GND
GND
GND

<34,37,38> LID_SW# NUMLED# 10 <20> USBP5+ USBP5- 7

<34,37,38> NUMLED# 11 <20> USBP5- 8
@ R384 MUTE_LED 11 8
Base I/O Address <31,34,40> MUTE_LED 12
12
9
9
4.7K_0402_5% SLD9630TT_TSSOP28 0 = 02Eh 13 SPDIFO 10
4
10
18
24

13 <31,40> SPDIFO 10
* 1 = 04Eh 14 11
2

PWR_ACTIVE# 14 R582 11
<34,37,38> PWR_ACTIVE# 15 12
15 18K_0402_5% 12
+5VALW 16 13
PA_LED_ALW 16 DOCK_MIC 1 13
<34,36,38> PA_LED_ALW 17 <40> DOCK_MIC 2 14
PR_LED_ALW 17 MIC 14
<34,36> PR_LED_ALW 18 <31> MIC 15
18 15
+5V 19 16
PA_LED 19 16
<34,36> PA_LED 20 +5VS 17
PR_LED 20 HP_PLUG# 17
<34,36> PR_LED 21 <33> HP_PLUG# 18
21 SPKR+ 18
+5VS 22 <33> SPKR+ 19
JP30 PA_LED_VS 22 SPKL+ 19
<34,36> PA_LED_VS 23 <33> SPKL+ 20
PR_LED_VS 23 20
1 24
1 +5VS FOR LPC SIO DEBUG PORT <34,36> PR_LED_VS 24

2
2
2
3
+3VALW 25
25 2005/07/21 R583 ACES_87213-2000
3 +3VS
4 ACES_85201-2505 2K_0402_5%
4
5
5
6 8/23 Add +3VALW power rail

1
6 LPC_AD[0..3] <19,37,38>
LPC_AD0
7
7
8 LPC_AD1 for Boxster lid Switch 5/3 pin swap
8 LPC_AD2
9 9
A LPC_AD3 A
10 10
11 LPC_FRAME#
11 LDRQ0# LPC_FRAME# <19,37,38>
12 LDRQ0# <19> @ R385
12 PCI_RST# 10K_0402_5%
13 13 PCI_RST# <19,25,27,29,30,37,38>
14 14 2 1
15 CLK_PCI_SIO 1 2
15 CLK_PCI_SIO_R <19,23>
16 16 SIRQ <19,25,37,38>
17 @ R386
17
18 22_0402_5% Security Classification Compal Secret Data
18
19 19 Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
20 20 KBD,ON/OFF,T/P,LED/B,DEBUG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ACES_85201-2005 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 35 of 53
5 4 3 2 1
 5 4 3 2 1

For PA For PR
FOR POWER BUTTON BACKLIGHT SYSTEM POWER FOR POWER BUTTON BACKLIGHT SYSTEM POWER
"Vertical" "Right Angle"
R390 D18 15.4@
D 150_0402_5% R389 15.4@ D17 D

<37,38> PMLED_1# 1 2 1 2 680_0402_5% 2

PA_LED <34,35> PMLED_1# PR_LED <34,35>
1 2 1
HT-170NBQA_0805 3

12-21UYOC/S530-A2/TR8_YEL

15.4@
R392 R391 15.4@ D19
D20
150_0402_5% 680_0402_5% 2
BATLED_0# 2 PR_LED_ALW <34,35>
<37,38> BATLED_0# 2 1 1 2 PA_LED_ALW <34,35,38> 1 1
3

HT-170NBQA_0805 12-21UYOC/S530-A2/TR8_YEL

15.4@
R393 R394 15.4@ D22
D21
150_0402_5% 680_0402_5% 2
ACT_LED PR_LED_VS <34,35>
<24> ACT_LED 1 2 1 2 PA_LED_VS <34,35> 1 2 1
3

HT-170NBQA_0805 12-21UYOC/S530-A2/TR8_YEL
5/4 change

R395 D@ D@ D23 R396 15.4@ D24 15.4@

150_0402_5% 680_0402_5%
1 2 1 2 PA_LED_VS CAPSLED# 1 2 1 2 PR_LED_VS
C <37,38> CAPSLED# C
17-21UYOC/S530-A2/TR8_ORG
HT-170NBQA_0805

15.4@ R574 15.4@ D34 for 15.4 PA

150_0402_5%
CAPSLED# 1 2 1 2 PA_LED_VS

HT-170NBQA_0805

PR_LED_VS <34,35>
5/10 change
PA_LED_VS <34,35>

"Vertical" "Right Angle"

2

D25 D26 PA@

17-21UYOC/S530-A2/TR8_ORG
B HT-110NBQA_0805 B
PR@
1

1
2

PR@ R566 R397

680_0402_5% 150_0402_5%
PA@
1

R468
1

1K_0402_5% Q21
CARD_LED 2 1 2
<25,26> CARD_LED
MMBT3904_SOT23
7411@
3

7411@

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
INDICATE LED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 36 of 53
5 4 3 2 1
 A B C D E

+3VL +EC_AVCC
5/3 change
ECAGND <38> 5/3 change
+3VL
1

ECAGND
910@ C614
1U_0603_10V6K
2

123
136
157
166

122
167
137

161
159
16
34
45

17
35
46

95
96
BATT_TEMP <38,49>
U32
0.01U_0402_16V7K

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

GND1
GND2
GND3
GND4
GND6
GND7

VCCA

VCCBAT
AGND

BATGND
SIRQ 7 81 C616 1 2 ECAGND
1 <19,25,35,38> SIRQ SERIRQ AD0/GPIAD0 1
LPC_FRAME# 9 82
<19,35,38> LPC_FRAME# LPC_AD0 LFRAME# AD1/GPIAD1 BATT_OVP ADP_IR <38>
<19,35,38> LPC_AD0 15 83 BATT_OVP <38,44>
LPC_AD1 LAD0/FWH0 PWR/GND AD2/GPIAD2 ADP_IR
<38> EC_RST# <19,35,38> LPC_AD1 14 84 1 2 ADP_I <44>
LPC_AD2 LAD1/FWH1 AD3/GPIAD3 R399
<19,35,38> LPC_AD2 13 87
R400 LPC_AD3 LAD2/FWH2 AD4/GPIAD4
AD Input or GPI BID 10K_0402_5%
5/3 change 47K_0402_5%
<19,35,38> LPC_AD3
CLK_PCI_EC
10
18
LAD3/FWH3 AD5/GPIAD5
88
89
BID <38> 1
<19,23,38> CLK_PCI_EC EC_RST# LCLK Host interface AD6/GPIAD6 DOCK_VOL_DWN#
1 2 19 90 C617
+3VL
31
ECRST# AD7/GPIAD7 DOCK_VOL_DWN# <38,40>
0.22U_0603_10V7K
5/3 change
1 ECSCI#
1

J3 C618 99 DAC_BRIG 2
DA0/GPODA0 DAC_BRIG <17,38> +3VL
0.1U_0402_16V4Z EC_GA20 5 100 EN_FAN1
<20,38> EC_GA20 KB_RST# GPIO02/GA20 DA1/GPODA1 IR EF EN_FAN1 <4,38>
JOPEN 6 101 @ R401
2

2 <20,38> KB_RST# KSI[0..7] GPIO03/KBRST# DA2/GPODA2 IREF <38,44>

102 10K_0402_5%
<34,35,38> KSI[0..7] KSI0 DA output or GPO DA3/GPODA3 KBA1
71 KSI0/GPIK0 DA4/GPODA4 1 1 2
KSI1 72 42
KSI2 KSI1/GPIK1 DA5/GPODA5 @ R402
73 KSI2/GPIK2 DA6/GPODA6 47
KSI3 74 174 10K_0402_5%
+5VS KSI4 KSI3/GPIK3 DA7/GPODA7 KBA3
77 KSI4/GPIK4 1 2
R403 910@ KSI5 78 32 INVT_PWM
KBD_DATA KSI6 KSI5/GPIK5 PWM0/GPOW0 INVT_PWM <17,38>
10K_0402_5% 2 1 79 33 910@ R404
R405 910@ KSI7 KSI6/GPIK6 PWM1/GPOW1 ACOFF 10K_0402_5%
80 KSI7/GPIK7 PWM3/GPOW3 37 ACOFF <38,44>
10K_0402_5% 2 1 KBD_CLK KSO[0..17] PWM 38 KBA5 1 2
<34,35,38> KSO[0..17] KSO0 or GPOW PWM4/GPOW4 EC_ON
49 KSO0/GPOK0 PWM5/GPOW5 39 EC_ON <35,38,45>

1
+5VS KSO1 50 40 LID_OUT#
KSO2 KSO1/GPOK1 PWM6/GPOW6 LID_OUT# <20,38>
R407 910@ 51 D@ R406
10K_0402_5% 2 PS2_DATA KSO3 KSO2/GPOK2 Key matrix scan VLDT_EN 1K_0402_5%
1 52 36 VLDT_EN <38,42>
R408 910@ KSO4 KSO3/GPOK3 PWM2/GPOW2/FAN1PWM
53 KSO4/GPOK4 PWM7/GPOW7/FAN2PWM 43
10K_0402_5% 2 1 PS2_CLK KSO5 56 11 GPIO5

1 2
KSO6 KSO5/GPOK5 FAN/PWM GPIO05/FAN3PWM/TEST_TP FAN_SPEED1 BID
57 KSO6/GPOK6 FANFB1/TOUT1/GPIO2E 171 FAN_SPEED1 <4,38>
+5V KSO7 58 176
R410 KSO8 KSO7/GPOK7 GPWU7/TIN2/FANFB2 GPIO6 C@ R409
59 KSO8/GPOK8 GPIO06/FANFB3/DPLL_TP 12
10K_0402_5% 2 1 TP_DATA KSO9 60 1K_0402_5%
R411 KSO10 KSO9/GPOK9 EC_SMC_1
61 KSO10/GPOK10 SCL1 163 EC_SMC_1 <38,39,49>
2 10K_0402_5% TP_CLK KSO11 EC_SMD_1 2
2 1 64 164

2
KSO12 KSO11/GPOK11 SM BUS SDA1 EC_SMC_2 EC_SMD_1 <38,39,49>
65 KSO12/GPOK12 SCL2 169 EC_SMC_2 <4,38>
KSO13 66 170 EC_SMD_2
KSO14 KSO13/GPOK13 SDA2 EC_SMD_2 <4,38>
67 KSO14/GPOK14
KSO15 68 105 EC_TINIT#
KSO16 KSO15/GPOK15 GPIO20/E51CS#/ISPEN_TP URXD
153 KSO16/GPOK16 GPIO21/E51RXD/ISPCLK 106 URXD <38>
KSO17 UTXD
154 KSO17/GPOK17 GPIO22/E51TXD/ISPDAT 107
108
UTXD <38> Board ID
KBD_CLK A20/GPIO23 AIR_ACIN
110 109 AIR_ACIN <38,44>
KBD_DATA PSCLK1 GPIO24 LID_SW#
111
PSDAT1 GPIO25
118 LID_SW# <34,35,38> Cayenne 17" High R406
PS2_CLK 114 119
C R Y1 PS2_DATA PSCLK2 PS2 interface GPIO2 GPIO26 SYSON
<38> C R Y1 115 148 SYSON <28,38,41,46>
C R Y2 TP_CLK PSDAT2 GPIO27 SUSP#
<38> C R Y2 <35,38> TP_CLK 116
PSCLK3 GPIO28
149 SUSP# <28,38,39,41> Boxter 15.4" L ow R409
TP_DATA 117 155 VR_ON
<35,38> TP_DATA PSDAT3 GPIO29 VR_ON <38,48>
156
C R Y1 GPIO2A
158 162
C R Y2 XCLKI GPIO2B PCI_RST#
160 165 PCI_RST# <19,25,27,29,30,35,38>
XCLKO LRST#/GPIO2C PWRBTN_OUT#
168 PWRBTN_OUT# <20,38>
EC_RSMRST# GPIO2D EC_THERM#
<20,38> EC_RSMRST# 3 175 EC_THERM# <20,38>
GPIO00/E51IT0 TOUT2/GPIO2F
1 1 4
GPIO01/E51IT1 ON /OFF#
C619 C620 EC_SCI#
8
20
GPIO04 GPWU or GPI GPWU0
2
26 AC IN
ON/OFF# <35,38> 5/3 change
10P_0402_50V8K<20,38> EC_SCI# GPIO07 GPWU1 ACIN <38,43,45>
1

10P_0402_50V8K 21 29 CIR_IN
2 2 GPIO08 GPWU2 CIR_IN <35,38,40> +3VL
22 30 SLP_S3#
OUT
IN

GPIO09 GPWU3 SLP_S5# SLP_S3# <20,38>

23 44 SLP_S5# <20,38>
M_SEN# NUMLOCK#/GPIO0A GPIO0 GPWU4 VOL_DWN#
<18,38> M_SEN# 24 76 VOL_DWN# <34,35,38>
CONA# GPIO0B GPWU5 PME_EC#
<38,40> CONA# 25 172 PME_EC# <29,30,38>
CLKRUN#/GPIO0C GPWU6/TIN1

1
ENABLT
NC

NC

Y6 27
<13,17,38> ENABLT BKOFF# GPIO0D
32.768KHZ_12.5P_1TJS125DJ2A073 28 85 910@ R412
<17,38> BKOFF# DOCK_VOL_UP# GPIO0E GPIO18/XIO8CS# PMLED_1# 10K_0402_5%
<38,40> DOCK_VOL_UP# 41 86
2

SCROLLLOCK#/GPIO0F GPIO19/XIO9CS# PWR_ACTIVE# PMLED_1# <36,38>

91 PWR_ACTIVE# <34,35,38>
FSTCHG GPIO1A/XIOACS# BATLED_0#
<38,44> FSTCHG 48 92

2
3 GPIO10 GPIO1B/XIOBCS# BATLED_0# <36,38> 3
CAPSLED# 54 93
<36,38> CAPSLED# CAPLOCK#/GPIO11 GPIO1C/XIOCCS#
NUMLED# 55 94 EC_TINIT#
<34,35,38> NUMLED# EC_SMI# FNLOCK#/GPIO12 GPIO1D/XIODCS#
<20,38> EC_SMI# 62 97
EC_MUTE# GPIO13 GPIO1 GPIO1E/XIOECS# GPIO5
63 98
A5/EMWB_TP

<33,38> EC_MUTE# GPIO14 GPIO1F/XIOFCS# MUTE_GATE <31,38>

A4/DMRP_TP

69 BIOS I/F
A1/XIOP_TP

EC_SWI# GPIO15 GPIO6

70

MEMCS#
<20,38> EC_SWI# VOL_UP# GPIO16
<34,35,38> VOL_UP# 75
GPIO17

IOCS#
WR#
RD#
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

D0
D1
D2
D3
D4
D5
D6
D7
A0

A2
A3

A6
A7
A8
A9

910@

1
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103

138
139
140
141
144
145
146
147

150
151
152
173
KB910_LQFP176 910@ R413 910@ R414
10K_0402_5% 10K_0402_5%
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9

FSEL# <38,39>

2
FWR# FWR# <38,39>
FR D#
FRD# <38,39>
KBA[0..19]
<38,39> KBA[0..19]

AD B[0..7]
<38,39> ADB[0..7] EC DEBUG port
6/27 change
JP31
1 LDO5
1 URXD
2
2 UTXD
3
3
4
4
4 4
ACES_85205-0400

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
EC KB910
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 37 of 53
A B C D E
 5 4 3 2 1

5/3 change 5/3 change L30

0.1U_0402_16V4Z 0.01U_0402_16V7K FBML10160808121LMT_0603
+3VL +3VL 1 2 +EC_AVCC
1 1 1 1 1
2
C621 C622 C623 C624 C625 C626
4.7U_0805_6.3V6K 0.1U_0402_16V4Z
5/3 change 2 2 2 2 2
1
Close to PR184 0.1U_0402_16V4Z 0.1U_0402_16V4Z ECAGND
5/3 change L31
1 2

R576 FBML10160808121LMT_0603
0_0805_5% +3VL +EC_AVCC
LDO3 1 2 +3VL
D D

@ R577

105
127
141
0_0805_5%

11
26
37

75
+3VALW 1 2 U33
EC_GA20 1 71 BATT_TEMP

VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC
VCC

EC_AVCC / AVCC
<20,37> EC_GA20 KB_RST# GA20/ GPIO00/GA20 BATTEMP/AD0/GPIO38 BATT_OVP BATT_TEMP <37,49>
<20,37> KB_RST# 2 72 BATT_OVP <37,44>
SIRQ KBRST#/GPIO01/KBRST# BATT OVP/AD1/GPIO39 ADP_IR
<19,25,35,37> SIRQ 3 73 ADP_IR <37>
LPC_FRAME# SERIRQ ADP_I/AD2/GPIO3A BID
<19,35,37> LPC_FRAME# 5 74 BID <37>
LPC_AD3 LPC_FRAME# / LFRAME# AD BID0/AD3/GPIO3B
<19,35,37> LPC_AD3 6
LPC_AD2 LPC AD3/LAD3 AD INtput or GPI
<19,35,37> LPC_AD2 9 LPC AD2/LAD2
LPC_AD1 10 Host
<19,35,37> LPC_AD1 LPC AD1/LAD1 INTERFACE
LPC_AD0 12
<19,35,37> LPC_AD0 CLK_PCI_EC LPC AD0/LAD0 DAC_BRIG
<19,23,37> CLK_PCI_EC 14 CLK_PCI_EC/PCICLK DAC_BRIG/DA0/GPIO3D 76 DAC_BRIG <17,37>
PCI_RST# 15 PWR 78 EN_FAN1
<19,25,27,29,30,35,37> PCI_RST# EC_RST# PCIRST# EN DFAN1/DA1/GPIO3D IR EF EN_FAN1 <4,37>
R584 42 79
<37> EC_RST# EC_SCI# EC RST#/ ECRST# IREF2/DA2 AIR_ACIN IREF <37,44>
1K_0402_5% 24 80 AIR_ACIN <37,44>
<20,37> EC_SCI# EC SCI#/SCI#/GPIO0E EN DFAN2/DA3/ GPIO3F
<34,35,36> PA_LED_ALW 2 1 44 PM_CLKRUN#/ CLKRUN# DA output or GPO
2

FAN/PWM
R585 KSI[0..7] 25 INVT_PWM
<34,35,37> KSI[0..7] KSI0 INVT_PWM/GPIO0F/PWM1 CONA# INVT_PWM <17,37>
2K_0402_5% 63 KSI0/GPIO30 BEEP#/GPIO10/PWM2 27 CONA# <37,40>
KSI1 64 30 VLDT_EN
KSI2 KSI1/GPIO31 OUT BEEP/GPIO12/PWM3 ACOFF VLDT_EN <37,42>
5/11 add High : PA 65 31
1

KSI3 KSI2/GPI032 ACOFF/GPIO18/PWM4 FAN_SPEED1 ACOFF <37,44>

66 KSI3/GPIO33 FAN SPEED1/GPIO14/FANFB1 32 FAN_SPEED1 <4,37>
Low : PR KSI4
KSI5
67 KSI4/GPIO34 FAN SPEED2/GPIO15/FANFB2 33 VOL_DWN#
VOL_DWN# <34,35,37>
68 KSI5/GPI035
KSI6 69
KSI7 KSI6/GPIO36
70 KSI7/GPIO37 PSCLK1 91
KSO[0..16] key Matrix 92
<35,37> KSO[0..16] KSO0 scan PSDAT1 PWR_ACTIVE#
47 KSO0/GPIO20 PSCLK2 93 PWR_ACTIVE# <34,35,37>
C KSO1 PS2 interface DOCK_VOL_UP# C
48 KSO1/GPIO21 PSDAT2 94 DOCK_VOL_UP# <37,40>
KSO2 49 95 TP_CLK
KSO3 KSO2/GPIO22 PSCLK3 TP_DATA TP_CLK <35,37>
50 KSO3/GPIO23 PSDAT3 96 TP_DATA <35,37>
CLK_PCI_EC KSO4 51
KSO5 KSO4/GPIO24 ADB0 AD B[0..7]
52 KSO5/GPIO25 ADB0/D0 125 ADB[0..7] <37,39>
1

KSO6 53 126 ADB1

KSO7 KSO6/GPIO26 ADB1/D1 ADB2
07/04 for EMI 54 KSO7/GPIO27 ADB2/D2 128
R415 KSO8 55 Data 130 ADB3
10_0402_5% KSO9 KSO8/GPIO28 BUS ADB3/ D3 ADB4
56 131
KSO10 KSO9/GPIO29 ADB4/D4 ADB5
57 132
2

KSO11 KSO10/GPIO2A ADB5/D5 ADB6

1 58 133
KSO12 KSO11/GPIO2B ADB6/D6 ADB7
59 134
C628 KSO13 KSO12/GPIO2C ADB7/D7 KBA0 KBA[0..19]
60 111 KBA[0..19] <37,39>
15P_0402_50V8J KSO14 KSO13/GPIO2D KBA0/A0 KBA1
61 112
2 KSO15 KSO14/GPIO2E KBA1/A1 KBA2
62 113
KSO16 KSO15/GPIO2F KBA2/A2 KBA3
89 114
KSO17 EC URXD/KSO16/GPIO48 KBA3/A3 KBA4
<34,35,37> KSO17 90 115
EC UTXD/KSO17/GPIO49 KBA4/A4 KBA5
116
KBA5/A5 KBA6
117
+5VALW EC_SMD_2 Address KBA6/A6 KBA7
<4,37> EC_SMD_2 88 118
RP57 EC_SMC_2 EC SMD2/ GPIO47/SDA2 BUS KBA7/A7 KBA8
<4,37> EC_SMC_2 87 119
EC_SMD_2 EC_SMD_1 EC SMC2/GPIO46/SCL2 SM BUS KBA8/A8 KBA9
8 1 <37,39,49> EC_SMD_1 86 120
EC_SMC_2 EC_SMC_1 EC SMD1/GPIO44/SDA1 KBA9/A9 KBA10
7 2 <37,39,49> EC_SMC_1 85 121
EC_SMD_1 EC SMC1/GPIO44/SCL1 KBA10/A10 KBA11
6 3 122
EC_SMC_1 KBA11/A11 KBA12
5 4 123
UTXD KBA12/A12 KBA13
5/3 change 10K_0804_8P4R_5% <37> UTXD
URXD
34
35
PCM_SPK#/EMAIL_LED#/ GPIO16 KBA13/A13
124
110 KBA14
<37> URXD SB_SPKR/PWR_SUSP_LED#/ GPIO17 KBA14/A14
PMLED_1# 38 109 KBA15
+3VL <36,37> PMLED_1# NUMLED# PWRLED#/ GPIO19 KBA15/A15 KBA16
<34,35,37> NUMLED# 40 108
RP58 BATLED_0# NUMLED#/ GPIO1A KBA16/A16 KBA17
<36,37> BATLED_0# 99 107
FSEL# BATT CHGI LED#/ E51CS# KBA17/A17 KBA18
8 1 101 106
FR D# CAPSLED# BATT LOW LED#/ E51MR0 KBA18/A18 KBA19
7 2 <36,37> CAPSLED# 100 98
B EC_SMI# CAPS LED#/ E51TMR1 KBA19/A19 B
6 3 102
ARROW LED#/ E51 INT0
5 4 LID_SW# SYSON 104 84 ENABLT
<28,37,41,46> SYSON SYSON/GPIO56/ E51 INT1 SELIO2#/ GPIO43 DOCK_VOL_DWN# ENABLT <13,17,37>
97 DOCK_VOL_DWN# <37,40>
10K_0804_8P4R_5% EC_RSMRST# SELIO#/ GPIO50 FR D#
<20,37> EC_RSMRST# 4 135 FRD# <37,39>
BKOFF# EC_RSMRST#/ GPIO02 FRD#/RD# FWR#
7 136 FWR# <37,39>
<17,37> BKOFF# SLP_S3# BKOFF#/GPIO03 FWR#/WR# FSEL#
<20,37> SLP_S3# 8 144 FSEL# <37,39>
LID_OUT# PM SLP S3#/GPIO04 FSEL#/SELMEM#
<20,37> LID_OUT# 16
SLP_S5# EC LID OUT#/GPIO06 EC_ON
<20,37> SLP_S5# 17 41 EC_ON <35,37,45>
EC_SMI# PM SLP S05#/ GPIO07 EC ON/ GPIO1B AC IN
4/27 change <20,37> EC_SMI#
EC_SWI#
18
19
EC SMI#/GPIO08 AC IN/ GPIO1C
43
29 EC_THERM#
ACIN <37,43,45>
<20,37> EC_SWI# LID_SW# EC SWI#/GPIO09 ECTHERM#/GPIO11 ON /OFF# EC_THERM# <20,37>
<34,35,37> LID_SW# 20 36 ON/OFF# <35,37>
R575 SUSP# LID SW#/ GPIO0A ONOFF/GPIO18 VOL_UP#
<28,37,39,41> SUSP# 21 45 VOL_UP# <34,35,37>
4.7K_0402_5% PWRBTN_OUT# SUSP#/GPIO0B PCMRST#/GPIO1E
<20,37> PWRBTN_OUT# 22 46 MUTE_GATE <31,37>
PBTN_OUT#/GPIO0C WL OFF#/GPIO1F
+3VL 1 2 PME_EC# <29,30,37> PME_EC#
PME_EC# 23
EC PME#/GPIO0D
ALI/MH#/GPIO40
81 1 2 @ R600 0_0402_5% M_SEN# M_SEN# <18,37>
82 FSTCHG
FSTCHG/GPIO41 FSTCHG <37,44>
83 VR_ON
VR ON/ GPIO42 ACIN_2 VR_ON <37,48>
137
C R Y2 GPIO57/GPIO57 CIR_IN
<37> C R Y2 140 142 CIR_IN <35,37,40>
XCLKO GPIO58/GPIO58
AGND

C R Y1 138 143 EC_MUTE#

GND
GND
GND
GND
GND
GND

<37> C R Y1 XCLKI GPIO59/GPIO59 EC_MUTE# <33,37>

R418
10K_0402_5% 8/23 reseve R600, currently M_SEN# isn't used
+3VS 1 2 VOL_UP# KB910L_LQFP144
139
129
103
13
28
39

77

07/28 for lower power consumption

R419
10K_0402_5%
1 2 VOL_DWN# ECAGND
ECAGND <37>
R420 R596
10K_0402_5% 0_0402_5%
1 2 DOCK_VOL_UP# ACIN_2 1 2 AC IN
@
A R421 A
10K_0402_5%
1 2 DOCK_VOL_DWN#

4/27 pop Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
EC KB910L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 38 of 53
5 4 3 2 1
 AD B[0..7]
<37,38> ADB[0..7]
KBA[0..19]
<37,38> KBA[0..19]

5/3 change
U34
5/3 change JP32
KBA16 KBA17 +3VL +3VL
KBA18 KBA15 1 2
1 32 +3VL SUSP# <28,37,38,41>
KBA16 A18 VDD FWE# KBA14 3 4
2 31
A16 WE# 5 6

1
KBA15 3 30 KBA17 2 KBA13 KBA19
KBA12 A15 A17 KBA14 C629 KBA12 7 8 KBA10
4 29 1
KBA7 A12 A14 KBA13 KBA11 9 10 ADB7 @ C630 R422 @
5 28
KBA6 A7 A13 KBA8 0.1U_0402_16V4Z KBA9 11 12 ADB6 0.1U_0402_16V4Z 10K_0402_5%
6 27
KBA5 A6 A8 KBA9 1 KBA8 13 14 ADB5
7 26

2
KBA4 A5 A9 KBA11 FWE# 15 16 ADB4 2 Q22 @
8 25
A4 A11 17 18

2
KBA3 FR D# RESET# 2N7002_SOT23

G
14
9 24 +3VALW
KBA2 A3 OE# KBA10 19 20 U35A
10 23
KBA1 A2 A10 FSEL# 21 22
11 22 1 1 3

P
KBA0 A1 CE# ADB7 KBA18 23 24 ADB3 FWE# A EC_FLASH# <20>
12 21 3

S
ADB0 A0 DQ7 ADB6 KBA7 25 26 ADB2 O
13 20 2
DQ0 DQ6 27 28

G
ADB1 ADB5 KBA6 ADB1 B
14 19
ADB2 DQ1 DQ5 ADB4 KBA5 29 30 ADB0 @ SN74LVC32APWLE_TSSOP14
15 18

7
DQ2 DQ4 ADB3 KBA4 31 32 FR D# FWR# <37,38>
16 VSS DQ3 17 33 34
KBA3
KBA2 35 36 FSEL# R578
SST39VF040-70-4C-NH_PLCC32 KBA1 37 38 KBA0 0_0402_5%
39 40
1 2
SUYIN-80065A-040G2T

R579
5/4 change 0_0402_5%
+3VLE 1 2 LDO3
@ R580
5/3 change 0_0402_5%
1 2 +3VALW
U36 +3VL

KBA0 21 31
KBA1 20
A0 VCC0
30 +3VLE 5/3 change +3VLE
KBA2 A1 VCC1
19 A2
KBA3 18 A3

1
KBA4 17 25 ADB0 1
KBA5 A4 D0 ADB1 C631
16 A5 D1 26
KBA6 15 27 ADB2 0.1U_0402_16V4Z R423
KBA7 A6 D2 ADB3 100K_0402_5%
14 A7 D3 28
KBA8 8 32 ADB4 2 U37

2
KBA9 A8 D4 ADB5
7 33 8 1
KBA10 A9 D5 ADB6 VCC A0
36 34 5/3 change 7 2
KBA11 A10 D6 ADB7 WP A1
6 35 <37,38,49> EC_SMC_1 6 3
KBA12 A11 D7 SCL A2
5 <37,38,49> EC_SMD_1 5 4
KBA13 A12 SDA GND
4
KBA14 A13 RESET# AT24C16AN-10SI-2.7_SO8
3 10 1 2 +3VL
KBA15 A14 RP#
2 11
KBA16 A15 NC @ R424
1 12
A16 READY/BUSY#

1
KBA17 40 29 100K_0402_5%
KBA18 A17 NC0 R425
13 38
KBA19 A18 NC1 100K_0402_5%
37
A19
FSEL# 22
<37,38> FSEL#

2
FR D# CE#
<37,38> FRD# 24 23
FWE# OE# GND0
9 39
WE# GND1

@ SST39VF080-70_TSOP40

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
BIOS & EC I/O Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 39 of 53
 A B C D E

07/07 for EMI

R591
0_0402_5%
DOCK_LOUT_R_R 1 2 DOCK_LOUT_R <31>

1
@ C745
1000P_0402_50V7K
L32 DOCK@
KC FBM-L18-453215-900LMA90T_1812 2
DOCK_VIN 1 2 DOCKVIN

1
1 1 1
DOCK@ C632 C633 DOCK@ R592
1000P_0402_50V7K 1000P_0402_50V7K 0_0402_5%
2 2 DOCK_LOUT_L_R 1 2 DOCK_LOUT_L <31>

1
@ C746
1000P_0402_50V7K
Tampa 2 2

JP33
1 2 DOCK_PRES_GND
1 2
3 3 4 4
MDO1+ 5 6
<29> MDO1+ MDO1- 5 6 MDO0+
R426 DOCK@ 7 8
<29> MDO1- JACK_DET# 7 8 MDO0- MDO0+ <29>
22_0402_5% 9 10
<33> JACK_DET# SPDIFO_L 9 10 MDO0- <29>
<31,35> SPDIFO 1 2 11 11 12 12
+5VS DOCK@ R427 1 2 100_0402_5% 13 14 DOCK_MIC
13 14 DOCK_MIC <35>
<20,23> SB_SPDIFO 1 2 1 <31,34,35> MUTE_LED MUTE_LED 15 16
XTPA1+ 15 16 DOCK_LOUT_R_R R429 DOCK@
<25> XTPA1+ 17 17 18 18
@ R428 @ C729 XTPA1- 19 20 DOCK_LOUT_L_R 200_0402_5%
<25> XTPA1- XTPB1+ 19 20
22_0402_5% 1000P_0402_50V7K 21 22 1 2 DOCK_VOL_UP# <37,38>
2 <25> XTPB1+ XTPB1- 21 22 USBP1-
<25> XTPB1- 23 23 24 24 USBP1- <20>
25 26 USBP1+ 1
25 26 USBP1+ <20>
27 28 C634 DOCK@
27 28 1000P_0402_50V7K
29 29 30 30
31 32
EMI 33
31
33
32
34 34 2
35 35 36 36
37 37 38 38
2 TV_COMPS_R 2
39 39 40 40
41 42 TV_LUMA_R R431 DOCK@
41 42 TV_CRMA_R 200_0402_5%
43 43 44 44
45 45 46 46 2 1 DOCK_VOL_DWN# <37,38>
47 48 CIR_IN
47 48 CIR_IN <35,37,38>
+5V 49 50 +5V DOCK@ 1
49 50 1K_0402_5% 2
51 51 52 52 1 R432
DOCK_PRESENT 53 54 V_Bat V_Bat <44> C635 DOCK@
53 54 1000P_0402_50V7K
55 56
+3VALW 55 56 2
DOCKVIN 57 58 DOCKVIN
57 58
59 60
GND GND
1

FOX_QL11293-H212CR-FR
R430 DOCK@
10K_0402_5%
2

<37,38> CONA#
1

DOCK_PRESENT 2 Q23 DOCK@ 07/07 for EMI

MMBT3904_SOT23
3

+5V R593
C637 DOCK@ 0_0603_5%
DOCK_PRES_GND 10U_0805_10V4Z TV_COMPS_R 2 1 TV_COMPS <13,18>

1 1
1 1 1
DOCK@ C636 @ C638 C747 @ C748 @
0.1U_0402_16V4Z 1000P_0402_50V7K 270P_0402_25V8K 330P_0402_50V7K
3 2 2 3
2 2 2
R594
0_0603_5%
TV_LUMA_R 2 1 TV_LUMA <13,18>

1 1
C749 @ C750 @
270P_0402_25V8K 330P_0402_50V7K
2 2

R595
0_0603_5%
TV_CRMA_R 2 1 TV_CRMA <13,18>

1 1
C751 @ C752 @
270P_0402_25V8K 330P_0402_50V7K
2 2

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
DOCK CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 40 of 53
A B C D E
 A B C D E F G H I J

+5VALW +5VALW
+5VALW to +5V Transfer +5VALW +3VALW +1.8VS

1
1 R435 R436 1
1 1 1
+5VALW 10K_0402_5% 47K_0402_5%
+5V @ C732 @ C733 @ C734

2
U38 0.1U_0402_16V4Z SUSP SYSON# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
6,47 SUSP 47 SYSON# 2 2 2
8 1
D S

1
B+ C639 D D
1 7 2
10U_0805_10V4Z D S
6 3 1 1 28,37,38,39 SUSP# 2 28,37,38,46 SYSON 2
D S

1
5 4 G Q25 G Q26 +3VALW +3VS +3VS
D G
1

C640 C641 R437 S 2N7002_SOT23 S 2N7002_SOT23

3
R438 2 SI4800DY_SO8 10U_0805_10V4Z
100K_0402_5% 2 2 470_0402_5%

2
2

SUSON

1
D
2 1 +5VALW 2 SYSON# 2
1

D C642 G
SYSON# 2 0.01U_0402_16V7K 1 S Q27

3
G 2N7002_SOT23
S 2 + @ C703
3

Q28 100U_C_4VM
2N7002_SOT23
2

FM1 FM2 FM3 FM4 FM5 FM6

+5VALW to +5VS Transfer 1 1 1 1 1 1
3 3
+3VALW to +3VS Transfer
+5VALW +5VS CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9
+3VALW
U39 0.1U_0402_16V4Z +3VS
8 1 U40 0.1U_0402_16V4Z

1
C643 D S
B+ 1 7 D S 2 8 D S 1
10U_0805_10V4Z 6 3 1 1 1 7 2
D S D S

1
5 4 C646 6 3 CF10 CF11 CF12
D G D S 1 1
C644 C645 R439 10U_0805_10V4Z 5 4 C647 C648
D G
1

2 SI4800DY_SO8 10U_0805_10V4Z @ R440

R441 2 2 470_0402_5% 2 SI4800DY_SO8 10U_0805_10V4Z 470_0402_5%

1
100K_0402_5% 2 2
2

2
2

4 4

1
RU NON +3VALW D H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11
1

D RU NON 2 SUSP HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1 +5VALW 2 SUSP 1 G
1

D C649 G @Q29
S

3
SUSP 2 0.01U_0402_16V7K S Q30 + @ C704 2N7002_SOT23
1
3

1
G 2N7002_SOT23 100U_C_4VM
Q31 S 2 + @ C705
3

2N7002_SOT23 100U_C_4VM 2
H12 H13
2 HOLEA HOLEA

1
5 H14 H15 H16 H17
5
HOLEA HOLEA HOLEA HOLEA
+1.8VALW to +1.8VS Transfer
+2.5V to +2.5VS Transfer

1
+2.5V +2.5VS +1.8VALW +1.8VS

U41 0.1U_0402_16V4Z 07/11 change U42 0.1U_0402_16V4Z

8 1 8 1 H19 H20
D S D S HOLEA HOLEA
1 7 2 1 1 1 7 2 1 1
D S D S
1

1
C650 6 3 C653 6 3 C654 C655
10U_0805_10V4Z D S C651 C652 R442 10U_0805_10V4Z D S R443
5 4 5 4
D G 10U_0805_10V4Z D G 10U_0805_10V4Z

1
2 SI4800DY_SO8 2 2 10_0805_5% 2 SI4800DY_SO8 2 2 470_0402_5%
2

2
6 6
H22 H23 H25 H26
1

1
D D HOLEA HOLEA HOLEA HOLEA
RU NON 2 SUSP R444 2 SUSP
G 2 1 RU NON G
S Q32 S Q33
3

1
2N7002_SOT23 2 22K_0402_5% 2N7002_SOT23

C656
0.01U_0402_16V7K H27 H28 H29 H30 H31 H32
1 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
7 7
H33 H34
HOLEA HOLEA
+1.25V +2.5V

1
1

R445 R446

470_0402_5% 470_0402_5%
1 2

1 2

D D
2 SYSON# 2 SYSON#
Q34 G Q35 G
2N7002_SOT23 S 2N7002_SOT23 S
Security Classification Compal Secret Data
3

8 8
Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
DC/DC Interface & Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 41 of 53
A B C D E F G H I J
 5 4 3 2 1

+3VALW

2
C657 +3VALW +3VALW +3VALW
0.1U_0402_16V4Z
D D
1

14

14

14

14
R447 R448 R449
470K_0402_5% 200K_0402_5% 10_0402_5%

P
VLDT_EN 1 2 1 2 3 4 1 2 5 6 9 8 1 2
37,38 VLDT_EN I O I O I O I O SB_PWRGD 20

G
1
1 U43A U43B 1 U43C U43D
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

7
R450 C658 C659
10K_0402_5% 0.1U_0402_16V4Z 0.47U_0603_16V7K
2 2

2
NB_PWRGD 13

note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms,

+3VALW SUSP# goes to low after SB_PWRGD goes to low for power
down.
14

T1
P

VLDT_EN 11 10 VLDT_EN#
I O VLDT_EN# 47
VLDT_EN
G

C U43E C
SN74LVC14APWLE_TSSOP14
7

NB_PWRGD

SB_PWRGD
T2
SUSP#

+1.8VS

B B

+3VL +3VL
14

14

U35B U35C
10

U44C 4 9
P

A A
6 8
OE#

O O
9 8 5 10
I O B B
G

SN74LVC32APWLE_TSSOP14 SN74LVC32APWLE_TSSOP14
7

SN74LVC125APWLE_TSSOP14

+3VL +3VALW
13

14

14

U44D U35D
12
OE#

A
12 11 11 13 12
I O O I O
13
B
G

U43F
SN74LVC125APWLE_TSSOP14 SN74LVC32APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
7

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
P_OK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 42 of 53
5 4 3 2 1
 5 4 3 2 1

VIN

Detector
2
DOCK_VIN 1
3
PD29
@ SBM1040-13_POWERMITE3 Vin Detector : Cayenne Vin Detector : Boxster
18.234 17.841 17.449 14.352 13.950 13.555
ADPIN
1
1 2
2 17.597 17.210 16.813 13.818 13.411 13.000
D PJP20 D
PL1 @ JUMP_43X118
FBM-L18-453215-900LMA90T_1812 PR1
2 1M_0603_0.5%
ADPIN 1 2 N50 1 1 2
ACES_88290-0400M 3 VIN
PD1 VS VIN

0.01U_0603_50V7K
4 @ SBM1040-13_POWERMITE3

1
1000P_0402_50V7K
PR3 PR4

1
1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J

PC5
1 2 PR2 10K_0805_5% 1K_0603_5%
1 2

1
PC2

PC4
3
82.5K_0603_0.1% 1 2
ACIN <37,38,45>

PC1

PC3

2
PJP21 PR5

2
8
2
@ JUMP_43X118 22K_0603_1%
N41 1 2 N40 3

P
+ PACIN
O 1
PACIN <44>

19.6K_0603_0.1%
0.022U_0603_25V7K
N35 2 -

G
1

1
1

1
PC6

PR6
PU1A PR7

4
PCN1 PC7 LM393M_SO8 PZD1 10K_0603_5%
1000P_0402_50V7K RLZ4.3B_LL34

2
2

2
PR9
10K_0603_5%
1 2
B+ 8/29 Change to 0.022uF 2 1
PR8 for AC Off issue RTCVREF
VIN 1K_1206_5%
3.3V
PD2
C N34 C
1 2 2 1

1 PR10 1N4148_SOD80
Cayenne : PR5=22K; PR6=19.6K
1K_1206_5%

PR11
Boxster : PR5=47K; PR6=27K
47_1206_5% 1 2
2

N37 PR12
2 1 1K_1206_5%
BATT+
2

PJP24
@ JUMP_43X39 VS
PD3 2 2 PD4
1N4148_SOD80 1 1 1N4148_SOD80
PR183 PR15 PR16
1

47_1206_5% 10K_0603_5% 1M_0402_1%

CHGRTCP 3 1 N621 2 1 2 2 1
VL
PQ1
1

0.1U_0603_25V7K

TP0610K_SOT23 B+
2
1

PR13 PC8
VS
PC9

100K_0603_1% 0.22U_1206_25V7K
2

1
2

1 2 N33 PR18
<35> EC_PWR_ON#
280K_0603_1%
PR14 PD5

2
8
22K_0603_5% RB715F_SOT323
2 5 N30

P
<44> ACON 1 N29 7
+
O
1

3 6 N38
<45,49> MAINPWON -

1
1000P_0603_50V7K
B RTCVREF B

1
0.1U_0603_25V7K
PR17 PU1B

4
1

PC14
PU2 200_0603_5% LM393M_SO8 PR21 PR22 PC12

PC13
G920AT24U_SOT89 200K_0603_1% 1.5M_0603_1% 1000P_0402_50V7K
3.3V ACIN : Cayenne
2

2
2

2
1 2 N39 1 2 3 2 N36
CHGRTC OUT IN N31
Precharge detector
1

PR19 PR20
1

@ 200_0603_5% @ 200_0603_5% GND PC10

14.805 14.333 13.872

1
1U_0805_50V4Z VL D
2

1
PC11 13.355 12.933 12.465 PR24 2N32 2 1 PACIN
2

4.7U_0805_6.3V6K 10K_0603_5% G

1
2 1 S PR23

3
PQ2 1M_0402_1%
ACIN : Boxster 2N7002_SOT23
+5VALWP
2
PJP1 PJP2 Precharge detector
@ JUMP_43X118 @ JUMP_43X118 PQ3
1 1 12.384 12.000 11.624 DTC115EUA_SC70
2 2
1 1
+5VALWP +5VALW +1.8VALWP 2 2 +1.8VALW

3
10.927 10.600 10.223
PJP3 PJP4
@ JUMP_43X118 @ JUMP_43X118
1 1
2 2
1 1
+1.5VSP 2 2 +1.5VS
BATT
PJP5 PJP6
@ JUMP_43X118 @ JUMP_43X118 Detector
+3VALWP
1 1
2 2 +3VALW +1.25VP
1 1
2 2 +1.25V Cayenne : PR21=200K
7.558 7.333 7.112
A PJP7 PJP8 6.108 5.933 5.704 Boxster : PR21=300K A
@ JUMP_43X118 @ JUMP_43X118
1 1 2 2 1 1 2 2
+2.5VP +2.5V +1.2V_HTP +1.2V_HT

PJP9 PJP10
@ JUMP_43X118 @ JUMP_43X118
1 1 2 2 1 1 2 2 Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
DCIN / Precharge
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 43 of 53
5 4 3 2 1
 5 4 3 2 1

1 2 B+
Charger
<40> V_Bat
PD30
SKS30-04AT_TSMA
1 8
1 2 P2 2 7
3 6
PD31 Iadp=0~3.0A 5
SKS30-04AT_TSMA B++
PQ39 PQ4 P3 PQ5

4
AO4407_SO8 AO4407_SO8 PJP12 AO4407_SO8
VIN 8 1 1 8 PR25 @ JUMP_43X118
D D
7 2 2 7 2 1 1 1
2 2

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

0.1U_0603_25V7K
6 3 3 6
5 5 0.02_2512_1%

1
4

4
1

PC15

PC16

PC17

PC18
2

2
PR26 PR188

1
15K_0603_5% 47K_0402_5%

0.1U_0603_25V7K
PQ40
Cayenne : PR34=2.74k D IS
2

47K

1
DTA144EUA_SC70
Boxster : PR34=4.7K

PC156
2 PR27 PR28

2
47K
200K_0402_5% 1 2

2
VIN

2
<37> ADP_I
1

PU3 47K_0603_5%
1 24 PR29
-INC2 +INC2

1
0_0402_5%

1
N12

1
2 2 1 2 23 PR30
PR31 OUTC2 GND 10K_0603_5%

1
PQ41 10K_0402_1% PC19 2200P_0402_50V7K

2
DTC115EUA_SC70 3887+INE2
3 +INE2 22 3887CS 1 2
CS
1

D ACOFF#
3

31.6K_0603_1%
2 PR32

3
2
1
2N7002_SOT23

G 150K_0402_1% 3887-INE2
4 21 3887VCC(O) 1 2

N1 2
-INE2 VCC(o)

1
S PQ6
3

PQ42

ACOFF# 1 2 PC21 PR34 PC20 AO4407_SO8

11K_0402_1%

PR33
0.1U_0402_16V7K
1 2 N161 2 3887FB25 FB2 OUT 20 3887OUT 0.1U_0603_25V7K 4

1
PD8

2
1
D

PC22
1SS355_SOD323 0.01U_0603_50V7K 2.74K_0402_1% PC23 2
3887VREF 6 3887VH ACOFF <37,38>
2 19 1 2

2
VREF VH

2N7002_SOT23

PR35
G PQ7
5.0V

0.1U_0402_16V7K
C PACIN 0.1U_0603_25V7K PC26 0.1U_0603_25V7K DTC115EUA_SC70 C
1 2 S

3
<43>PACIN

PQ8
1 2 N151 2 3887FB17 18 1 2

5
6
7
8

3
FB1 VCC

PC24
PR36 PR37

2
3K_0603_5% PC25 1K_0603_1% PR38
1500P_0603_50V7K 3887-INE1 8 17 3887RT 1 2
-INE1 RT 68K_0603_5%
<43> ACON
N49
3887+INE1 9 16 3887-INE3 PL2
+INE1 -INE3 15U_PLFC1045P-150A_3.7A_20%
PR41 PC27 1 2 2 1
3887OUTC1 3887FB3 BATT+
2 1 10
OUTC1 FB3
15 1 2 N141 2
PR40 47K_0603_1% PR39
10K_0603_1% 1500P_0603_50V7K 0.02_2512_1%

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
3887OUTD11 14 ACON
OUTD CTL

1
PC28

PC29

PC30
<37,38> IREF 1 PR42 2 PD9 PD10
3887-INC112 13 3887+INC1 @ SKS30-04AT_TSMA SKS30-04AT_TSMA

2
174K_0603_1% -INC1 +INC1

2
1

IREF=1.096*Icharge PR43 0.1U_0402_16V7K MB3887_SSOP24

1

IREF=0.548~3.288V
PC31

100K_0603_1%
2

2 1
4.2V 2 1
Battery OVP voltage : PR44 PR45
49.9K_0603_0.1% 150K_0603_0.1%
4S2P : 18V--> BATT_OVP= 2.0V
B B
(BAT_OVP=0.1112*VMB)
CC=0.4~3.0A
3S2P/3S3P : 13.5V--> BATT_OVP= 2.0V BATT_Charge Voltage Select
(BAT_OVP=0.14753 *BATT+) 4S2P CV=16.8V PR44 = 49.9K_0603_0.1% PR45=150K_0603_0.1%
3S2P/3S3P CV=12.6V PR44 = 150K_0603_0.1% PR45=300K_0603_0.1%
VS BATT++
<37,38> AIR_ACIN
1

+3VALWP
PR46 VS
0.01U_0402_25V7Z

340K_0603_1% 3887CS 3887CS

1
2
1

PR47
PC32

N17 PU4A
1

LM358ADR_SO8 47K_0603_5%
2

1
PR49 D

2
8

PR48 PR50 10K_0603_5% N11 2 PQ10

PU4B 499K_0603_1% 4.22K_0603_1% 3 N19 2 1 G
P

+ RTCVREF

1
LM358ADR_SO8 2 2 1 N181 S 2N7002_SOT23
2

3
PQ9 0 N20
2 2 1 VIN
-
G

5 N13 DTC115EUA_SC70
+
1

<37,38> BATT_OVP 7 PR51 (17V+-5%)

4

0
2

6 42.2K_0603_1% 2
3

- <37,38> FSTCHG
1

PZD2 PR52
RLZ4.3B_LL34 10K_0603_5% PQ11
PR54 PR53 DTC115EUA_SC70
2

2
1

A 105K_0603_0.5% 10.2K_0603_1% A
1

3
PC33
2

N21 0.01U_0402_25V7Z
2
1

BATT_OVP Select PR55

0_0603_5%
4S2P PR55 = 0_0603_5% Security Classification Compal Secret Data
2

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

3S2P/3S3P PR55 = 40.2K_0603_1% Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 44 of 53
5 4 3 2 1
 5 4 3 2 1

+3VALWP/+5VALWP

D D

B+
1
1
2

PJP23
@ JUMP_43X118 PC136 PC137
2

0.1U_0603_25V7K 0.1U_0603_25V7K
2 1 BST5B BST3B 2 1

3
1999_B++
PD26
CHP202U_SC70
VL
2200P_0402_50V7K

1
1999_B++
4.7U_1206_25V6K

4.7U_1206_25V6K
1

2
PC140

P2
PC138

PC139

PR164

8
7
6
5

47_0402_5%
0_0402_5% PQ32
2

1
1 8

D
D
D
D
D1 G1

PR165
PQ33 PR166 PC141 2 7

1
D1 S1/D2

2200P_0402_50V7K
SI4800BDY-T1-E3_SO8 4.7_1206_5% 0.1U_0402_16V7K 3 6

2
G2 S1/D2

4.7U_1206_25V6K

4.7U_1206_25V6K
4 5

1
S2 S1/D2

1
S
S
S

PC144
C C
LDO5 VL

PC142

PC143
PR163 N63 SI4914DY-T1-E3 SO8
1
2
3
4

0.1U_0603_25V7K
0_0402_5%

2
1

2
4.7U_1206_25V6K
5HG 1 2

PC145
PR185 PR167
0_0805_5% 0_0402_5%

2
2VREF_1999

4.7U_0805_6.3V6K

1U_0603_10V6K
1 2 N58

1PC148
3HG

1
8
7
6
5

499K_0402_1% 118K_0402_1%

499K_0402_1% 200K_0402_1%
2

2
PC146
D
D
D
D

PR168

PR169
PQ34
1

PC147
SI4810BDY-T1-E3 SO8

2
PR170

2
G
S
S
S

PL11 0_0402_5%

2 1

2 1
10UH_D104C-919AS-100M_4.5A_20%

18

20

13

17
1
2
3
4

PU12

PR171
BST5A 14

LD05

V+

TON

VCC
2

1
BST5

PR172
5 ILIM3
D H5 ILIM3
16
+5VALWP DH5

1
1

1
LX5 15
DL5 LX5 ILIM5 PL12
19 11
DL5 ILIM5 10UH_D104C-919AS-100M_4.5A_20%
21
OUT5
@ 10.2K_0402_1%

FB5 9 28 BST3A
FB5 BST3 D H3
1 26

2
N.C. DH3
2

P2 24 DL3
DL3
SKUL30-02AT_SMA

PR173

N56 6 27 LX3
SHDN# LX3
220U_6.3VM_R15

4 22
ON5 OUT3
1

1
47K_0402_5%

PR175 3
+ 10K_0402_5% ON3 FB3
7
1

ACIN FB3
PC154

PR174

1 2 N57 12 2 +3VALWP
SKIP# PGOOD
<38,44>
PD28

PRO#
B B

LDO3
8

GND
2VREF_1999
2

REF
2

0_0402_5%

2
PR176

SKUL30-02AT_SMA
@
1

MAX8734AEEI+_QSOP28 PR177

23

25

10
VL

220U_6.3VM_R15
PR179 @ 3.57K_0402_1%

1
0.22U_0603_16V7K

PC150 0_0402_5%
1

@ 1U_1206_25V7K N601 2 +

1
1

PC151

PC155
PD27
PR181
2

2
4.7U_0805_6.3V6K
LDO3

2
806K_0603_1% @
PR182 LDO3P 1 2 PR178
2

0_0402_5% 0_0402_5%

1
2 1 N59 PR184

1
MAINPWON
PC152
0_0805_5%
2
LDO3P
1

PC153
0.047U_0603_16V7K
2
2

PR187
100K_0402_5%
1

D
1

N61 2 PQ37
G 2N7002_SOT23
S
3
1

D D
2 2
EC_ON G ACIN G
A A
S S
3

PQ38 PQ36
2N7002_SOT23 2N7002_SOT23

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
+3VALWP/+5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 45 of 53
5 4 3 2 1
 5 4 3 2 1

+1.8VALWP/+2.5VP

D D

B+
PJP15
@ JUMP_43X118
MAX8743_B++ 1 1
2 2

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC59

PC60

PC61

2
PR81
0_0603_5% +5VALWP

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PD16 PC62

1
CHP202U_SC70 4.7U_1206_25V6K

MAX8743B_V+

PC63

PC64

PC65
2

2
1
PR82

2
20_0603_1% PC66

2
4.7U_0805_6.3V6K

BST1.8A
PQ16

5
6
7
8
1 D1 G1 8
2 7 BST2.5A

D
D
D
D
D1 S1/D2 PQ17
3 G2 S1/D2 6
C SI4800BDY-T1-E3_SO8 C
4 S2 S1/D2 5
MAX8743_VCCB

0.1U_0603_25V7K

G
S
S
S
V+ 1U_0603_16V6K
SI4914DY-T1-E3 SO8 +2.5VP

VDDB
1

1
+1.8VALWP PR83 PR84 PL5

4
3
2
1
PC67

PC68
0_0402_5% 0_0402_5% 4.7UH_PLFC1045P-4R7A_5.5A_30%
1 2 2 1 1 2 BST2.5 1 2 2 1 1 2

5
6
7
8
220U_6.3VM_R15

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

@SKS10-04AT_TSMA
PL4 PC69 PC70

22
1

9
@SKS10-04AT_TSMA

220U_6.3VM_R15
5U_TPRH6D38-5R0M-N_2.9A_20% 0.1U_0603_25V7K PU6 0.1U_0603_25V7K

D
D
D
D
1

1
@ 0_0402_5%
PD17

+ PR86 BST1.8 25 21

UVP
VCC
BST1 VDD
1

1
PC131

PC72

0_0402_5% PR88 PQ18 +

@ 15K_0402_1%
PR85

PC132
DH1.8A 1 2 D H1.8 26 19 0_0402_5% SI4810BDY-T1-E3 SO8
2

DH1 BST2

G
S
S
S

PC74

PD18
18 D H2.5 1 2 DH2.5A
2

2
LX1.8 DH2 LX2.5
27 17

4
3
2
1

2
DL1.8 LX1 LX2 DL2.5
24 20
2

2
DL1 DL2

PR87
16
28 MAX8743EEI_QSOP28 CS2
CS1
1 15
OUT1 OUT2 FB2.5
14
FB2

@ 100P_0402_50V8K
FB1.8 2 12 2.5ON 2 1
FB1 ON2 SYSON <37,38,41>
PR89
@ 100P_0402_50V8K

7 0_0402_5%
PGOOD

1
5
TON
1

1
0_0402_5%

0_0402_5%
+3VALWP 1 2 1.8ON 11
ON1
1

PC76

13 1.936V MAX8743B_ILIM2
ILIM2
PR92

PC75
PR90 3 1.365V MAX8743B_ILIM1

SKIP
GND
OVP

2
REF
ILIM1

PR91
0_0402_5%
2

2
2

PR93

23

10
3.3K_0603_1%
2 1

1MAX8743B_REF
B B
2 1

100K_0603_1%
MAX8743_VCCB 1 2 MAX8743B_SKIP# PR94

1
69.8K_0603_1%

PR97
PR95

0.22U_0603_16V7K
@ 0_0402_5% PR96
150K_0603_1%
PR98

2
0_0402_5%

PC77

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
+1.8VALWP/+2.5VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 46 of 53
5 4 3 2 1
 5 4 3 2 1

+1.2V_HTP/+1.5VSP/+1.25VP

+2.5V +1.8VS

D D

2
2

2
PJP16 PJP17
@ JUMP_43X118 @ JUMP_43X118

1
1

1
PU7 PU8
VIN1.25 1 6 VIN1.5 1 6
VIN VCNTL +3VALW VIN VCNTL +3VALW

1U_0603_10V6K

1U_0603_10V6K
2 GND NC 5 2 GND NC 5

2
1

PC79

PC81
PC78 3 7 PC80 PR99 3 7
10U_1206_6.3V7K VREF NC 10U_1206_6.3V7K 2K_0402_1% VREF NC

1
PR100 4 8 4 8
3.3K_0603_1% VOUT NC VOUT NC

2
9 9

2
TP TP
VREF1.25 APL5331KAC-TR_SO8 VREF1.5 APL5331KAC-TR_SO8

PR101 PR103
1

1
0_0402_5% D 0_0402_5% D
+1.25VP +1.5VSP
1 2 N4 2 PQ19 PC82 1 2 N9 2 PQ20 PC83
<41> SYSON# SUSP

10U_1206_6.3V7K
G 2N7002_SOT23 PR102 0.1U_0402_16V7K G 2N7002_SOT23 PR104 0.1U_0402_16V7K

1
10U_1206_6.3V7K
S 3.3K_0603_1% S 10K_0402_1%
3

3
1

1
2

2
PC86

PC84
PC85 PC87

2
@ 0.1U_0402_16V7K @ 0.1U_0402_16V7K
2

2
C C

+5VALW
2
2

PJP18
@ JUMP_43X39
1
1

APW7057_VCC 1 2 N5 2 1 +5VALW
2 1

22U_1206_6.3V6M
PR105 PJP19

1
@ 10_0603_5% @ JUMP_43X118
PD19 PC90
2

PC89
PC88 1N4148_SOD80 22U_1206_6.3V6M

2
1

PC91 1U_0603_6.3V6M

1
470P_0402_50V8J

0.1U_0402_16V7K
2

5
6
7
8
PR106 PU9
1

B 6.49K_0402_1% B
VCC

D
D
D
D
1

PC92
1 BOOT1.2
OCSET1.2 BOOT PQ21
7
OCSET

G
S
S
S
SI4800BDY-T1-E3_SO8

4
3
2
1
2 UGATE1.2 2 1UGATE1.21
UGATE
1

D
1 2 N6 2 PQ22 FB1.2 6 PR161 PL6
<42> VLDT_EN# G 2N7002_SOT23 FB 0_0402_5% 2.0UH_PLC-0735-2R0_5A_30%
PR108 S 8 PHASE1.2 1 2 +1.2V_HTP
3

PHASE
2

0_0402_5%

5
6
7
8

220U_6.3VM_R15

220U_6.3VM_R15
PC95
1

@ 0.1U_0402_16V7K 3 4 LGATE1.2

D
D
D
D
GND LGATE + +

PC133

PC134
APW7057KC-TRL_SOP8 PQ24

G
S
S
S
SI4810BDY-T1-E3 SO8

4
3
2
1
PR109
5.1K_0402_1%
1 2
2

1 2
PC96
PR110 0.1U_0402_16V7K
10K_0402_1%
1

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
+1.2VSP/+1.5VP/+1.25VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 47 of 53
5 4 3 2 1
 5 4 3 2 1

CPU_B+ PL7 B+
+5VS
FBM-L18-453215-900LMA90T_1812

PR111 10_0402_5%
+3VS
1 2
D D

2200P_0402_50V7K
0.01U_0402_50V4Z
4.7U_1206_25V6K

4.7U_1206_25V6K
1 1

1
10K_0402_5%
+ +

68U_25V_M

68U_25V_M
PC100
PC99
2

2
1
2 2

PC101

PC102

PC98

PC135
2
PC103
2.2U_0603_6.3V6K +5VS

5
6
7
8
PR112

0.01U_0402_50V4Z
PC104

2
1U_0603_10V6K 1544BSTMA 1 2 PQ25

1
PC105
FDS6294_SO8

0.22U_0603_16V7K
PD20

1
1SS355_SOD323

1
1544VCC 10 30 4
VCC VDD

PC106
2 1 D0 24 36

2
<6> VID0 PR113 0_0402_5% D0 V+
2 1 D1 23 26 1544BSTM 1 PR115 2 PR117 PL8

3
2
1
<6> VID1 D1 BSTM
PR114 0_0402_5% 0_0402_5% +CPU_CORE
2 1 D2 22 28 1544DHM 2.2_0402_5% 1 2 1544DHMA .56UH_MPC1040LR56_ 23A_20%
<6> VID2 PR116 0_0402_5% D2 DHM
2 1 D3 21 27 1544LXM 1 2 N25 1 2
<6> VID3 D3 LXM

4.7_1206_5%
PR118 0_0402_5%

5
6
7
8

5
6
7
8

1
2 1 D4 20 PU10 29 1544DLM PR119
<6> VID4 D4 DLM

SKS30-04AT_TSMA
PR120 0_0402_5% 0.001_2512_5% PR121

820_0402_5%
PR123
1544VCC 2 1 1544OVP 19 31 @10_0402_5%
OVP PGND

1
FDS6676AS_SO8

FDS6676AS_SO8
PR122 0_0402_5% CPU VCC SENSE
1 2 1544VROK 25 MAX1544ETL 37 1544CMP

2
VGATE VROK CMP

PR124
PR125 0_0402_5% 4 4 N3

1
499_0402_1%

499_0402_1%
PQ26

PQ27

PD21
C 1544CMN N47 C
4 38

2
S0 CMN

PR129 1.82K_0402_1%
2
1

PR126

PR127
5 17 1544OAIN+ 1 2
S1 OAIN+ PC108

3
2
1

3
2
1

0_0402_5%
1000P_0402_50V7K
1 2 1544SHDN# 6 16 1544OAIN- 680P_0603_50V8J PC107

2
SHDN# OAIN-

PR130
0.47U_0603_16V7K

PC109
38> VR_ON PR128 1 2 2 PR132
1 1544TIME 1 15 1544FB
0_0402_5% PR131 60.4K_0603_1% TIME FB

1
@ 100K_0402_5% 1 2 1544CCV 12 14 1544CCI 1 2 PR133 820_0402_5%

2
PC110 CCV CCI PC111 470P_0402_50V8J 1 2
1 2 270P_0402_50V7K 1544TON 2 35 1544BSTS
PR134 TON BSTS
200K_0402_1% 1 2 1544REF 8 33 1544DHS PR135 @
PC112 REF DHS
1 2
1 PR136
2 0.22U_0603_16V7K 1544ILIM 9 34 1544LXS
71.5K_0402_1% ILIM LXS 1.82K_0402_1%

<6>
CPU_COREFB
1544REF1 2 1544OFS 7 32 1544DLS
OFS DLS +5VS

2.2_0402_5%
100P_0402_50V8J
80.6K_0402_1%

PR137 1544SUS 3 40 1544CSP

SUS CSP
2

121K_0402_1%

2
PC113

PR138
1544REF 2 1 N26 18 39 1544CSN
SKIP CSN
PR139

PR140
2

1
0_0402_5% 11 13 1544GNDS
GND GNDS PD22
1

1SS355_SOD323

1
1544BSTSA CPU_B+
1
1000P_0402_50V7K

2200P_0402_50V7K
100_0402_5%
2

5
6
7
8
PR141

0.01U_0402_50V4Z
4.7U_1206_25V6K

4.7U_1206_25V6K
PQ28

1
0.22U_0603_16V7K
FDS6294_SO8
1

1
PC114

B B
2

PC119

2
PC115

PC116

PC117

PC118
1 21544DHMB4
2 PL9
PR142
0_0402_5% .56UH_MPC1040LR56_ 23A_20%

3
2
1
N55 1 2

4.7_1206_5%
1

5
6
7
8

5
6
7
8
1

2
0_0402_5%

PR143
PR159

PR144
@10_0402_5% PR145

SKS30-04AT_TSMA
FDS6676AS_SO8

FDS6676AS_SO8
820_0402_5%

1
2

PD23
4 4
2

1
PQ29

PQ30
N48
1 2

1
Near CPU GND

2
PC121 PC120

3
2
1

3
2
1
680P_0603_50V8J 0.47U_0603_16V7K

2
<6>
CPU_COREFB#

1 2

PC122 PR146
2 1 1544OAIN+ 820_0402_5%

@ 1000P_0402_50V7K
PC123
A 1544OAIN+ A
2 1

@ 1000P_0402_50V7K

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 48 of 53
5 4 3 2 1
 5 4 3 2 1

D D

BATT++ BATT+
Battery Connect/OTP

BATT+
2 1

PL10
FBM-L18-453215-900LMA90T_1812

1
PC125 PC124

2
1000P_0402_50V7K 0.01U_0402_25V7Z

1 PR150
BATT+ 100_0402_5%
2 SMD 1 2 EC_SMD_1 <37,38,39>
SMD
SMC
SMC 3 1 2 EC_SMC_1 <37,38,39> PH1 under CPU botten side :
PR151
RES 4
100_0402_5% CPU CPU thermal protection at 90 +-3 degree C
TS 2 BATT_TEMP
C
8 G Temp 5 1
BATT_TEMP <37,38> Recovery at 50 +-3 degree C C
7 6 PR147
G GND
2

1K_0402_5%

PCN2
SUYIN_200045MR006G110ZR PR162 1 2
@ 0_0402_5% +3VALWP
1

PR149
6.49K_0402_1% VL
VS

0.1U_0603_25V7K
PJPB1 battery connector

<43,46>
MAINPWON
1
S M A RT

PC126
1
Battery: VL

2
1 . B ATT+ PH1
2.SMBD 100K_0603_1%_TH11-4H104FT

2
3 . S M BC
PR152
N28 470K_0402_1%
4 . R es

1
1 2

1
PR153
5 . T e mp PR154 470K_0402_1%
6 . G ND 0_0402_5%
PR155

2
8
215K_0603_1% PU11A

1
N27 N10 D
1 2 3

P
+ N22 PQ31
1 2
B OTPREF O G 2N7002_SOT23 B
1 2 2
-

G
VL PR156 S

3
470K_0402_1% LM393M_SO8

4
1
1

1
PR157

1
PC127 20K_0603_1% PR158
0.22U_0603_16V7K 470K_0402_1%

2
PC128

2
1000P_0402_50V7K VS

8
PU11B
5

P
+
7
O
6
-

G
LM393M_SO8

4
A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
BATTERY CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 49 of 53
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Power section Page 1 of 1

Item Reason for change PG# Modify List Date B.Ver#

D 1 Add the functionality to turn on the system on from Off D

45 Change 3/5VALWP regulator from MAX1902 to MAX1999 2005.04.08
and S4 with the consumer IR.

2 Change PCN1 from SP020022200 to SP020024800. 49 Change PCN1 from SP02000AO00 to DC040001P00. 2005.04.08

Change CPU_CORE HI-SIDE MOS from

3 Because EMI test fail 48
AO4408 to FDS6294, LOW-SIDE from AO4410 to FDS6676AS 2005.05.18

Because V_bat to Calgary havn a leakage current,

4 44 Add PD30 and PD31 to supply the V_bat power. 2005.06.09
cause precharge can't finisn.

C
5 Add air-adapter detector 44 Add PU4 to detector air-adapter in. 2005.07.02 C

6 Adjust the MB3887 CC to CP response cause the adapter OCP. 44 Change the PR31 from 100k_0402_1% to 10k_0402_1% 2005.07.29
Change the PR34 from 10k_0402_1% to 2.74k_0402_1%
Change the PC21 from 4700p_0603_50V to 0.01u_0603_50v

B B

A A

Compal Electronics, Inc.

Title
PWR PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.8
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, August 30, 2005 Sheet 50 of 53
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.

<2005.04.18> 1 H P Jac k + SPDIF change type 3 1 , 33 Del : U 27 , C563 , C564 0 .2

A dd: Q 52 , Q 53 , Q 54 , Q 56 , Q 57 , R571 , C730 , C731 , R567 , R569 , R568 , R570
4 , 37 ,
2 38 , 41 , 12V A LW change to B+
Support CI R wake up from battery mode +3V A LW c hange to LDO3 , +5VALW change to LDO5 0 .2
35

3 A dd: Q 55
D D

for Marvell express card Rest timing 2 0 , 28 0 .2

4
for s o me HDD's LED alway on 24 Del: D29 , R259 , Q10 0 .2

5 for card bus can't work 27 S1_ V CC and S1_ V PP c ha nge to +S1_VCC and +S1_VPP 0 .2

6 For nissan common design 35 JP28 an d JP29 pin swap 0 .2

0 .2
7
For keyboard issue 37 Del: D 27

<2005.04.27> 1 w ak e u p fr om LAN 38 A dd: R575(Pu ll UP PME_EC#) 0 .3

C 2 For V O L_UP,DOWN function issue 38 P O P: R418, R419, R420, R421 0 .3 C

<2005.05.3> 1 For CI R wake up 38 A dd: R576 , R577 to option 0 .3

<2005.05.4> 1 E C 910L include portion circuit 39 A dd: R578 , Del: C630 , R422 , Q22 , U35A 0 .3

2 ME c hange LED type 36 D18, D20,D21 from right angle change to vertical type 0 .3

<2005.05.6> 1 Add wireless LED c urrent limit resister 17 Add: R581 current limit resister 0 .3

<2005.05.9> 1 TP conn pin reverse 35 Pin swap

<2005.05.10> 1 ME c hange LED type 36 D25 from right angle change to vertical type

2 HP requirement from 75 ohm change to 33 ohm 33 R567 , R569 from 75 ohm c h ange to 33 ohm

B
3 For nissan common design 35 A dd: R582 , R583 B

<2005.05.11> 1 For 2 w ay and 4 way touch pad 36 A dd: R584 , R585

<2005.06.10> update JP23 dual USB connector to reverse type 0 .4

DFX modific atio n for Rev0.4 MB

C h a n g e M R 9 5 4 , M C 9 2 8 , M R 9 2 4 , M R 9 22, MR932, MC944, MC970,

MC976, MC978, MC926 to c orrec t pad size with Compal layout rule

update USB connector to reverse type

Change D6 form RB411 to RB491

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 51 of 53
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.

<2005.06.27> 1 For clear H_RST# glitch 41 Add Q61 0 .5

<2005.07.04> 1
For +1.8VS EMI 11 Change R61, R84 value from 0 ohm to 120 ohm 0 .5

2
D D
Change C197, C209, C254, C248, C251, C256, C258 value
For +1.2V_HT power ripple 14 0 .5
from 0.1U 16V4Z 0402 to 1U 6.3V4Z 0402

3
For +2.5VS EMI 15 Add C737, C738, C741, C742 220P 50V8J 0402 0 .5

4 For +2.5VS EMI 15 Add C739, C740, C743, C744 1000P 50V7K 0402 0 .5

5 For Mini-PCI_CLK EMI 30 Mount R325 and C512

6 mount R279 and C442

For CardBus chip PCI_CLK EMI 25
0 .5

For LAN chip PCI_CLK EMI 29 Mount R322 and C504 0 .5

7

C 8 For EC K/B chip PCI_CLK EMI 30 Mount R415 and C628 C

<2005.07.05> 1 For USB EMI 34 Add L33, L34

2 For USB EMI 34 change R561,R559,R562,R560 size from 0603 to 0402

<2005.07.07> 1 For dock Docking audio noise 31 Add Q58, R589, Q60, R590, Q59, R589

2 For Dock_LOUTR/L EMI 40 Add R591, C745, R592, C746

3 For Docking TV_out signals EMI 40 Add R593, C747, R594, C748,C749, C750, R595, C751, C752

<2005.07.11> 1 For accelerate +2.5VS discharge speed 40 change R442 size and value from 470_0402 to 10_0805

2 For LAN lamp 29 Swap Activity and Link Lamp

B B

<2005.07.25> 1 For SanDisk SD 256M card could not work issue 25 delete U48 Quick switch reserve schematics

For SanDisk SD 256M card could not work issue 25 Delete R463, R465, R466, R476, R268
2

3 For SanDisk SD 256M card could not work issue 26 Delete R270, R267, R547, R548

4
For SanDisk SD 256M card could not work issue 26 Mount R550 and R549

<2005.07.28> 1 For lower power consumption 38 Add and un-mount R596

2 For CRT Assy

18 change CRT footprint

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 52 of 53
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.

<2005.08.11> 1 Delect all reserve 0 ohm resistors. 41 Delete R24, R125, R21 , R73 , R263, R565 0 .5

2 For EMI solution on switch connector 11 Add C753~C771 total 19 pcs 0 .5

D D
Change C200, C202, C242, C232
3 For ATI suggestion on RS480 14 0 .5
from 0.1U 16V4Z 0402 to 1U 6.3V4K 0402

<2005.08.23> 4 Relocate damping resistor to solve Sandisk issue 26 Relocate R266, R458, R459, R460, R461, R462 0 .8

5 Change from AGND to DGND for Codec precision improvement 31 Change Q16/Q17 pin3 and R334 pin2 to DGND 0 .8

6 Add +3VALW power rail for Boxster lid switch use 35 Add +3VALW to JP28 pin25 0 .8

7 Reserve C700, for soft start if necessary Reserve C700 0 .8

31

Reserve R600 M_SEN#, currently this signal isn't used 38 Reserve R600 0 .8
8

C C

B B

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2771 0.8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 30, 2005 Sheet 53 of 53
5 4 3 2 1
www.s-manuals.com