University of Texas at Dallas

Department of Electrical Engineering

EEDG 6306 - Application Specific Integrated Circuit Design

Synopsys Tools Tutorial

By
Zhaori Bi

Fall 2016
Table of Contents
Chapter 1 Design Compiler .......................................................................................................................... 3
Introduction ............................................................................................................................................... 3
Tutorial example ....................................................................................................................................... 3
1. Write RTL description by Verilog/VHDL. ....................................................................................... 3
2. Log into giant server and source Synopsys. ...................................................................................... 3
3. Copy .synopsys_dc.setup file to your working directory. (DO NOT MODIFY THIS FILE!) ......... 4
4. Open Design Vision .......................................................................................................................... 4
5. Read in your RTL design .................................................................................................................. 5
6. Check to see if the design is in a good state. ..................................................................................... 6
7. Copy cons.tcl to your working directory........................................................................................... 6
8. Run cons.tcl file. ............................................................................................................................... 7
9. Compile your design. ........................................................................................................................ 7
10. Copy dc_rpt.tcl to your working directory. ..................................................................................... 7
11. Dump report files. ........................................................................................................................... 7
12. Check the schematic of your critical path. .................................................................................... 11
13. Dump *.sdc and *.v file. ............................................................................................................... 12
14. Run gate level simulation. ............................................................................................................. 12
Chapter 1 Design Compiler
Introduction
In this section you will learn how to use Synopsys Design Compiler (DC) tool to synthesis your HDL
code. The compiler takes your HDL codes and cell library as inputs, then generate a technology based
gate-level netlist. The DC tool also performs the task of logical optimization. Below is a brief design flow
for DC:

1. Read in technology files (*.db and *.sdb) and RTL files (*.v or *.vhd). The technology library consists
of the basic logic gates and flip-flops. Most industry libraries include advance cells such as adders and
comparators etc. The RTL files should be well written and followed your architecture descriptions. A bad
coding manner may result in failure of synthesis.

2. Compile your RTL files, and perform logical optimization. DC tool will do the job automatically.
Before hit the run button, you need to apply the design constrains, such as the specification of time delay
and environmental restrictions (areas, power, process etc.) to the synthesis tool.

3. Design for Test (DFT). Our tutorial will not cover this topic.

4. Run the gate-level simulation. To verify the correctness of this netlist, you have to re-run the simulation
for the netlist file by using the same testbench in previous behavior simulation. The malfunction may be
caused by improper use of variables and signals.

If you fail to pass the synthesis or simulations, it is important to check the log files and reports.
Sometimes the warnings do matters.

Tutorial example
1. Write RTL description by Verilog/VHDL.
2. Log into giant server and source Synopsys. When the command prompt, type in:

{giant:~} . /proj/cad/startup/profile.synopsys

*Note that there is a space between ‘.’ and ‘/’

This command enable you open synopsis tools. You should make sure this step is performed before
opening any synopsis tools.
3. Copy .synopsys_dc.setup file to your working directory. (DO NOT MODIFY THIS FILE!)

This script file is invoked when you open the design compiler which defines the technology libraries path.
You can either create a file name as .synopsys_dc.setup then copy the content from my web to this file, or
you can download this file from my web (make sure the name is .synopsys_dc.setup don’t missing the
leading dot). The followings are explanations for the scripts content.

set search_path: this parameter is used to specify the synthesis tool all the paths that it should search
when looking for the synthesis technology library for reference during synthesis.

set target_library: this parameter specifies the file contains all the logic cells that should be used for
mapping during synthesis.

set link_library: this parameter points to all the reference libraries contain the information on logic gate in
this technology.

set symbol_library: this parameter points to the library that contains the “visual” information on the logic
cells in the synthesis technology library.

4. Open Design Vision, under your working directory type in:

{giant:~/ASIC_14F/T_DC} design_vision&
5. Read in your RTL design

For Verilog user click, File -> Read

For VHDL user click, File->Analyze and after analyzing without error, click File -> Elaborate

When you read/analyze your design make sure your top design block is located at the bottom of the
reading list. Otherwise you will receive errors.
In the elaborate step, make sure the top design is chosen (Verilog user may skip this step).

6. Check to see if the design is in a good state. Make sure there is no error such as unconnected ports,
logical constant-value ports, cells with no input or output pins, mismatches between a cell and its
reference, multiple driver nets etc. Type in:

design_vision>check_design -multiple_designs

7. Copy cons.tcl to your working directory. This script will help you set up the design constrains. Don’t
forget to modify the system clock period to fit your design.

create_clock: this command is used to define a clock object with a particular period time. The –period
option defines the clock period, while the –waveform option controls the duty cycle and the starting edge
of the clock.

The following is an example to specify a port name as Sclk with a period of 38ns and 50% duty cycle.
The positive edge of the clock start at time 0ns and the falling edge occur at time 19ns.

create_clock -period 38 -waveform {0 19} [get_ports {Sclk}]

8. Run cons.tcl file. Type in source cons.tcl on your command line:

9. Compile your design. Click “Compile Design” under “Design” menu. Leave the setting as default.

10. Copy dc_rpt.tcl to your working directory. This script will help you generate report files.

report_timing > dc_reports/timing.rpt //timing report

report_area > dc_reports/area.rpt //area report
report_cell > dc_reports/cell.rpt //cell report
report_qor > dc_reports/qor.rpt //summary
report_resources > dc_reports/resources.rpt //resource report
11. Dump report files. Create a folder named “dc_reports” under your working directory. Type in
“source dc_rpt.tcl”

You will get 4 report files under dc_reports folder. They are:

area.rpt: this report contains the information of chip area

****************************************
Report : area
Design : MSDAP
Version: D-2010.03-SP3
Date : Thu Oct 30 22:48:44 2014
****************************************
Library(s) Used:
ss_1v62_125c (File: /proj/txace/zxb107020/MSDAP/Tech/synopsys/ss_1v62_125c.db)
Number of ports: 11
Number of nets: 24
Number of cells: 3
Number of references: 3
Combinational area: 557321.758080
Noncombinational area: 878549.794113
Net Interconnect area: undefined (No wire load specified)
Total cell area: 1435871.552193
Total area: undefined
1

cell.rpt: from this report you will see the breakup of each cell area in the design
****************************************
Report : cell
Design : MSDAP
Version: D-2010.03-SP3
Date : Thu Oct 30 22:48:44 2014
****************************************
Attributes:
b - black box (unknown)
h - hierarchical
n - noncombinational
r - removable
u - contains unmapped logic

Cell Reference Library Area Attributes

--------------------------------------------------------------------------------
Datapath_L datapath_0 715450.809668
h, n
Datapath_R datapath_1 715103.968073
h, n
Main_Controller Main_Controller 5316.774452
h, n
--------------------------------------------------------------------------------
Total 3 cells 1435871.552193
1

qor_report: this report summaries the information of area, timing, critical paths violations etc.

****************************************
Report : qor
Design : MSDAP
Version: D-2010.03-SP3
Date : Thu Oct 30 22:48:44 2014
****************************************

Timing Path Group 'Dclk'

-----------------------------------
Levels of Logic: 3.00
Critical Path Length: 0.55
Critical Path Slack: 1.32
Critical Path Clk Period: 1302.00
Total Negative Slack: 0.00
No. of Violating Paths: 0.00
Worst Hold Violation: 0.00
Total Hold Violation: 0.00
No. of Hold Violations: 0.00
-----------------------------------
 Timing Path Group 'Sclk'
-----------------------------------
Levels of Logic: 9.00
Critical Path Length: 2.79
Critical Path Slack: 0.06
Critical Path Clk Period: 30.00
Total Negative Slack: 0.00
No. of Violating Paths: 0.00
Worst Hold Violation: 0.00
Total Hold Violation: 0.00
No. of Hold Violations: 0.00
-----------------------------------

Cell Count
-----------------------------------
Hierarchical Cell Count: 32
Hierarchical Port Count: 1635
Leaf Cell Count: 63694
Buf/Inv Cell Count: 12623
CT Buf/Inv Cell Count: 0
-----------------------------------

Area
-----------------------------------
Combinational Area: 557321.758080
Noncombinational Area:
878549.794113
Net Area: 0.000000
-----------------------------------
Cell Area: 1435871.552193
Design Area: 1435871.552193

Design Rules
-----------------------------------
Total Number of Nets: 66244
Nets With Violations: 0
-----------------------------------

Hostname: giant

Compile CPU Statistics

-----------------------------------
Resource Sharing: 13.85
Logic Optimization: 83.83
Mapping Optimization: 170.41
-----------------------------------
Overall Compile Time: 285.83

timing_report: this report contains the critical timing paths information. The critical path is the slowest
logic path between any two registers and is therefore the limiting factor prevents you from decreasing the
clock period constraint (and thus increasing performance). In below example we have two critical paths
one is for Dclk and the other one is for Sclk. They are marked as red color. Notice that the last line for
each clock should be printed as slack (MET). If you get a slack (VIOLATED) that means your design
fails to fulfill the timing requirement. You may modify the system clock frequency to solve the problem.
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : MSDAP
Version: D-2010.03-SP3
Date : Thu Oct 30 22:48:44 2014
****************************************

Operating Conditions: ss_1v62_125c Library: ss_1v62_125c

Wire Load Model Mode: top

Startpoint: Reset_n (input port clocked by Sclk)

Endpoint: Main_Controller/zeros_reg
(falling edge-triggered flip-flop clocked by Dclk)
Path Group: Dclk
Path Type: max

Point Incr Path

--------------------------------------------------------------------------
clock Sclk (rise edge) 1950.00 1950.00
clock network delay (ideal) 0.00 1950.00
input external delay 1.00 1951.00 r
Reset_n (in) 0.00 1951.00 r
Main_Controller/reset_n (Main_Controller) 0.00 1951.00 r
Main_Controller/U47/Y (OAI31X1M) 0.11 1951.11 f
Main_Controller/U51/Y (NOR4X1M) 0.31 1951.42 r
Main_Controller/U49/Y (AOI22X1M) 0.13 1951.55 f
Main_Controller/zeros_reg/D (DFFNSRHX1M) 0.00 1951.55 f
data arrival time 1951.55

clock Dclk (fall edge) 1953.00 1953.00

clock network delay (ideal) 0.00 1953.00
Main_Controller/zeros_reg/CKN (DFFNSRHX1M) 0.00 1953.00 f
library setup time -0.13 1952.88
data required time 1952.88
--------------------------------------------------------------------------
data required time 1952.88
data arrival time -1951.55
--------------------------------------------------------------------------
slack (MET) 1.32

Startpoint: Datapath_R/S2P/temp_reg[0]
(falling edge-triggered flip-flop clocked by Dclk)
Endpoint: Main_Controller/current_state_reg[2]
(rising edge-triggered flip-flop clocked by Sclk)
Path Group: Sclk
Path Type: max

Point Incr Path

--------------------------------------------------------------------------
clock Dclk (fall edge) 4557.00 4557.00
clock network delay (ideal) 0.00 4557.00
Datapath_R/S2P/temp_reg[0]/CKN (DFFNSRHX1M) 0.00 4557.00 f
Datapath_R/S2P/temp_reg[0]/Q (DFFNSRHX1M) 0.57 4557.57 f
Datapath_R/S2P/dataout[0] (S2P_1) 0.00 4557.57 f
Datapath_R/RAM/P_In[0] (RAM_1) 0.00 4557.57 f
Datapath_R/RAM/U10443/Y (CLKINVX2M) 0.12 4557.68 r
Datapath_R/RAM/U5163/Y (BUFX2M) 0.17 4557.85 r
Datapath_R/RAM/U3876/Y (BUFX2M) 0.16 4558.01 r
Datapath_R/RAM/U2248/Y (BUFX2M) 0.40 4558.41 r
Datapath_R/RAM/U2245/Y (NAND4X2M) 0.20 4558.61 f
Datapath_R/RAM/U2247/Y (NOR4X1M) 0.34 4558.95 r
Datapath_R/RAM/zero (RAM_1) 0.00 4558.95 r
Datapath_R/zero (datapath_1) 0.00 4558.95 r
Main_Controller/zero_R (Main_Controller) 0.00 4558.95 r
 Main_Controller/U4/Y (NAND2X2M) 0.20 4559.16 f
Main_Controller/U12/Y (AOI211X2M) 0.29 4559.45 r
Main_Controller/U13/Y (OAI222X1M) 0.34 4559.79 f
Main_Controller/current_state_reg[2]/D (DFFRX2M) 0.00 4559.79 f
data arrival time 4559.79

clock Sclk (rise edge) 4560.00 4560.00

clock network delay (ideal) 0.00 4560.00
Main_Controller/current_state_reg[2]/CK (DFFRX2M) 0.00 4560.00 r
library setup time -0.15 4559.85
data required time 4559.85
--------------------------------------------------------------------------
data required time 4559.85
data arrival time -4559.79
--------------------------------------------------------------------------
slack (MET) 0.06

12. Check the schematic of your critical path. Click Schematic->New Design Schematic View

You will see your top view of schematic. Now click Schematic->Add Path From/Through/To ..
Simply click ‘OK’ and ignore the warning, the default setting will bring you the critical path.

13. Dump *.sdc and *.v file. Create a folder named ‘dc_out’ under your working directory, and type in
“source dc_sv.tcl”

14. Run gate level simulation. Go to your dc_out folder open the netlist file MSDAP_NETLIST.v. Add
two lines on the top of this file:

`include “18m.v “// specify the gate library

`timescale 1ns/1ps // set the time resolution

Then, download the gate library (18m.v) from my web.

Put 18m.v MSDAP_NETLIST.v and your testbench files to your Modelsim working directory.

Open Modelsim and Click Compile->Compile All

Click Simulate->Start Simulation

Choose your testbench module and change the resolution as ps. Now you are ready to check the
functionality of this gate level netlist. Make sure this netlist is working well before going to next chapter.