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Final Report ADVD Analog Assignment

Analog VLSI Design Project Report for telescopic Opamp

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ritik12041998
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125 views12 pages

Final Report ADVD Analog Assignment

Analog VLSI Design Project Report for telescopic Opamp

Uploaded by

ritik12041998
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Analog Assignment Report

Group 11

Single Ended Folded Cascode Topology


By

Name of the Student ID No.


Aditya Manglik 2014A3PS296P
Sagar Seth 2014A3PS224P
Siddharth Iyer 2014A8PS529P
Siddharth K 2014A3PS219P

EEE F313 Analog and Digital VLSI Design


BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI
November, 2016
Problem Statement

Design a Single-ended output Folded Cascode OTA with the following


requirements:

a) Analog schematic for OTA


b) Analysis of all equations for OTA, with a systematic derivative of all transistors
W/L ratios and spectre simulation of circuit for the following specifications.
i) DC Gain ≥ 120 dB
ii) Phase margin ≈ 55 degrees
c) Show a biasing circuitry to bias all the voltages in your design.
d) Use STB analysis to measure the closed loop gain and phase margin.
e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode
plot for AC gain and phase, CMRR plot, ICMR plot, PSRR plot, Slew Rate,
Output voltage swing (DC + Transient), Power Consumption, and Input & Output
offset voltage.

Parameter Design
Gain 137.77dB
Phase Margin 55.5 degrees
Vdd 3.5 V
Power Consumption 0.879 mW
Number of MOSFETs 22
Slew rate 3.3267 x 106 V/s
ICMR 3.446V-1.241V= 2.205 V
PSRR 127.05 dB
CMRR 158.346 dB
Output Voltage Swing 3.005–0.6317=2.3733 V
Output offset voltage 12.5 nV
Input offset voltage -12.5 nV
Analysis
Schematic- with current biasing circuitry
Aspect Ratios
W/L Ratios

W L
Device
Current Biasing
Circuitry
NMOS-1 2.5809u 2u
NMOS-2 2.8618u 350n
NMOS-3 2.0007u 2u
NMOS-4 7.2036u 2u
NMOS-5 4.8136u 350n
PMOS-1 70.822u 2u
PMOS-2 68.241u 2u

Folded Cascode
PMOS-3 157.9u 2u
PMOS-4 157.9u 2u
PMOS-5 52.427u 2u
PMOS-6 52.427u 2u
PMOS-7 52.794u 2u
PMOS-8 52.794u 2u
NMOS-6 17.142u 2u
NMOS-7 17.142u 2u
NMOS-8 18.953u 2u
NMOS-9 7.7718u 2u
NMOS-10 7.7718u 2u
NMOS-11 16.117u 2u
NMOS-12 16.117u 2u
NMOS-13 13.224u 2u
NMOS-14 13.224u 2u
Results
DC Gain = 137.77 dB

Biasing Circuitry

Shown in the schematic.

STB Analysis- Closed Loop Gain and Phase Margin


Phase Margin = 55.445 degrees
Loop Gain = 100 dB
Bode plot for AC Gain & Phase
CMRR plot CMRR Range= 158.346 dB

ICMR plot ICMR Range= 3.446 V - 1.241 V= 2.205 V


PSRR plot PSRR = 127.05 dB

Slew Rate =3.3267 x 106 V/s


Output Waveform (DC + Transient)

FF & SS Analysis

Temperature for FF= 100 C

Temperature for SS=0 C

FF SS
Gain 129.98 dB 135.41 dB
Phase Margin 55.3 degrees 55.6 degrees
FF Gain & Phase Plot Gain=129.98 dB Phase=55.3 degrees

SS Gain & Phase Plot Gain=135.41 dB Phase=55.6 degrees


Output Voltage Swing Plot =3.005 V – 0.6317V= 2.368 V

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