Chapter 2: Central Processing

Unit

KESHAV RAJ JOSHI

 Central processing unit
• Part of the computer that performs the bulk of
data processing operations
• Purpose is to interpret instruction cycles
received from memory and perform
arithmetic, logic and control operations
• CPU is usually divided into two parts namely
processor unit (Register Unit & Arithmetic
Logic Unit) and control unit

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Processor Unit
• Consists of: arithmetic unit, logic unit, a number of registers
and internal buses
• Registers are connected through common buses for data
transfer
Control Unit:
• Consists of: a program counter, instruction register, timing
and control logic
• The control unit decides what the instructions mean and
directs the necessary data to be moved from memory to ALU
• Control unit must communicate with both ALU and main
memory and coordinates all activities of processor unit,
peripheral devices and storage devices

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Input to control unit
• Flag: flags are headed to determine the status of
processor and outcome of previous ALU
operation (zero, negative, carry, overflow etc.)
• Clock: All micro-operations are performed within
each clock pulse. This clock pulse is also called as
processor cycle time or clock cycle time.
• Instruction Register: The op-code of instruction
determines which micro-operation to perform
during execution cycle.
• Control signal from control bus: The control bus
portion of system bus provides interrupt,
acknowledgement signals to control unit.
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Output from control unit
• Control signal within processor: These
signals causes data transfer between
registers, activate ALU functions
• Control signal to control bus: These are
signals to memory and I/O module.

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CPU Structure and Function
• Processor Organization:
– Things that processor must do:
• Fetch Instructions
• Interpret Instructions
• Fetch Data
• Process Data
• Write Data
• To do these things, the processor needs to store
some data temporarily
• It must remember the location of the last
instruction so that it can know where to get the next
instruction
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Register Organization
• Registers function as a level of memory above main
memory and cache in the hierarchy
• Register memory is faster, smaller, and more
expensive (Per bit)
• The registers in the processor perform two roles:
– User-visible registers: Enable the machine or assembly
language programmer to minimize main memory
references by optimizing use of registers.
– Control and status registers: Used by the control unit to
control the operation of the processor and by privileged,
operating system programs to control the execution of
programs.

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User visible registers
• General-purpose registers: can be assigned to a variety of
functions by the programmer (e.g. can contain the
operand, used for addressing function)
– any general-purpose register can contain the operand for any
opcode
• Data registers: may be used only to hold data, not address
• Address registers: Hold addresses
– Segment pointers - hold base address of the segment in use
– Index registers - used for indexed addressing (address of the
operand is obtained by adding to the contents of the general
register (called index register) a constant value)
– Stack Pointer - a dedicated register that points to top of a
stack(Push, pop)
• Condition codes: flags

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• Design Issues:
• whether to use completely general-purpose registers
or to specialized use?
– Specialized registers save bits in instructions because their
use can be implicit
– General-purpose registers are more flexible
– Trend is toward use of specialized registers
• Number of registers provided?
– More registers require more operand specifier bits in
instructions
– 8 to 32 registers appears optimum
• Register Length?
– Address registers must be long enough to hold the largest
address
– Data registers should be able to hold values of most data
types

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Control and status registers
• Four registers are essential to instruction execution: used for the
movement of data between the processor and memory
– Program Counter (PC)
– Instruction Register (IR)
– Memory Address Register (MAR) - usually connected directly to address lines
of bus
– Memory Buffer Register (MBR) - usually connected directly to data lines of bus
• Register: program status word (PSW), that contain status information
– Sign - sign bit of last arithmetic operation
– Zero - set when result of last arithmetic operation is 0
– Carry - set if last operation resulted in a carry into or borrow out of a
high-order bit
– Equal - set if a logical compare result is equality
– Overflow - set when last arithmetic operation caused overflow
– Interrupt Enable/Disable - used to enable or disable interrupts
– Supervisor: Indicates whether the processor is executing in supervisor
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or user mode.
Instruction cycle
• Basic instruction cycle contains the following
sub-cycles.
• Fetch - read next instruction from memory
into CPU
• Execute - Interpret the opcode and perform
the indicated operation
• Interrupt - if interrupts are enabled and one
has occurred, save the current process state
and service the interrupt

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The indirect cycle
• Think of as another instruction sub-cycle
• May require just another fetch (involve one or more
operands in memory, each of which requires a memory
access)
• Might also require arithmetic, like indexing (fetching of
indirect addresses as one more instruction stages)

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Data Flow
• Fetch cycle: an instruction is read from memory

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• PC contains address of next instruction to be
fetched
• This address is moved to MAR and placed on
address bus
• Control unit requests a memory read
• Result is
– placed on data bus
– result copied to MBR
– then moved to IR
• Meanwhile, PC is incremented

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• Indirect cycle: Once the fetch cycle is over, the
control unit examines the contents of the IR to
determine if it contains an operand specifier
using indirect addressing
• If so, an indirect cycle is performed
• The rightmost N bits of the MBR, which
contain the address reference, are transferred
to the MAR
• Then the control unit requests a memory
read, to get the desired address of the
operand into the MBR
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Interrupt cycle

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• Current contents of PC must be saved (for
resume after interrupt), so PC is transferred to
MBR to be written to memory
• The special memory location reserved for this
purpose is loaded into MAR from the control
unit
• PC is loaded with address of interrupt routine
(so next instruction cycle will begin by fetching
appropriate instruction)

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Arithmetic and Logic Unit
• part of the computer that actually performs
arithmetic and logical operations on data
• Figure indicates in general term how ALU is
interconnected with rest of the processor
• Data are presented to ALU in register and the
result of operation is stored in register
• registers are temporarily storage location
within the processor
• The flags values are also stored in registers
within the processor
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Design the arithmetic section
• The basic component of arithmetic circuit is a
parallel adder which is constructed with a
number of full adder circuits connected in
cascade
• By controlling the data inputs to the parallel
adder, it is possible to obtain different types of
arithmetic operations
• Below figure shows the arithmetic circuit and
its functional table

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Design the logical section
• The basic components of logical circuit are
AND, OR, XOR and NOT gate circuits
connected accordingly

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Combine these 2 sections to form the ALU

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Elements of a machine instruction
• Each instruction must contain the information
required by the processor for execution
– Operation code: Specifies the operation to be
performed (e.g., ADD, I/O) - a binary code
– Source operand reference: The operation may
involve one or more source operands, that is,
operands that are inputs for the operation.
– Result operand reference: The operation may
produce a result.
– Next instruction reference: This tells the
processor where to fetch the next instruction
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Instruction Formats
• Computer can be used to perform a specific task,
only by specifying the necessary steps to
complete the task
• The collection of such ordered steps forms a
‘program’ of a computer
• Ordered steps are the instructions
• Instructions are stored in central memory
locations and are executed sequentially one at a
time
• Instruction format is required to interpret each
instruction code and provide the necessary
control functions needed to process the
instruction
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• An n bit instruction that k bits in the address field and m bits
in the operation code field come addressed 2k location
directly and specify 2m different operation
• The most common fields in instruction formats are:
– An Operation code field that specifies the operation to be
performed
– An Address field that designates a memory address or a
processor register
– A Mode field that specifies the way the operand or the
effective address is determined

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• The operation code field (Opcode) of an
instruction is a group of bits that define
various processor operations such as add,
subtract, complement, shift etc.
• Bits that define the mode field of an
instruction code specify a variety of
alternatives for choosing the operands from
the given address
• Operands residing in memory are specified by
their memory address
• Operands residing in processor register are
specified with a register address.
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Types of Instruction
• Computers may have instructions of several different
lengths containing varying number of addresses
• Most computers fall into one of 3 types of CPU
organizations:
– Single accumulator organization:- All the operations are
performed with an accumulator register. The instruction
format in this type of computer uses one address field. For
example: ADD X, where X is the address of the operands .
– General register organization:- The instruction format in
this type of computer needs three register address fields.
For example: ADD R1,R2,R3
– Stack organization:- The instruction in a stack computer
consists of an operation code with no address field. This
operation has the effect of popping the 2 top numbers
from the stack, operating the numbers and pushing the
sum into the stack. For example: ADD

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Following are the types of instructions:
1. Three address Instruction
– With this type of instruction, each instruction specifies
two operand location and a result location. A
temporary location T is used to store some intermediate
result so as not to alter any of the operand location. The
three address instruction format requires a very
complex design to hold the three address references.
– Format: Op X, Y, Z; X  Y Op Z
– Example: ADD X, Y, Z; X  Y + Z

• ADVANTAGE: It results in short programs when evaluating

arithmetic expressions.
• DISADVANTAGE: The instructions requires too many bits to
specify 3 addresses.

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2. Two address instruction
• Here again each address field can specify either a
processor register, or a memory word. One
address must do double duty as both operand
and result.
• The two address instruction format reduces the
space requirement. To avoid altering the value of
an operand, a MOV instruction is used to move
one of the values to a result or temporary
location T, before performing the operation.
• Format: Op X, Y; X  X Op Y
• Example: SUB X, Y; XX-Y

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3. One address Instruction
• The accumulator contains one of the operand
and is used to store the result
• One-address instruction uses an implied
accumulator (Ac) register for all data
manipulation
• All operations are done between the AC
register and a memory operand. We use LOAD
and STORE instruction for transfer to and from
memory and Ac register
• Format: Op X; Ac Ac  Op X
• Example: MUL X; Ac  Ac * X
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4. Zero address Instruction
• It does not use address field for the
instruction like ADD, SUB, MUL, DIV etc.
• The PUSH and POP instructions, however,
need an address field to specify the operand
that communicates with the stack.
• Format: Op; TOS  TOS Op (TOS – 1)
• Example: DIV; TOS  TOS DIV (TOS – 1)

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Example:
• Arithmetic statement X=(A+B)*(C+D) using
Zero, one, two, or three address instructions
• It is assumed that the computer has two
processor registers R1 and R2. The symbol
M[A] denotes the operand at memory address
symbolized by A
• 1. Three-Address Instructions:
ADD R1, A, B; R1  M[A] + M[B]
ADD R2, C, D; R2  M[C] + M[D]
MUL X, R1,R2; M[X]  R1 * R2
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2. Two-Address Instructions:
MOV R1, A; R1  M[A]
ADD R1, B; R1  R1 + M[B]
MOV R2, C; R2  M[C]
ADD R2, D; R2  R2 + M[D]
MUL R1, R2; R1  R1 * R2
MOV X, R1; M[X]  R1
3. One-Address Instruction:
LOAD A; Ac  M[A]
ADD B; Ac  Ac + M[B]
STORE T; M[T]  Ac
LOAD C; Ac  M[C]
ADD D; Ac  Ac + M[D]
MUL T; Ac  Ac * M[T]
STORE X; M[X]  Ac
Here, T is the temporary memory location required for storing
the intermediate result.

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4. Zero-Address Instructions:
PUSH A; TOS  A
PUSH B; TOS  B
ADD; TOS  (A + B)
PUSH C; TOS  C
PUSH D; TOS  D
ADD; TOS  (C + D)
MUL; TOS  (C + D) * (A + B)
POP X ; M[X]  TOS

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Addressing Modes
• Specifies a rule for interpreting or modifying
the address field of the instruction before the
operand is actually referenced
• Computers use addressing mode techniques
for the purpose of:
– Provides facilities as pointers to memory, counters
for loop control, indexing of data
• Effective address (EA):
– Is the memory address obtained from the
computation dictated by the given addressing
mode

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Types of Addressing Modes
• Implied
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack

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Implied Addressing Mode
• In this mode the operands are specified implicitly in
the definition of the instruction
• CMA - “complement accumulator” (provides a 1’s
complement) is an implied-mode instruction because
the operand in the accumulator register is implied in
the definition of the instruction
• Advantage: no memory reference.
• Disadvantage: limited operand

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Immediate Addressing
• The operand is specified in the instruction itself
• Operand = address field
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Typically, the number will be stored in twos
complement form; the leftmost bit of the
operand field is used as a sign bit

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 Immediate Addressing Diagram

Instruction
Opcode Operand

• Disadvantage is that the size of the number is

restricted to the size of the address field

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Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out
effective address
• limited address space
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Direct Addressing Diagram

Instruction

Opcode Address A
Memory

Operand

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Indirect Addressing (1)
• Memory cell pointed to by address field
contains the address of (pointer to) the
operand
• EA = (A)
– Look in A, find address (A) and look there for
operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to
accumulator

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 Indirect Addressing (2)
• Large address space
• The advantage of this approach is that for a word
(operand)length of n, an address space of 2n is now
available
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• disadvantage is that instruction execution requires two
memory references to fetch the operand: one to get its
address and a second to get its value.
• Hence slower

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 Indirect Addressing Diagram

Instruction

Opcode Address A
Memory

Pointer to operand

Operand

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Register Direct Addressing (1)
• Operand is held in register named in address filed
• EA = R
• E.g. if the contents of a register address field in an
instruction is 5, then register R5 is the intended
address, and the operand value is contained in R5
• Limited number of registers
• Very small address field needed (from 3 to 5 bits,
so that a total of from 8 to 32 general-purpose
registers can be referenced)
– Shorter instructions
– Faster instruction fetch
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Register Addressing (2)
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance

Instruction

Opcode Register Address R

Registers

Operand

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Register Indirect Addressing
• The instruction specifies a register in the CPU
whose contents give the address of the
operand in the memory
• EA = (R)
• Operand is in memory cell pointed to by
contents of register R
• Large address space (2n)
• One fewer memory access than indirect
addressing

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Register Indirect Addressing Diagram

Instruction

Opcode Register Address R

Memory

Registers

Pointer to Operand Operand

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Displacement Addressing
• Combines the capabilities of direct addressing
and register indirect addressing
• EA = A + (R)
• Address field hold two values
– A = base value
– R = register that holds displacement
– or vice versa

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Displacement Addressing Diagram

Instruction

Opcode Register R Address A

Memory

Registers

Pointer to Operand +
Operand

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• Three of the most common uses of
displacement addressing:
• Relative addressing
• Base-register addressing
• Indexing

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Relative Addressing
• The content of the program counter (PC) is
added to the address part of the instruction in
order to obtain the effective address
• EA = A + (PC)
• i.e. get operand from A cells from current
location pointed to by PC

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Base-Register Addressing
• The content of a base register (BR) is added to
the address part of the instruction to obtain
the effective address.
• A holds displacement
• R holds pointer to base address
• Effective Address (EA) = BR + A
(Base Register is the register, acts as a address
holder of the base storage location from
where the data was stored continuously)

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Indexed Addressing
• In this mode the content of an index register (XR)
is added to the address part of the instruction to
obtain the effective address.
• A = base
• R = displacement
• EA = A + R
• Good for accessing arrays
– EA = A + R
– R++
(An index register is a processor register used for
modifying operand addresses during the run of a
program, typically for doing vector/array operations)

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Stack Addressing
• The stack is the linear array of locations. It is
some times referred to as push down list or
last in First out (LIFO) queue. The stack pointer
is maintained in register
• Operand is (implicitly) on top of stack
• e.g.
– ADD Pop top two items from stack
and add

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Summary

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Data Transfer and Manipulation
• Data transfer instructions cause transfer of data from one
location to another without changing the binary information
• The most common transfer are between the
– Memory and Processor registers
– Processor registers and input output devices
– Processor registers themselves

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Data manipulation Instructions
• Data manipulation instructions perform operations
on data and provide the computational capabilities
for the computer
• These instructions perform arithmetic, logic and shift
operations

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 S= Sign bit

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Program Control Instructions
• These instructions provide decision making capabilities and
change the path taken by the program when executed in
computer
• These instructions specify conditions for altering the content
of the program counter
• Some typical program control instructions are:

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Subroutine call and Return
• A subroutine call instruction consists of an
operation code together with an address that
specifies the beginning of the subroutine
• The address of the next instruction available in
the program counter (the return address) is
stored in a temporary location (stack) so the
subroutine knows where to return
• Control is transferred to the beginning of the
subroutine
• The last instruction of subroutine transfer the
return address from the temporary location into
the program counter. This results in a transfer of
program control to the instruction where address
was originally stored in the temporary location.
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Interrupt
• The interrupt procedure is, in principle, quite
similar to a subroutine call except for three
variations:
– The interrupt is usually initiated by an external or
internal signal rather than from execution of an
instruction
– The address of the interrupt service program is
determined by the hardware rather than from the
address field of an instruction
– An interrupt procedure usually stores all the
information necessary to define the state of the CPU
rather than storing only the program counter

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 RISC & CISC
• Instruction set is the structure of the computer that provides
commands to the computer to guide the computer for
processing data manipulation
• Instruction set consists of instructions, addressing modes,
native data types, registers, interrupt, exception handling and
memory architecture

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Complex Instruction Set Computers (CISC)
• A computer with a large number of instructions is
classified as a complex instruction set computer (CISC)
• The essential goal of CISC architecture is to attempt to
provide a single machine instruction for each statement
that is written in a high-level language
• Each instruction executes multiple low level operations.
– Ex. A single instruction can load from memory,
perform an arithmetic operation, and store the result
in memory.
• Examples of CISC architecture are the DEC VAX computer
and the IBM 370 computer. Other are 8085, 8086, 80x86
etc.
• Hardware of the Intel is termed as Complex Instruction
Set Computer (CISC)

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 Major characteristics of CISC architecture
• A large number of instructions– typically from 100 to
250 instructions
• Some instructions that perform specialized tasks and
are used infrequently
• A large variety of addressing modes—typically from 5
to 20 different modes
• Variable-length instruction formats (Instructions that
require register operands may be only two bytes in
length, but instructions that need two memory
addresses may need five bytes to include the entire
instruction code)
• Instructions that manipulate operands in memory
(e.g. , an ADD instruction may specify one operand in
memory through index addressing and a second
operand in memory through a direct addressing.
Another memory location may be in-cluded in the
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instruction to store the sum)
• Reduced speed due to memory read/write
operations
• Use of micro program – special program in
control memory of a computer to perform the
timing and sequencing of the micro
operations – fetch, decode, execute etc.
• Major complexity in the design of micro
program
• No large number of registers – single register
set of general purpose and low cost

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Reduced Instruction Set Computers (RISC)
• A computer uses fewer instructions with simple constructs
so they can be executed much faster within the CPU
without having to use memory as often
• every instruction is expected to attain very small jobs
• RISC concept – an attempt to reduce the execution cycle by
simplifying the instruction set
• Small set of instructions – mostly register to register
operations and simple load/store operations for memory
access
• May include immediate operands
• Simplify instruction set and encourages the optimization of
register manipulation
• Each operand – brought into register using load instruction,
computations are done among data in registers and results
transferred to memory using store instruction
– Apple hardware is Reduced Instruction Set Computer (RISC)
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 The major characteristics of RISC architecture
• Relatively few instructions
• Relatively few addressing modes
• Memory access limited to load and store instructions
• All operations done within the registers of the CPU
• Fixed-length, easily decoded instruction format :
– Generally, only one or a few formats are used
– Field locations, especially the opcode, are fixed
– Simplified formats simplify the control unit
• Single-cycle instruction execution:
– Machine cycle: time it takes to fetch two operands from
registers, perform an ALU operation, and store the result in
a register.
– there is one machine instruction per machine cycle
• Hardwired rather than micro programmed control
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 Other characteristics attributed to RISC architecture
• A relatively large number of registers in the processor
unit
• Use of overlapped register windows to speed-up
procedure call and return
• Efficient instruction pipeline – fetch, decode and
execute overlap
• Compiler support for efficient translation of high-level
language programs into machine language programs
• RISC processors often achieve 2 to 4 times the
performance of CISC processors.
• Simple addressing modes:
– Almost all RISC instructions use simple register addressing
• RISC processors are simpler than corresponding CISC
processors, they can beKeshav
designed
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 Comparison between RISC and CISC Architectures

RISC CISC
Simple instructions taking one Complex instructions taking
cycle multiple cycles
Only load and store memory Any instructions may reference
references memory
Heavily pipelined Not/less pipelined
Fixed format instructions Variable format instructions
Few instructions and modes Large instructions and modes

Instructions executed by Instructions interpreted by

hardware micro-programming

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 Overlapped register windows
• Some computers provide multiple-register banks,
and each procedure is allocated its own bank of
registers. This eliminates the need for saving and
restoring register values.
• Some computers use the memory stack to store
the parameters that are needed by the
procedure, but this required a memory access
every time the stack is accessed.
• A characteristic of some RISC processors is their
use of overlapped register windows to provide
the passing of parameters and avoid the need for
saving and restoring register values.
• The concept of overlapped register windows is
illustrated in below figure.
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• In general, the organization of register windows
will have the following relationships:
– Number of global registers = G
– Number of local registers in each window = L
– Number of registers common to two windows = C
– Number of windows = W
• The number of registers available for each
window is calculated as followed:
• Window size = L + 2C + G
• The total number of registers needed in the
processor is Register file = (L + C)W + G
– A total of 74 registers
– Global Registers = 10  common to all procedures
– 64 registers divided into 4 windows A, B, C & D
– Each register window = 10 registers  local
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 Berkeley RISC I
• The Berkeley RISC I is a 32-bit integrated circuit CPU.
– It supports 32-bit address and either 8-, 16-, or 32-bit data.
– It has a 32-bit instruction format and a total of 31
instructions.
– There are three basic addressing modes: Register
addressing, immediate operand, and relative to PC
addressing for branch instructions.
– It has a register file of 138 registers; 10 global register and
8 windows of 32 registers in each
– The 32 registers in each window have an organization
similar to overlapped register window.
• Seven of the bits in the operation code specify an
operation, and the eighth bit indicates whether to
update the status bits after an ALU operation.
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 For register-to-register instructions :
• The 5-bit Rd field select one of the 32 registers
as a destination for the result of the
operation
• The operation is performed with the data
specified in fields Rs and S2.
• Thus the instruction has a three-address
format, but the second source may be either a
register or an immediate operand.

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 For memory access instructions
• Rs to specify a 32-bit address in a register
• S2 to specify an offset (use to points random
position in segment)

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• The third instruction format combines the last
three fields to form a 19-bit relative address Y
and is used primarily with the jump and call
instructions.
– The COND field replaces the Rd field for jump
instructions and is used to specify one of 16
possible branch conditions.

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 64 – bit Processor
• The brain of the PC is processor or CPU.
• It performs the system’s calculating and processing
operations.
• The term N-bits means that its ALU, internal registers and
most of its instructions are designed to work with N-bit binary
words
• The major components of CPU are:

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• 64-bit processors have 64-bit ALUs, 64-bit registers, and 64-bit
buses.
• A 64-bit register can address up to 264 bytes of logical address.
• 64-bit processors have been with us since 1992.
– Eg: 64-bit AMD processor.

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 Internal Architecture
• logic design of microprocessor which determines how and
when various operations are performed
• The various function performed by the microprocessor can be
classified as:
– Microprocessor initiated operations
– Internal operations
– Peripheral operations
• Microprocessor initiated operations mainly deal with memory
and I/O read and write operations.
• External initiated operations are initiated by the external
devices to perform special operations like reset, interrupt,
ready, etc.
• Internal operations determines how and what operations can
be performed with the data. The operations include:
– storing
– performing arithmetic and logical operations
– test for conditions
– store in the stack Keshav Raj Joshi 87
 The block diagram of 64-bit microprocessor
• The major parts of the block diagram are:
– General register unit
– Control and decoding unit
– Bus unit
– Cache memory unit
– Floating point register unit
– Issue ports

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 Architecture Elements
• Addressing mode:
– This addressing mode determines the working
environment. i.e 24,32 or 64 bit mode
– Program status word (PSW) bits 31 and 32
designate addressing mode (out of 64 bit)
– Addressing modes bits:
• 00=24 bit-mode
• 01=32 bit-mode
• 11=64 bit-mode

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 General purposes register (GPR)
• The register is treated as 64-bits for:
– Address generation in 64-bit mode.
• The register is treated as 32-bits for:
– Address generation in 24/32-bit mode.

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 Comparison of 64-bit with 32-bit
• Contains 32-bit data lines whereas 64-bit
contains 64 data lines.
• Can address max 2^32(4 GB) of data whereas
64 bit can address 2^64(18 billion GB).
• Speed and execution is both fast in 64-bit
processors.
• 64-bit processors can drive 32-bit applications
even faster, by handling more data per clock
cycle than a 32-bit processor.
• The table shows the basic difference between
two:
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Advantages Disadvantages
•Previous processors can • Compatibility difficulty
have max 4 Gb of physical with existing software as
memory but 64-bit can they are mostly developed
handle more. to the 32-bit processors.
•More general purpose •64-bit OS must have 64-
registers than in older bit drivers, for working
processors. efficiently.
•Significant increase in •They are costly.
speed due to wider data
bus and processing is fast.

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Thank you!

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