Verilog HDL

Prof. Dhaval Shah

Assistant Professor, ECE, IT-NU
dhaval.shah@nirmauni.ac.in
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 Acknowledgement
• Samir Palnitkar, Verilog HDL : A Guide to
Digital Design and Synthesis, Pearson
Education
 Verilog Program Structure
• Verilog language describes a digital system as a set of
modules.
• Each of these modules has an interface to other modules to
describe how they are interconnected.
• Usually we place one module per file but that is not a
requirement.
• The modules may run concurrently, but usually we have
one top level module which specifies a closed system
containing both test data and hardware models.
• The top level module invokes instances of other modules.
• Modules can represent bits of hardware ranging from simple
gates to complete systems, e. g., a microprocessor. Modules
can either be specified behaviourally or structurally (or a
combination of the two).
• Verilog HDL is case sensitive.
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 Verilog Program Structure
module <module_name> (<port_list>); Begins with keyword module
and ends with endmodule
Port Declaration The <module name> is an
identifier that uniquely names
Data type Declaration the module. All the rules of C
identifier are applicable. i.e. it
Must start with alphabets,
Circuit Functionality
should not start with numb or
special character. It should not
Timing Specification End with special character
endmodule

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 Verilog Program Structure
module <module_name> (<port_list>);
Continuous assignments use the
Port Declaration keyword assign whereas
procedural assignments have
Data type Declaration the form
<reg variable> = <expression>
Circuit Functionality where the <reg variable> must be
a register or memory.
Procedural assignment may only
Timing Specification
appear in initial and always
endmodule constructs.
Ways to Specify the functionality
1. Gate Level
2. Structural
3. Data-flow
4. Behavioral 5
 Data Flow Modeling
• Next level up: Dataflow modeling
• Continuous assignment
• The assign keyword is used

• Rules for assign Statement

1. LHS data type: only net (wire)
2. RHS data type: any type (register, net) or function

module fa1bit (a, b, cin, s, cout);

input a,b,cin;
output s, cout;
assign s = a ^ b ^ Cin;
assign cout = (a&b)|(b&cin)|(cin&a);
end module
 Rules for assign statement
• LHS data type: only net (wire)
• RHS data type: any type (register, net) or
function
Implicit continuous assignment

Implicit net declaration

Specifying Delays at Dataflow Level
1. Regular Assignment Delay
assign #10 out = in1 & in2;

2. Implicit Continuous Assignment Delay

wire #10 out = in1 & in2;

//same as
wire out;
assign #10 out = in1 & in2;

3. Net Declaration Delay

wire # 10 out;
assign out = in1 & in2;
 Delays at Dataflow Level are
Inertial Delay
assign #10 out = in1 & in2;
 Operators
Operator category Operators symbol
Arithmetic * / + - % **
Logical ! && ||
Relational > < <= >=
Equality == != === !===
Bitwise ~ & | ^ ^~ ~^
Reduction & ~& | ~| ^ ~^ ^~
Shift >> << >>> <<<
Concatenation { }
Replication { { } }
Conditional ? :
 Arithmetic Operators
A = 4'b0011; +5 // positive 5
B = 4'b0100; -4 // Negative 4
D = 6; E = 4; F=2;
-10/5
A * B -6’d10/5 // Do NOT use
D / E // =(2's complement of 10)/5
A + B // =(232 - 10)/5
B - A
F = E ** F;
• 4-valued logic issue:
13 % 3 // evaluate to 1 x and z values
16 % 4 // evaluate to 0
-7 % 2 // evaluate to -1 in1 = 4'b101x;
7 % -2 // evaluate to +1 in2 = 4'b1010;
sum = in1 + in2;// output
will be 4’bx
 Logical and Relational Operators
• Outcome: 0,1,x
• ‘x’ value usually treated as false
 Equality Operators

// A = 4, B = 3 // Z = 4'b1xxz, M = 4'b1xxz
// X = 4'b1010, Y = 4'b1101 // N = 4'b1xxx

A == B X == Z
X != Y Z === M
Z === N
M !== N
 Bitwise Operators
// X = 4'b1010
// Y = 4'b1101
// Z = 4'b10x1

~X // negation. Result = 4’b0101

X & Y // Result = 4’b1000
X | Y // Result = 4’b1111
X ^ Y // Result = 4’b0111
X ^~ Y // Result = 4’b1000
X & Z // Result = 4'b10x1
 Reduction Operators
// X = 4'b1010

&X
|X
^X
 Shift Operators
// X = 4'b1100

Y = X >> 1;
Y = X << 1;
Y = X << 2;

integer a, b, c;
a = 0;
b = -10;
c = a + (b >>> 3);
 Concatenation Operator
• Unsized operands not allowed
// A = 1'b1, B = 2'b00,
// C = 2'b10, D = 3'b110

Y = {B , C}
Y = {A , B , C , D , 3'b001}
Y = {A , B[0], C[1]}
 Replication Operator
reg A;
reg [1:0] B, C;
reg [2:0] D;
A = 1'b1;
B = 2'b00;
C = 2'b10;
D = 3'b110;
Y = { 4{A} }
Y = { 4{A} , 2{B} }
Y = { 4{A} , 2{B} , C }

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Conditional Operator

assign addr_bus = drive_enable ?

addr_out : 36'bz;

assign out = control ? in1 : in0;

assign out = (A == 3) ?
( control ? x : y ):
( control ? m : n) ;
Operators Precedence
 Data Flow Modeling - Example

module mux4_to_1 (output out,

input i0, i1, i2, i3, s1, s0);

assign out = (~s1 & ~s0 & i0)|

(~s1 & s0 & i1)|
( s1 & ~s0 & i2)|
( s1 & s0 & i3);
endmodule

4 x 1 Multiplexer
 4 X 1 using Conditional operator

module mux4_to_1 (output out,

input i0, i1, i2, i3, s1, s0);

assign out = s1 ? (s0 ? I3 :

i2) : (so ? i1 : i0);
endmodule 4 x 1 Multiplexer
 4-bit Full adder

module fa1bit (a, b, cin, s, cout);

input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
assign {cout , sum} = a + b + Cin;
end module
4-bit Full adder with carry look ahead
 4-bit Full adder with carry look ahead
module fulladd4(sum, c_out, assign c1 = g0 | (p0 & c_in),
a, b, c_in); c2 = g1 | (p1 & g0) |
(p1 & p0 & c_in),
output [3:0] sum;
c3 = g2 | (p2 & g1) |
output c_out;
(p2 & p1 & g0) |
input [3:0] a,b;
(p2 & p1 & p0 & c_in),
input c_in;
c4 = g3 | (p3 & g2) |
wire p0,g0, p1,g1, p2,g2, (p3 & p2 & g1) |
p3,g3, c4, c3, c2, c1; (p3 & p2 & p1 & g0) |
(p3 & p2 & p1 & p0 & c_in);
assign p0 = a[0] ^ b[0],
p1 = a[1] ^ b[1], assign sum[0] = p0 ^ c_in,
p2 = a[2] ^ b[2], sum[1] = p1 ^ c1,
p3 = a[3] ^ b[3]; sum[2] = p2 ^ c2,
sum[3] = p3 ^ c3;
assign g0 = a[0] & b[0],
g1 = a[1] & b[1], assign c_out = c4;
g2 = a[2] & b[2],
endmodule
g3 = a[3] & b[3];
Behavioural Modelling
 Introduction
• The move toward higher abstractions
– Gate-level modeling
• Netlist of gates

– Dataflow modeling
• Boolean function assigned to a net

– Now, behavioral modeling

• A sequential algorithm (quite similar to software) that
determines the value(s) of variable(s)

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 Structured Procedures

• Two basic structured procedure statements

always
initial

– All behavioral statements appear only inside these blocks

– Each always or initial block has a separate activity flow
(multithreading, concurrency)
– Start from simulation time 0
– No nesting

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Structured Procedures: initial statement

• Starts at time 0
• Executes only once during a simulation
• Multiple initial blocks, execute in parallel
– All start at time 0
– Each finishes independently

• Syntax:
initial
begin
// behavioral statements
end
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 Example
module stimulus;
reg x, y, a, b, m;
initial
initial #50 $finish;
m= 1’b0; endmodule

initial
begin
#5 a=1’b1;
#25 b=1’b0;
end

initial
begin
#10 x=1’b0;
#25 y=1’b1;
end

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 Initializing variables
• Ordinary style, using initial block
reg clock;
initial clock = 0;

• Combined declaration and initialization

reg clock = 0; // RHS must be constant

module adder (
output reg [7:0] sum = 0,
output reg co = 0,
input [7:0] a, b,
input ci);
...
endmodule

DSD 33
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Structured Procedures: always statement

• Start at time 0
• Execute the statements in a looping fashion

module clkgen ( output reg clock);

Initial
clock = 1’b0;
Always
#10 clock = ~clock;
Initial
#1000 $finish;
...
endmodule

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 Procedural Assignments

• Assignments inside initial and always

• To update values of “register, integer, real or
time” variables.
– The value remains unchanged until another
procedural assignment updates it

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 Cont…
• Syntax
<lvalue> = <expression>

– <lvalue> can be
• reg, integer, real, time
• A bit-select of the above (e.g., addr[0])
• A part-select of the above (e.g., addr[31:16])
• A concatenation of any of the above
– <expression> is the same as introduced in dataflow modeling

– What happens if the widths do not match?

• LHS wider than RHS => RHS is zero-extended
• RHS wider than LHS => RHS is truncated (Least significant part is kept)

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 Blocking Procedural Assignments
• The two types of procedural assignments
– Blocking assignments
– Non-blocking assignments
• Blocking assignments
– are executed in order (sequentially)
– Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count; All executed at time 0
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
#15 reg_a[2] = 1’b1; executed at time 15
#10 reg_b[15:13] = {x, y, z};
count = count + 1;
end All executed at time 2537
 Non-Blocking Procedural Assignments
• Non-blocking assignments
– Processing of the next statements is not blocked for this one
– Transactions created sequentially (in order), but executed after all
blocking assignments in the corresponding simulation cycle
– Syntax:
<lvalue> <= <expression>
– Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
All executed at time 0
integer count;
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
reg_a[2] <= #15 1’b1; Scheduled to run at time 15
reg_b[15:13] <= #10 {x, y, z};
count <= count + 1; Scheduled to run at time 10
end
Non-Blocking Assignments (cont’d)
• Application of non-blocking assignments
– Used to model concurrent data transfers
– Example: Write behavioral statements to swap values of two
variables

always @(posedge clock)

begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1;
end The old value of reg1 is used

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 Cont..
• When the final result of simulating two (or more)
concurrent processes depends on their order of execution
• Example:
always @(posedge clock)
b = a;
always @(posedge clock)
a = b;
• Solution: always @(posedge clock)
always @(posedge clock) begin
b <= a; temp_b = b;
always @(posedge clock) temp_a = a;
b = temp_a;
a <= b;
a = temp_b;
end
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 Timing Controls in
Behavioral Modeling
 Timing Control Methods
• No timing controls  No advance in simulation time

• Three methods of timing control

– delay-based
– event-based
– level-sensitive

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 Delay-based Timing Controls
• Delay  Duration between encountering and
executing a statement

• Delay symbol: #

• Types of delay-based timing controls

1. Regular delay control
2. Intra-assignment delay control
3. Zero-delay control

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 Regular Delay Control
• Symbol: non-zero delay before a procedural assignment

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 Intra-assignment Delay Control
• Symbol: non-zero delay to the right of the
assignment operator

• Operation sequence:
1. Compute the RHS expression at current time.
2. Defer the assignment of the above computed
value to the LHS by the specified delay.

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Intra-assignment Delay Control
 Zero-Delay Control
• Symbol: #0

• Different initial/always blocks in the same simulation

time
– Execution order non-deterministic
• #0 ensures execution after all other statements
– Eliminates race conditions (only in simulation)

• Multiple zero-delay statements

– Non-deterministic execution order

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Zero-Delay Control

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 Event-based Timing Control
• Event
– Change in the value of a register or net
– Used to trigger execution of a statement or block
(reactive behavior/reactivity)

• Types of Event-based timing control

1. Regular event control
2. Named event control
3. Event OR control

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 Regular Event Control
• Symbol: @(<event>)
• Events to specify:
– posedge sig
• Change of sig from any value to 1 or from 0 to any value
– negedge sig
• Change of sig from any value to 0 or from 1 to any value
– sig
• Any change in sig value

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 Named Event Control
• You can declare (name) an event, and then trigger
and recognize it.

• Keyword: event
event calc_finished;

• Verilog symbol for triggering: ->

->calc_finished
• Verilog symbol for recognizing: @()
@(calc_finished)
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Named Event Control

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 Event OR control
• Used when need to trigger a block upon occurrence
of any of a set of events.
• The list of the events: sensitivity list
• Keyword: or

• Simpler syntax
– always @( reset, clock, d)
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 Event OR control
• Simpler syntax
– @* and @(*)

• OR

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 Level-sensitive Timing Control
• Level-sensitive vs. event-based
– event-based: wait for triggering of an event
(change in signal value)
– level-sensitive: wait for a certain condition (on
values/levels of signals)

• Keyword: wait()
always
wait(count_enable) #20 count=count+1;

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Conditional Statements
Multiway Branching
 Behavioral Modeling Statements:
Conditional Statements
• Just the same as if-else in C
• Syntax:
if (<expression>) true_statement;

if (<expression>) true_statement;
else false_statement;

if (<expression>) true_statement1;
else if (<expression>) true_statement2;
else if (<expression>) true_statement3;
else default_statement;

• True is 1 or non-zero
• False is 0 or ambiguous (x or z)
• More than one statement: begin end
 Behavioural Modelling – (if - else statement)
module FA (A, B, Cin, COUT, S );
input A,B,Cin;
output COUT,S;
reg S,COUT;
always@(A or B or C)
begin
if(A==0 && B==0 && C==0)
begin
S=0; COUT=0;
end

....write all combinations as per truth table…

else if(A==1 && B==1 && Cin==1)
begin S=1; Cout=1;
end
end
endmodule
 Behavioral Modeling Statements:
Multiway Branching
• Similar to switch-case statement in C

• Syntax:
case (<expression>)
alternative1: statement1;
alternative2: statement2;
...
default: default_statement; // optional
endcase

• Notes:
– <expression> is compared to the alternatives in the order
specified.
– Default statement is optional

2010 DSD 59
59
 Behavioural Modelling – Case statement
module mux4bit( i, s, out);
input [3:0] i;
input [1:0] s;
Output reg out;
always @(i or s)
begin
case (s)
2’b00:out=i[0];
2’b01:out=i[1];
2’b10:out=i[2];
2’b11:out=i[3];
default:out=0;
endcase
end
endmodule
 Behavioural Modelling – (case statement)
module FA (input wire A, B, Cin, output reg S,
output reg Cout);
always @(A or B or Cin)
begin
case (A | B | Cin)
3'b000: begin S = 0; Cout = 0; end
3'b001: begin S = 1; Cout = 0; end
3'b010: begin S = 1; Cout = 0; end
3'b011: begin S = 0; Cout = 1; end
3'b100: begin S = 1; Cout = 0; end
3'b101: begin S = 0; Cout = 1; end
3'b110: begin S = 0; Cout = 1; end
3'b111: begin S = 1; Cout = 1; end
endcase
end
 Behavioral Modeling Statements: Loops
• Loops in Verilog
– while, for, repeat, forever
• The while loop syntax:
while (<expression>)
statement;

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 Loops (cont’d)
• The for loop
– Similar to C
– Syntax:
for( init_expr; cond_expr; change_expr)
statement;

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 Loops (cont’d)
• The repeat loop
– Syntax:
repeat( number_of_iterations )
statement;
– The number_of_iterations expression is evaluated only
when the loop is first encountered

integer count;
initial
begin
count = 0;
repeat(128) begin
$display("Count = %d", count);
count = count + 1;
end
end
64
 Loops (cont’d)
• The forever loop
– Syntax:
forever
statement;

– Equivalent to while(1)
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 Generate Statement
• Allows Verilog code to be generated
dynamically at elaboration time before the
simulation begin.
• Convenient when the same operation or
module instance is repeated for a multiple bit
of vector or when certain Verilog code is
conditionally is conditionally included based on
parameter definitions

66
 Example 1: Bitwise XOR for two N-bit buses
module bitwise_xor (out, i0, i1);
parameter N = 32; // 32-bit bus size
output [N-1 : 0] out;
Input [N-1: 0] i0, i1;
// Declared a temporary loop variable. This variable is used only in the evaluation of
generate blocks. It does not exist during simulation of a Verilog design
genvar j;
generate
for (j=0; j<N, j=j+1)
begin: xor_loop
xor g1 (out [j], i0[j], i1[j]); always @ (i0[j] or i1[j] )
OR
out [j] = i0[j] ^ i1[j];
end
endgenerate
endmodule

67
 Example 2: 32-bit binary adder
module prac2_3a #(parameter N = 32)(input [N-1:0] a, b,input c_in,output [N-1:0]
c_out, s);
adder1 h1 (a[0],b[0], c_in, c_out[0], s[0]);
generate
genvar i;
for(i = 1; i< 32; i = i+1)
begin: prac2_3a
adder1 h1 (a[i],b[i], c_out[i-1],c_out[i], s[i]);
end
endgenerate
endmodule
module adder1 ( input a, input b, input c_in, output c_out, output sum);
assign {c_out, sum} = a + b + c_in;
endmodule

68
 Example 3: N-bit look ahead adder
module prac2_lookahead #(parameter N =32)(input [N-1:0] a,input [N-1:0] b, output
[N:0] result);
wire [N:0] C;
wire [N-1:0] G, P, SUM;
genvar i;
generate
for (i=0; i<N; i=i+1)
begin: x1
adder1 h1(.a(a[i]),.b(b[i]),.c_in(C[i]),.sum(SUM[i]),.c_out());
end
endgenerate

genvar j;
generate

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 Cont…
for (j=0; j<N; j=j+1)
begin: x2
assign G[j] = a[j] & b[j]; //Generate (G) Terms: Gj=Aj*Bj
assign P[j] = a[j] ^ b[j]; //Propagate Terms: Pj=Aj+Bj
assign C[j+1] = G[j] | (P[j] & C[j]); //Carry Terms
end
endgenerate

assign C[0] = 1'b0; // no carry input on first

assign result = {C[N], SUM};

endmodule
module adder1 ( input a, input b, input c_in, output c_out, output sum);
assign {c_out, sum} = a + b + c_in; endmodule
2010 DSD 70
70
 Blocks
• Some more constructs on Behavioral
Modeling
– Parallel blocks
– Nested blocks

• Verilog® Scheduling Semantics

2011 DSD 71
71
 Sequential blocks
• Used to group multiple statements
• Sequential blocks
– Keywords: begin end
– Statements are processed in order.
– A statement is executed only after its preceding
one completes.
• Exceptions: non-blocking assignments and
intra-assignment delays
– A delay or event is relative to the simulation time
when the previous statement completed
execution

2011 DSD 72
72
 Parallel Blocks

• Parallel Blocks
– Keywords: fork, join
– Statements in the blocks are executed concurrently
– Timing controls specify the order of execution of the
statements
– All delays are relative to the time the block was entered
• The written order of statements is not important
• The join is done when all the parallel statements are finished

2011 DSD 73
73
 Sequential vs. Parallel Blocks
initial
begin
x=1’b0;
#5 y=1’b1;
#10 z={x,y};
#20 w={y,x};
end

initial
fork
x=1’b0;
#5 y=1’b1;
#10 z={x,y};
#20 w={y,x};
join

2011 DSD 74
74
 Parallel Blocks and Race

• Parallel execution  Race conditions may arise

initial
fork
x=1’b0;
y=1’b1;
z={x,y};
w={y,x};
join

• z,w can take either 2’b01, 2’b10

or 2’bxx, 2’bxx or other combinations
depending on simulator

75
Task and Function
 Introduction
• Procedures/Subroutines/Functions in SW
programming languages
– The same functionality, in different places
• Verilog equivalence:
– Tasks and Functions
– Used in behavioral modeling
– Part of design hierarchy  Hierarchical name

2010 DSD 77
77
 Functions
• Keyword: function, endfunction
• Can be used if the procedure
– does not have any timing control constructs
– returns exactly one single value
– has at least one input argument

2010 DSD 78
78
 Function Declaration Syntax

function <range_or_type> <func_name>;

input <input argument(s)> // at least one input
<variable_declaration(s)> // optional
begin // if more than one statement needed
<statements>
end // if begin used
endfunction

2010 DSD 79
79
 Function Invocation Syntax
<func_name> ( <argument(s)> );

• Example:
function my_not;
input in;
my_not= ~in;
endfunction

reg ni;
initial
ni = my_not(i);

2010 DSD 80
80
 Function Semantics
– much like function in Pascal
– An internal implicit reg is declared inside the
function with the same name
– The return value is specified by setting that
implicit reg
– <range_or_type> defines width and type of
the implicit reg
•<type> can be integer or real
•default bit width is 1

2010 DSD 81
81
 Examples: Parity Calculation
//Define a module that contains the function calc_parity
module parity;
reg [31:0] addr;
reg parity;
// compute new parity whenever address value changes

always@(addr)
begin
parity = calc_parity(addr) // first invocation of calc_parity function
$display (“Parity calculated = %b”, calc_parity(addr)); // second invocation
end

// Define the function

Function calc_parity;
Input [31:0] address;
begin
calc_parity = ^address; // return the XOR of all address bits
end
end function
end module
2010 DSD 82
82
 Tasks

• Keywords: task, endtask

• Must be used if the procedure has
– any timing control constructs
– zero or more than one output arguments
– no input arguments

2010 DSD 83
83
 Task Declaration Syntax

task <task_name>;
<I/O declarations> // optional
<variable and event declarations>
begin // if more than one statement needed
<statement(s)>
end // if begin used!
endtask

2010 DSD 84
84
 Task Invocation Syntax

<task_name>;
<task_name> (<arguments>);

– input and inout arguments are passed into the

task
– output and inout arguments are passed back
to the invoking statement when task is completed

2010 DSD 85
85
I/O declaration in modules vs. tasks
– Both use keywords: input, output, inout
– In modules, represent ports
•connect to external signals
– In tasks, represent arguments
•pass values to and from the task

2010 DSD 86
86
 Task Examples : Use of input and output arguments
//Define a module called operation that contains the task bitwise_oper
module operation
parameter delay = 10;
reg [15:0] A, B;
reg [15:0] AB_AND, AB_OR, AB_XOR;
always@(A or B)
begin
bitwise_oper (AB_AND, AB_OR, AB_XOR); // invoke the task
end

// Define the task

Task bitwise_oper;
input [31:0] a, b ;
output [15:0] ab_and, ab_or, ab_xor;
begin
#delay ab_and = a & b;
ab_or = a | b;
ab_xor = a ^ b;
end
end task
end module
2010 DSD 87
87
 Automatic Tasks and Functions
• Used for re-entrant code
– Task called from multiple locations
– Recursive function calls
• Keyword
– automatic
• Example
function automatic integer factorial;
task automatic bitwise_xor;

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 Differences between...
• Functions • Tasks
– Can enable (call) just – Can enable other tasks
another function (not task) and functions
– Execute in 0 simulation time – May execute in non-zero
– No timing control simulation time
statements allowed – May contain any timing
– At least one input control statements
– May have arbitrary
input, output, or
– Return only a single value inout
– Do not return any value

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Nothing ever becomes real till it is
experienced

John Keats
 Gate Level Modeling
• Usages of gate-level modeling t1
Small designs
Netlist of gates, Logic Synthesis
module fa1bit (a, b, c, s,
cout);
input a,b,c;
output s, cout; t2
wire t1,t2,t3;
xor (t1, a, b);
xor (s, t1,cin);
and (t2, a, b);
and (t3, t1, cin);
or (cout, t2, t3);
t3

endmodule

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 Gate Level Modeling

module mux4_to_1 (output out,

input i0, i1, i2, i3, s1, s0);

wire s1n, s0n, y0, y1, y2, y3;

not (s1n, s1);

not (s0n, s0);

and (y0, i0, s1n, s0n);

and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3);

endmodule

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 Gate Delays in Verilog
❖Rise delay

❖Fall delay

❖Turn-off delay

❖Delay for value change to x

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 Specifying Gate Delay
// Delay of delay_time for all transitions
and #(delay_time) a1(out, i1, i2);

// Rise and Fall Delay Specification.

and #(rise_val, fall_val) a2(out, i1, i2);

// Rise, Fall, and Turn-off Delay Specification

bufif0 #(rise_val, fall_val, turnoff_val) b1 (out, in, control);

Examples:

and #(5) a1(out, i1, i2); //Delay of 5 for all transitions

and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6
bufif0 #(3,4,5) b1 (out, in, control);
// Rise = 3, Fall = 4, Turn-off = 5

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 Min/Typ/Max Delay values
❖Can be separately specified for each delay type
// One delay
// if +mindelays, delay= 4
// if +typdelays, delay= 5
// if +maxdelays, delay= 6
and #(4:5:6) a1(out, i1, i2);

// Two delays
// if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)
// if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)
// if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)
and #(3:4:5, 5:6:7) a2(out, i1, i2);

// Three delays
// if +mindelays, rise= 2 fall= 3 turn-off = 4
// if +typdelays, rise= 3 fall= 4 turn-off = 5
// if +maxdelays, rise= 4 fall= 5 turn-off = 6
bufif0 #(2:3:4, 3:4:5, 4:5:6) a3(out, in, ctrl);
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 Switch level Modeling
module my_nor (a, b, out);
input a,b;
output out;
wire c;

supply1 power1;
supply0 gnd;

pmos (c, pwr, b);

pmos (out, c, a);

Nmos (out, gnd, a);

nmos (out, gnd, b);

end module

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