POLITECNICO DI TORINO

Master’s degree
in Electronic Engineering

Master’s thesis
Analysis and design of half-bridge LLC resonant
power converters

Supervisor Author
Prof. Gianluca Setti Giovanni Giorgino
Co-supervisor
Prof. Fabio Pareschi

Academic Year 2019/2020

Contents

1 Introduction 3

2 The LLC resonant power converter 4

2.1 Resonant conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 LLC overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 The switching procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 At resonance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.2 Above resonance . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.3 Below resonance . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.4 Cut-off mode (zero output current mode) . . . . . . . . . . . . . . 17
2.4.5 Short-circuit load . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Reactive parasitic elements . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6 Power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 First Harmonic Approximation (FHA) 22

3.1 FHA analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.1 Inductive and capacitive modes . . . . . . . . . . . . . . . . . . . 28
3.2 FHA design technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.1 Nominal operation . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.2 Inductor ratio selection . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.3 Zero-voltage switching condition . . . . . . . . . . . . . . . . . . 32
3.2.4 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4 Sequence of switching states approach 37

4.1 Main operating regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.1 Above-Resonance-High-Power (ARHP) . . . . . . . . . . . . . . . 41
4.1.2 Above-Resonance-Low-Power (ARLP) . . . . . . . . . . . . . . . 42
4.1.3 Below-Resonance-High-Power (BRHP) . . . . . . . . . . . . . . . 43
4.1.4 Below-Resonance-Low-Power (BRLP) . . . . . . . . . . . . . . . 44
4.2 Region boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2.1 ARHP-BRHP (Resonance-High-Power, RHP) . . . . . . . . . . . . 45
4.2.2 ARHP-ARLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.3 BRHP-BRLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.4 Zero-Current-Switched (ZCS) . . . . . . . . . . . . . . . . . . . . 48
4.2.5 Resonant-Reversal (RR) . . . . . . . . . . . . . . . . . . . . . . . 48
4.2.6 Map of operating regions . . . . . . . . . . . . . . . . . . . . . . . 49
4.3 Design proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

1
 CONTENTS 2

4.3.1 Turns ratio selection . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.3.2 Inductor ratio selection . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3.3 Remaining components selection . . . . . . . . . . . . . . . . . . 53

5 Modelling and design with parasitic effects 56

5.1 Design at resonance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1.1 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Generalised model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2.1 ZCS from Below-Resonance-Very-High-Power (BRHVP) . . . . . 66
5.2.2 ZCS from Below-Below-Resonance-High-Power (BBRHP) . . . . . 67
5.2.3 BVRHP-BBRHP boundary . . . . . . . . . . . . . . . . . . . . . . 67
5.2.4 BBRHP-BRHP boundary . . . . . . . . . . . . . . . . . . . . . . . 68
5.2.5 BRHP-LP boundary . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2.6 ARHP-ARLP boundary . . . . . . . . . . . . . . . . . . . . . . . 69
5.2.7 ARLP-LP boundary . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.2.8 LP boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2.9 Complete map of regions and operating curve . . . . . . . . . . . . 71

6 Conclusion 74

Appendix A MATLAB scripts 75

A.1 FHA design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
A.2 ARHP steady-state analysis (lossless LLC) . . . . . . . . . . . . . . . . . . 77
A.3 RHP border (lossy LLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
A.4 Proposed design (lossy LLC) . . . . . . . . . . . . . . . . . . . . . . . . . 80
A.5 ZCS from BVRHP (lossy LLC) . . . . . . . . . . . . . . . . . . . . . . . . 82

References 86
Chapter 1

Introduction

The field of power electronics mainly covers the control and the conversion of electric
power. In order to fulfil these tasks, solid-state devices of power electronics (power diodes,
thyristors, power MOSFETs, IGBTs, etc..) generally differ from the ones typical of analog
and digital electronics (usually CMOS-based): this is due to the fact that operating voltages,
currents and even frequencies are very different in these two fields of electronics. In fact,
while analog and digital electronics deal with low levels of power (generally, currents less than
some amperes and voltages less than some tens of volts) with the objective of transmitting
some information, power electronics usually handles higher or even much higher (in the case
of industrial applications) power levels, which need properly suited devices. One of the most
typical power application is the AC-DC converter (rectifier), which is required for correctly
supplying many consumer electronic devices (such as TVs, PCs, battery charges, etc...),
starting from the conversion of mains electricity. Other power conversion systems include
DC-AC, AC-AC and DC-DC devices. In particular, one of the possible DC-DC converters,
namely the LLC one, is the main focus of the following chapters. Its many benefits and
few drawbacks result in an increasingly use of this converter in many applications, such as
flat-panel TVs, ATX power supplies, small form factor PCs, high-efficiency solar PVs [1]
etc... However, the design of the LLC converter is unfortunately very hard to be performed
accurately due to its strong nonlinearity and to the reactive effects of the system. The thesis
focuses on analysis and design techniques, oriented towards the LLC converter (rather than on
control techniques), trying to give a detailed analysis and an organic presentation of the state-
of-the-art knowledge of the LLC converter operation. Moreover, it is shown how the existing
design methods try to exploit different approaches for the optimal choice of the components.
Therefore, state-of-the-art methods are compared making uniform as much as possible the
descriptive notations, in order to obtain a better overall understanding and to underline the
main advantages and drawbacks of each approach. Finally, the last contribution of this thesis
is the attempt to go a little further by exploiting an accurate description of the converter
to analyse and design it, considering the effect of parasitic elements, e.g. resistances. In
particular, the developed analysis and design of the converter are carried out through several
MATLAB scripts, comparing the obtained results with the ones extracted from LTspice
simulations of the converter schematic.

3
Chapter 2

The LLC resonant power converter

2.1 Resonant conversion

Two distinct family of solutions exist in power electronics when the driving of a load
is required and they, respectively, resort to linear circuits and switching ones. The main
problem of linear topologies is that generally there is a high power loss across the transistor
(e.g. working as a current generator) which is used to regulate the output load current: in
fact, in all these circuits, the transistors work in saturation mode thus being characterised by
a large voltage drop between the drain and source terminals.

Figure 2.1: Circuit for current control through the use of a MOSFET working in saturation

This issue practically limits the maximum output power that can be handled by this class of
circuits, which can achieve low levels of efficiency. Switching topologies, instead, exploits
power switches (generally MOSFETs) able to cyclically turn on and off at high frequencies
(kHz-MHz) in order to fix the mean value of the load current, which can then be modulated
through e.g. the duty cycle of the command signal applied to the gate of the transistor.

4
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 5

Figure 2.2: Switching circuit for the driving a resistive load

This solution drastically reduces power losses across transistors, since they are used in triode
region and therefore their drain-to-source voltage is negligible (ideally zero).
One of the possible applications of switching configurations is in circuits of static conversion
like DC-DC converters. These switching converters are characterised by high conversion
efficiency (usually higher than 80%) since power losses are confined only to switching tran-
sitions, on-state resistance of power transistors and parasitic resistances of reactive elements.
It is important to underline that every DC-DC converter can be used as a building block for a
switching voltage regulator, i.e. a circuit which keeps constant the output voltage despite the
variations of input voltage, load current, environmental parameters (e.g. temperature), etc...
Of course, in order to obtain an actually working voltage regulator, a DC-DC converter has
to be integrated with a control circuit [2] able to modulate the duty cycle or the frequency
of the signal driving the power MOSFETs, depending on the measurement of some "error"
signal (e.g. the difference between the output voltage and a reference voltage).

Figure 2.3: Block diagram of a voltage regulator

 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 6

The design of this control circuit is critical as well as the one of the converter and it is rather
difficult because of the fact that switching converters are time-varying non linear circuits.
Finally, switching regulators can be embedded in more complex systems in order to build
switched-mode power supplies (SMPS).
Focusing on DC-DC converters, they can be classified as follows [3], depending on their
architecture and on their working principle:

Figure 2.4: Classification of DC-DC converters

As clear from the figure above, many different families of DC-DC converters can be found in
literature, each characterised by different topologies and characteristics.
The class of soft-switching (resonant) converters (SSCs), in particular, has received more
and more attention and interest in nowadays electronics. This is due to the fact that these
converters are able to overcome the limitations which are typical of the converters working in
hard-switching mode. This last group of circuits make use of switching devices to increase the
conversion efficiency (as in the case of soft-switching converters) but they are characterised
by non-negligible power losses associated to the switching transitions which can lead to
limited values of efficiency. A reduction of the power losses can be obtained by the use of
appropriate circuits, e.g. snubbers that reduce the stress on power switches or simply by
choosing devices able to perform with lower switching time: the former solution is able to
effectively limit switch losses but also implies a constraint on the maximum frequency at which
the converter can work; the latter one, instead, causes an increase of time-derivative voltages
and currents, eventually resulting in a higher electromagnetic interferences (EMI). In order to
surpass the frequency limitations and further reduce power losses, soft-switching converters
are used: in particular, the idea is to turn on and off switching devices when either their
voltage or current is zero (Zero-Voltage-Switching, ZVS, and Zero-Current-Switching, ZCS)
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 7

and, possibly, with zero (low) time-derivative (Zero-Voltage-Derivative-Switching, ZVDS,

and Zero-Current-Derivative-Switching, ZCDS). Of course, in practical applications, zero
voltage/current actually means a very low/low value compared to the other voltages/currents
characterising the circuit.

Figure 2.5: Current and voltage waveforms of hard-switching and soft-switching

The benefits of a soft-switching topology (with respect to hard-switching ones) are several
and are summarised in the following list:

• absence of Miller plateau (which means less energy required to drive power switches);

• lower noise;

• lower EMI (smoother waveforms);

• lower switching losses;

• higher operating frequencies (resulting in a reduced components size, i.e. higher power
densities);

• increased efficiencies at higher frequency;

SSCs are very often also named Resonant Power Converters (RPCs), since, in order to
obtain soft-switching (either ZVS or ZCS), resonant circuits have to be used. RPCs are,
in turn, divided in two more sub-categories: resonant tank converters and resonant switch
converters (also called quasi-resonant converters, QRCs). In particular, QRCs are obtained by
substituting the "simple" power switches of hard-switched converters with resonant ones [4],
which consist of one switch, one diode and one resonant LC network, in a basic configuration.
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 8

Figure 2.6: Example of a resonant switch

This last solution allows the power switches to reach the ZVS or ZCS condition thus bringing
all the benefits previously discussed.
Resonant tank converters are instead modelled as 2-stage networks: the first stage is a DC-AC
resonant inverter (which consists of a control switching network and a resonant tank) while
the second one is made of a high-frequency rectifier followed by a low pass filter (LPF).

Figure 2.7: General block scheme of a resonant tank converter

In particular, the switching network is typically a half-bridge or full-bridge configuration

able to generate a square wave voltage from a DC input. The generated square wave, in turn,
becomes the input of the resonant tank (i.e. a circuit made of reactive elements based on a
LC configuration), generally tuned to the fundamental component of the square wave voltage
in order to produce a low-harmonic content AC voltage (e.g. sinusoidal). Then, in most
cases, the rectifier stage is coupled to the inverter through a transformer to guarantee galvanic
isolation required by safety regulations: in these cases, the rectifier devices are usually
referred to as "secondary rectifiers" because they are located at the secondary side of the
transformer. The rectification is usually achieved through the use of power diodes (full wave
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 9

or bridge rectifier) or more complex switched circuits (active or synchronous rectification)

and it is useful to convert the AC voltage from the resonant network to the output DC voltage.
Moreover, rectifiers are needed to provide DC power to the load. As usual, the power flow
from input to output can be controlled by the switch network either by changing the frequency
of the square wave voltage or its duty cycle.
Resonant tank converters can be divided in three main groups: series load resonant converters
(SLRCs), parallel load resonant converters (PLRCs) and hybrid (or series-parallel) load
resonant converters (SPLRCs).

Figure 2.8: Basic series and parallel resonant converters

This very last group of converters (SPLRCs) is able to combine the principal advantages of
SLRs and PLRs (i.e. limited short-circuit currents and constant voltage generation) [5]: that
is the very reason they are so much studied and analysed. Two main hybrid resonant converter
topologies can be found: the LCC converter and the LLC one, which is, in the end, the focus
of this thesis work.

Figure 2.9: Basic hybrid load resonant converters

In order to get a complete look on resonant conversion, not only advantages should be
highlighted but also weaknesses. Indeed, many problems affect the resonant conversion
technique: first of all, the design can be optimised only for a specific operating point and
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 10

not for wide voltage/frequency/load variations; high (or even very high) levels of current can
flow into the resonant network when load resistance is very low; efficiency rapidly drops at
low output power; sinusoidal or quasi-sinusoidal waveforms yield higher peak values than
corresponding triangular ones (typical of hard-switching converters), leading to an increase
of conduction losses (i.e. losses across parasitic resistances); the control technique is usually
based on a frequency modulation (PFM) rather than a duty-cycle modulation (PWM) and
the range of involved frequencies can be very wide; last but not least the complexity of the
analysis (and therefore of the design) is substantial with respect to linear and hard-switched
solutions.

2.2 LLC overview

Among all the existing resonant converters, the LLC topology, especially in its half-bridge
implementation, has experienced growing popularity in the last decades [6]. The schematic
of the circuit (without the presence of the control circuitry) is shown in Figure 2.10.

Figure 2.10: LLC circuit schematics

As highlighted in the figure above, for what concerns the rectifier stage, a full-wave (centre-
tapped) rectifier is preferred for low-voltage/high-current applications, while a bridge rectifier
can be the optimum choice in high-voltage/low-current applications. In fact, in the first case,
there is only the voltage drop of one power diode from the secondary windings of the
transformer to the output load whereas, in the second case, where the voltage drop across
two diodes is not a significant problem, the use of a bridge configuration allows to reduce
overall size of the device (four diodes and two windings generally prove to be less bulky than
two diodes and three windings). For the sake of completeness, it must be said that some
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 11

implementations even exploit synchronous rectifiers instead of power diodes in order to better
the LLC converter performances [7].
As in all the other resonant converters, also in the case of the LLC, the typical cascade of
blocks can be noticed:

Figure 2.11: Detailed blocks cascade in the case of LLC converters

Despite its increasing use, the main problem regarding the LLC converter is still the absence
of precise information about the way it works and, as a consequence, the lack of a systematic,
accurate and general design technique. The reasons behind this fact are to be traced mainly to
the intrinsic nature of the converter: in fact, another possible classification of the LLC is that
of a multi-resonant converter [8]. This class of converters can be considered a particular case
of the RPCs, since it includes circuits characterised by more than one resonant frequencies
(i.e. where the resonant tank is made of three or more reactive elements). In the specific
case of the LLC, given the fact that the resonant circuit consists of two inductors and one
capacitor, there are two resonant frequencies associated to the converter:

1
fR1 = √ (2.1)
2π Lr Cr
1
fR2 = p (2.2)
2π (Lr + Lm )Cr
The first one, i.e. the main resonance frequency (fR1 ), is related to the condition of secondary
winding(s) conducting while the second one, i.e. the second (or lower) resonance frequency
(fR2 ) corresponds to the condition of secondary winding(s) not conducting (i.e. open circuit).
Because Cr and Lr characterise the main resonance frequency, they are referred to as resonant
capacitor and resonant inductor. It is apparent from eq. (2.1) and (2.2) that fR1 > fR2 :
in particular, the distance between the two frequencies depends on the inductance ratio
lm = Lm /Lr , as shown in the following equation:
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 12

fR1 p
= 1 + lm (2.3)
fR2
Therefore the inductance ratio, which is typically set above one, can be a key design parameter
since it fixes the ratio between the main resonance frequency and the second one.
Focusing on the switch network, it is interesting to notice that the input signal to the half-bridge
(composed by a high-side and a low-side power MOSFETs) is almost always characterised
by a 50% duty cycle (apart from special cases, e.g. [9]): this is due to the fact that only
this duty cycle is able to equalise, under all operating condition, the electrical stress on the
secondary rectifiers (both in terms of reverse voltage and of forward conducting current)
since each rectifier carries half of the total output current. Actually, to be precise, a small
dead-time is inserted between the on time of the high-side MOSFET and the one of the
low-side one: this is of critical importance for the correct (and efficient) behaviour of the
converter. Another important aspect to be observed is that the energy-taking (from the input)
phase covers a little portion of the whole period in the case of a half-bridge LLC: this can
result in poor power handling capability, if the input voltage is low. For this reason, the
half-bridge switch network is usually exploited in high input voltage applications (e.g. with a
PFC front-end, which provides a 400 V input bus [10]). This limitation can be overcome by
using a full-bridge configuration which then allows to improve the operation of the converter.
Moving to the resonant tank, it is useful to point out that the capacitor Cr does not only
contributes to the main resonance frequency but it also works as a DC blocking capacitor. In
fact, writing the Fourier series expansion of the input square wave excitation (applied to node
HB), i.e the bridge leg voltage:
∞
Vin 2Vin X 1
VHB = + sin(2πnfsw t) (2.4)
2 π n=1 n

it is clear that the DC component is equal to Vin /2. In addition, at steady-state (namely periodic
waveforms) the average voltage across inductors is zero which leads to the conclusion that
the average voltage across the resonant capacitor is Vin /2. One of the advantages of the
LLC topology comes from the use of the so-called "magnetic integration" [10]: through this
technique, not only the ideal transformer but also Lr and Lm can be implemented by a single
physical device (a "real" transformer), thus helping to further decrease the converter size. In
particular, this is probably the main benefit of the LLC configuration over the LCC one. This
is also one of the reasons that lead to the adoption of the all primary referred (APR) model
of the transformer in the circuital scheme of the LLC converter, where Lr represents the
primary leakage inductance, Lm stands for the magnetising component and there is an ideal
transformer (fully described by the number of turns) which regulates the coupling between
primary side and secondary side.
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 13

Figure 2.12: APR model of the lossless transformer

Actually, the APR model is derived from the complete lossless physical model of the trans-
former:

Figure 2.13: Physical model of the lossless transformer

Of course, it is possible to extract the physical parameters of the actual transformer (Fig-
ure 2.13) from the "artificial" ones of the APR model (or vice versa), by means of the
following relationship:

Lr + Lm = LL1 + Lµ (2.5)
with the additional assumption of magnetic circuit symmetry, meaning:

LL1
LL2a = LL2b = (2.6)
n2t
from which the physical number of turns can be found:
r r
Lm + Lr 1
nt = n =n 1+ (2.7)
Lm lm
Fortunately, it is possible to find many existing transformer structures where the magnetic
symmetry is respected (e.g. the ferrite E-core plus slotted bobbin assembly, with an air gap
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 14

between the windings [10]). It is useful to point out that secondary leakage inductances
are undesired parasitic elements and their effect will be discussed in one of the following
sections.
Moving to the rectifier stage, it is useful to underline that, in the LLC converter, also the
soft-switching of the secondary rectifiers is achieved, in terms of ZCS (both at turn on and
turn off): moreover and more importantly, this property does not depend on the design or on
the operating condition.
Finally, it is useful to point out that, when closed in a loop for the control of the output
voltage, the LLC allows to increase the level of power by reducing the switching frequency
and vice versa (negative feedback), during normal and correct operation.

2.3 The switching procedure

Power MOSFETs are an optimum fit to implement power switches in the case of the LLC
switch network because of body diodes and parasitic capacitances [11]. In fact, these two
additional devices are naturally embedded into power MOSFETs and they prove particularly
useful during the dead-time. Indeed, half-bridge resonant LLC also belongs to the family of
resonant-transition converters, i.e. devices where the driving of power switches is such that it
produces an excitation of the resonant tank which then offers a zero-voltage drain-to-source
condition at their turn on, thus achieving the already mentioned ZVS [8]. In particular, this
condition is met by inserting a small dead-time between the conduction of power MOSFETs:
therefore, in this case, the dead-time does not simply avoid the conduction overlap of the
switches (cross-conduction) but it plays a much more important role.

Figure 2.14: Reference scheme for the study of the switching mechanism

In order to better analyse what happens during the dead-time and how ZVS can be achieved,
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 15

it is convenient to suppose that initially the high-side MOSFET (Q1) is on and the low-side
one (Q2) is off (Figure 2.14). Let’s now consider the instant in which Q1 turns off and let’s
suppose that at this point the current is entering the tank circuit (positive current); since M1 is
turning off, its drain-to-source current is rapidly decreasing down to zero; in addition to that,
Q2 is still off because of the dead-time; the tank current, however, keeps on flowing with little
changes because of the inductance of the resonant tank (Lr ) which acts as a current flywheel.
The electrical charge needed to maintain this current flow comes initially from CHB , which
is initially charged at Vin and that therefore starts to discharge. The capacitor CHB simply
models all the capacitive contributions at node HB. In this phase, it is as if the inductive
portion of the resonant tank resonates with CHB rather than with Cr (this is the concept of
resonant transition). Given the fact that the value of the tank current (Ir ) at Q1 turn off is large
enough, the voltage at node HB (VHB ) is able to decrease, within the dead-time, until the
turn on of the body diode of Q2 (DQ2), which clamps VHB to −VF (where VF is the forward
voltage of the body diode): from this instant on, the tank current continues to flow through
DQ2 until the end of the dead-time. Finally, when Q2 turns on, its on-state resistance shunts
the body diode. Of course, considering the Q2 turn off transition, the reasoning is similar
since in that case the only difference is that the tank current is negative and the starting value
of VHB is zero. To sum up, it is possible to observe that both Q1 and Q2 turn off with their
VDS equal to VF , which is a voltage negligible with respect to Vin , thus achieving ZVS. As
a consequence, the turn on transition of the power MOSFETs is performed with negligible
dissipation but, on the other hand, the turn off is instead characterised by a non-negligible
power dissipation (since in that case VDS = Vin ). Stemming from all these considerations,
it can be concluded that a necessary condition for obtaining soft-switching in terms of ZVS
at the turn on of the transistors is that the tank current is positive whenever VHB = Vin and
negative when VHB = 0. This condition can be achieved only if the tank current lags the
bridge leg voltage VHB . It is useful to highlight that this phase lag is a typical condition in
case of inductors. Of course, this is only a necessary condition: the sufficient one is that
the inductive energy level associated with the resonant tank (which depends on the resonant
current) must be higher than the capacitive energy level of CHB (which is a function of Vin )
so that the capacitor CHB can be completely discharged before the end of the dead-time. In
fact, in order to achieve ZVS at turn on, the transition of the node HB has to be completed
within the dead-time.

2.4 Main operating modes

The LLC converter is characterised by a considerable number of different operating modes
[12], principally due to its multi-resonant nature: depending on the switching frequency (fsw ),
on the resistive load and on the characteristics of the resonant tank, the secondary rectifiers
can always conduct (Continuous-Conduction-Mode, CCM) or there can be a finite amount
of time in which none of them is conducting (Discontinuous-Conduction-Mode, DCM). In a
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 16

lossless LLC (as the on the depicted in Figure 2.11), the CCM condition is characterised by the
fact that the inductance Lm is always shunted by the load resistance reflected to the primary
side (which has the effect of excluding the magnetising inductance from the resonance) while
in a DCM condition, there are time intervals in which Lm becomes an active part of the
resonance. Given the multi-resonant nature of the converter, it is rather difficult to get a
comprehensive picture of all the possible operating modes. Nonetheless, in order to better
understand and to put more in detail the main differences in the behaviour of the converter
working in the principal operating modes, it is useful to analyse the the main characteristics
of an LLC:

Figure 2.15: LLC reference schematic for the analysis of main operating regions

The figure above shows the schematic of LLC converter (with a full-wave rectifier), that
can be therefore simulated (e.g. through a .tran simulation performed in LTspice) under
difference frequency and load conditions, imposing typical values of the components.

2.4.1 At resonance
Starting from resonance (i.e. fixing the switching frequency to fR1 and having a sufficient
level of power), it is possible to notice that the operation is always CCM which means that
there is always one diode conducting. This also means that the voltage across Lm is constant,
resulting in a triangular current flowing on it. Another important consequence of this fact is
that the value of Lm does not influence the behaviour of the waveforms at resonance (outside
the dead-time) in any significant way because it is always ac-shorted. On the other hand, the
presence of Lm is of paramount importance: in fact, the circuit can be seen composed by an
LC tank supplying an RL load (where R is represented by the load resistance reflected to the
primary side and L is the magnetising inductance), whose effect is the phase-shifting between
current and voltage, necessary to achieve ZVS. Without Lm , ZVS could not be reached, not
even at resonance because in an LC circuit with a purely resistive load, voltage and current
are exactly in phase. The most important relationship characterising the resonance region, in
the ideal case, is the following:
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 17

Vout 1
M (fR1 ) = = (2.8)
Vin fsw =fR1 2n
which ties the conversion ratio (M = Vout /Vin ) with the turns ratio (n). Of course,as usual in
converter applications, as the load resistor value is increased, the CCM operation gradually
transforms into DCM.

2.4.2 Above resonance

In this operating mode, which characterises the converter for frequencies above fR1 , CCM
operation progressively turns into DCM as the output power is reduced and/or the frequency
is increased. Furthermore, The conversion ratio is modified with respect to the resonance
value: in particular,

Vout 1
M (fsw > fR1 ) = < (2.9)
Vin fsw >fR1 2n
and the operation of the LLC is referred to as step-down or buck-like, since there is a
progressive decrease of the conversation ratio with respect to its value at resonance.

2.4.3 Below resonance

When decreasing the frequency below fR1 , the converter enters the most risky operating
mode, since only DCM is possible and soft-switching can be more easily lost. The conversion
ratio is again modified but in a different direction, meaning that

Vout 1
M (fsw < fR1 ) = > (2.10)
Vin fsw <fR1 2n
and therefore the LLC is characterised in this region by a step-up or boost-like behaviour.
To be precise, this is true for the switching frequencies that can be actually applied to the
converter (i.e. that ensure ZVS): instead, when moving to deep below resonance regions, the
conversion ratio starts to decrease, just like above resonance.

2.4.4 Cut-off mode (zero output current mode)

This region is entered when an open circuit load is taken into account: in that condition,
the current flowing into secondary rectifiers is zero throughout the whole switching cycle. The
LLC is ideally able to regulate the output voltage even in cut-off mode at a finite frequency
(with proper design of Lm ) and this is often considered one of the main benefits of this
topology. Of course, this property actually means that the LLC converter is able to control
the output voltage even at low output power levels (i.e. with high resistive loads).
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 18

Figure 2.16: Circuit schematic in the case of open-circuit load

2.4.5 Short-circuit load

In this operating mode, Lm is shunted by the short-circuit load reflected back to the
primary side: this means that the LLC actually degenerates into a simple LC circuit. As a
consequence, the output current will simply be n times the input current. Two major issues
afflict this operating region: very high current levels and likely loss of ZVS. In order to limit
these problems, overcurrent protection (OCP) circuits are used: they also allow to avoid too
high heat dissipation and malfunctioning of the whole system.

Figure 2.17: Circuit schematic in the case of short-circuit load

 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 19

2.5 Reactive parasitic elements

Many different reactive parasitic contributions can be found in the circuit. For example,
the so-called stray capacitance (depicted in Figure 2.18), which is connected between node
HB and ground, includes capacitive effects between the power MOSFETs case and the heat
sink, the intra-winding capacitor of the resonant inductor, etc.. This parasitic capacitance is
very important especially together with other capacitive contributions related to the non linear
time-varying gate-to-drain and drain-to-source capacitors (CGD and CDS ) of the high-side
and low-side power switches. In fact, as far as voltage variations of node HB are concerned,
CGD and CDS are effectively in parallel, which allows to write an overall equivalent expression

Coss1,2 = CGD1,2 + CDS1,2 (2.11)

In particular, this capacitors can be modelled through an effective constant value, depending
on the switching conditions (as shown e.g. in [13]). These equivalent capacitors are present
as well in Figure 2.18 and it can be noticed that also Coss1 , Coss2 and Cstray are in parallel,
when considering voltage variations at node HB. This consideration allows to further lump
them all together in a single effective capacitive contribution, useful to analyse the circuit in
terms of the soft-switching:

CZV S = CHB = Coss1 + Coss2 + Cstray (2.12)

Figure 2.18: Capacitive contributions at node HB

This lumped contribution (CZV S ) is usually referred to as capacitance of the midpoint of the
half bridge LLC: this capacitance is the very reason why the transition of this midpoint node
(HB) requires energy and therefore takes a finite amount of time to complete.
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 20

Another reactive parasitic element consists of the contributions coming from the distributed
capacitance of the transformer windings and junction capacitances of secondary rectifiers
(reverse-biased power diodes): in combination with the windings inductances, these addi-
tional capacitive elements give rise to the so-called transformer «self-resonance» effect. In
fact, the contributions of all this parasitic capacitance can be modelled with a single capacitor
Cp connected in parallel to Lm.

Figure 2.19: Equivalent schematic of a transformer including self-resonance capacitor

Starting from this model, it can be easily seen that the resonant tank circuit turns from a
third-order reactive network (LLC) to a fourth-order one (LLCC): this modification leads to
the origin of a third resonance frequency, namely fLSR , which is higher than fR1 ). It is very
important to stress the influence of this effect. In particular, when fsw  fLSR , the impact of
Cp is negligible while for f > fR1 and for high enough load impedances, its effect becomes
relevant eventually resulting in reversing the output power vs frequency relationship. In
closed-loop operation, the result of the fact that the power increases with frequency is the
so-called «feedback reversal» (i.e. the negative feedback turns into a positive), ultimately
meaning the loss of control of the output voltage. Therefore, the converter must always
work with fsw  fLSR : this effect sets the practical upper limit to the maximum operating
switching frequency of the LLC converter.
Finally, focusing on secondary leakage inductances, it is worth to underline that they decrease
the voltage actually available at the secondary side of the transformer. Furthermore, another
drawback shows up when the LLC converter is exploited to drive more loads, through the use
of more secondary sides of the transformers. In all of these multi-output LLC converters,
cross-regulation between the different outputs is negatively affected because of decoupling
effect operated by the secondary leakage inductors.

2.6 Power losses

In order to get a more accurate and realistic analysis of the converter operation, it is
certainly very useful to study and design the LLC behaviour considering parasitic resistive
 CHAPTER 2. THE LLC RESONANT POWER CONVERTER 21

components. In fact, despite the fact that switching losses are very much reduced in the
case of the LLC (thanks to soft-switching), conductive power losses may be still present and,
since they are the main cause of efficiency drop, it is important to understand where they
are located, what is their effect and how they can be reduced. Several factors of conduction
power losses can be found in the physical LLC circuit.
In particular, starting with conduction losses at the primary side, it is possible to list the
following contributions:

• on-state resistance of the power MOSFETs (Ron );

• equivalent series resistance (ESR) of Cr ;

• high frequency copper losses associated to the primary side of the transformer.

Moving to the secondary side of the transformer, other contributions to the overall conduction
losses can be found:

• parasitic resistive losses corresponding to the secondary side of the transformer;

• power diodes series resistances;

• output capacitor resistive effects.

Of course, measured efficiencies of the LLC converter are in any case high/very high, being
in the range of about 90 ÷ 97 % [10].
Chapter 3

First Harmonic Approximation (FHA)

3.1 FHA analysis

The First (or Fundamental) Harmonic Approximation (FHA) is the most common and easy
model which is typically used to obtain a fast (even though strongly approximated) analysis of
any resonant power converter [14]. In particular, it can be successfully exploited whenever the
input-to-output power transfer is almost completely dependent on the fundamental harmonic
component of currents and voltages of the circuit. In the specific case of the LLC converter, as
a consequence of the frequency-selective behaviour of the resonant tank, the FHA modelling
approach can be exploited, thus neglecting all the higher harmonics of the waveforms ([5] and
[10]). This simplification also allows to analyse the circuit in terms of the impedances and
transfer functions. The FHA gives quite accurate results for operating points characterised
by a fsw ≥ fR1 and CCM operation (i.e., typically, high power levels). On the other hand,
its accuracy decreases moving to DCM operation and in particular moving the switching
frequency below resonance. Furthermore, many details of circuit operation are not addressed
in any way by the FHA, e.g. the ZCS of the secondary rectifiers. One of the main problems
of these approximations is that it is not able to provide a sufficient condition for ZVS across
the whole operating curve of the converter.
In order to show how the converter can be modelled through the FHA, it is convenient to start
from the ideal schematic of the LLC (show in the following figure), assuming zero dead-time:

Figure 3.1: LLC starting schematic for the FHA analysis

Since power MOSFETs are driven alternatively with a 50% duty cycle, the voltage at the
input of the resonant tank is a square wave (as already mentioned in the previous chapter),
whose Fourier series expansion is represented in the following equation:

22
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 23

∞
Vin 2Vin X 1
Vinv = + sin(2πnfsw t) (3.1)
2 π n=1,3,5 n

Of course, Vinv = VHB but the subscript "inv" specifies, in this case, that this is the voltage
at the input of the inverter stage. As can be seen in the equation above, the fundamental
component of Vinv is

2Vin
VinvF HA = sin(2πfsw t) (3.2)
π
which is, as expected, a function of the switching frequency (controlling the power MOS-
FETs). In particular, its root mean square (RMS) value is important for the following
computations and it is equal to:
√
2
VinvF HA,RM S = Vin (3.3)
π
Focusing on the secondary side, it can be noticed that also the resulting voltage across the
output rectifier is a square wave, whose Fourier expression is
∞
4Vout X 1
Vrect = sin(2πnfsw t − ψ) (3.4)
π n=1,3,5 n

neglecting the voltage drops across the power diodes. ψ represents the phase shift with
respect to Vinv . As in the case of inverter input voltage, also for Vrect , it is useful to highlight
its fundamental component:

4Vout
VrectF HA = sin(2πfsw t − ψ) (3.5)
π
whose RMS value is
√
2 2
VrectF HA,RM S = Vout (3.6)
π
Moreover, the current flowing into the secondary rectifiers is quasi-sinusoidal (actually it is
a sine wave plus a linear curve) and, in the frame of the FHA, it is approximated as well with
its fundamental component (which is in phase with VinvF HA ):

πIout
IrectF HA = sin(2πfsw t − ψ) (3.7)
2
where the RMS value is represented by:

πIout
IrectF HA,RM S = √ (3.8)
2 2
Due to the zero phase lag between Vrect and Irect , the rectifier stage can be simply modelled
by an effective resistive load, equal to:
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 24

VrectF HA 8
Ro,ac = Ro,rectF HA = = 2 Rout (3.9)
IrectF HA π
Therefore, as a consequence of all this chain of definitions and approximations, the circuit
can be represented with the following two-port model:

Figure 3.2: Linearised model of the LLC under the FHA

where the input current to the resonant tank (i.e. the resonant current) is denoted as Irt , the
voltage at the input of the inverter as Vi,F HA and the rectifier voltage as Vo,F HA . The advantage
of analysing the approximate circuit shown in Figure 3.2 over the complete one contained in
Figure 3.1 is that the former is fully linear: in particular, it is driven by an effective input sine
voltage source and supplies an effective resistive load. Moreover, the resonant tank can be
easily analysed in terms of input impedance (Zintank ) and voltage forward trans-characteristic
(FTC), Htank :

1
Zintank = Vi,F HA /Irt = + sLr + n2 Ro,ac //sLm (3.10)
sCr

1 n2 Ro,ac //sLm
Htank = Vo,F HA /Vi,F HA = (3.11)
n Zin
The FTC of the tank (also referred to as H(jω)) is particularly important since its absolute
value can be related to the RMS values of Vrect and Vinv and therefore, indirectly, to Vout and
Vin . Moreover it is possible to write the input-to-output DC-DC voltage conversion ratio as
a function of the magnitude of this FTC:

Vout H(j2πfsw )
M (f sw) = = (3.12)
Vin 2
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 25

and, considering the normalised conversion ratio (also named "voltage gain", defined as:

M (fsw ) Vout
m(fsw ) , = 2n (3.13)
M (fR1 ) Vin
the relationship is simply modified as:

m(fsw ) = n H(j2πfsw ) (3.14)

The following idea is to compute the expression of the modulus of H(jω) with the objective
of obtaining the normalised conversion ratio (m) as a function of the switching frequency
and other circuital parameters. To do that, the following set of definitions can be exploited:

• resonance frequency,
1 1
fr = = fR1 = √ (3.15)
Tr 2π Lr Cr

• normalized switching frequency,

fsw
fn = (3.16)
fr

• characteristic impedance,
r
Lr
Z0 = (3.17)
Cr

• quality factor of the loaded filter composed by the resonant tank and the load resistance
moved to the primary side (i.e. in parallel with Lm ),

Z0
Q= 2
(3.18)
n Ro,ac

• inductance ratio,

Lm
lm = (3.19)
Lr
Combining (3.14) with these definitions, it is possible to find the following expression of the
normalized conversion ratio:

1
m(fn , lm , Q) = s 2  2 (3.20)
1 1 1
1+ − + Q2 fn −
lm lm fn2 fn
Once the explicit expression of m is obtained, it is useful to plot it (e.g. through MATLAB)
versus fn and for different values of Q, fixing a certain inductance ratio (lm ):
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 26

Figure 3.3: Voltage gain characteristics for different values of Q and lm = 10

Figure 3.4: Voltage gain characteristics for different values of Q and lm = 5

 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 27

Figure 3.5: Voltage gain characteristics for different values of Q and lm = 1.1

The analysis of the normalised conversion ratio allows to understand how the regulation of
the converter output voltage is achieved by changing the switching frequency in response to
e.g. a increase/decrease of the input voltage. In fact, the effect of varying the frequency is a
variation of the input-to-output voltage gain and therefore it is evident how the output voltage
can be kept (almost) constant despite the variations of the input voltage. Of course, the higher
the input voltage swing, the wider the frequency range required to restore the desired output
voltage. Moving to the influence of the load resistance on the regulated output voltage, the
most notable aspect that can be deduced from all the previous plots is the presence of a
load-independent point corresponding to the resonance frequency (i.e. fn = 1), where the
normalized conversion ratio is obviously equal to 1. Another important remark on the figures
is that, once Q (i.e the load resistance) and lm are fixed, the voltage gain initially increases with
frequency until it reaches a peak, after which it starts decreasing with a further frequency rise.
The shape of the curves therefore follows a bell-like behaviour. Fixing the inductance ratio
and varying the quality factor generates instead a family of curves characterised by different
peaks (of m) and different frequencies associated with these peaks: in particular, a reduction
of Q (i.e. an increase of the load resistance) causes a left-shift and a rise of the m peak value,
eventually leading (for a zero quality factor) to an infinite m value in correspondence of the
lower resonance frequency (fR2 ). The position of this second resonance frequency depends,
in turn, on the inductance ratio, as demonstrated by the following equation:
r
1
fn2 = fR2 /fr = (3.21)
lm + 1
Therefore, the effect of decreasing lm is a horizontal shrink of all the curves towards the
resonance frequency (fr ) and a resulting increase of the peak values of the voltage gain.
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 28

3.1.1 Inductive and capacitive modes

Understanding the behaviour of the conversion ratio is, of course, very important to
obtain a clearer picture of how a frequency change can vary the input-to-output relationship
but it is not enough. The key idea which allows a more comprehensive analysis of the
converter operation is the study of the input impedance of the resonant tank. In fact, the
LLC is normally operated in the region where the input impedance of the resonant tank has
an inductive behaviour (i.e. it increases with fsw ): this means that the power flow can be
controlled by changing the operating frequency so that a higher output power is obtained by
reducing the frequency and vice versa. This is due to the fact that soft-switching must be
ensured in every operating point and in order to reach a ZVS the tank current must lag the
impressed voltage which is, as already mentioned, a behaviour typical of inductors. In other
words, ZVS occurs only if the tank input impedance is inductive (necessary but not sufficient
condition). For this reason, it is very useful to find the boundary (in the conversion ratio vs
frequency plot) between the so-called inductive region (i.e. where the input impedance is
characterised by an inductive nature) and the so-called capacitive region (i.e. where the input
impedance follows a capacitive behaviour and ZVS cannot be certainly ensured).
The first step is to write the normalized input impedance Zn as a function of fn , lm and Q,
starting from the expression contained in (3.10):

Zin jfn 1 − fn2

Zn (fn , lm , Q) = = + (3.22)
Z0 1/lm + jfn Q jfn
By manipulating this expression, it is possible to compute the modulus (magnitude) of Zn
and therefore plot it versus the normalised switching frequency for different values of the
quality factor:

Figure 3.6: Study of the normalised input impedance behaviour

 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 29

The above plot clearly shows that, for frequencies higher than the resonance one (fsw > fR1 ),
the behaviour of Zin is inductive (i.e. the magnitude of the input impedance increases with
the switching frequency) while, for frequencies below the second resonance one (fsw < fR2 ),
Zin has capacitive nature (i.e. its absolute value decreases with frequency). Between the
two resonance frequencies (fR2 < fsw < fR1 ), there is a middle region in which Zin can
assume either inductive or capacitive behaviour depending on the specific Q value, which
tunes the Zin phase angle. This means that for each switching frequency of these middle
region, there is a critical maximum quality factor (meaning a critical load resistance), above
which the behaviour of Zin can only be capacitive. In order to find the borderline between
the capacitive and inductive regions in terms of normalized conversion ratio, it is enough to
impose that the imaginary part of Zn is zero (meaning that Zn is purely real, which is exactly
the boundary between capacitive and inductive behaviour, characterised by a zero phase shift
between voltage and current). The result in terms of the critical quality factor, as a function
of fn and lm , is contained in the following equation:
s  2
1/lm 1/lm
Qcrit = − (3.23)
1 − fn2 fn
From this expression, the critical value of the load resistance (above which the operation of
the converter lies in the inductive region, even below resonance) can be immediately found:

π 2 Z0
Rcrit = (3.24)
8 n2 Qcrit
As a consequence, it is also possible to find the expression of the critical conversion ratio as
a function of the frequency. In particular, in terms of voltage gain:

fn
mcrit = s   (3.25)
1 1
fn2 1+ −
lm lm
Therefore the capacitive and inductive region can finally be represented in the m-fn plane:
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 30

Figure 3.7: Inductive and capacitive regions in the voltage gain characteristic

It is important to point out that as converter operation is moved away from the capacitive
inductive boundary towards the inductive region, there is a gradual (not abrupt) passage from
hard switching to soft switching.
One important feature of the above plot is that it clearly shows that the peak value of each
conversion ratio curve lies inside the capacitive region. This justifies what described in
the previous chapter, i.e. the fact that the converter is always used in step-up mode for
frequencies below the resonance: in fact further moving below resonance would allow step-
down operation at the unbearable cost of losing ZVS (thus losing all of the advantages of using
a soft-switching converter). Fortunately, the above resonance region can be successfully
used for step-down operation since Zin has inductive behaviour regardless of the output
load resistance. Because of this, it is useful to impose that the minimum required voltage
conversion ratio (corresponding to the maximum expected input voltage) can be reached at
the extreme condition of infinite load resistance (zero quality factor) and at a maximum finite
frequency. In particular, starting from the expression of m, evaluated at Q = 0:

1
m0Q = (3.26)
1 1/lm
1+ − 2
lm fn
and defining:

Vout
mmin = 2n (3.27)
Vin,max
the maximum required normalised frequency found to be equal to:
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 31

v
fmax u 1
fn,max = =u (3.28)
u  
fr 1
1 + lm 1 −
t
mmin
Furthermore, eq. (3.25) can be exploited to find the minimum operating frequency, imposing
Vout
mcrit = mmax = 2n (max required voltage gain, corresponding to the minimum
Vin,min
expected input voltage). The minimum required normalised frequency is described by the
following equation:
v
fmin u 1
fn,min = =u (3.29)
u  
fr 1
1 + lm 1 −
t
m2max
This expression can be in turn substituted in eq. (3.23) to find the maximum allowed quality
factor as a function of mmax and λ:
s
1/lm m2max
Qmax = lm + (3.30)
mmax m2max − 1
As a result from all these considerations, it can be concluded that operation at resonance
(in CCM) must be preferred because load regulation is ideally zero and tank waveforms are
maximally sinusoidal. Therefore the converter must be designed to work at resonance under
nominal conditions, below resonance operation must handle input voltage dips and above
resonance can well deal with input voltage rises. Lastly, one the most critical aspects of this
analysis is that capacitive region must be avoided in every possible way.

3.2 FHA design technique

Based on the analysis conducted on the linearised circuit (Figure 3.2) in the previous
section, many different design procedures can be extracted (e.g. the ones described in [15]
and [16]). However, one of the most interesting and complete is the one described in [10] and
[17], since it exploits the FHA to find also some conditions for imposing ZVS at maximum
and minimum frequencies. In particular, given the following list of specifications:

• nominal input voltage, Vin,nom ;

• input voltage range, [Vin,min , Vin,max ];

• regulated output voltage, Vout ;

• nominal operating frequency, fr ;

• maximum operating frequency, fmax ;

 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 32

• maximum output power, Pout ;

• total parasitic capacitance at node HB, CZV S ;

• dead-time, TD ,

the proposed design flow follows three main general design criteria:

1. the converter is designed to work at resonance under nominal input voltage;

2. the converter must be able to regulate Vout even when Pout = 0 and Vin = Vin,max ;

3. the converter must work in ZVS across all the operating range (from a certain fmin to
a fmax ).

These three criteria are the guidelines used to find the constraints useful to obtain a complete
design of the converter components and they are detailed in the following sections.

3.2.1 Nominal operation

The first criterion simply translates in imposing the nominal normalized voltage conver-
sion ratio at resonance to one (m(fn = 1) = 1), from which the turns ratio of the transformer
can be derived:

1 Vin,nom
n= (3.31)
2 Vout

3.2.2 Inductor ratio selection

The second criterion imply that the converter must work at a maximum switching fre-
quency (fmax ) when regulating the output voltage in the extreme condition of zero output
power (open circuit load) and maximum input voltage. Therefore, resorting to eq. (3.28), the
inductor ratio can be found as:
2
mmin fn,max −1
lm = 2
(3.32)
1 − mmin fn,max

3.2.3 Zero-voltage switching condition

The third and last criterion is the most difficult to be fulfilled. To begin with, the ZVS
condition can be translated in terms of the phase angle of the input impedance: in fact, this
angle equals the shift between the bridge leg voltage and the resonant current (namely φ) and
therefore it must as well be enough to ensure that VHB is able to reach ground within the end
of the dead-time. Moreover, assuming that the duration of the dead-time is negligible with
respect to the the switching period, the value of the resonant current can be approximated as a
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 33

constant value throughout the whole duration of the dead-time. Following this approximation
(and therefore assuming a linear discharge of CZV S ), a condition for the minimum tank current
value at the end of the first half-cycle (i.e. when the high-side MOSFET turns off) can be
easily found:

CZV S Vin
IZV S = (3.33)
TD
In particular, in the FHA model, this current corresponds to the peak amplitude of the reactive
component of the overall resonant current:

IZV S
Ireact = Ires sin(φ) = √ (3.34)
2
while the active component is related to the input active power (which can be assumed equal
to the output power in a lossless system):

Pin Pin
Iact = Ires sin(φ) = = √ (3.35)
Vi,F HA 2Vin
π
From the active and reactive components, magnitude and phase angle of the resonant current
can be found. The phase angle is the element of major interest because, as already stressed,
it corresponds to the phase angle of the input impedance. Therefore:
p
Ires = 2
Iact 2
+ Ireact (3.36)

Vin IZV S CZV S Vin2

tan(φ)min = = (3.37)
πPin πTD Pin
This equation provides the minimum allowed phase angle ensuring ZVS and therefore the
sufficient condition for imposing ZVS is the following:

Im[Zn ]
tan(φ) = > tan(φ)min (3.38)
Re[Zn ]
However, the solution of the above-equation for obtaining the maximum allowed quality
factor at minimum input voltage is not straightforward thus leading to the need of finding an
approximate workaround to impose the ZVS condition.
First of all, the idea is to start with the value of the quality factor at the inductive-capacitive
border, at minimum input voltage (i.e. Qmax , eq. (3.30)). In correspondence of Qmax , the
input impedance exhibits zero phase angle, meaning that is is purely resistive. Therefore, in
order to ensure some phase margin to reach the ZVS condition, the simple idea is to compute
a possible quality factor ensuring the expected ZVS as:

QZV S1 = 90% ÷ 95%Qmax (3.39)

 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 34

This is the first of the two constraints on the quality factor. In fact, in order to ensure
ZVS across the whole operating region, the other extreme condition to be imposed is the
one regarding zero output power (i.e. zero quality factor) and maximum input voltage. In
this particular operating point, a sufficient constraint can be successfully found since the
expression of the input impedance at zero output power can be manipulated more easily.
Therefore it is enough to impose:

Vi,F HA,max IZV S (Vin,max )

≥ √ (3.40)
Zin,0Q (fn,max ) 2
with

" #
1
Zin,0Q (fn,max ) = Zin (Q = 0, fn,max ) = jZ0 fn,max (1 + lm ) − (3.41)
fn,max

Finally the other constraint on the quality factor is found:

2 fn,max TD
QZV S2 = 2
(3.42)
π (1 + lm )fn,max − 1 Rac CZV S
Therefore, in order to guarantee full ZVS, the chosen quality factor must fulfil the following
condition:

QZV S ≤ min(QZV S1 , QZV S2 ) (3.43)

At this point, it is also possible to compute the corresponding minimum switching frequency,
through the following approximate equation:
v
u 1
fmin ≈ fr u (3.44)
u  
u
u  
u
u 
u 1 + lm 1 −
 1 

4
QZV S 
u  
u 
 1+  
Qmax
t
Mmax
Once all this procedure has ended, the input impedance must be evaluated at fn,min , lm and
QZV S :

jfn,min 1 − fn,min2
Zn (fn,min , lm , QZV S ) = + (3.45)
1/lm + jfn,min QZV S jfn,min
in order to check if the sufficient condition for ZVS (eq. (3.38)) is actually respected at min-
imum frequency, with the chosen quality factor. If the inequality is found to be unverified, a
wider margin should be chosen in the computation of QZV S1 , re-iterating all the procedure
previously detailed until the sufficient condition for ZVS is met.
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 35

Finally, the values of the converter components can be computed, starting from the compu-
tation of
2
8 2 Vout
Rac = n2 Ro,ac = n (3.46)
π 2 Pout
and

Z0 = QZV S Rac (3.47)

In the end:

1
Cr = (3.48)
2πfr Z0

Z0
Lr = (3.49)
2πfr

Lm = lm · Lr (3.50)
Following this design methodology leads to the possibility of working with the LLC in the
operating region coloured in light blue in the following figure, where the ZVS is always
ensured.

Figure 3.8: Operating region of the LLC converter in the voltage gain characteristic

At this point the design is complete since the LLC is completely determined. A MATLAB
script implementing the just described design method is proposed in Appendix A.1, where
the re-iteration process is performed through the use of a "for" loop.
 CHAPTER 3. FIRST HARMONIC APPROXIMATION (FHA) 36

3.2.4 Design example

A design example is now provided starting from the following table, where a set of
possible design specifications is summarised:

Vin,nom [V] 400

Vin,min [V] 380
Vin,max [V] 420
Vout [V] 30
Pout [W] 300
fr [kHz] 120
fmax [kHz] 150
CZVS [nF] 400
TD [ns] 200

Exploiting the MATLAB script presented in Appendix A.1, the converter components are
found and gathered together in the table below:

n [none] 6.67
Cr [nF] 40
Lr [µH] 44
Lm [µH] 315

This example is also useful because it allows to understand the order of magnitude of the
typical components of the LLC converter. For instance, for operating frequencies of the order
of 100 kHz, the value of the resonant capacitor is generally of the order of tens or hundreds of
nF while the resonant inductor assumes values between tens and hundreds of uH. Moreover,
the magnetizing inductance is almost always a multiple of Lr but usually does not exceed 10
times the value of the resonant inductor. Finally, as regards the ideal transformer, the turns
ratio is often about 10 because the LLC converter, as already highlighted, is usually put at
the output of a PFC pre-regulator, which provides a high voltage (generally about 400 V) and
the desired LLC output voltage is usually much lower.
Chapter 4

Sequence of switching states approach

As highlighted in the previous chapter, the FHA leads to a strongly simplified model
which has the advantage of being very easy analysed but it is not able to accurately match the
behaviour of the converter, especially when away from resonance. It is possible to complicate
the FHA model by limiting the number of waveforms to be approximated as sinusoidal. This is
certainly an improvement and it allows a more realistic description of the converter. However,
given the strong non-linearity of the LLC, even this model (namely extended FHA, eFHA) is
not enough to obtain an accurate description of the circuit. In particular, this is demonstrated
by the work of [18]. Furthermore, the FHA analysis is based on the linearised model of
Figure 3.2 and on the definition of quality factor and input impedance: this prevents the
possibility to compare the approximate model with the signals (voltages and currents) of the
physical device. Therefore, a more analytical approach should be followed, resorting to the
exact time-domain solution of the LLC converter. One of the most notable attempt pointing
in this direction is found in [19], where the main advantage of the developed model is its
accuracy, which is independent on the frequency or on the output load, since the full non-
linear model is taken into account instead of just its linearised version. Here, this analysis
is presented with some variations in the notation and some additional remarks, which are
consistent to the work presented in the previous chapter and the following one.
Going more in detail, the analysis procedure starts from the schematic of the converter shown
in Figure 4.1 which is manipulated to refer every component to the primary side (APR
equivalent model, Figure 4.2) of the transformer with the objective of getting more readable
circuital equations.

Figure 4.1: LLC converter schematic

Moreover, the APR equivalent circuit is described in terms of normalised voltages and

37
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 38

currents to get a more general analysis. In particular, the adopted normalisation is detailed
in the following:
r
Lr
• Z0 =
Cr
1
• ωr = √
Lr Cr
• θ = ωr t
Vout
• m = 2n
Vin
1 Lm
• lm = =
λ Lr
Z0
• Irn (θ) = Ir (θ)
Vin
Z0
• Imn (θ) = Im (θ)
Vin
1
• Vrn (θ) = Vr (θ)
Vin

Figure 4.2: LLC converter normalised APR equivalent circuit

Then, the core of the analysis consists in breaking one switching period of the converter (at
steady-state) into a sequence of the so-called "switch states", i.e. zones in which the circuit
can be fully described and characterised by one or more switching devices in the on state
while the remaining ones are off. Each switch state of the circuit can be analytically solved
for obtaining the exact expression of all the signals. In particular, assuming to neglect the
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 39

duration of the dead-time, there is always one transistor on (at a time) while the power diodes
can be on or off, depending on the operating point (e.g. CCM or DCM operation). Therefore,
two different circuits (branching from the one depicted in Figure 4.2) can be found to describe
the conditions in which one rectifier is on (MD equivalent circuit) or both rectifiers are off (M
equivalent circuit), independently on which MOSFET (high-side or low-side) is on. These
schematic are shown in Figure 4.3 and Figure 4.4 while, in the following, the differential
equations describing each equivalent scheme are presented and then analytically solved. It
is important to underline that the two MOSFETs can be replaced by an ideal normalised
voltage source VP SN n = VHB /Vin whose value can be either one or zero depending on which
transistor is actually on in that particular zone (VP SN n = 1 when Q1 is on and VP SN = 0
when Q2 is on). Moreover, the rectifiers (moved to the primary side) and the ideal transformer
can also be modelled through an ideal normalised voltage source, VP RSn , which assumes the
value of +m/2 when D1 is on and −m/2 when D2 is on while it is disconnected when both
rectifiers are off (M states). Of course, there can be four possible MD states (Q1 on with D1
or D2 on and the analogous with Q2 on) and only two possible M states (D1 or D2 on).
Starting from the MD equivalent circuit, the following table summarises the values of VP SN n
and VP RSn for each different MD state. Each specific MD state is referred to as xMyD, where
x = 1 if the high-side MOSFET is on and x = 2 if the low-side MOSFET is on, while y = 1
if the high-side rectifier is on and y = 2 if the low-side diode is on.

1M1D 1M2D 2M1D 2M2D

VPSNn 1 1 0 0
VPRSn +m/2 +m/2 -m/2 -m/2

Figure 4.3: MD equivalent circuit

 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 40

The circuit in the above figure is described by the following system of differential equations
constraining the main variables:

 dVrn

 Irn =

 dθ
dIrn

VP SN n = Vrn + VP RSn +
 dθ
dImn


 VP RSn = lm


dθ
The solution of this system can be found in closed-form and it is reported in the following
expressions:

Irn (θ) = (VP SN n − VP RSn − Vr0n )sin(θ) + Ir0n cos(θ) (4.1)

VP RSn · θ
Imn (θ) = + Im0n (4.2)
lm

Vrn (θ) = (VP SN n − VP RSn ) − (VP SN n − VP RSn − Vr0n )cos(θ) + Ir0n sin(θ) (4.3)

where Ir0 , Im0 and Vr0 are the values of the corresponding variables evaluated at θ = 0.
Moving to the M equivalent circuit (Figure 4.4), the following table contains the values of
VP SN n for each M state (VP RSn is not defined in this case). Moreover, since diodes are always
off, the states are simply referred to as xM, where x = 1, if the high-side MOSFET is on, and
x = 2, if the low-side MOSFET is on. The system of equations characterising M states is
modified (with respect to the previous case) as follows:

1M 2M
VPSNn 1 0

Figure 4.4: M equivalent circuit

 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 41


dVrn
Irn =


dθ
dI dI
VP SN n = Vrn + lm rn + rn

dθ dθ
Since both rectifiers are off in the M states, Irn = Imn (meaning also that current at the
secondary side is zero). Therefore, solving the above system of differential equations:
   
VP SN n − Vr0n θ θ
Irn (θ) = √ sin √ + Ir0n cos √ (4.4)
1 + lm 1 + lm 1 + lm

   
θ p θ
Vrn (θ) = VP SN n − (VP SN n − Vr0n )cos √ + Ir0n 1 + lm sin √
1 + lm 1 + lm
(4.5)

4.1 Main operating regions

The equations previously found are very useful to describe the waveforms periodic evo-
lution if the exact sequence of zones is known. In particular, four main operating modes can
be found, each of the ones characterised by a different sequence of states:

• above resonance high power (ARHP);

• above resonance low power (ARLP);

• below resonance high power (BRHP);

• below resonance low power (BRLP)

Each of these regions is detailed in the following sub-sections, considering the behaviour
of the lossless converter. It is interesting to notice that M states start to characterise the
operating regions as the output power level decreases (or the frequency is lowered): this is
in agreement with the fact that, as already highlighted, CCM operation (i.e. no M states) is
associated with a higher output power level while DCM (i.e. presence of M states) operation
is usually found when the output power becomes lower.

4.1.1 Above-Resonance-High-Power (ARHP)

In this region, where the switching frequency is higher than the resonance one (fr ) and the
output power level is high, no M states are present within a cycle period, meaning that there
is always one diode rectifier in the on state (CCM operation). Moreover, at the beginning
of each half-period (identified by one of the two MOSFETs in the on state), there is a small
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 42

time interval (i.e. angle interval in the normalised model) in which the rectifier forward
biased at the end of the preceding half-period stays still on. In other words, the on times of
MOSFETs and the ones of the rectifiers are shifted in time (angle), ones with respect to the
others. Therefore, in terms of switch states, a complete switching cycle is characterised, in
this region, by the following sequence:
1M2D 1M1D 2M1D 2M2D
VPSNn 1 1 0 0
VPRSn -m/2 +m/2 +m/2 -m/2

Figure 4.5: Normalised waveforms example (ARHP region: m = 0.6, lm = 5, ∆Vrn =

1.642)

The main waveforms of the converters, working in the ARHP region, are shown in the figure
above. A MATLAB script which is able to find of all the unknowns (Im0n , Ir0n , θ0, θ1)
needed to plot the above-shown waveforms, once a given triple (m, lm , ∆Vrn ) is chosen, is
provided in Appendix A.2. Finally, it is useful to point out that ∆Vrn simply represents the
gradient of Vrn between its value at half-period and its initial one (Vr0n ): therefore, once
1 − ∆Vrn
∆Vrn is set, Vr0n can be simply found computing .
2

4.1.2 Above-Resonance-Low-Power (ARLP)

Keeping the frequency above the resonance value and moving towards lower output power
levels allows to simulate a different operating region. In this case, the sequence of states
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 43

describing one complete period is different from the one described in the previous sub-
section: in particular, with respect to the ARHP sequence, each half-cycle simply integrates
an additional M state. This modification suggests that there are time (angle) intervals in which
none of the rectifiers is on (DCM operation). The exact sequence of states characterising this
region is summarised in the following table and then an example showing the main waveforms
is provided:

1M2D 1M 1M1D 2M1D 2M 2M2D

VPSNn 1 1 1 0 0 0
VPRSn -m/2 NaN +m/2 +m/2 NaN -m/2

Figure 4.6: Normalised waveforms example (ARLP region: m = 0.94, lm = 5, ∆Vrn = 0.1)

4.1.3 Below-Resonance-High-Power (BRHP)

Lowering the input frequency below fR1 leads the LLC converter into different operating
regions. In particular, in agreement to what said in the previous chapter, there is no CCM
possible below resonance that allows at the same time ZVS. Therefore, independently on the
output power level, the operation of the converter, below resonance, will happen in DCM.
This consideration justifies the presence of M states in both BRHP and BRLP regions. On
the other hand, even below resonance there is a difference in terms of sequence of states when
varying the output power level. Starting from the BRHP region, it is possible to notice the
presence of only one M state in each half-cycle, leading to the following sequence:
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 44

1M1D 1M 2M2D 2M
VPSNn 1 1 0 0
VPRSn +m/2 NaN -m/2 NaN

Figure 4.7: Normalised waveforms example (BRHP region: m = 2, lm = 5, ∆Vrn = 2.4)

4.1.4 Below-Resonance-Low-Power (BRLP)

Moving to the condition of low output power (always staying below resonance), the
number of M states per half-period increases to two (which is consistent with the fact that
DCM operation becomes more pronounced when lowering the output power). In particular,
the sequence of zones describing the evolution of LLC waveforms at BRLP is shown in the
following table:

1M 1M1D 1M 2M 2M2D 2M
VPSNn 1 1 1 0 0 0
VPRSn NaN +m/2 NaN NaN -m/2 NaN
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 45

Figure 4.8: Normalised waveforms example (BRLP region: m = 2, lm = 5, ∆Vrn = 0.7)

4.2 Region boundaries

As shown in all of the previous figures containing examples of normalised waveforms,
a steady-state operating point can be fully defined by a set of three main variables (namely
m, lm , ∆V rn). Then, imposing several constraints (e.g. Appendix A.2) regarding the
periodicity of the signals and the proper sequence of zones, the evolution of the waveforms
(for that specific operating point) can be represented. Therefore, the main issue is to find the
correct sequence of states corresponding to each possible triple of m, lm , ∆V rn. With the
objective of finding this correspondence, the idea is to compute all the boundaries between
different regions and obtain, as a consequence, a chart able to map any given set of LLC
main parameters onto a specific region (i.e. a specific sequence of zones). In particular, each
boundary is expressed in terms of ∆Vrn as a function of m, for a given lm .

4.2.1 ARHP-BRHP (Resonance-High-Power, RHP)

The most important boundary is the one related to the resonance operation (fsw = fR1 ) at
high power (CCM), that is the nominal condition for which the converter is usually designed.
This fundamental border can be characterised by considering the switching states in common
between ARHP and BRHP regions: therefore, the RHP sequence of states simply consists of
two MD zones (as shown in the following table).

1M1D 2M2D
VPSNn 1 0
VPRSn +m/2 -m/2
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 46

It is apparent from the table above that the RHP boundary is the only possible condition in
which on states of the power MOSFETs and the ones of the corresponding power diodes are
exactly in phase (that leads to smoother and maximally sinusoidal waveforms).

Figure 4.9: Normalised waveforms example (RHP boundary: m = 1, lm = 5, ∆Vrn = 0.6)

Moreover, along the RHP boundary, some additional constraints on the differential equations
can be found:

1
θ0 = 2π fr = π (4.6)
2fr

Ir0n = Im0n (4.7)

mπ
Ir1n = −Ir0n = Im1n = Ir0n + (4.8)
2 lm
from which, the following equation is extracted:

mπ
Ir0n = − (4.9)
4 lm
Another peculiarity of the RHP border is the fact that m = 1 independently on the output
power (in agreement to what seen within the frame of the FHA model). In fact, starting from
eq. (4.3), the following limit can be computed:

lim Vrn (θ) = Vrn (π − ) = 2 − m − Vr0n

θ→π −

Then, exploiting the following relationship:

lim Vrn (θ) = Vr1n = Vr0n + ∆Vrn = −Vr0n + 1

θ→π
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 47

(which simply tells that the limit exists and it returns its value), it can be concluded that

Vr1n = Vrn (π − ) (4.10)

thanks to the theorem on the uniqueness of limits. This last equality finally leads to m = 1.
It is interesting to observe that, since the voltage gain is fixed at one along the RHP border,
both Ir0n and Ir1n are only dependent on lm (eq. (4.9)). In particular, it can be useful to
compute the de-normalised value of Ir1n :
r
Vin πVin Lr Cr Vin 1
Ir (Tr /2) = Ir1n = = (4.11)
Z0 4 Lm Lr 8Lm fr
In order to achieve ZVS, this current level must be higher than the minimum one required
to switch the voltage at node HB within the specified dead-time (i.e. IZV S , eq. (3.33)).
Imposing this condition, a constraint on the maximum magnetising inductance can be found:

TD 1
Lm ≤ (4.12)
8fr CZV S

4.2.2 ARHP-ARLP
The boundary between ARHP and ARLP regions can be characterised in terms of voltage
constraints. In particular, starting from the sequence of states of ARHP and imposing that
the de-normalised voltage across Lm is at the minimum possible value able to turn on the
secondary rectifier D1 at the end of the 1M2D state allows to simulate this border condition.
Therefore, the following constraint must be added to the system of equations for finding the
unknowns (∆Vrn , in particular):
 
m lm + 1
Vr1n =1− (4.13)
2 lm
Further lowering the output power would lead to an insufficient voltage on the anode of D1
so that the 1M2D zone would be followed by a 1M state (ARLP region) rather than a 1M1D
one (ARHP region).

4.2.3 BRHP-BRLP
This boundary simply represents the condition in which the converter operation switches
from a high-power region to a low-power one, when the frequency is above the resonance
value and it is therefore analysed in a similar way with respect to the border of the previous
sub-section. In particular, to find the corresponding steady-state operating points, it is enough
to consider as a constraint the voltage across D2. In fact, if this voltage is exactly equal to
Vout + VD2,on (in terms of de-normalised values) at the start of the first half-cycle of BRHP
operation, it means that the output power level is just enough for starting the sequence of
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 48

states with an MD state. This considerations translates into the fact that the BRHP-BRLP is
represented by the following relationship:
 
lm + 1
∆Vrn = m −1 (4.14)
lm
By further reducing the power level, the sequence of zones is modified as it begins with an
M state (1M) meaning that BRLP region is entered.

4.2.4 Zero-Current-Switched (ZCS)

This is the non-linear equivalent of the inductive-capacitive boundary computed within
the FHA frame and therefore mainly concerns below-resonance operation. In particular,
the ZCS border can be found by imposing that the resonant current at the end of the first
half-period (considering BRHP operation) is zero (i.e. Ir2n = −Ir0n = 0). This condition is
the one in which the resonant current flowing in the tank and the VHB voltage are exactly in
phase and therefore ZVS has already been lost (because there is certainly not enough current
to discharge CHB ).

Figure 4.10: Normalised waveforms example (ZCS border: m = 2.6, lm = 7, ∆Vrn = 3.88)

4.2.5 Resonant-Reversal (RR)

This condition is also mainly related to the most risky operating region (BRHP) and
it is found as a boundary with higher-power/lower-frequency regions, characterised by the
presence of one 1M2D state at the end of the first half-period. Therefore, in order to compute
the RR boundary, it must be imposed that the voltage across D2 is just enough to turn it on
at the end of the first half-cycle. In particular, the relationship characterising this boundary
is the following:
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 49

 
lm + 1
∆Vrn = m +1 (4.15)
lm
Actually the RR boundary gives looser constraints than ZCS for the most part of the below-
resonance region but it is used as an actual upper boundary for ensuring ZVS operation for
the remaining parts of the below-resonance and also above-resonance. In fact, when a 1M2D
state is found at the end of the first half-period, there is a corresponding drop of the resonant
current which, as soon as the frequency is reduced or the power increased, can rapidly lead to
the loss of ZVS. Since ZCS and RR boundaries can give more or less tight constraints on the
maximum ∆Vrn , it is recommended to consider a mix of the two, named ZCS/RR boundary,
which simply consists of the minimum between ∆Vrn,ZCS and ∆Vrn,RR .

4.2.6 Map of operating regions

Computing the values of ∆Vrn as a function of m (for different lm ), corresponding to the
previously-described boundary conditions, leads to the map addressed at the start of this
section. This chart (shown in the figure below) is very useful to analyse the converter across
different operating regions but it is also important as a starting point for building a more
precise design procedure.

Figure 4.11: Plot of operating regions and boundaries

One of the limitations of this model is that it does not address what happens at the boundary
between ARLP and BRLP regions. Another issue is that the map of the regions does
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 50

not explicitly contains any quantitative frequency information. Furthermore, the use of
∆Vrn as a characterising parameter is not very practical because it is a quantity related
to the voltage gradient of the resonant capacitor rather than a parameter coming from a
specification. However, ∆Vrn gives a rough estimate of the output power (current) level, for
a given a voltage gain, as can be qualitatively seen from Figure 4.11. This statement can
be easily demonstrated in the case of the RHP boundary, by relating the expression of the
de-normalised output current (Iout ) to ∆Vrn . In particular, referring to the de-normalised
circuit (Figure 4.1), Iout can be found as:
Z Tr /2
Pout 2n
Iout = = n · mean(Ir − Im ) = (Ir − Im )dt (4.16)
Vout Tr 0
Considering that
Z Tr /2
Ir dt = Cr [Vr (Tr /2) − Vr (0)] = Cr ∆Vrn Vin (4.17)
0
Tr
and that, for 0 < t < , the integral of Im is zero, the integral of eq. (4.16) can be easily
2
solved and, re-arranging the terms, it is possible to write the expression of ∆Vrn as a function
of Iout :

Iout Tr 1
∆Vrn = (4.18)
2n Cr Vin
This expression can be also used to compute the minimum current level ensuring to work at
resonance in CCM (i.e. along the RHP boundary). In particular, writing Iout as a function of
∆Vrn :

Cr
∆Vrn
Iout = 2nVin (4.19)
Tr
and imposing the value of ∆Vrn at the boundary between BRHP and BRLP (eq. (4.14) ) for
m → 1, it is found that the value of Iout,min is:
√
Cr Lr Vin C r Lr
Iout,min = 2nVin =n (4.20)
Tr Lm π Lm

4.3 Design proposal

Also in this case, a design procedure can be based on the analysis: the advantage is its
level of accuracy, since it can make use of the exact expression of voltages and currents (of
the lossless converter). This design method is explicitly proposed as an alternative the one
derived from the FHA in [20]. In particular, it useful to notice that, once a steady-state
operating point has been computed through the previously described analysis, any circuital
signal (voltage, current, power etc..) can be computed. Therefore, the idea proposed in [19]
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 51

is to compute the so-called "current loss factor" (CLF) and to use it as a figure of merit for
narrowing the design choice. This parameter is in fact a rough qualitative measurement of
the conduction losses inside the circuit and it is defined as follows:
2 2
Ipri,RM S + Isec,RM S
CLF = 2
(4.21)
Iin,avg
where Ipri,RM S and Isec,RM S are the RMS values of the primary and secondary side currents
while Iin,avg represents the input average current. Therefore, CLF is evaluated for different
operating points in order to understand its behaviour. The main results are summarised in the
following two figures:

Figure 4.12: Plot of CLF as a function of normalised switching period (Tpn = T /Tr ) for
different values of ∆Vrn (pink curves) and lm = 5
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 52

Figure 4.13: Plot of CLF as a function of m, for different values of lm

In particular, from Figure 4.12, it can be understood that, for a given inductor ratio, the most
efficient region in which the converter can operate is close to the ZCS/RR boundary, where
conduction losses are at their minimum value. Furthermore, Figure 4.13 clearly shows that a
lower value of lm must be preferred in order to minimise power losses in the region above-
resonance. The last important consideration which can be derived from both Figure 4.12 and
Figure 4.13 is that losses rapidly increases when moving away from resonance (particularly
in the below-resonance direction) and it is therefore recommended to limit the switching
frequency range (which unfortunately results in a reduced m range). As a consequence of all
these considerations, the actual design flow can be presented. In particular, the procedure is
detailed in three main steps, described in the following.

4.3.1 Turns ratio selection

The LLC is usually expected to regulate the output voltage to a fixed value, regardless of
input voltage variations [Vin,min , Vin,max ]. The actual voltage conversion ratio of the converter
depends on both turns ratio and normalised conversion ratio m. As underlined before, the m
range should be very limited with the objective of limiting conduction losses. In particular,
a reasonable choice is to choose constrain m inside the range of [0.7, 4]. Therefore, the turns
ratio of the transformer can be chosen through the following equation:

mmin Vin,max
n= (4.22)
2 Vout
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 53

4.3.2 Inductor ratio selection

The inductor ratio is selected to minimise the CLF: in particular, the range of possible
lm can be reasonably limited to [3, 7]. As a matter of fact, this consideration alone is not
enough to choose the inductor ratio. In fact, this parameters also strongly impacts on the ZVS
condition. In particular, the maxim dead-time (needed at maximum frequency) for ensuring
ZVS can be related to lm through the following equation:

   
r " √ #
1 + lm  −0.5 Ir,pk 1 + lm Crn 
TD,max = arccos   − arctan
 
q
Crn  2
0.25 + (1 + lm)Crn Ir,pk 0.5 

(4.23)

Cr Tmin
where Crn = and Ir,pk = . Therefore, it must be checked if the actual
CHB 4(1 + lm )
dead-time (which is usually an a-priori set) is higher than TD,max , for the chosen inductor
ratio. If not, lm must be further reduced and/or the value of CHB must be increased.

4.3.3 Remaining components selection

As previously stated, given an operating point, each signal of the circuit can be computed,
if the corresponding operating region is known. In particular, this can be applied to the
Z0 2
computation of the normalised average input current (Iinavno = Iin,avg ), whose value
Vin m
is represented in the figure below, as a function of the normalised period (Tpn = T /Tr )and
for different values of m and ∆Vrn (pink curves),
 CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 54

Figure 4.14: Plot of Iinavno as a function of Tpn for different values of ∆Vrn (pink curves)

Focusing on the ZCS/RR border, Figure 4.14 clearly shows that the normalised average input
current increases with the rise of the frequency. Therefore, the design suggests to choose
the maximum allowed normalised average input current (IinavM axno ) in correspondence of
mmax , along the ZCS/RR border (which also sets the maximum normalised switching period,
Tpn,max ). Of course, this means that the converter should not work above the orange line. As
a consequence of the choice of Tpn,max , the resonance frequency can be found through the
following expression (assuming that fmin is a specification):

ωr = 2πTpn,max fmin (4.24)

Then, the actual un-normalised value of the maximum input average current can be roughly
evaluated starting from the specifications and considering an efficiency (η) of the converter
of e.g. 90%:

1 Pout,max
Iin,avg,max = (4.25)
Vin,min η
Combining this value with its normalised version (IinavM axno ), it possible to evaluate the
characteristic impedance Z0 :

IinavM axno
Z0 = nVout (4.26)
Iin,avg,max
Finally, the values of Cr , Lr , Lp can be found:
CHAPTER 4. SEQUENCE OF SWITCHING STATES APPROACH 55

1
Cr = (4.27)
Z0 · ωr

Z0
Lr = (4.28)
ωr

Lp = lm · Lr (4.29)
Chapter 5

Modelling and design with parasitic effects

In this chapter, the idea is to complicate a bit the previous model with the introduction of
parasitic elements (in order to get a more realistic description of the LLC converter) while
maintaining the analytical approach and following the strategy described in [21], for the
design of Class-E resonant converters. In particular, the effect of parasitic resistances at the
primary and secondary side is studied. A first attempt was made to describe the converter
periodic evolution by considering even the dead-time: however that model led to a very
complex analysis (too many different zones involved) which simply was not worth it because
the resulting variations introduced by the dead-time (always very short with respect to the
switching period) were not very significant. Therefore, in the following, the duration of the
dead-time is never taken into account in the sequence of states characterising an operating
region. This assumption allows to approximate the lossy circuit as follows:

Figure 5.1: Lossy LLC schematic under the assumption of zero dead-time

As visible in the figure above, the lossy LLC schematic under exam presents a square wave
generator (VHB ) at its input: in particular, this voltage source models the behaviour of the two
power MOSFETs (as shown in the previous chapter). In fact, neglecting the dead-time (i.e.
assuming instantaneous switching), the voltage at node HB is simply Vin , when the high-side
transistor is on, while node HB switches to zero voltage, when the low-side MOSFET is
on. Moreover, a resistor (RM ) is added at the primary side, in series with the resonant
tank: this resistor is actually an effective element which lumps together all the parasitic
resistive contributions at the primary side, i.e. the on-resistance of the power transistors,
the ESR of Cr and the series resistance of Lr . At the secondary side of the transformer,
another effective resistance (RD ) is inserted in series with the power diodes to model the
leakage effects of the secondary windings and the finite transconductance of the diodes.
This modification leads to systems of Ordinary-Differential-Equations (ODEs) (describing

56
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 57

the circuit relationships) which are not solvable in closed-form, thus requiring the need of
numerical solutions. In particular, the MATLAB environment has been exploited for the
manipulation of the differential equations coming from the analysis of the lossy LLC. At
first, the symbolic computation was chosen for obtaining solutions of the systems of first-
order ODEs but its computational effort was found to be too high, resulting in very slow
simulations of each operating point. Therefore, given the high nonlinearity of the non-ideal
LLC, the next idea was to move onto a purely numerical approach, by exploiting a proper
MATLAB function, e.g. ode45. This last method can be effectively used for the solution
of few operating points since it gives better performances (in terms of computational time)
with respect to the symbolic approach. However, a different solution has been eventually
exploited, based on the theory of matrix differential equations, which allows to further reduce
the computational effort required by the LLC analysis (e.g. by directly computing the value
of an integral rather than exploiting MATLAB functions such as trapz). As a consequence,
simulations of a considerable number of operating points can be carried out more easily, with
the objective of getting a more complete description of the converter behaviour.

5.1 Design at resonance

Given the fact that, as already stressed, the design of the converter can be optimised just
for one single operating point, the idea is to focus the attention only to resonance operation
(in CCM), which is usually the preferred condition in which the LLC has to work. Therefore,
the first aspect is to fix the sequence of states characterising the RHP boundary: as shown
in the previous chapter, this sequence consists of just two states and the turn on and turn off
of each power MOSFET are exactly synchronised with the ones of the corresponding power
diode. In terms of the previously-introduced notation, this means that the sequence under
exam is 1M1D-2M2D (Figure 4.9). The next step is to find the systems of first-order ODEs
describing these two states. In particular, choosing as state variables the resonant current
Ir , the resonant capacitor voltage Vr , and the secondary-side current (either ID1 or ID2 ), the
following system is obtained, in the case of the 1M1D state:

dVCr
Ir = Cr





 dt
dIr d(Ir − ID1 /n)

Vin = RM Ir + Vr + Lr + Lm

 dt dt
L d(Ir − ID1 /n)


Vout = m − RD ID1 − VD1,on


n dt
while in the case of the 2M2D state:
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 58


dVCr
Ir = Cr





 dt
dIr d(Ir + ID2 /n)

0 = RM Ir + Vr + Lr + Lm

 dt dt
L d(I + I /n)

 m r D2
Vout = − − RD ID2 − VD2,on


n dt
As shown above, both the half-periods of resonance operation are characterised by a III order
system of first-order ODEs (where also the forward voltages of the power diodes are taken
into account). The only differences between the two differential systems are the value of the
voltage at node HB (which is either Vin or zero) and the quantities regarding the secondary
diode which is actually on (either D1 or D2). It is important to notice that the choice of the
above-cited state variables is different from the one exploited in the previous chapter. The
reason behind this choice lies in the will of allowing for a more practical design: in fact, for
instance, the output current flowing in the resistive load can be simply obtained starting from
ID1 and ID2 . The above-shown systems of ODEs are rearranged and written in MATLAB in
matrix form, i.e. y = A · x + b, where y is the vector of the derivates of the state variables
while x represents the vector of the state variables themselves. In particular, the matrices A
and B are found through the use of symbolic computations. Then, assuming that the initial
values of the state variables are known, it is possible to plot their periodic evolution, by
exploiting the matrices A and B inside the ode45 MATLAB function:

Figure 5.2: Example of the periodic evolution of Vr

 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 59

Figure 5.3: Example of the periodic evolution of Ir

Figure 5.4: Example of the periodic evolution of ID1 and ID2

The plot of the lossy converter waveforms can be useful but it is even more useful to find a
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 60

design approach capable of imposing some analytical constraints on the system starting from
a set of specifications. In particular, in order to find the optimal choice of the LLC elements,
the following specifications are taken into account:

• input voltage, Vin ;

• output voltage, Vout ;

• either the nominal operating frequency, fr , or the values of Lr and Cr ;

• output load, RL (or output power or output current);

• overall parasitic capacitance at node HB, CZV S ;

• dead-time, TD ,

The above-listed specifications are used to impose a set of four main constraints:

1. periodicity of Vr , i.e. Vr (T /2) = Vin − Vr (0);

2. periodicity of Ir , i.e. Ir (T /2) = −Ir (0) = 1.2 · IZV S ;

3. periodicity of ID1 , i.e. ID1 (T /2) = ID1 (0) = 0;

Vout
4. average value of the diode current equal to the output current, i.e. mean(ID1 ) =
RL
As shown above, the converter can be constrained simply resorting to its first half-period
(1M1D state), since the second one (2M2D state) is redundant. In fact, since the duty cycle
of the signals driving the power MOSFETs is exactly 50%, during the second half-cycle,
the evolution of ID2 is exactly equal to the one of ID1 in the first half-cycle, the plot Ir
equals −Ir (0 < t < T /2) and Vr can be found as Vin − Vr (0 < t < T /2). Furthermore,
Vout
the output current (i.e. ) can be found as integral mean of ID1 over the first half-
RL
cycle. This consideration remains valid also away from the RHP border and it allows for
faster simulations, since, for each operating region, it is enough to simulate only half of the
sequence of states. Another important aspect to be clarified is the one regarding the initial
value of the resonant current: this value must be imposed lower than −IZV S so that Ir (T /2)
is, in turn, set higher than the minimum value required to reach ZVS. On the other hand, the
value of Ir (T /2) must not be too far from the minimum allowed one because, otherwise, turn
off losses are heavily increased: this is the why Ir (T /2) is chosen to be only e.g. 20% higher
than the minimum value (meaning 1.2 · IZV S ).
These four constraints are exploited inside a MATLAB script for the choice of a corresponding
number (i.e. four) of LLC parameters to be optimised for working at the RHP boundary, with
the given specifications. In particular, the MATLAB optimiser tries to minimise the norm of
the difference between the vector:
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 61

[Vin − Vr (T /2), ID1 (T /2), −Ir (T /2), mean(ID1 )] (5.1)

computed starting from a random set of the LLC parameters to be found, and the vector:
 
Vout
Vr (0), 0, −1.2 · IZV S , (5.2)
RL
By tuning the values of the LLC parameters to be optimised, the norm is modified until it is
found to be lower than a certain threshold, meaning that the optimisation process is over.
In the first place, Vr (0), Lm , n and the effective resonance period (Tr,ef f ) are chosen as
parameters to be found by the optimiser, which means that, instead, the resonant components
(inductor Lr and capacitor Cr ) are already fixed. This approach is useful for understanding
the effect of parasitic elements on the turns ratio, on the magnetising inductance and on
the effective resonance frequency (1/Tr,ef f ). The results of this design approach show that
the effective value of the resonance frequency slightly differs from fR1 . Moreover, once
the converter has been designed, the full RHP border operation can be simulated, e.g. by
sweeping the output load and finding the remaining unknowns (Vr (0), Ir (0), Vout , Tr,ef f ):
the simulations show that the deviation of the effective resonance frequency from its ideal
value is more marked at high output loads (i.e. lower output power levels). This is clearly
shown from the following figure, containing an example of RHP border (described in terms
of output voltage, Vout as a function of the normalised switching frequency, fn = fsw /fR1 ) in
the case of a lossy LLC converter. In particular, the converter under exam is characterised by
Vin = 400 V, n = 7.73, TD = 90 ns, CZV S = 200 pF, Lr = 201 µs, Lm = 603 µs, Cr = 22
ns and it is simulated (Appendix A.3) by sweeping the output load from approximately 8 Ω
(top) to 0.1 Ω (bottom):

Figure 5.5: RHP border of the lossy LLC (RM = 1 Ω and RD = 0.1 Ω)
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 62

The same kind of simulation can be used to understand how the parasitic resistances affect
the dependency of the output voltage (and therefore the conversion ratio) on the output load:
as seen in the ideal lossless case, working at resonance means working in a load-independent
point. However, this is no more true in the case of the lossy converter (as already evident
from Figure 5.5), where the degree of load-dependency can therefore be a key parameter.
In particular, the RHP boundary can be simulated with lower values of parasitic resistances
(for the same range of output loads) to evaluate how much the ideal operation at resonance is
impacted when changing the output resistive load. The results are shown in the following:

Figure 5.6: RHP border of the lossy LLC (RM = 0.1 Ω and RD = 0.01 Ω)

Figure 5.7: RHP border of the lossy LLC (RM = 0.01 Ω and RD = 0.001 Ω)
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 63

As expected, lower parasitic resistances lead to a reduced dependency of the output voltage
on the output load: the proposed approach has the advantage of quantitatively evaluating this
dependency.
In addition, similarly with the reasoning followed in the previous chapter, it is possible to
compute the maximum output resistive load (i.e. the minimum output current) which allows
to work along the RHP boundary, exploiting another strategy derived from the previous one:
in fact, in this case, the output load becomes one of the values to be found by the optimiser
and therefore an additional constraint must be added. In particular, the voltage across D1
must be imposed just enough for it to turn on (i.e. VD1,on ) at the beginning of the switching
period, in order to obtain the above-mentioned threshold load. This threshold output load is
also useful to understand where to stop the sweep of the output loads when simulating the
RHP border.
A similar but more effective approach to the design consists of starting from a specification
on the operating frequency (which is usually the case) and to find, as a result of the MATLAB
optimisation, the value of Cr , in addition to n, Lm and Vr (0). It is useful to point out that the
Lm
inductor ratio (lm = ) remains a degree of freedom in this model and therefore it could be
Lr
optimised for other specifications. In this case, since it is known from the ideal lossless circuit
that lm controls the distance between the main resonance frequency and the secondary one
(eq. (2.3)) and that a lower value of lm allows to limit conduction losses (Figure 4.13), it seems
reasonable to choose lm = 3. Of course, while in the ideal model, this would imply that the
ratio between the main resonance frequency and the lower one is exactly two, this is no more
true with exact precision, in the case of the lossy converter. Therefore a modified MATLAB
script is used to perform the proposed design (Appendix A.4). This design approach allows to
easily and rapidly find the values of all the LLC components without strong approximations
and also taking into account the modifications introduced by the parasitic losses. Of course,
a similar procedure could also be applied to design the lossy converter to work in regions
different from the RHP border (when required): in that case, the MATLAB model must be
modified accordingly to the correct sequence of zones characterising the desired operating
region.

5.1.1 Design example

A design example is now provided starting from a set of specifications, summarised in
the table below:

Vin [V] 400

Vout [V] 24
RL [Ω] 1.92
fnominal [kHz] 75.874
CZVS [nF] 200
TD [ns] 90
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 64

Exploiting the MATLAB script presented in Appendix A.4, the converter components are
optimised for the given specifications and for RHP operation and then listed together in the
following table:

n [none] 7.73
Cr [nF] 22
Lr [µH] 201
Lm [µH] 603

5.2 Generalised model

The arrangement of the operating regions appears slightly modified in the case of the lossy
LLC with respect to what seen regarding the lossless converter in the previous chapter (Fig-
ure 4.11). In particular, this result is found from the analysis of the lossy LLC schematic under
different switching frequencies and output loads, performed through LTspice simulations.

Figure 5.8: LTspice schematic of the complete lossy LLC converter

The approach oriented towards the design and followed in the previous section can be however
exploited, with proper modifications, to obtain a complete description, in terms of operating
regions, of an already-designed converter. This can be, of course, very useful since, as already
underlined, the converter can be used to build more complex circuits for voltage regulation,
through feedback control, tuning the switching frequency of the LLC in order to maintain
constant the output voltage, when the input voltage or the output load vary. In particular,
through the proposed method of analysis, it is possible to generate the complete map of all
the main operating regions in a output voltage vs normalised frequency plot (similar to the
one obtained in the case of the FHA model, Figure 3.7, but more accurate and complex).
Of course, this requires, first of all, to find the systems of ODEs characterising all the states
involved in the principal regions of interest, which are: 1M2D, 2M1D, 1M and 2M (apart from
the already described 1M1D and 2M2D). In particular, referring to the circuit in Figure 5.1
and starting from 1M2D, the system of ODEs is the following:
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 65


dVCr
Ir = Cr





 dt
dIr d(Ir + ID2 /n)

Vin = RM Ir + Vr + Lr + Lm

 dt dt
L d(I + I /n)

 m r D2
Vout = − − RD ID2 − VD2,on


n dt
while in the case of 2M1D:

dVCr
Ir = Cr





 dt
dIr d(Ir − ID1 /n)

0 = RM Ir + Vr + Lr + Lm

 dt dt
L d(Ir − ID1 /n)


Vout = m − RD ID1 − VD1,on


n dt
Moving to the M states, the systems of ODEs are simply of the II order. In particular,
concerning 1M:

dV
 Ir = Cr Cr


dt
dI
Vin = RM Ir + Vr + (Lr + Lm ) r


dt
while in the case of 2M:

dV
Ir = Cr Cr


dt
dI
 0 = RM Ir + Vr + (Lr + Lm ) r


dt
It is important to notice that, through LTspice simulations, two new operating regions
are found, in addition to the ones already shown in the previous chapter (i.e. ARHP,
BRHP, ARLP, BRLP). These two additional regions are both found below-resonance and are
named Below-Below-Resonance-High-Power (BBRHP) and Below-Resonance-Very-High-
Power (BRVHP). In particular, the sequences of states characterising these two additional
regions are summarised in the following tables. For what concerns BBRHP:

1M1D 1M 1M2D 2M2D 2M 2M1D

while, in the case of BRVHP:

1M1D 1M2D 2M2D 2M1D

These two new operating regions are rather important because they can be used as a starting
point for the computation of the ZCS boundary, differently from what seen in the previous
chapter (lossless converter), where the BRHP region is used. In particular, it is observed that,
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 66

for lower output loads, a decrease of the frequency moves the LLC from the RHP boundary to
the BRVHP region while, in the case of higher output loads, the BBRHP region is entered. As
a final remark, it is useful to point out that the BRLP region described in the previous chapter
is found to actually characterise both below-resonance and above-resonance operation of the
lossy LLC, when the output power is rather low. Therefore, in this chapter, the sequence
of states corresponding the BRLP region is referred to as Low-Power (LP) region. The
following sub-sections describe in detail each main boundary: as usual, in order to impose
some constraints on the converter waveforms, it is enough to focus on the first half-period.
Moreover, the MATLAB code for imposing these constraints is detailed (Appendix A.4) only
for the first analysed boundary: in fact, the other borders can be simply simulated through
properly modified versions of the same code.

5.2.1 ZCS from Below-Resonance-Very-High-Power (BRHVP)

At low output voltages (corresponding to low resistive loads), this boundary approaches
the RHP one and therefore values extracted from the RHP simulation can be used as input
values to be tuned for characterising this boundary. In particular, the sequence of states is
to be exploited in this case is 1M1D-1M2D while the parameters to be optimised are the
following:
1. duration of the 1M1D state, TD1 ;

2. duration of the 1M2D state, TD2 ;

3. Vr (0);

4. ID1 (0);

5. RL
These values are optimised by a proper MATLAB script (Appendix A.5), imposing several
constraints:
1. Vin − Vr (TD1 + TD2 ) = Vr (0);

2. ID2 (TD1 + TD2 ) = ID1 (0);

3. Ir (TD1 + TD2 ) = −Ir (0);

4. ID1 (TD1 ) = 0;

5. RL · mean(ID1 + ID2 ) = Vout

In order to move along the boundary, either Vout or RL could be swept: in this case, it is
convenient to sweep Vout and finding the corresponding RL in order to get faster simulations.
Moreover, the upper value of Vout for the computation of this boundary can be computed with
a dedicated MATLAB script, imposing an additional constraint for taking into account the
approaching of the BBRHP region.
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 67

5.2.2 ZCS from Below-Below-Resonance-High-Power (BBRHP)

This boundary can be seen as the prosecution of the previous one but, since there happens
a change of regions,a different sequence of states must be exploited in the optimisation. In
particular, in this case the MATLAB code exploits the 1M1D-1M-1M2D sequence of states.
Again, Vout is swept for moving along the boundary. Going more in detail, the values to be
found by the MATLAB optimiser are:

1. duration of the 1M1D state, TD1 ;

2. duration of the 1M state, TD0 ;

3. duration of the 1M2D state, TD2 ;

4. Vr (0);

5. ID1 (0);

6. RL

while the constraints to be imposed are:

1. Vin − Vr (TD1 + TD0 + TD2 ) = Vr (0);

2. ID2 (TD1 + TD0 + TD2 ) = ID1 (0);

3. Ir (TD1 + TD0 + TD2 ) = −Ir (0);

4. ID1 (TD1 ) = 0;

5. VD2 (TD1 + TD0 ) = VD2,on ;

6. RL · mean(ID1 + ID2 ) = Vout

5.2.3 BVRHP-BBRHP boundary

This edge occurs between the new introduced operating regions (BVRHP and BBRHP).
In order to simulate this condition, the idea is to start from the sequence states of BVHP (i.e.
1M1D-1M2D) and to impose the following set of constraints:

1. Vin − Vr (TD1 + TD2 ) = Vr (0);

2. ID2 (TD1 + TD2 ) = ID1 (0);

3. Ir (TD1 + TD2 ) = −Ir (0);

4. ID1 (TD1 ) = 0;
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 68

5. VD2 (TD1 ) = VD2,on ;

6. RL · mean(ID1 + ID2 ) = Vout

with the objective of find, as outputs of the MATLAB optimiser, the following parameters:
1. duration of the 1M1D state, TD1 ;

2. duration of the 1M2D state, TD2 ;

3. Vr (0);

4. ID1 (0);

5. Ir (0);

6. RL
In this case, it is convenient to start from the set of initial parameter values corresponding to
the passage between ZCS-BBRHP and ZCS-BVRHP and then to sweep the output voltage,
stopping at the RHP boundary.

5.2.4 BBRHP-BRHP boundary

This boundary marks the entering of a more "stable" region (i.e. characterised by a
frequency closer to the resonance one and/or lower output power). In order to simulate the
operation along the BBRHP-BRHP boundary, it is practical to start from the BRHP region
(characterised by a 1M1D-1M sequence of states) and to impose the below shown constraints:
Lm + Ls
1. Vin − Vr (TD1 + TD0 ) = Vr (0) = RM · Ir (0) − n(Vout + VD1,on ) ;
Lm
2. ID1 (TD1 ) = ID1 (0) = 0;

3. Ir (TD1 + TD2 ) = −Ir (0);

4. RL · mean(ID1 ) = Vout
The implementations of these constraints in a proper MATLAB script allows to evaluate the
optimised value of the following set of parameters:
1. duration of the 1M1D state, TD1 ;

2. duration of the 1M state, TD0 ;

3. Ir (0);

4. RL
As a starting point of the simulation, the cross point between RHP and BVRHP-BBRHP
boundary could be used.
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 69

5.2.5 BRHP-LP boundary

In this sub-section, the border between BRHP and LP regions is analysed. In order to
simulate this condition, it can be useful to start from the upper limit of RHP boundary,
exploiting the sequence of states characterising the BRHP region (i.e. 1M1D-1M). Then,
Vout can be swept (increased) to move along the BRHP-LP border, imposing the following
constraints:
Lm + Ls
1. Vin − Vr (TD1 + TD0 ) = Vr (0) = Vin − RM · Ir (0) − n(Vout + VD1,on ) ;
Lm
2. ID1 (TD1 ) = ID1 (0) = 0;

3. Ir (TD1 + TD2 ) = −Ir (0);

4. RL · mean(ID1 ) = Vout

in order to obtain the optimisation below-shown parameters:

1. duration of the 1M1D state, TD1 ;

2. duration of the 1M state, TD0 ;

3. Ir (0);

4. RL

5.2.6 ARHP-ARLP boundary

This limit marks the passage from a high-power region to a low-power region, when above
resonance. Therefore, in order to simulate it, the idea is to exploit the sequence of states
characterising the ARHP region (1M2D-1M1D) and to impose the following constraints:

1. Vin − Vr (TD2 + TD1 ) = Vr (0);

2. ID1 (TD2 + TD1 ) = ID2 (0);

3. Ir (TD2 + TD1 ) = −Ir (0);

4. ID2 (TD2 ) = 0;

5. VD1 (TD2 ) = VD1,on ;

Vout
6. mean(ID2 + ID1 ) =
RL
with the aim of optimising the value of the following quantities:

1. duration of the 1M2D state, TD2 ;

 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 70

2. duration of the 1M1D state, TD1 ;

3. Vr (0);

4. ID2 (0);

5. Ir (0);

6. Vout

It is useful to notice that, in this case, the output load can be swept rather than Vout .

5.2.7 ARLP-LP boundary

At frequencies higher than the resonance one, there is a gradual passage to the LP region,
when increasing the output load. In particular, in order to find the border between ARLP and
LP regions, it is possible to exploit the sequence of states which exactly characterises this
boundary, i.e. 1M-1M1D. Moreover, a set of constraints must be imposed:

1. Vin − Vr (TD0 + TD1 ) = Vr (0);

2. ID1 (TD0 + TD1 ) = 0;

3. Ir (TD0 + TD1 ) = −Ir (0);

4. VD1 (TD0 ) = VD1,on ;

Vout
5. mean(ID1 ) =
RL
As a result of the MATLAB optimisation, the following parameters are found:

1. duration of the 1M state, TD0 ;

2. duration of the 1M1D state, TD1 ;

3. Vr (0);

4. Ir (0);

5. RL
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 71

5.2.8 LP boundary
Depending on the lowest expected output power level, the LP boundary can be computed.
In fact, this border simply represents the operating curve of the LLC converter corresponding
to the highest resistive output load. As already underlined, at very low output power, there is
no difference between the behaviour above or below resonance, in terms of operating regions:
in particular, the sequence characterising the LP region is 1M-1M1D-1M. Therefore, fixing
a rather high output load, it is possible to simulate this boundary by imposing the following
expressions:

1. Vin − Vr (TD01 + TD1 + TD02 ) = Vr (0);

2. ID1 (TD01 + TD1 ) = 0;

3. Ir (TD01 + TD1 + TD02 ) = −Ir (0);

4. VD1 (TD01 ) = VD1,on ;

Vout
5. mean(ID1 ) =
RL
and finding an optimisation of the following set of parameters:

1. duration of the first 1M state, TD01 ;

2. duration of the 1M1D state, TD1 ;

3. duration of the second 1M state, TD02 ;

4. Vr (0);

5. Ir (0)

5.2.9 Complete map of regions and operating curve

Putting together all the previously-analysed boundaries, it is possible to get the map of
all the main operating regions of the converter. In particular this is performed for the LLC
circuit characterised in the design example of the previous section and the results are shown
in the following.
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 72

Figure 5.9: Map of regions of the designed converter

The computational effort required to find this chart is rather heavy but the advantage is that
then every signal can be quantitatively evaluated as a function of the frequency and/or of the
output load. Moreover, once the map of operating regions is obtained, it is easy to plot the
operating curve of the LLC converter, i.e. the behaviour of the output voltage as a function
of the frequency, for a fixed value of the output load. In particular, considering RL = 1.92
(which is the value resulting from the specifications of the design example under exam), the
following plot is obtained:

Figure 5.10: Operating curve of the designed LLC

The circles on the operating curve represent the values extracted from LTspice simulations
of the LLC lossy schematic, taking into account the duration of the dead-time (Figure 5.8):
as clearly evident, the MATLAB model is able to accurately predict the behaviour of the
 CHAPTER 5. MODELLING AND DESIGN WITH PARASITIC EFFECTS 73

converter. Of course, as already highlighted, any other signal of the circuit can be studied
as a function of the frequency and/or the output load. For example, it is possible to evaluate
the frequency trend of the resonant current magnitude at half-period (i.e. Ir (T /2)), useful
to understand at what frequencies the LLC is able to work in ZVS. An example of this kind
of study (referring to the already quoted designed LLC converter) is shown in the following
figure, where the data obtained from the MATLAB model (solid lines) are also compared
to the corresponding values (evaluated at T /2 − TD ) extracted from LTspice simulations
(circles):

Figure 5.11: Trend of Ir (T /2) as a function of the normalised frequency

Chapter 6

Conclusion

Different approaches to the analysis and design of half-bridge LLC resonant power con-
verters has been shown, highlighting differences, advantages and limitations. In the first
place, the FHA model has been studied in detail, showing how it can be used to approxi-
mately describe the LLC operation and how a design flow can be based on it. Then, a less
approximate analysis has been described, based on the exact time-domain solution of the
differential equations characterising the lossless converter. Also in this case, a design flow
has been provided. Finally, the influence of parasitic elements (resistances, in particular)
has been studied. Hence, an exact design method oriented to the optimal operation of the
lossy converter in one specific operating point has been developed. Then, the same analytical
approach exploited in this design procedure has been modified to find a thorough and rather
accurate description of the signals of the lossy converter circuit when changing the switching
frequency and/or the output power. The main results of this analysis have been compared
to LTspice simulations of the lossy LLC converter, in order to prove the high accuracy level
reached through the developed model. Possible improvements of the presented design and
analysis methods concern the development of an enhanced design procedure (always based
on the accurate description of the lossy LLC converter) capable of ensuring soft-switching (in
terms of ZVS) despite the variations of the input voltage in a limited range and the choice of
a circuital normalisation able to provide a more general description. Moreover, the presented
approach could also be used for the study of other non-idealities afflicting the LLC converter.

74
 Appendix A

MATLAB scripts

A.1 FHA design

1 g l o b a l Q_max Q_ZVS2 f r lambda m_max C_ZVS Vin_min T_D P o u t

2

3 Vin_nom = 4 0 0 ;
4 Vin_min = 3 8 0 ;
5 Vin_max = 4 2 0 ;
6 Vout = 3 0 ;
7 Iout = 10;
8 P o u t = Vout ∗ I o u t ;
9 f r = 120 e3 ;
10 fmax = 150 e3 ;
11 C_ZVS = 400 e −12;
12 T_D = 200 e −9;
13 perc_0 = 0.95;
14

15 % A)
16

17 n = ( 1 / 2 ) ∗Vin_nom / Vout ;
18

19 % B)
20

21 m_min = 2∗ n∗ Vout / Vin_max ;

22 fn_max = fmax / f r ;
23

24 lambda = ( ( 1 − m_min ) / m_min ) ∗ ( fn_max ^ 2 ) / ( fn_max ^2 − 1 ) ;

25 lm = 1 / lambda ;
26

27 % C)
28

29 m_max = 2∗ n∗ Vout / Vin_min ;

30 Q_max = ( lambda / m_max ) ∗ s q r t ( 1 / lambda + ( m_max ^ 2 ) / ( m_max^2 −
1) ) ;
31

75
 APPENDIX A. MATLAB SCRIPTS 76

32 Rac = ( 8 / ( p i ^ 2 ) ) ∗ ( n ^ 2 ) ∗ ( ( Vout ^ 2 ) / P o u t ) ;
33

34 Q_ZVS2 = ( 2 / p i ) ∗ ( lambda ∗ fn_max / ( ( lambda + 1 ) ∗ fn_max ^2 −

lambda ) ) ∗T_D / ( Rac ∗C_ZVS ) ;
35

36 f = @Q_ZVS_eval ;
37 perc = fzero ( f , perc_0 ) ;
38

39 Q_ZVS1 = p e r c ∗Q_max ;
40

41 Q_ZVS = min ( [ Q_ZVS1 Q_ZVS2 ] ) ;

42

43 % F i n a l c o m p u t a t i o n o f LLC c o m p o n e n t s
44

45 Zo = Q_ZVS∗ Rac ;
46

47 Cr = 1 / ( 2 ∗ p i ∗ f r ∗Zo ) ;
48 Lr = Zo / ( 2 ∗ p i ∗ f r ) ;
49 Lm = Lr / lambda ;
50

51 % Check i f ZVS c o n s t r a i n t i s a c t u a l l y r e s p e c t e d
52

53 f u n c t i o n y = Q_ZVS_eval ( x )
54

55 g l o b a l Q_max Q_ZVS2 f r lambda m_max C_ZVS Vin_min T_D P o u t

56

57 Q_ZVS1 = x∗Q_max ;
58

59 Q_ZVS = min ( [ Q_ZVS1 Q_ZVS2 ] ) ;

60

61 f _ m i n = f r ∗ s q r t ( 1 / ( 1 + ( 1 / lambda ) ∗ ( 1 − 1 / power ( m_max , 1 + (

Q_ZVS / Q_max ) ^ 4 ) ) ) ) ;
62 fn_min = f_min / f r ;
63

64 %% ZVS c h e c k a t f u l l l o a d and f m i n
65

66 Zn = 1 j ∗ f n _ m i n / ( lambda + 1 j ∗ f n _ m i n ∗Q_ZVS ) + ( 1 − f n _ m i n ^ 2 ) / ( 1
j ∗ fn_min ) ;
67 y = imag ( Zn ) / r e a l ( Zn ) − C_ZVS ∗ ( Vin_min ^ 2 ) / ( p i ∗T_D∗ P o u t ) ;
68 y = y − 0 . 1 ; %( t o i m p o s e some m a r g i n )
69
 APPENDIX A. MATLAB SCRIPTS 77

70 end

A.2 ARHP steady-state analysis (lossless LLC)

1 g l o b a l x lm Vr0n Vr2n
2

3 % D e f i n i t i o n o f main v a r i a b l e s
4 m = 0.6;
5 x = m/ 2 ;
6 lm = 5 ;
7 AVrn = 1 . 6 4 2 ;
8

9 Vr0n = ( 1 − AVrn ) / 2 ;
10 Vr2n = Vr0n + AVrn ;
11

12 f u n = @root4d ;
13

14 % Vector of i n i t i a l guess
15 x0 = [ − 1 . 5 , − 0 . 0 5 , 0 . 7 , 2 ] ;
16

17 y = f s o l v e ( fun , x0 ) ;
18 Ir0n = y (1)
19 Im0n = y ( 2 )
20 theta0 = y (3)
21 theta1 = y (4)
22

23 fswn = p i / ( t h e t a 0 + t h e t a 1 )
24

25 % AH c o n s t r a i n t s i m p l e m e n t e d i n a f u n c t i o n
26 function F = root4d (y )
27

28 % y ( 1 ) = I r 0 n ; y ( 2 ) =Im0n ; y ( 3 ) = t h e t a 0 ; y ( 4 ) = t h e t a 1
29

30 g l o b a l x lm Vr0n Vr2n
31

32 I r 1 n = ( 1+ x−Vr0n ) ∗ s i n ( y ( 3 ) ) +y ( 1 ) ∗ c o s ( y ( 3 ) ) ;
33 Im1n = −x∗y ( 3 ) / lm+y ( 2 ) ;
34 Vr1n =(1+ x ) −(1+x−Vr0n ) ∗ c o s ( y ( 3 ) ) +y ( 1 ) ∗ s i n ( y ( 3 ) ) ;
35

36 F ( 1 ) = (1−x−Vr1n ) ∗ s i n ( y ( 4 ) ) + I r 1 n ∗ c o s ( y ( 4 ) ) + y ( 1 ) ;
37 F ( 2 ) = x∗y ( 4 ) / lm+Im1n + y ( 2 ) ;
 APPENDIX A. MATLAB SCRIPTS 78

38 F ( 3 ) = (1−x ) −(1−x−Vr1n ) ∗ c o s ( y ( 4 ) ) + I r 1 n ∗ s i n ( y ( 4 ) ) − Vr2n ;

39 F ( 4 ) = I r 1 n −Im1n ;
40

41 end

A.3 RHP border (lossy LLC)

1 g l o b a l Vin VD1_on VD2_on R_M R_D Lr Lm Cr n

2

3 % P a r a m e t e r s o f t h e c o n v e r t e r u n d e r exam
4 Vin = 4 0 0 ;
5 Td = 90 e −9;
6 C1 = 100 e −12;
7 C2 = 100 e −12;
8 Cr = 2 . 2 0 6 7 2 0 3 3 8 6 1 6 6 9 4 e −08;
9 Lm = 6 . 0 2 8 2 9 5 4 7 4 5 6 2 0 0 4 e −04;
10 Lr = Lm / 3 ;
11 VD1_on = 0 ;
12 VD2_on = 0 ;
13 n = 7.728849370975870;
14 Tr = 2∗ p i ∗ s q r t ( Lr ∗ Cr ) ;
15 R_M = 1 ;
16 R_D = 0 . 1 ;
17

18 % I n i t a l g u e s s o f unknowns
19 Vr_0 = −41.221126719601630;
20 I r _ 0 = −1.2∗( C1+C2 ) ∗ Vin / Td ;
21 Vout_0 = 2 4 ;
22 f r _ e f f = 7 5 . 8 7 4 e3 ;
23 T_0 = 1 / f r _ e f f ;
24

25 fn = zeros (1 ,83) ;
26 Vo = z e r o s ( 1 , 8 3 ) ;
27

28 options = optimset ( ’ Display ’ , ’ i t e r ’ , ’ PlotFcns ’ , @optimplotfval

, ’ TolFun ’ , 1 e −9 , ’ MaxFunEvals ’ , 2 5 0 0 ) ;
29

30 tic
31 f o r i =1:83
32 Rl = 8 . 2 7 8 1 5 2 9 4 0 1 7 0 9 0 9 − 0 . 1 ∗ ( i −1) ;
33
 APPENDIX A. MATLAB SCRIPTS 79

34 f = @( x ) norm ( e n d _ c o n d _ f i n d e r ( x ( 1 ) , x ( 2 ) , x ( 3 ) , x ( 4 ) ) −[x ( 1 ) ,
0 , x ( 2 ) , x ( 3 ) / Rl ] ) ;
35 [ X _ s t a r t , f v a l , e x i t f l a g , o u t p u t ] = f m i n s e a r c h ( f , [ Vr_0 , I r _ 0 ,
Vout_0 , T_0 ] , o p t i o n s ) ;
36

37 Vr_0 = X _ s t a r t ( 1 ) ;
38 Ir_0 = X_start (2) ;
39 Vout_0 = X _ s t a r t ( 3 ) ;
40 T_0 = X _ s t a r t ( 4 ) ;
41

42 f n ( i ) = Tr / T_0 ;
43 Vo ( i ) = Vout_0 ;
44 end
45 toc
46

47 p l o t ( fn , Vo ) ;
48 x l a b e l ( ’ fn ’ ) ;
49 y l a b e l ( ’Vo ’ ) ;
50

51 f u n c t i o n y = e n d _ c o n d _ f i n d e r ( Vr0 , I r 0 , Vout , T )
52

53 g l o b a l Vin VD1_on R_M R_D Lr Lm Cr n

54

55 % ZONE 1MD
56

57 A1 = [ 0, 0,
1 / Cr ;
58 −n / Lr , −(n ∗ (Lm∗R_D∗n + Lr ∗R_D∗n ) ) / ( Lm∗ Lr ) , −(R_M∗n ) / Lr ;
59 −1/ Lr , −(R_D∗n ) / Lr , −R_M/ Lr ] ;
60

61 b1 = [

0;
62 −(n ∗ (Lm∗VD1_on∗n − Lm∗ Vin + Lr ∗VD1_on∗n + Lm∗ Vout ∗n +
Lr ∗ Vout ∗n ) ) / ( Lm∗ Lr ) ;
63 −(VD1_on∗n −
Vin +
Vout ∗n ) /
Lr ] ;
64

65 xp1 = −A1 \ b1 ;
 APPENDIX A. MATLAB SCRIPTS 80

66

67 [EVEC , EVAL] = e i g ( A1 ) ;
68 x0 = [ Vr0 ; 0 ; I r 0 ] ;
69 K = e y e ( 3 ) ∗ (EVEC \ ( x0−xp1 ) ) ;
70 x1_end = r e a l (EVEC∗ ( d i a g ( exp ( d i a g (EVAL) ∗ ( T / 2 ) ) ) ∗K) + xp1 ) ;
71

72 y ( 1 ) = Vin − x1_end ( 1 ) ;
73 y ( 2 ) = x1_end ( 2 ) ;
74 y ( 3 ) = −x1_end ( 3 ) ;
75

76 k1 = K( 1 ) ∗EVEC ( 2 , 1 ) / EVAL ( 1 , 1 ) ;
77 k2 = K( 2 ) ∗EVEC ( 2 , 2 ) / EVAL ( 2 , 2 ) ;
78 k3 = K( 3 ) ∗EVEC ( 2 , 3 ) / EVAL ( 3 , 3 ) ;
79 y ( 4 ) = ( r e a l ( k1 ∗ ( exp (EVAL ( 1 , 1 ) ∗T / 2 ) −1) + k2 ∗ ( exp (EVAL ( 2 , 2 ) ∗T
/ 2 ) −1) + k3 ∗ ( exp (EVAL ( 3 , 3 ) ∗T / 2 ) −1) ) + xp1 ( 2 ) ∗T / 2 ) / ( T / 2 ) ;
80

81 end

A.4 Proposed design (lossy LLC)

1 g l o b a l Vin VD1_on VD2_on Vout Td C1 C2 R_M R_D T I r _ 0

2

3 % Specifications
4 Vin = 4 0 0 ;
5 Td = 90 e −9;
6 C1 = 100 e −12;
7 C2 = 100 e −12;
8 I r _ 0 = −1.2∗( C1+C2 ) ∗ Vin / Td ; % −IZVS
9 VD1_on = 0 ;
10 VD2_on = 0 ;
11 Vout = 2 4 ;
12 f _ o p = 7 5 . 8 7 4 e3 ;
13 T = 1/ f_op ;
14 R_M = 1 ;
15 R_D = 0 . 1 ;
16 Rl = 1 . 9 2 ;
17

18 % I n i t i a l g u e s s o f unknowns
19 n_0 = 7 . 7 2 8 8 4 9 3 7 0 9 7 5 8 7 0 ;
20 Vr_0 = −41.221126719601630;
21 Lm_0 = 6 . 0 2 8 2 9 5 4 7 4 5 6 2 0 0 4 e −04;
 APPENDIX A. MATLAB SCRIPTS 81

22 Cr_0 = 2 . 2 0 6 7 2 0 3 3 8 6 1 6 6 9 4 e −08;
23

24 f = @( x ) norm ( e n d _ c o n d _ f i n d e r ( x ( 1 ) , x ( 2 ) , x ( 3 ) , x ( 4 ) ) −[x ( 2 ) ,
0 , I r _ 0 , Vout / Rl ] ) ;
25

26 options = optimset ( ’ Display ’ , ’ i t e r ’ , ’ PlotFcns ’ , @optimplotfval

, ’ TolFun ’ , 1 e −9 , ’ MaxFunEvals ’ , 2 5 0 0 , ’ M a x I t e r ’ , 2 5 0 0 ) ;
27 tic
28 % M i n i m i s a t i o n o f t h e norm
29 [ X _ s t a r t , f v a l , e x i t f l a g , o u t p u t ] = f m i n s e a r c h ( f , [ n_0 , Vr_0 , Lm_0
, Cr_0 ] , o p t i o n s ) ;
30 toc
31

32 % Final values
33 n = X_start (1) ;
34 Vr = X _ s t a r t ( 2 ) ;
35 Lm = X _ s t a r t ( 3 ) ;
36 Lr = Lm / 3 ;
37 Cr = X _ s t a r t ( 4 ) ;
38

39 f u n c t i o n y = e n d _ c o n d _ f i n d e r ( n , Vr0 , Lm, Cr )
40

41 g l o b a l Vin VD1_on Vout R_M R_D T I r _ 0

42

43 Lr = Lm / 3 ;
44

45 % ZONE 1M1D
46

47 A1 = [ 0, 0,
1 / Cr ;
48 −n / Lr , −(n ∗ (Lm∗R_D∗n + Lr ∗R_D∗n ) ) / ( Lm∗ Lr ) , −(R_M∗n ) / Lr ;
49 −1/ Lr , −(R_D∗n ) / Lr , −R_M/ Lr ] ;
50

51 b1 = [

0;
52 −(n ∗ (Lm∗VD1_on∗n − Lm∗ Vin + Lr ∗VD1_on∗n + Lm∗ Vout ∗n +
Lr ∗ Vout ∗n ) ) / ( Lm∗ Lr ) ;
53 −(VD1_on∗n −
Vin +
Vout ∗n ) /
 APPENDIX A. MATLAB SCRIPTS 82

Lr ] ;
54

55 xp1 = −A1 \ b1 ;
56

57 [EVEC , EVAL] = e i g ( A1 ) ;
58 x0 = [ Vr0 ; 0 ; I r _ 0 ] ;
59 K = e y e ( 3 ) ∗ (EVEC \ ( x0−xp1 ) ) ;
60

61 x1_end = r e a l (EVEC∗ ( d i a g ( exp ( d i a g (EVAL) ∗ ( T / 2 ) ) ) ∗K) + xp1 ) ;

62

63 y ( 1 ) = Vin − x1_end ( 1 ) ;
64 y ( 2 ) = x1_end ( 2 ) ;
65 y ( 3 ) = −x1_end ( 3 ) ;
66

67 k1 = K( 1 ) ∗EVEC ( 2 , 1 ) / EVAL ( 1 , 1 ) ;
68 k2 = K( 2 ) ∗EVEC ( 2 , 2 ) / EVAL ( 2 , 2 ) ;
69 k3 = K( 3 ) ∗EVEC ( 2 , 3 ) / EVAL ( 3 , 3 ) ;
70 y ( 4 ) = ( r e a l ( k1 ∗ ( exp (EVAL ( 1 , 1 ) ∗T / 2 ) −1) + k2 ∗ ( exp (EVAL ( 2 , 2 ) ∗T
/ 2 ) −1) + k3 ∗ ( exp (EVAL ( 3 , 3 ) ∗T / 2 ) −1) ) + xp1 ( 2 ) ∗T / 2 ) / ( T / 2 ) ;
71

72 end

A.5 ZCS from BVRHP (lossy LLC)

1 % 1M1D−1M2D
2

3 g l o b a l Lr Cr Lm Vin VD1_on VD2_on R_M R_D n Vout

4

5 % P a r a m e t e r s o f t h e c o n v e r t e r u n d e r exam
6 Cr = 2 . 2 0 6 7 2 0 3 3 8 6 1 6 6 9 4 e −08;
7 Lm = 6 . 0 2 8 2 9 5 4 7 4 5 6 2 0 0 4 e −04;
8 Lr = Lm / 3 ;
9 Vin = 4 0 0 ;
10 VD1_on = 0 ;
11 VD2_on = 0 ;
12 n = 7.728849370975870;
13 R_M = 1 ;
14 R_D = 0 . 1 ;
15 fn = zeros (1 ,170) ;
16 Rl_v = z e r o s ( 1 , 1 7 0 ) ;
17 Vo = z e r o s ( 1 , 1 7 0 ) ;
 APPENDIX A. MATLAB SCRIPTS 83

18

19 % I n i t a l g u e s s o f t h e unknowns
20 TD1_0 = 5 . 9 4 3 0 6 9 2 8 3 2 8 0 9 3 4 e −06;
21 TD2_0 = 2 . 3 5 0 4 7 8 2 0 4 9 6 8 5 7 7 e −06;
22 Vr_0 = −4.024684998907401 e + 0 2 ;
23 ID1_0 = 5 . 3 4 9 2 5 7 8 1 7 5 0 9 8 8 3 ;
24 Rl_0 = 1 . 6 8 5 1 7 8 6 7 1 5 3 3 4 6 7 ;
25

26 options = optimset ( ’ Display ’ , ’ i t e r ’ , ’ PlotFcns ’ , @optimplotfval

, ’ TolFun ’ , 1 e −9 , ’ MaxFunEvals ’ , 2 5 0 0 , ’ M a x I t e r ’ , 2 5 0 0 ) ;
27 tic
28 f o r i =1:170
29 Vout = 2 7 . 1 − 0 . 1 ∗ i ;
30 f = @( x ) norm ( e n d _ c o n d _ f i n d e r ( x ( 1 ) , x ( 2 ) , x ( 3 ) , x ( 4 ) , x ( 5 ) ) −[
x ( 3 ) , x ( 4 ) , 0 , 0 , Vout ] ) ;
31 [ X _ s t a r t , f v a l , e x i t f l a g , o u t p u t ] = f m i n s e a r c h ( f , [ TD1_0 , TD2_0 ,
Vr_0 , ID1_0 , Rl_0 ] , o p t i o n s ) ;
32 TD1_0 = X _ s t a r t ( 1 ) ;
33 TD2_0 = X _ s t a r t ( 2 ) ;
34 Vr_0 = X _ s t a r t ( 3 ) ;
35 ID1_0 = X _ s t a r t ( 4 ) ;
36 Rl_0 = X _ s t a r t ( 5 ) ;
37 Rl_v ( i ) = Rl_0 ;
38 f n ( i ) = p i ∗ s q r t ( Lr ∗ Cr ) / ( TD1_0+TD2_0 ) ;
39 Vo ( i ) = Vout ;
40 end
41 toc
42

43 p l o t ( fn , Vo )
44 x l a b e l ( ’ fn ’ )
45 y l a b e l ( ’ Vout [V] ’ )
46

47 f u n c t i o n y = e n d _ c o n d _ f i n d e r ( TD1 , TD2 , Vr0 , ID10 , Rl )

48

49 g l o b a l Lr Vin VD1_on VD2_on R_M R_D Lm Cr n Vout

50

51 y (1) = 10;
52 y (2) = 10;
53 y (3) = 10;
54 y (4) = 10;
55 y (5) = 10;
 APPENDIX A. MATLAB SCRIPTS 84

56

57 i f TD1 > 0
58 i f TD2 > 0
59 i f Rl > 0
60

61 x0 = [ Vr0 ; ID10 ; 0 ] ;
62

63 % ZONE 1M1D
64 A1 = [ 0, 0,
1 / Cr ;
65 −n / Lr , −(n ∗ (Lm∗R_D∗n + Lr ∗R_D∗n ) ) / ( Lm∗ Lr ) , −(R_M∗n ) / Lr ;
66 −1/ Lr , −(R_D∗n ) / Lr , −R_M/ Lr ] ;
67

68 b1 = [

0;
69 −(n ∗ (Lm∗VD1_on∗n − Lm∗ Vin + Lr ∗VD1_on∗n + Lm∗ Vout ∗n +
Lr ∗ Vout ∗n ) ) / ( Lm∗ Lr ) ;
70 −(VD1_on∗n −
Vin +
Vout ∗n ) /
Lr ] ;
71

72 xp1 = −A1 \ b1 ;
73

74 [EVEC , EVAL] = e i g ( A1 ) ;
75 K = e y e ( 3 ) ∗ (EVEC \ ( x0−xp1 ) ) ;
76 x1_end = r e a l (EVEC∗ ( d i a g ( exp ( d i a g (EVAL) ∗TD1 ) ) ∗K) + xp1 ) ;
77

78 k1 = K( 1 ) ∗EVEC ( 2 , 1 ) / EVAL ( 1 , 1 ) ;
79 k2 = K( 2 ) ∗EVEC ( 2 , 2 ) / EVAL ( 2 , 2 ) ;
80 k3 = K( 3 ) ∗EVEC ( 2 , 3 ) / EVAL ( 3 , 3 ) ;
81 i n t 1 = ( r e a l ( k1 ∗ ( exp (EVAL ( 1 , 1 ) ∗TD1 ) −1) + k2 ∗ ( exp (EVAL ( 2 , 2 ) ∗
TD1 ) −1) + k3 ∗ ( exp (EVAL ( 3 , 3 ) ∗TD1 ) −1) ) + xp1 ( 2 ) ∗TD1 ) ;
82

83 % ZONE 1M2D
84 A2 = [ 0, 0, 1 / Cr ;
85 n / Lr , −(n ∗ (Lm∗R_D∗n + Lr ∗R_D∗n ) ) / ( Lm∗ Lr ) , (R_M∗n ) / Lr ;
86 −1/ Lr , ( R_D∗n ) / Lr , −R_M/ Lr ] ;
87

88 b2 = [
 APPENDIX A. MATLAB SCRIPTS 85

0;
89 −(n ∗ (Lm∗ Vin + Lm∗VD2_on∗n + Lr ∗VD2_on∗n + Lm∗ Vout ∗n + Lr ∗
Vout ∗n ) ) / ( Lm∗ Lr ) ;
90 ( Vin + VD2_on∗n
+ Vout ∗n ) /
Lr ] ;
91

92 xp2 = −A2 \ b2 ;
93

94 [EVEC , EVAL] = e i g ( A2 ) ;
95 K = e y e ( 3 ) ∗ (EVEC \ ( x1_end−xp2 ) ) ;
96 x2_end = r e a l (EVEC∗ ( d i a g ( exp ( d i a g (EVAL) ∗TD2 ) ) ∗K) + xp2 ) ;
97

98 k1 = K( 1 ) ∗EVEC ( 2 , 1 ) / EVAL ( 1 , 1 ) ;
99 k2 = K( 2 ) ∗EVEC ( 2 , 2 ) / EVAL ( 2 , 2 ) ;
100 k3 = K( 3 ) ∗EVEC ( 2 , 3 ) / EVAL ( 3 , 3 ) ;
101 i n t 2 = ( r e a l ( k1 ∗ ( exp (EVAL ( 1 , 1 ) ∗TD2 ) −1) + k2 ∗ ( exp (EVAL ( 2 , 2 ) ∗
TD2 ) −1) + k3 ∗ ( exp (EVAL ( 3 , 3 ) ∗TD2 ) −1) ) + xp2 ( 2 ) ∗TD2 ) ;
102

103 y (1) = Vin − x2_end ( 1 ) ;

104 y (2) = x2_end ( 2 ) ;
105 y (3) = −x2_end ( 3 ) ;
106 y (4) = x1_end ( 2 ) ;
107 y (5) = Rl ∗ ( i n t 1 + i n t 2 ) / ( TD1+TD2 ) ;
108

109 end
110 end
111 end
112

113 end
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