Scribd
Upload
77 views8 pages

Netlist GDS

Uploaded by

kishorechiya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
77 views8 pages

Netlist GDS

Uploaded by

kishorechiya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 8

NETLIST TO GDS

File--> import--> verilog

Add Layout name in LAYOUT CELL:


Verilog NETLIST: add netlist file (verliog file that got generated from Leonardo Spectrum )
ADD Process : (from $ADK/technology/ic/process/ami05)
Rule: $ADK/technology/ic/process/ami05.rules
Library : $ADK/technology/ic/process/ami05

Click OK:

A Layout window comes.

From the right hand IC PALLATE: go to Plan & place (end of the pallate)

Go to Floorplanner & click on Autofp--> OK


You will be getting a row like structure:
In the same pallete – Auto Placement--> STDCELLS--> select the area inside the rows:
Auto Placement--> PORTS-->OK

Blocks and ports will be placed.

Select the total layout. Go to ROUTE on the top.


Go to Aroute Commands--> RUN--> Routing will be done:

If there are overflows, please do it manually.


Calibre Physical Verification.
First make the schematic from verilog code:

Open Design Architect : da_ic

File-> import Verilog...

Netlist--> add netlist file (file from Leonardo Spectrum)


Output Directory: some directory as o/p
MAP File : $ADK/technology/adk_map.vmp

Click OK.

File --> Open the schematic that got generated in output folder.

Make symbol for the schematic

Add--> generate Symbol.--> OK

A symbol gets generated. Check & Save it.

Now close all the schematic & symbols.

Create a new schematic by File--> New--> schematic ; give some name & OK

Add the symbol in new schematic ; Add--> Instance--> Choose symbol.


Select the symbol of schematic that got generated.

Go for simulation on the right hand side pallet & click for new configuration, select Spice Netlister
from it. OK & OK, it will entering into simulation environment.

Just click on Netlist on right hand side pallete.

A Spice- netlist file gets generated.

Calibre DRC;

Close the design architect.

In ICStation, Tools--> Calibre--> RUN DRC; Cancel the rule rest window.;

Add Rules: $ADK/technology/ic/process/ami05.rules

Click on RUN DRC; Check DRC errors if any ; Make DRC errors “ZERO”

Once DRC is clean close DRC tool


Calibre LVS:
In ICStation, File--> Export--> Calibre; A window gets opened --> Options-->ChecK “ADD TEXT on
PORTS ” On right hand side. OK--> Cancel;

In ICStation, Tools--> Calibre-->RUN LVS;

Add Rules: $ADK/technology/ic/process/ami05.rules;


Input: Netlist--> Browse and add the netlist that got generated in design architect. (schematic folder-->
eldonet--> .spi file )

In TOP CELL: give the same name of schematic/ verilog module

INPUT-> HCELLS--> USE H-CELLS FILE: $ADK/technology/adk.hcell

RUN LVS:

If there are any shorts/opens please check the layout connections.


Once LVS is clean ,close the Calibre nmLVS tool.

Calibre Parasitic extraction:

In ICStation, Tools--> Calibre-->RUN PEX;

Add Rules: $ADK/technology/ic/process/ami05.rules;


Input: Netlist--> Browse and add the netlist that got generated in design architect. (schematic folder-->
eldonet--> .spi file )

In TOP CELL: give the same name of schematic/ verilog module


Outputs: Extraction Type: Tranisitor Level, R + C;
Format DSPF ; Use Names from: Schematic

RUN PEX;

You will be getting a XXX.PEX.NETLIST


Post Layout Simulation:

Add these commands at the end of the DSPF file that got generated. (Source_X is the source name in
circuit)

V2 Source_1 0 PULSE ( 0V 5V 1nS 1nS 1nS 20nS 50nS )

V1 Source_2 0 PULSE ( 0V 5V 1nS 1nS 1nS 20nS 50nS )

X_XXX GND VCC GROUND (PORTS) VDD XXX


(Make sure the names & ports in the last line)

---Make a file test.cir & place these in them

.LIB $ADK/technology/ic/models/ami05.mod

.Plot TRAN V(*)

.INCLUDE XXX.pex.netlist

VFORCE__VDD VDD 0 dc 5

VFORCE__GND GND 0 dc 0

VFORCE__GROUND GROUND 0 dc 0

.OPTION NOASCII

.OPTION MODWL

.OPTION ENGNOT

.OPTION AEX

.TEMP 27

.TRAN 0 1000N

(Make sure the names & ports in the last line)

Simulate on terminal using : “eldo test.cir” command

view waves using : “ezwave command.”

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy