Scribd
Upload
15 views2 pages

Tutorial 8

Uploaded by

pizza.kataleya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
15 views2 pages

Tutorial 8

Uploaded by

pizza.kataleya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

EE210A: Microelectronics I

Problem Set 8
Instructor: Imon Mondal, imon@iitk.ac.in

1) : Consider VDD =5V, R1 = 3kΩ, R2 = 2kΩ, VDD


R3 = 1kΩ, RD = 3kΩ, |Vtp | = 1V , µp Cox = Moa Mo
100µA/V 2 , W/L = 20, C1 = 10pF , C2 = 1pF 40 40
(Ignore CLM)
a) : Find vo (jω)/vi (jω). M1 M2
Io
b) : Plot the bode-plot for the gain and phase of 20 20 Vcm-vi/2
vo (jω)/vi (jω).
Vcm+vi/2
Vo
c) : What are the corner frequencies? M3 M4
d) : What are the pole and zero locations of 10 10
vo (s)/vi (s)?

Figure 2: Problem 2.

3) : Refer figure3.
VDD a) : Find vo1 /vi and vo2 /vi symbolically.
b) : Find incremental and quiescent vX .
C1 R2 c) : Find the max and min Vi which will keep all
the transistors in saturation. Assume R << rds
for any transistor.
RS d): If the inputs to M1 and M2 are Vcm + vicm
R1 RD CL then find the vo1 /vicm , and the swing limits of
vi vicm .

VDD

Figure 1: Problem 1. Io

Vcm+vi/2 M1 M2 Vcm-vi/2

R Vx R
Vo2 Vo1

M3 M4

2) : Consider µn Cox = 200µA/V 2 ,


µp Cox = 100µA/V 2 Io = 2mA, |Vtp | = 1V Figure 3: Problem 3.
λn = λp = 0.1V −1 and VDD = 3V .
a) : Find vo /vi (make necessary approximations).
b) : Find the max(Vcm ) and min(Vcm ) which
you can have while keeping all transistors in
saturation. Assume Vo(quiescent) = 1V, 1.5V
c) : How will you change the design to increase
max(Vcm ) by 500mV?
4) : Assume M1 is biased in saturation,
C1 → ∞, R1 ||R2 → ∞. (Ignore CLM)
a) : Find vo (s)/vi (s).
b) : Sketch the bode-magnitude plot of
|vo (jω)/vi (jω)| while marking the poles and
zeros. Assume the poles are far apart from each
other.
VDD

R1 Cgd RD
C1 vo
Rs
M1
R2 Cdb
vi
Cgs

Figure 4: Problem 4.

5) : Figure (i) and (ii) shows two possible out-


put stages, being driven by a Gm (which has an in-
cremental o/p resistance r1 ). Assume Gm r1 =100.
a) : Find the quiescent Vo in (i) and (ii).
b) : Find the open-loop o/p impedance in both the
architectures.
c) : Find the max and min possible Vo . Assume Io
requires at least 100mV across it to behave like a
current source.

VDD=5V

M2
VB+vi

vo
GM
r1 M1

(i)

VDD=5V

Io

V3
M3
VB+vi
M1

GM Vo
r1
M2
M4
V4

Io
(ii)

Figure 5: Problem 5.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy