PH4418 Physics in Industry-

Semiconductor Industry
Part 5

SZU HUAT, GOH

Outline
• Introduction to Semiconductor Industry and Manufacturing
• Introduction to Semiconductor Memories
• Introduction to Integrated Circuits Product Test and Yield Engineering
• Introduction to Failure Analysis
• Opportunities of AI / Machine/ Deep Learning in Semiconductor Industry

• Quiz ( 5th lesson): 25%

2
Learning Objectives
Opportunities of AI / Machine/ Deep Learning in Semiconductor Industry
• Introduction to Machine Learning Algorithms
• Understand the significance of machine learning workflow and deployment
• Introduction to applications in different functional domains
• Appreciate the challenges involved

3
Scope
Opportunities of AI / Machine/ Deep Learning in Semiconductor Industry
• Trends
• Overview of semiconductor industries – scope: Foundry and Fabless
• Distinguish between AI/ML/Deep learning
• Hype cycle- what it means to us
• Where to start
• Paint points, value proposition, biz case
• Types of data
• List some algorithms of machine learning and their applications
• Foundry applications
• Process
• PCM
• Yield
• Fabless applications
• Design
• Test
• FA

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Artificial Intelligence

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Automation Vs AI

Automation Algorithm ML Algorithm

Automates processes Automates processes
Coded recipe create new algorithms, adapt and
grow based on new data
(“intelligence”)
Criteria for actions are preset Criteria for actions are train
Takes action based on instructions Takes action based on data
More control and transparency in “black box” techniques
maintenance and re-calibration

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Decision Consideration

Automation AI
Cost of slow decisions is not high Speed for decision is critical
Cost of wrong decisions is high Cost of wrong decisions is low
Data size is small, or at least not too Data size is too big for manual
big analysis or traditional algorithm
Ability to explain is critical Prediction accuracy is more
important
Regulatory requirements are less

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Before you embark on any ML projects

? Pain-point
• Motivation

? Problem to Solve
• Capability
• Productivity

? Automation or ML

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Opportunities of AI in our work

• Accelerate Productivity and Enhance Capability

• Finding issues earlier
• More effective learning
• Finding issues that really matters (significant)
• Harness strengths (in volume data) and overcome limitations of conventional
workflows

• Innovate
• Think out-of-the-box
• Leverage Cross-functional domain knowledge to discover unknown
relationships

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History…

200 million possible chess positions/s

10360 possible moves

The Birth of Internet

AlphaGo

Deep Blue

1950s 1960s 1970s 1980s 1990s 2000s 2010s

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 # Publications in Semiconductor Manufacturing

[Source: Pedro Espadinha-Cruz, Processes 2021, 9, 305. https://doi.org/10.3390/pr9020305] 11

Artificial Intelligence

A program that can sense, reason, act, adapt

creation of machines having intelligence

Algorithm that improves from data

ability to “learn” with data

Large models that improve from vast data

inspired from the structural and functional behavior of
brain(the network of billion’s of the neuron)

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Semiconductor Driving Forces

Deep blue AlphaGo

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Hype Cycle for AI , 2022

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 Approaches

Deep Network for Defect

Pattern Recognition

Convolutional Generative
Auto-encoder (AE)
Neural Network Adversial Network
(CNN) (GAN)

Custom-made CNN for multi-label Pre-defined CNN

CNN for single- defect and Transfer
label defect classification Learning
classification

[U. Batool, M. I. Shapiai, M. Tahir, Z. H. Ismail, N. J. Zakaria and A. Elfakharany, "A Systematic Review of Deep Learning for Silicon Wafer Defect Recognition," in IEEE Access, vol. 9, pp. 116572-
116593, 2021, doi: 10.1109/ACCESS.2021.3106171.]
Convolutional Neural Network
Fully connected
Feature extraction layer (Hidden
(Convolution and pooling) layer in ANN)
Image
Input Image Processing

Classification

Convolution ≈ apply filters to extract features

Pooling ≈ downsampling matrix e.g. Max pooling

Machine Learning: A Simple Perspective

Simple Regression Complex relationship,

Modelling required
Neural Network Learning
 Artificial
Intelligence

Machine Automation Optimization

Learning

Supervised Unsupervised Reinforcement Evolutionary

Learning Learning Learning Computation
Task-driven Data-driven Learn from mistake Biological Evolution
Data without
Data with Label Decision Making Metaheuristic
Label

Classification Regression Clustering Dimension Model-free

Model-free
Reduction*
1. Genetic
1. Logistic 1. Linear 1. K-means 1. Principal 1. Q-Learning Algorithm
Regression Regression 2. Gaussian Mixture Component 2. R-Learning 2. Particle swarm
2. Naïve Bayes 2. Ordinary least 3. Hierarchical Analysis 3. Ant colony
3. K-nearest Squares 4. Density-Based
neighbour Regression Spatial Clustering of
4. Neural network 3. Ride Regression Applications with
5. Support vector 4. Decision Trees Noise (DBSCAN)
machines 5. Neural Network
6. Random Forest
 Artificial
Intelligence

Machine Automation Optimization

Learning

Supervised Unsupervised Reinforcement Evolutionary

Learning Learning Learning Computation
Task-driven Data-driven Learn from mistake Biological Evolution
Data without
Data with Label Decision Making Metaheuristic
Label

Classification Regression Clustering Dimension Model-free

Model-free
Reduction*
1. Genetic
1. Logistic 1. Linear 1. K-means 1. Principal 1. Q-Learning Algorithm
Regression Regression 2. Gaussian Mixture Component 2. R-Learning 2. Particle swarm
2. Naïve Bayes 2. Ordinary least 3. Hierarchical Analysis 3. Ant colony
3. K-nearest Squares 4. Density-Based
neighbour Regression Spatial Clustering
4. Neural network 3. Ride Regression of Applications
5. Support vector 4. Decision Trees with Noise
machines 5. Neural Network (DBSCAN)
6. Random Forest
2021

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2022

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2022

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2022

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2010

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2018

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 defective
bright bump

defective dark bump

intact C4 bumps

a structural area

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Initial Population

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Fitness Evaluation: Elimination

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Reproduction

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Natural Selection

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Selection Process Terminates:
Survival of the Fittest

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Failing Die Test Shmoo

• Shmoo holes => soft failures

• 1) silicon-induced, 2) test margin, 3) silicon-design marginality

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Pin Margin Analysis

* - pass
. - fail V - current setting
Timing Settings
Pin/Group Function 0ns 0.8ns/step 32ns
SIO scan .......*********V**********............. 1
SCLK clk ..******************V***********........ 2
BPI_BUS1 enable B1 ........V******......................... 3
BPI_BUS2 enable B2 .................****V**................
4

Pin/Group Function 0ns 0.8ns/step 32ns

SIO scan ..............**V**********.............
SCLK clk ..******************V***********........
BPI_BUS1 enable B1 ........***V***.........................
BPI_BUS2 enable B2 .................****V**................

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Multi-dimensional Problem

EINT_Rising: 34.5 ns EINT_Rising: 34 ns

• Eliminate blind spots involve multiple iterations

• multivariable problem ( variable Permutate sweep step size) ; almost impossible to inspect manually

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Better Test Margin = Larger Process Margin

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Wider Test Margin

28 nm Process Technology

Before Optimization After Optimization

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Industry 4.0
• Employ artificial intelligence technologies, data mining techniques, big data and deep learning
analysis to current industrial infrastructure
• Leverage IoT
• Develop innovations that are disruptive (to current workflows, practice)

Outcome
• Smart Manufacturing
• Flexible decision-making
• deliver higher performances
• at lower costs is something semiconductor companies are well

38
The Important Role of Machine
Learning in Strengthening
Manufacturing Line of Defense

ASTC 2022

39
Overview
• Introduction
• Big Data Unique to foundry
• Opportunities for Machines Learning
• Manufacturing Lines of Defense (LoD) Enhancement
• Pre-requisites
• Big data management (Cloud- Data Lake)
• Machine learning Applications
• Sort Wafermap classification
• ETest-to-Wafer yield prediction
• Virtual Metrology
Delivering Quality Manufacturing
Modules
CMP

Etch FAB: 700kw/yr capacity

Litho # Tools: 100s

Diffusion # recipes/ wfr: ~20

Thin Film # process parameters/ recipe:

20-30
Clean
# recipe steps/parameter: 2-20
Implant
 steps
•
•
•

Recipe
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Fault Detection Control (FDC)

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Trace data: Time-series (raw data)

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DEV Spin rotation speed
1 sample/s resolution (10k+ data points) – 1 wafer

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FDC Big Data

100-1000s
Process Tools across 7 main modules

80-100s
Process Steps

2-30
recipes

20-30
Process parameters

1-10Hz
Trace Data
FDC Summary Data
1 2
• Statistical grouping
of data
• Critical information
could be lost

…
Mean …
… Control limit
Median …
…
Min …
…
Max …

… … … … … …
Scribe Line Electrical Test

reticle

Total # parameters/reticle:
>5000

Wafer:
All sites (500K-900K)
Wafer Acceptance Test (WAT)

Sampling:
9/17 sites (> 50k)

WAT – Critical parameters:

~10-15%
 Manufacturing Lines of Defense

Package/
Inline system-
Process eTest Wafer-level
defect level
Tool (WAT) ATE
inspection ATE
FDC Parametric Wafer-level Unit-level
Defect data sort
sort

Metrology

Inline CD

Mfg step LoD 1 LoD 2 LoD 3 LoD 4

Data Type
Wafers exposure
Line of Defense (LoD) 25 500-1k Several k 10 k+
Data Lake

Application/ Analytics Zone/ Yield Machine/

Fab Efficiency
Data Warehouse/Data mart Management Dashboard Deep
Analytics
Systems Learning
Curated/ Cleansed
Zone

Data Ingestation/
Standardization

Landing Zone/ Raw

Zone

ETest
SORT
Manufacturing Metrology Process FDC
Systems Database Inline CFM
Sort Wafer map Classification

Fast wafers disposition at

LoD4

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Sort Map Classification
CenterPatch OffCenterPatch EdgePatch Curvature Donut

Gross Random Edge Scratch Streak

Traditional visual recognition approach performed by an experienced person can be expensive and time-consuming
still hard to classify when two or more patterns are mixed on the same map
Neural Network Learning
 Approaches

Deep Network for Defect

Pattern Recognition

Convolutional Generative
Auto-encoder (AE)
Neural Network Adversial Network
(CNN) (GAN)

Custom-made CNN for multi-label Pre-defined CNN

CNN for single- defect and Transfer
label defect classification Learning
classification

[U. Batool, M. I. Shapiai, M. Tahir, Z. H. Ismail, N. J. Zakaria and A. Elfakharany, "A Systematic Review of Deep Learning for Silicon Wafer Defect Recognition," in IEEE Access, vol. 9, pp. 116572-
116593, 2021, doi: 10.1109/ACCESS.2021.3106171.]
Convolutional Neural Network
Fully connected
Feature extraction layer (Hidden
(Convolution and pooling) layer in ANN)
Image
Input Image Processing

Classification

Convolution ≈ apply filters to extract features

Pooling ≈ downsampling matrix e.g. Max pooling

 Results
Pattern Accuracy
Off center Patch > 95%
Edge Patch > 95%
Center Patch > 95%
Scratch > 95%
Gross >95%
Curvature 50%
Donut 60%

Performance in-line with

industry benchmark

[Byun, Y., , “Mixed pattern recognition methodology on wafer maps with pre-trained convolutional neural networks”, ICAART 2020, Volume 2, 2020, Pages 974-979]
 Complexity

Random Patch Mixture

[[1] U. Batool, M. I. Shapiai, M. Tahir, Z. H. Ismail, N. J. Zakaria and A. Elfakharany, "A Systematic Review of Deep Learning for Silicon Wafer Defect Recognition," in IEEE Access, vol. 9, pp.
116572-116593, 2021, doi: 10.1109/ACCESS.2021.3106171.
[2] Byun, Y., , “Mixed pattern recognition methodology on wafer maps with pre-trained convolutional neural networks”, ICAART 2020, Volume 2, 2020, Pages 974-979]
ETest-to-Wafer yield prediction

LoD 4 to LoD 3

56
Yield Prediction

Predict
Actual
Median Yield (%)

Undesirable

Wafers
Modeling

Features = Parameters
Results (High Yield Wafers)

Yield (%)
97

96
95

94
93
Wafers
92

Delta =0 %
Results (High Yield Wafers)
Yield (%)
96

95
Delta =0.4 – 0.6 %
94

93
Wafers
Yield (%)

96 Delta =0.8 – 1.9 %

95

94

93
Wafers
Results (Low Yield Wafers)

Yield (%)

80

70 Delta = < 1.8 %

60

50

40
Wafers
Effect of Modeling
Complexity

1 ET site –to- 1 Die/ reticle 1 ET site –to- X Die/ reticle

Virtual Metrology

LoD 2 to LoD 1

64
Optical Metrology

Process
Wafer Tools
Substrate >85% wafers not
measured
Critical Statistical
Dimension Process
measurement Control
Sampling

2/3 wafers

• Opportunity to increase metrology coverage

• Opportunity for APC enhancement Advanced Process Control
• Increase number of tools => cost impact (APC) Compensation
Virtual Metrology
Process
Wafer Tools
Substrate >85% wafers not
Predict
measured
Critical
Dimension
measurement
Sampling

2/3 wafers

XGBoost
FDC Metrology Modeling
Results: Regression

Guessing Mean Model

Predicted CD

Predicted CD
Actual CD Actual CD
Results: Statistics

Guessing Mean

Model
 Results: Distribution

Guessing Mean
Model

• Guessing Mean using 3

wafers have 94.3% actual
wafer measurement fall
under ±1.5σ

• Model have 100% actual

wafer measurement fall
under ±1.5σ

1.5σ

Residuals
Complexity

Metrology Process FDC Metrology

Good
VM Accuracy
(N-1) (N) (N)
Physical Predicted
measured wfrs unmeasured
(3 wfrs) wfrs
(22 wfrs)

Metrology Process FDC Metrology Challenging

VM (N)
(N-1) (N)

Predicted
unmeasured
wfrs
(25 wfrs)
Conclusions

• Manufacturing Lines of Defense (LoD) critical to quality and business

• Machine learning Applications potential as means to strengthen and
enhance LoD
• Proof-of-concept not good enough
• Key to prototyping success: Overcome Complexity
Thank you