Article https://doi.org/10.

1038/s41467-024-49182-4

The SpinBus architecture for scaling spin

qubits with electron shuttling

Received: 9 August 2023 Matthias Künne 1,3, Alexander Willmes 1,3, Max Oberländer1,
Christian Gorjaew1, Julian D. Teske 1, Harsh Bhardwaj 1, Max Beer 1
,
Accepted: 24 May 2024
Eugen Kammerloher1, René Otten 1,2, Inga Seidler 1, Ran Xue 1,
Lars R. Schreiber1,2 & Hendrik Bluhm 1,2

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Quantum processor architectures must enable scaling to large qubit numbers
while providing two-dimensional qubit connectivity and exquisite operation
1234567890():,;
1234567890():,;

fidelities. For microwave-controlled semiconductor spin qubits, dense arrays

have made considerable progress, but are still limited in size by wiring fan-out
and exhibit significant crosstalk between qubits. To overcome these limita-
tions, we introduce the SpinBus architecture, which uses electron shuttling to
connect qubits and features low operating frequencies and enhanced qubit
coherence. Device simulations for all relevant operations in the Si/SiGe plat-
form validate the feasibility with established semiconductor patterning tech-
nology and operation fidelities exceeding 99.9%. Control using room
temperature instruments can plausibly support at least 144 qubits, but much
larger numbers are conceivable with cryogenic control circuits. Building on
the theoretical feasibility of high-fidelity spin-coherent electron shuttling as
key enabling factor, the SpinBus architecture may be the basis for a spin-based
quantum processor that meets the scalability requirements for practical
quantum computing.

The prospect of noisy intermediate-scale quantum (NISQ) computing needed for NISQ computing, i.e., on the order of 100 qubits. To fully
raises high expectations. However, it is likely that a significant part of deliver on the promises associated with CMOS compatibility, a way to
the foreseen applications will only be accessible via quantum error scale up to millions of qubits must be found. A key challenge at the
correction to mitigate errors caused by noise, spurious coupling, and quantum layer is the short range (≈100 nm) of the exchange interac-
crosstalk1. The resulting overhead leads to a need for millions of phy- tion typically used for high-fidelity two-qubit gate operations. Archi-
sical qubits, which requires highly nontrivial advances compared to tectures based on direct coupling thus lead to crowding of gate
today’s devices. Electron-spin qubits in semiconductor quantum dots electrodes and their wiring2,16, referred to as the wiring fan-out pro-
have the unique feature of being directly compatible with industrial blem, as well as significant inter-qubit crosstalk17.
CMOS processing2. At the level of few-qubit devices, all-electrical To address these challenges, dense qubit arrays using crossbar
operation of single- and two-qubit gates above the error correction network addressing schemes with reduced wiring density, as well as
threshold have been demonstrated3–11. Furthermore, the operation of sparse arrays of qubits with integrated classical electronics at cryo-
multi-qubit devices has been shown in several material systems12–15. genic temperatures, have been proposed18. Dense architectures
Building on these promising results, the immediate next challenge for based on crossbar addressing schemes typically apply the same
semiconductor qubits is scaling-up in two dimensions while simulta- control pulse to many qubits and thus require a challenging level of
neously maintaining high operation fidelities to realize qubit numbers qubit homogeneity19. Tuning the qubit properties with local

1
JARA-FIT Institute for Quantum Information, Forschungszentrum Jülich GmbH and RWTH Aachen University, 52074 Aachen, Germany. 2ARQUE Systems
GmbH, 52074 Aachen, Germany. 3These authors contributed equally: Matthias Künne, Alexander Willmes. e-mail: lars.schreiber@physik.rwth-aachen.de;
bluhm@physik.rwth-aachen.de

Nature Communications | (2024)15:4977 1

Article https://doi.org/10.1038/s41467-024-49182-4

transistor-based circuits can somewhat ameliorate this issue, but The signals Vi have the form27
imposes demands on transistor and capacitor size20 that are well

beyond current capabilities. As an alternative path to avoiding these V i = AS cos φ ðt Þ  Δφi : ð1Þ
difficulties, we propose a concrete realization of the quantum layer
that is based on readily available technology. A key element is the use Here, AS ~100 mV is the signal amplitude and φðt Þ = 2πf  t with fre-
of electron shuttling to form a sparse qubit array with sufficient space quency f is the phase with phase offset Δφi = π=2ði  1Þ. Hence, the
for wiring in near-term implementations and local control electronics number of required signals is independent of the distance between
with a footprint commensurate with the qubit density for very large qubit sites. A DC bias relative to the Vi can be applied to Ohmic con-
qubit numbers in the longer term. This detailing of the quantum-level tacts to adjust the chemical potential. Lateral shifts of the shuttling
architecture complements the proposal for scaling such a shuttling- path to avoid critical regions (see Supplementary Note 1) can be
based sparse array using cryoelectronic control circuits16. The use of achieved by antisymmetric changes of the voltages on the screening
electron shuttling, i.e., moving electrons between sites where qubits gates synchronized with the electron motion30,31.
are manipulated, enables local exchange-based two-qubit gates Based on the QuBus component as a coherent link, we propose a
without requiring a dense qubit array. Gate-based electron shuttling layout of tileable unit cells as building blocks for the quantum layer of
has been realized in both GaAs/(Al,Ga)As and Si/SiGe. By imple- the SpinBus architecture (Fig. 1c). The unit cell (Fig. 1d) provides the
menting Landau-Zener transitions between adjacent quantum dots means for initializing, reading-out and performing gate operations in
in the so-called bucket brigade mode, the transport of single elec- two specialized zones, i.e., the initialization and readout (IR) and the
trons and coherent transfer of electron spins has already been manipulation zone. Shuttling lanes connect both the operational zones
demonstrated21–26. Recently, single-electron transport by so-called and adjacent unit cells. We anticipate that the length of the shuttling
conveyor-mode shuttling was shown27, where a quantum dot used to lanes in the order of 10 μm will reflect a reasonable trade-off between
trap the qubit is continuously translated to distant qubit sites, shuttling-induced errors and time versus space for wiring and local
requiring a length-independent number of wires and also less tuning. electronics33. The spatial separation between different manipulation
In a 10-μm-long prototype device, charge shuttling in one direction zones and qubits avoids unwanted inter-qubit coupling and helps to
and back across a distance of 19 μm with a fidelity of 99.7% has been address qubits individually, thus avoiding control crosstalk errors. This
achieved28. comes at the cost of shuttling errors, which add to the errors of locally
The concept and feasibility of coherent conveyor-mode electron executed gates.
shuttling was analyzed in detail by ref. 29. The confinement potential is The QuBus geometry is based on the recent demonstration
chosen much stronger than the background disorder potential, tar- experiments of conveyor-mode shuttling, where a separation of the
geting an adiabatic motion that leaves the electron in the orbital screening gates by 200 nm, a gate width of 62 nm, and a gate pitch of
ground state. With a shuttling velocity of a few m/s, electrons can be 70 nm have been used27. For the validation of the gate layouts with
transferred fast enough to limit spin dephasing due to T *2 -effects such electrostatic finite-element-method (FEM) models (see Methods sec-
as charge and hyperfine noise. However, nonadiabatic transitions tion “Electrostatic simulations and orbital splitting”), we chose a
between different valley and potentially orbital states set an upper slightly larger gate pitch of 100 nm, including a global top gate that can
bound on the velocity. For a minimal valley splitting of 20 μeV, a be biased with a separate voltage Vtg ~100 mV. For the operation of
coherent transfer with an error rate below 10−3 over a distance of 10 μm some elements, micromagnets are placed in suitable locations
is predicted for a shuttling velocity of v = 8 m/s, which we assume approximately 150 nm above the quantum well. For magnetostatic
throughout this paper. A subsequent study30, as well as the first modeling (see Methods section “Micromagnet design”), we assumed
experiments31, show that occasional lower values of the valley splitting an external in-plane magnetic field Bext = 20–50 mT in the y-direction.
can be avoided by laterally shifting the trajectory of the shuttled Two-dimensional connectivity is implemented by a three-way
electron. In a 1 μm Si/SiGe prototype device with a natural abundance T-junction connecting two perpendicular shuttling lanes (Fig. 2a)
of Si isotopes (similar to ref. 27), spin-coherent shuttling with a max- without requiring any additional gates. Compared to a four-way
imum velocity of 2.8 m/s across an accumulated distance of at least junction16, gate crowding is reduced and potential shaping simplified.
2.4 μm has been demonstrated. The spin dephasing time of the shut- The two supported operations are qubit motion in a straight line
tled electron spin is enhanced by motional narrowing, which con- (straight shuttling) and around the corner (corner shuttling). Straight
tributes even in the absence of 29Si isotopes due to remaining 73Ge shuttling is implemented analogously to normal conveyor-mode
isotopes, and leads to a fidelity of ~99% for the transfer of a spin operation, with the voltages on the perpendicular branch being con-
quantum state over a nominal shuttling distance of 560 nm32. In stant. Due to the rapid decay of electric fields, crosstalk is avoided by
addition, motional narrowing is also expected for charge noise, albeit storing qubits in the perpendicular branch at least 100 nm away from
with a longer correlation length set roughly by the distance of the noise the junction when operating the straight branch. For corner shuttling,
source from the channel29. a quantum dot initially moving along the straight branch is stopped at
the intersection and then transferred into the perpendicular branch.
Results Figure 2b shows the corresponding potentials for different points in
The SpinBus architecture and its elements time during the adiabatic transfer using appropriately adjusted voltage
In this manuscript, we present the SpinBus architecture, which pulses. Selected line cuts of the potential and the time evolution of the
leverages the conveyor-mode shuttling device named Quantum Bus shuttling phases are presented in Supplementary Figs. 1, 2, respec-
(QuBus) as used in demonstration experiments27,28,32 to connect qubits tively. For both operations, the transport direction can be inverted by
(Fig. 1a). Like established semiconductor qubit devices, the QuBus reversing the shuttling pulses. For coherent shuttling, the electron
device employs a stack of electrostatic gates on top of a Si/SiGe het- motion should reflect a smooth translation of the potential, rather than
erostructure that confines electrons in the z-direction (Fig. 1b). Lateral tunneling between disorder-induced stationary quantum dots. A use-
screening gates define a one-dimensional channel in the xy-plane, ful metric for this requirement is the orbital splitting for the moving
while clavier gates placed above are used to generate moving quantum quantum dot containing the qubit. Langrock, Krzywda et al. deter-
dots. Every fourth clavier gate is electrically connected, thus elim- mined that the required confinement strength to safely prevent the
inating the need for fanning out each individual gate. Four phase- splitting of the shuttled potential minimum into a double quantum dot
shifted sinusoidal signals Vi, i = 1 ... 4, applied to the resulting four sets configuration in the presence of ensembles of randomly distributed
of clavier gates enable a continuous translation of the quantum dots. charged defects at the Si/SiO2 interface corresponds to an orbital

Nature Communications | (2024)15:4977 2

Article https://doi.org/10.1038/s41467-024-49182-4

a b

φ(t) = 0 φ(t) = π
Global top gate
Clavier φ(t) = π/2 φ(t) = 3π/2
gates
Si cap

Potential (meV)
Si0.7Ge0.3 20
0
Si QW -20
Si0.7Ge0.3
0 100 300 500 700
Shuttling channel length (nm)

c d

Bext
Initialization /
Readout Zone

T-Junction T-Junction

Manipulation T-Junction
Zone
y

~ 10 µm

Fig. 1 | Layout and operation of the QuBus device as a building block for the processor chip consists of unit cells tiled like a brick wall. One unit cell is high-
SpinBus architecture. a 3D visualization of the QuBus device consisting of two lighted, the heterostructure is visualized transparently in most areas, and local
lateral screening gates defining a 1D electron channel and periodically connected electronic components are shown symbolically. Unit cells are connected via the
clavier gates. The four gate sets connected to different control signals Vi are color- green-colored shuttling lanes controlled by a signal set shared across unit cells. Red
coded. b Schematic of the Si/SiGe heterostructure providing the quantum well and blue-colored shuttling lanes are controlled individually in each unit cell. d A
(QW). Line cuts of the traveling potential generated by the gate stack are depicted unit cell consists of three T-junctions for 2D connectivity, an initialization and
for four different phases φðt Þ. The occupied potential minimum is indicated by a readout zone, and a manipulation zone. We expect a spatial extent of unit cells in
blue circle. The gate stack is depicted above the potential line cuts. c The quantum the order of 10 μm.

splitting of at least 1 meV. This criterion is in agreement with experi- second the potential of the first quantum dot in the QuBus channel. A
mentally obtained values typically found in static quantum dots34. second moving quantum dot can be controlled independently by the
During straight shuttling, the orbital splitting equals or exceeds the four sets of clavier gates. For qubit initialization and readout, Pauli spin
threshold at all times (Fig. 2c). A drop in the orbital splitting during blockade (PSB) in the resulting double quantum dot is utilized to
corner shuttling caused by the asymmetry of the gate layout at the enable simpler and faster readout discrimination than, e.g., spin-
junction which reduces confinement can safely be prevented (Fig. 2d) selective tunneling35,36. The required parallel magnetic field gradient
by dynamically pulsing the outer screening gate of the straight branch ∂B∥ is generated by a micromagnet placed directly above the shuttling
during transfer (Supplementary Fig. 2). The pulse pushes the electron lane adjacent to the SET. The initialization sequence follows standard
towards the branching channel, reduces the effect of the asymmetry procedures and is presented in Fig. 3c. It starts with loading two
and thus increases the confinement. To avoid any influence on other electrons into a first quantum dot (step I), forming a tunnel-coupled
qubits stored in the straight branch, a segmentation of the outer double quantum dot configuration (step II) while the second quantum
screening gate at the junction can allow a local pulsing. dot is kept at a sufficiently higher potential during the adjustment of
The initialization and readout (IR) zone consists of a single- the inter-dot tunnel barrier (step III) to remain in a S(2,0) state.
electron transistor (SET) tunnel-coupled to a shuttling lane, thus Sweeping the detuning ϵ transfers the S(2,0) state to a (1,1) config-
enabling loading and detecting charges (Fig. 3a). Ohmic contacts on uration,
 where the gradient magnetic field splits
 the T0 and S(1,1) into
both sides of the SET provide source and drain reservoirs, and elec- ∣ "# and ∣ #" (step IV). Thus, the ∣ #" will be occupied if the
trons are injected into the shuttling lane via the SET. Besides one detuning is pulsed adiabatically with respect to orbital, spin, and valley
plunger and two barrier gates for the SET, we propose two additional excitations, but including a short diabatic sweep over the ST−-crossing.
individually contacted gates at the beginning of the shuttling lane Lastly, the spin-up state is shuttled away to be used as a qubit. The spin-
(Fig. 3b). The first controls the tunnel barrier to the SET, and the down electron can be kept in the first quantum dot as a reference spin

Nature Communications | (2024)15:4977 3

Article https://doi.org/10.1038/s41467-024-49182-4

a c

1.4

Orbital splitting (meV)

1.3

1.2

1.1

1.0

-400 -300 -200 -100 0 100 200 300 400

Distance from T-junction (nm)
b d

200 nm 40 1.4

Orbital splitting (meV)

1.3

Potential (meV)
20
1.2

1.1
0

1.0

-400 -300 -200 -100 0 100 200 300 400

-20
Distance from T-junction (nm)

Fig. 2 | Layout and operation of the T-junction. a 3D visualization of the the shuttling direction, and white dashed lines indicate the positions and lengths of
T-junction consisting of two perpendicularly joined QuBus elements. Straight the line cuts in Supplementary Fig. 1. c The orbital splitting during straight shuttling
shuttling (red path) and corner shuttling (green path) are shown. b 2D potential at is always sufficiently large. d During corner shuttling, dynamically adjusting the
the T-junction for different points in time during corner shuttling. Arrows indicate screening gate voltage ensures an orbital splitting within the target range.

state for later readout. The corresponding time traces for the shuttling shuttling has been found to be minor29, it can safely be neglected for
phase φðt Þ and detuning are shown in Supplementary Fig. 3. To manipulation as the synthetic SOI used for EDSR is normally dominant.
implement readout, the initialization sequence is reversed, and PSB is Regarding crosstalk, driving a single-qubit gate on a qubit right of the
employed to determine the qubit’s state. Any established method for junction in Fig. 4b causes a relative electrostatic shift corresponding to
SET readout can be used, though we speculate that baseband readout 0.5% of the driving amplitude for the other qubit located left of the
with cryogenic transistors37–39 will yield the best performance- junction (orange circle), 250 nm from the driven shuttling element.
complexity trade-off. Conservatively assuming the same resonance frequency, this trans-
Single- and two-qubit gate operations are performed in the lates to an infidelity of approximately 6 × 10−5 for a π-gate. For the more
manipulation zone, which is formed by joining two shuttling lanes distant qubit in the right single-qubit manipulation region, crosstalk is
(Fig. 4a). Two independent QuBus elements enable sufficient control even weaker. In addition, the remaining crosstalk can be reduced
over both detuning and tunnel coupling of a double quantum dot further by specifically tailored pulses accounting for the respective
potential formed at the junction, thus eliminating the need for addi- opposite single-qubit operation.
tional separately contacted gates. Two micromagnets provide the For electron-spin qubit platforms utilizing micromagnets, the
necessary magnetic field gradients (Fig. 4b). For single- and two-qubit natural choice for the implementation of CNOT-like two-qubit gates
gates, a micromagnet is placed off-center from the junction above one (see Methods section “CNOT gate synthesis”) is the controlled-phase
QuBus element. On the other side of the junction, an additional (CPHASE) gate based on the exchange interaction J ðt Þ between two
micromagnet for single-qubit gates is located above the other QuBus tunnel-coupled quantum dots40–42, which is switched adiabatically with
element at a sufficient distance to avoid compromising the long- respect to a Zeeman energy difference ΔEZ between the two quantum
itudinal field gradient at the junction. Thus, the manipulation zone dots. This configuration is achieved by shuttling both electrons to the
allows performing single-qubit gates on two qubits independently. junction at the center of the manipulation zone (Fig. 4c) with pulses as
Single-qubit gates are implemented by electric-dipole spin reso- shown in Supplementary Fig. 4 while maintaining zero detuning. The
nance (EDSR), in which an effective oscillatory transverse magnetic control of the exchange coupling via the inter-qubit distance while
field for driving Rabi oscillations is generated by displacing the elec- maintaining zero detuning essentially amounts to barrier control,
tron in a perpendicular magnetic field gradient. Unlike conventional which features a lower charge noise sensitivity compared to control-
EDSR manipulation, where the electron position oscillates typically up ling the exchange interaction via the detuning5,43. Figure 4c shows the
to one nanometer3, we propose a shuttling-mode EDSR building on the simulated potentials during the formation of a double quantum dot.
capability of moving the electron over arbitrary distances. For high The separation and barrier height during the two qubit gates are
fidelities, we estimate an oscillation amplitude in the order of 10 nm to similar as in conventional quantum dot structures, thus validating the
be a good choice. The larger amplitude allows the use of significantly robustness of the procedure with respect to disorder. The absence of
weaker magnetic field gradients, which reduces the sensitivity to tunnel coupling to other sites further increases this robustness in
charge noise. While the influence of spin-orbit interaction (SOI) during comparison to arrays with multiple quantum dots.

Nature Communications | (2024)15:4977 4

Article https://doi.org/10.1038/s41467-024-49182-4

a c

Vi (mV) Pot. (meV) Vi (mV) Pot. (meV) Vi (mV) Pot. (meV) Vi (mV) Pot. (meV)
200
I
0

20

-20

200
II 0

20

-20

200
III
0

20
b
0
Detuning ε Micromagnet
-20
SET 200
IV
0
Potential (meV)

∂yB
∂yB (mT/nm)

0.01 20 20
Potential
0 0 0
-0.01 -20 -20

0 100 300 500 700 -100 0 100 300 500 700

Position in IR zone (nm) Position in IR zone (nm)

Fig. 3 | Layout and operation of the initialization and readout (IR) zone. a 3D correspond to the gates from panels a and b, and their vertical positions indicate
visualization of the IR zone consisting of a QuBus element adjacent to an SET, and a the applied voltage Vi. Tunneling is indicated by dashed black arrows and solid
micromagnet. Two gates next to four sets of clavier gates are individually con- black arrows mark the translation of quantum dots. Step I: loading of a S(2,0) state
trolled. b Cross-section including the gate layout showing the schematic double from the SET into the first quantum dot. Step II: moving a second quantum dot
quantum dot potential and simulated magnetic field gradient ∂yB∥ along the close to the first quantum dot. Step III: detuned double quantum dot. Step IV:

shuttling channel. Red and blue circles represent the positions of two electrons in a applying a detuning sweep to transfer S(2,0) to ∣ "# followed by a shuttling pulse
double quantum dot configuration. c Potential line cuts while initializing a qubit to inject the qubit into the shuttling channel.
using PSB (blue arrows represent the electrons' spin states). The color-coded bars

Fidelity of quantum operations fidelities exceeding 99.9% as long as the valley splitting is greater than
To estimate the achievable performance, we simulated the dynamics 30 μeV and exhibits integrated variations of less than 100 μeV along
of each quantum operation using the simulation package qopt44, the path. For two-qubit gates, the relevant infidelity contribution arises
including optimization of the control pulses (see Methods section from quasistatic position noise affecting the exchange interaction, and
“Operation fidelities”). The fidelities were computed based on a noise we obtain a fidelity of 99.9%.
model including quasistatic nuclear spin noise affecting the Zeeman
splitting as well as quasistatic and white charge noise with amplitudes Operating concept and system complexity
extracted from past experiments3,45,46. With appropriate calibration, The two-dimensional array of the architecture is well suited for the
the combination of quasistatic and white charge noise can serve as a implementation of surface codes, which can be considered the main-
conservative proxy for 1/f-noise typically found in real devices. We stream concept for quantum error correction1, as well as NISQ algo-
included coupling of the charge noise to the qubit via the detuning rithms. As an exemplary operation, we show the elementary surface
affecting the exchange coupling as well as via position fluctuations. code gate sequence in Fig. 5, requiring a square array of qubits with
The latter affects the single spin dynamics due to the magnetic field nearest-neighbor coupling. Every second qubit serves as a data qubit
gradient as well as the exchange coupling at zero detuning. This noise storing quantum information, and every other one as an ancilla qubit,
model covers the effects we consider as experimentally most relevant each detecting one of two possible types of errors called X^ and Z^
and was shown to be in good agreement with experimental results47. stabilizers48. As each manipulation zone can simultaneously operate
For the initialization and readout procedure, we identified fast charge two qubits, each unit cell is identified with one data qubit highlighted
noise as the main limiting factor and obtained fidelities above 99.9% if in blue and one adjacent ancilla qubit highlighted in green and yellow,
parasitic inter-dot orthogonal magnetic field gradients remain suffi- respectively (Fig. 5a). An error detection cycle consists of initializing
ciently small (see Methods section “Micromagnet design”). To evaluate the ancilla qubits, CNOT gates with the four adjacent data qubits,
single-qubit operations, we applied a sinusoidal shuttling EDSR-pulse which we choose as stationary, and subsequent readout of the ancilla
in resonance with the Zeeman splitting to a qubit model with spin and qubits. Realizing such a cycle in the SpinBus architecture requires the
valley degree of freedom. We identified fast charge noise causing shuttling of ancilla qubits to and from different manipulation zones
position fluctuations as the dominating noise contribution and find between local gate operations (Fig. 5b).

Nature Communications | (2024)15:4977 5

Article https://doi.org/10.1038/s41467-024-49182-4

a c
200

Vi (mV)
I
0

Pot. (meV)
0

-20

200

Vi (mV)
II
0

Pot. (meV)
0

b -20

Micromagnet
200

Vi (mV)
III
0
∂xB (mT/nm)

Pot. (meV)
0.10 0
∂xB
0.05
∂xB
-20
0

-500 -300 -100 0 100 300 -500 -300 -100 0 100 300
Position in manipulation zone (nm) Position in manipulation zone (nm)

Fig. 4 | Layout and operation of the manipulation zone. a 3D visualization of the indicate the positions of the qubits during the two-qubit gate operations, respec-
manipulation zone consisting of two joined QuBus elements and two micro- tively. Both are pushed together at the location of a large parallel magnetic field
magnets. Shown is an exemplary two-qubit operation. b Cross-section including the gradient ∣∂xB∥∣. c Potential line cuts showing the smooth formation of a tunnel-
gate layout showing the required magnetic field gradients for single- and two-qubit coupled double quantum dot potential appropriate for two-qubit operations as the
gates along the manipulation zone. The orange circle shows the position of the two translated quantum dots approach the center of the manipulation zone. The
qubit during the single-qubit gate operation and is driven periodically in the region color-coded bars correspond to the gates from panels a and b, and their vertical
of a large perpendicular magnetic field gradient ∣∂xB⊥∣. The red and blue circles positions indicate the applied voltage Vi.

The predicted fidelities are in the range of what is needed to because the purely capacitive impedance of control electrodes, low
achieve a reasonable, logical qubit performance and overhead. Thus, operating frequency, and robust coherence of spin qubits facilitate the
individual logical qubits are within reach for qubit numbers that can be use of cryogenic CMOS control circuits. The variable unit cell size can
realized with conventional control and packaging approaches. Since be adjusted to the required size of dedicated control circuits for each
integrating on the order of 100 qubits approaches the limits of con- unit cell, so that direct wiring, e.g., via flip-chip bonding, can eliminate
necting room temperature control, we first present a near-term the wiring fan-out problem. First, estimates of the size of control cir-
implementation with 144 qubits based on realistic assumptions cuits for spin qubits lead to values in a compatible range16,33. Next to
regarding qubit homogeneity, control electronics, and cooling hard- the size of control circuits, their power dissipation will be a concern in
ware. The estimate of the number of required signals is based on an the light of limited cooling power at low temperature. For DC bias, a
economical operating strategy detailed in Supplementary Note 2. We consumption at a level of a few nW per channel has already been
then discuss a concrete scaling perspective to much larger qubit shown50. While we favor a qubit temperature on the order of 100 mK to
numbers by using cryoelectronic control circuits, which significantly ensure a minimal loss of gate fidelity, thermally isolating flip-chip
reduce the number of required external control lines. solutions may allow the operation of electronics at a higher tempera-
Considering shuttling signals (also used for qubit control) and ture than the qubits. Working around 2 K would potentially make
additional local AC and DC signals of the IR zone and the screening cooling powers at the level of Watts accessible. For this purpose, we
gates, a quantum processor chip with N unit cells requires 15 N + 4 AC propose the implementation of thermal insulation of the quantum
and 3 N + 4 DC signals. While there are no inherent scaling limitations layer from the electronics by a broadband phononic Bragg reflector51
to our architecture at the quantum layer, the wiring requirements have to sustain a temperature gradient over a high-density interconnect
to be compatible with cryostat wiring, packaging, and back-end-of-line solution. Simulations52 indicate that a heat load below 1 mW/cm2 can
(BEOL) technology. We estimate that currently available wiring solu- be achieved with a thickness compatible with high-density vias with a
tions in cryostats of about 1000 coaxial cables49 are the most limiting micron-scale pitch. Using superconductors such as NbN or NbTiN with
factor and can accommodate a quantum processor chip with 9 × 8 = 72 a critical temperature of a multiple of the operating temperature can
unit cells. This corresponds to 144 simultaneously operable qubits if lead to a very small heat transfer through the vias. While it remains to
two qubits per unit cell are loaded. Storing additional qubits away from be seen if the dynamic qubit and shuttling control signals can be
manipulation zones can further increase the qubit number. generated within the resulting power budget, qubit control can also be
implemented by multiplexing of externally generated pulses53, for
Scaling perspective using cryoelectronic control circuits example, using simple cryo-CMOS switches54,55. As a reverse approach
For large-scale quantum computing with many error-corrected qubits, to adapting pulses to individual qubits, the qubit response could be
however, conventional control and packaging approaches are less tuned to these fixed pulses using DC gate voltages. While
appealing. Here, integrated control solutions offer an attractive path- more demanding and arguably less elegant than global crossbar
way. The SpinBus architecture features good prospects in this respect addressing, this approach has the advantage of not making

Nature Communications | (2024)15:4977 6

Article https://doi.org/10.1038/s41467-024-49182-4

a b

2
a

b
3

Data qubit Ancilla qubits d

Fig. 5 | Exemplary surface code implementation in the SpinBus architecture. Arrows mark the shuttling paths to all involved manipulation zones, whereas the
a Mapping of data and ancilla qubits to unit cells. Each diagonal line segment numbers indicate the order of operations. Steps 1 and 5 include the initialization
represents a required qubit interaction. b Shuttling paths for an ancilla qubit in and readout of the ancilla qubit, respectively.
order to implement an X^ stabilizer. Associated data qubits are designated with a–d.

assumptions regarding the homogeneity of the qubit parameters. For by the variable qubit spacing, robust coherence of semiconductor
readout, heterojunction-bipolar-transistors (HBTs) allow single-shot qubits, the purely capacitive load of gate electrodes and the relatively
readout in less than 10 μs at powers below 800 nW39, which likely can low operating frequency could carry to much larger systems, even-
be reduced with optimized sensor designs56,57. tually enabling error-corrected quantum computing. Recent advances
in cryoelectronics and packaging provide concrete perspectives on
Discussion how this goal can be tackled.
In summary, we have detailed a concept to leverage electron shuttling
for the realization of a semiconductor-based quantum processor with Methods
2D coupling, as required for quantum error correction based on the Electrostatic simulations and orbital splitting
surface code. The proposed layout can be optimized for other use For the calculation of the electrostatic potentials, we employed finite-
cases or according to a trade-off between shuttling and gate errors. For element-method (FEM) simulations using COMSOL Multiphysics®. For
example, it was found that for parity encoding of quantum approx- each operational element, as shown in Figs. 2a, 3a, 4a of the main text,
imate optimization algorithms, four rather than two single-qubit we solved Poisson’s equation:
manipulation zones promise a very good performance58. To validate
the feasibility, we performed electrostatic simulations for all device 1
∇ðϵðrÞ∇ΦÞ = ρ, ð2Þ
layouts and modes of operation. For the estimation of operation ϵ0
fidelities, we used realistic noise models and obtained fidelities for
single- and two-qubit gates exceeding 99.9%. The fabrication is pos- with the electrostatic potential Φ, charge density ρ, the dielectric
sible with present-day industrial semiconductor processing. Further- constant of the sample ϵ(r) and the vacuum permittivity ϵ0. Dirichlet
more, the architecture is compatible with established packaging and boundary conditions corresponding to the applied voltages were
wiring techniques such as BEOL via fabrication and flip-chip bonding. imposed at metallic gates. As the structure is intended to be filled with
While we considered an implementation in Si/SiGe, the SpinBus dilute electrons representing qubits whose behavior will be fully gov-
architecture can potentially be transferred to other types of gate- erned by the electrostatic potential in their absence, their charge was
defined semiconductor qubits. not included in ρ. We used the linearity of the model to simplify the
Our architecture proposal features a number of strengths, but it variation of the applied voltages Vi by calculating basis potentials Φ of
clearly hinges on the theoretically predicted feasibility of spin- each gate i separately and combining the resulting total potential
coherent electron shuttling. While the first experiments on spin- X
coherent transport are promising, an implementation with high fidelity Φ= V i Φi : ð3Þ
and mitigating low values of the valley splitting in Si/SiGe (see Sup- i
plementary Note 1 for details) will be an essential next step. Reaching
the projected fidelities and required yield could quickly put semi- Specifically, Φi is the potential for gate i set to 1 V with all others at 0 V.
conductor qubits on the map for NISQ-type quantum computing. The This superposition approach is justified in regions where no or only
combination with cryoelectronic control systems, which is facilitated very few electrons are present. In the IR zone, however, one needs to

Nature Communications | (2024)15:4977 7

Article https://doi.org/10.1038/s41467-024-49182-4

Table 1 | Dimensions of the micromagnets for the IR zone and readout, single-qubit gates and two-qubit gates. To extract
manipulation zone, respectively, and associated magnetic meaningful fidelities, we included realistic noise values from past
field gradients experiments3,45,46. All simulations were performed assuming the
g-factor of Si.
Case dimension/nm3 ΔB⊥∣∂B⊥ ΔB∥∣∂B∥
For the initialization and readout procedure, we simulated
 a linear
IR 700 × 200 × 20 <0.3 mT 1.3 mT
ramping pulse which converts between the S(2, 0) and ∣ #" -state by
SQG 400 × 200 × 20 0.075 mT/nm <0.01 mT/nm
sweeping the potential detuning ϵ of a double quantum dot adiabati-
TQG 400 × 200 × 20 4 mT 8.7 mT cally, besides a jump over the avoided ST−-crossing. We utilized a
Quantities given in mT/nm refer to the derivative of the field at the assumed operation point Hamiltonian
denoted via ∂, quantities in mT to the total field difference between two qubits during the
  truncated to the relevant three-state basis of
f∣T 0 , ∣Si, ∣T  g,
operation denoted via Δ.
IR initialization and readout, SQT single-qubit gates, TQG two-qubit gates. 0 1
0 ΔBk =2 0
B pffiffiffi C
H =B
@ ΔBk =2 JðεÞ ΔB? =ð2 2Þ CA, ð4Þ
pffiffiffi
take the reservoir’s contribution to ρ into account. To do so, we first 0 ΔB? =ð2 2Þ Bk
used the Thomas-Fermi approximation and solved the Poisson
equation self-consistently, assuming a depleted two-dimensional taking the Zeeman splitting (B∥), parallel (ΔB∥) and orthogonal (ΔB⊥)
electron gas (2DEG) in the channel and SET, for a specific gate voltage field differences between two dots spaced ~ 100 nm apart from
configuration that leads to the intended occupation of the reservoirs. micromagnet simulations and experimental data for the exchange
To simplify fine-tuning of the gate voltages via the superposition energy J(ε) from ref. 45. Including further
pffiffiffiffiffi fast chargepnoise
ffiffiffiffiffiffi on the
approach, we subsequently modeled the reservoirs analogous to detuning ε with a spectral density of Sε = 0:02 neV/ Hz (adapted
metallic gates, thus assuming perfect screening. The position of these from ref. 45 assuming a gate lever arm of0.1 eV/V) and optimizing a
gates was obtained from the region of nonzero charge density of the jump in ϵ at the avoided crossing of ∣T  and ∣Si induced by unin-
initial Thomas-Fermi solution. This neglects a change of the reservoir tentional orthogonal field gradients gives target state fidelities
region in response to gate voltages and introduces a small error as the exceeding 99.9% when choosing pulse lengths t ~200 ns, fields of
gradual screening by the 2DEG in the reservoirs is replaced by a hard B∥ ≥ 20 mT, ΔB∥ ~1 mT and a parasitic inter-dot orthogonal magnetic
boundary condition. As the reservoirs are relatively far from the region field difference ΔB⊥ ⪅ 0.3 mT. The separation of the electrons, which is
of interest, these approximations are compatible with our goal of well established, was assumed to occur perfectly adiabatically without
demonstrating the feasibility to create an appropriate potential. The thermal or dynamic excitation.
potential energies shown in the figures are referenced to the For single-qubit EDSR, spin and valley degree of freedom were
conduction band edge and given as V = −eΦ. considered in the Hamiltonian
For quantifying the effect of the variations in confinement in the
T-junction (Fig. 2), we calculated the orbital splitting for the simulated 1 1
H= B ðxÞσ z + B? ðxÞσ x + ΔVS,x ðxÞτ x + ΔVS,y ðxÞτ y
potential of the quantum dot confining the qubit by solving the time- 2 k 2 ð5Þ
independent Schrödinger equation in two dimensions for each + κ SVC,x τ x  σ z + κ SVC,y τ y  σ z
time step.
with σi and τi denoting Pauli matrices on spin and valley space,
Micromagnet design respectively, ΔVS = ΔVS,x + iΔVS,y is a complex matrix element describing
Considering the requirements for the gate operations, we identified the coupling of the two lowest near-degenerate valley states in silicon61
suitable dimensions for Cobalt micromagnets which provide the as a function of the electron position x and κSVC,i = 0.01 μeV
necessary field gradients. The resulting geometries and corresponding parametrizes a g-factor variation between the valley states. EDSR-
gradients are summarized in Table 1. Using thin layers ensures suffi- pulses as enveloped sinusoidal drives were then optimized for
cient remanent magnetization when operating at low external mag- resonance frequency with the software framework qopt44 and
netic fields, which we substantiated with OOMMF59 simulations using evaluated with respect to a process fidelity in the sense of ref. 62,
material parameters from ref. 60. Note that the perpendicular field
gradient ∂B⊥ for two-qubit gates arising from the magnet geometry is 1
F process ðUÞ = 2
jtrfV y ðU t Þtrunc gj2 , ð6Þ
neither required nor harmful. As it is weaker than in the single-qubit d1
zone and the gate duration is comparable, resulting relaxation errors
are expected to be negligible. where V describes the target gate unitary and Ut the propagator in the
The perpendicular field gradient for the IR zone, as well as the eigenbasis of our model. The subscript trunc denotes truncation to the
parallel gradient for the primary SQG position, are undesired and were two-dimensional (d1) spin subspace of the lower instantaneous valley
rounded conservatively from simulations of potential misalignments state. This takes into account valley-leakage as valley excitations entail
during device fabrication. Here, a Gaussian misalignment of phase errors in subsequent operations29. From the simulations, we
σxy = 30 nm in both horizontal directions was sampled. These gradients identified fast charge noise as the dominating noise contribution, which
were then included in the dynamics model described in the following we modeled
pffiffiffi as an
peffective
ffiffiffiffiffiffi positional fluctuation with a spectral density
Methods section “Operation fidelities”. A detrimental influence of of S = 0:1
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi fm= Hz based
pffiffiffiffiffiffi on the experimental observation of
micromagnets on other IR/SQG/TQG zones is negligible for the Sð1 MHzÞ = 0:2 nV/ Hz in ref. 45 transferred assuming a gate lever
∂x
assumed spatial separations. arm around 0.1 eV/V leading to assumed displacements of ∂V ∼ 0:4 nm/
mV using calculations from ref. 3. Taking into account the design choice
Operation fidelities of weaker magnetic gradients ∂B⊥ ~0.1 mT/nm, our results indicate
To verify the feasibility of the architecture, we performed quantum displacement amplitudes of around 20 nm (peak-to-peak) as a viable
dynamic simulations of each quantum operation using the simulation operation point to uphold a Rabi frequency near 10 MHz. This
package qopt44. We calculated the quantum dynamics by solving displacement amplitude constitutes a trade-off between achievable
the time-dependent Schrödinger equation for adequate model Rabi frequency and decoherence due to leakage on the valley space
Hamiltonians to identify simple control pulses for initialization and from potentially non-uniform valley splitting over the increased

Nature Communications | (2024)15:4977 8

Article https://doi.org/10.1038/s41467-024-49182-4

adiabatically turning on the exchange interaction J ðt Þ, which shifts the

energy levels of the antiparallel spin states in such a way that they
CZ
H H acquire additional phases. Applying an exchange pulse for a duration
τ = πℏ/J combined with appropriately calibrated single-qubit
Fig. 6 | CNOT gate synthesis. A CNOT gate is synthesized by a CZ gate, including gates5,7,11,66 allows the implementation of a controlled-Z (CZ) gate or
Hadamard-like operations to account for necessary single-qubit operations (e.g., z^ a CNOT gate to realize a universal gate set11.
rotations).
Data availability
Electrostatic simulation results as shown in the figures including
traveling distance of the electron during the pulse compared to additional intermediate steps and gate fidelity simulation scripts have
previous experiments. For the simulations, we assumed that the qubit been deposited in the Zenodo database (https://doi.org/10.5281/
response scales approximately linearly with the driving field, which zenodo.11110575).
directly corresponds to the displacement amplitude. However, for
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Nature Communications | (2024)15:4977 10

Article https://doi.org/10.1038/s41467-024-49182-4

Technologies implemented within the European Union’s Horizon 2020 RWTH Aachen University and Forschungszentrum Jülich GmbH, is cur-
research and innovation program. rently pending in the designated PCT-states. A method for avoiding
problematic spots in the shuttling channel by shifting the shuttling path
Author contributions laterally is covered by a patent family (PCT/EP2023/055058) by the work
M.K., A.W., I.S., L.R.S., and H.B. conceived the device layouts. M.K., A.W., of the inventors Klos, M.O., M.K., H.B., J.D.T., and the patent application,
H.Bh., M.B., E.K., I.S., and R.X. implemented and carried out electrostatic co-owned by RWTH Aachen University and Forschungszentrum Jülich
simulations. M.O., C.G., and J.D.T. carried out the dynamics simulations GmbH, is currently pending in the designated PCT-states. The modified
for each quantum operation. M.K., A.W., and H.B. conceived the oper- QuBus device, including a global top gate, is covered by a patent family
ating strategy. M.K., A.W., R.O., and H.B. developed the wiring concept. (PCT/EP2023/055061) by the work of the inventors L.R.S., Focke, I.S.,
H.B. and L.R.S. provided guidance to all authors. M.K., A.W., M.O., J.D.T., H.B., and the patent application, owned by RWTH Aachen University, is
and H.B. wrote the manuscript. currently pending in the designated PCT-states. The broadband pho-
nonic Bragg reflector is covered by a patent family (DE102021123046 B3,
Funding WO2023/031477 A1, CN117917211 A) by the work of the inventor H.B., and
Open Access funding enabled and organized by Projekt DEAL. the patent application, owned by Forschungszentrum Jülich GmbH, is
currently pending. L.R.S. and H.B. are founders and shareholders of
Competing interests ARQUE Systems GmbH. The remaining authors declare no competing
The conveyor-mode shuttling device QuBus is covered by a patent interests.
family (EP4031486, US 2022/0293846 A1, CN114424346 A) by the work
of the inventors M.K., I.S., H.B., L.R.S. and the patent application, co- Additional information
owned by RWTH Aachen University and Forschungszentrum Jülich Supplementary information The online version contains
GmbH, is currently pending. The IR zone and a method for operating it supplementary material available at
for initialization is covered by a patent family (EP4031489, US 2023/ https://doi.org/10.1038/s41467-024-49182-4.
0006669 A1, CN114402441) by the work of the inventors H.B., L.R.S.,
M.K. and the patent application, co-owned by RWTH Aachen University Correspondence and requests for materials should be addressed to
and Forschungszentrum Jülich GmbH, is currently pending. A method Lars R. Schreiber or Hendrik Bluhm.
for operating the IR zone for readout is covered by a patent family
(EP4031487, US 2022/0327072, CN114424344) by the work of the Peer review information Nature Communications thanks Kok Wai Chan,
inventors H.B., L.R.S., M.K. and the patent application, co-owned by Rajkumar Chinnasamy, MengKe Feng, Florian Ginzel, and the other,
RWTH Aachen University and Forschungszentrum Jülich GmbH, is cur- anonymous, reviewer for their contribution to the peer review of this
rently pending. The T-junction is covered by a patent family (EP4031490, work. A peer review file is available.
US 2022/0344565, CN114514618) by the work of the inventors H.B.,
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