Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

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Voodoo3
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HIGH PERFORMANCE
GRAPHICS ENGINE
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FOR
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3D GAME ACCELERATION
Data Book: Revision 1.9
August 24, 1999
Copyright 1998 3dfx Interactive, Inc. All Rights Reserved

3dfx Interactive, Inc.

4435 Fortran Drive
San Jose CA 95134
Phone: (408) 935-4400
Fax: (408) 935-4424

Copyright 1998  3dfx Interactive, Inc. Revision 1.9

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Notice:
3dfx Interactive, Inc. has made best efforts to ensure that the information contained in this document is
accurate and reliable. The information is subject to change without notice. No responsibility is assumed by
3dfx Interactive, Inc. for the use of this information, nor for infringements of patents or the rights of third
parties. This document is the property of 3dfx Interactive, Inc. and implies no license under patents,
copyrights, or trade secrets.

Trademarks:
All trademarks are the property of their respective owners.

Copyright Notice:
No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted in any
form or by any means, electronic, mechanical, photographic, or otherwise, or used as the basis for
manufacture or sale of any items without the prior written consent of 3dfx Interactive, Inc.
If this document is downloaded from the 3dfx Interactive, Inc. world wide web site, the user may view or
print it, but may not transmit copies to any other party and may not post it on any other site or location.

Proprietary Information:
This document contains proprietary information of 3Dfx Interactive, Inc., and its receipt or possession does
not convey any rights to reproduce, disclose its contents, or to manufacture, use or sell anything it may
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describe. Reproduction, disclosure or use without specific written authorization of 3Dfx Interactive, Inc., is
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strictly forbidden.

Preliminary Data:
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3dfx Interactive, Inc. has made best efforts to ensure that the information contained in this document is
accurate.
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Copyright 1998  3dfx Interactive, Inc. Revision 1.9

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table of Contents
1 Introduction ................................................................................................... 7
1.1 Scope of Document ...................................................................................... 7
1.2 Document History ......................................................................................... 7
1.3 Devices Covered ........................................................................................... 7
1.4 Audience ....................................................................................................... 7
1.5 Conventions .................................................................................................. 7
1.5.1 Acronyms ........................................................................................................................... 7
1.5.2 Number Base ..................................................................................................................... 7
1.5.3 Object Grouping ................................................................................................................. 8
1.5.4 Abbreviations ...................................................................................................................... 8
2 Product Overview .......................................................................................... 9
2.1 Introduction ................................................................................................... 9
2.1.1 Voodoo Graphics Compatibility .......................................................................................... 9
2.1.2 3D Performance and Quality .............................................................................................. 9
2.1.3 Optimized for Pentium‚ II and AGP-2X Platform ................................................................ 9
2.1.4 Windows‚ GUI/Video Acceleration ...................................................................................... 9
2.1.5 DVD Acceleration ............................................................................................................... 9
2.2 Feature List ................................................................................................... 9
2.2.1 General Features ............................................................................................................... 9
2.2.2 2D Acceleration ................................................................................................................ 10
2.2.3 3D Acceleration ................................................................................................................ 10
2.2.4 Video Acceleration ........................................................................................................... 10
2.2.5 Host Interface ................................................................................................................... 10
2.2.6 Memory System ............................................................................................................... 11
2.2.7 Process and Package Technology ................................................................................... 11
2.2.8 Software ........................................................................................................................... 11
3 Pins ............................................................................................................... 12
3.1 Introduction ................................................................................................. 12
3.2 Pin Diagrams .............................................................................................. 12
3.3 Pin Tables ................................................................................................... 14
3.4 Pin Descriptions .......................................................................................... 29
3.4.1 PCI Interface .................................................................................................................... 29
3.4.2 AGP Interface ................................................................................................................... 31
3.4.3 Frame Buffer Memory ...................................................................................................... 32
3.4.4 Monitor ............................................................................................................................. 34
3.4.5 VMI Interface .................................................................................................................... 35
3.4.6 Digital RGB Interface Signals ........................................................................................... 35
3.4.7 Miscellaneous Pins ........................................................................................................... 36
3.4.8 Power and Ground ........................................................................................................... 37
4 Configuration Options ................................................................................ 38
5 Digital RGB Data Formats .......................................................................... 39
6 General Purpose I/O .................................................................................... 40
7 Serial I/O ....................................................................................................... 41
8 ROM Access ................................................................................................ 42
9 DC Specifications ........................................................................................ 43
9.1 Absolute Maximum Ratings ........................................................................ 43
9.2 DC Characteristics and Recommended Operating Conditions ................... 43
9.3 VCC Limits .................................................................................................. 45
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9.4 Package Thermal Characteristics ............................................................... 46

9.5 DAC Characteristics .................................................................................... 46
10 AC Specifications ........................................................................................ 47
10.1 Maximum Clock Rates ................................................................................ 47
10.2 Clock Input Timing ...................................................................................... 47
10.3 Clock Out Timing ........................................................................................ 49
10.4 Reset Timing ............................................................................................... 50
10.5 PCI/AGP Transmitter (output) Timing ......................................................... 51
10.6 PCI/AGP Receiver (input) Timing ............................................................... 52
10.7 Frame Buffer Output Timing ....................................................................... 53
10.8 Frame Buffer Input Timing .......................................................................... 54
10.9 VMI Host Interface Mode A Timing ............................................................. 55
10.10 VMI Host Interface Mode B Timing ............................................................. 57
10.11 VMI Video In Timing .................................................................................... 59
10.12 Digital RGB Out Timing ............................................................................... 60
10.13 ROM Read Cycle ........................................................................................ 61
10.14 ROM Write Cycle ........................................................................................ 62
11 Package ........................................................................................................ 63
11.1 Introduction ................................................................................................. 63

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List of Tables
Table 1.1 Document History ................................................................................. 7
Table 1.2 Abbreviations ........................................................................................ 8
Table 3.1 Pin Diagram ........................................................................................ 13
Table 3.2 Pin Table Summary ............................................................................ 14
Table 3.3 PCI Interface Signals .......................................................................... 14
Table 3.4 AGP Interface Signals ........................................................................ 16
Table 3.5 Frame Buffer Memory Signals ............................................................ 17
Table 3.6 Monitor Signals ................................................................................... 23
Table 3.7 VMI Interface Signals ......................................................................... 24
Table 3.8 Digital RGB Interface Signals ............................................................. 25
Table 3.9 Miscellaneous Pins ............................................................................. 26
Table 3.10 Power and Ground Pins ..................................................................... 27
Table 4.1 Strapping Options ............................................................................... 38
Table 5.1 Digital RGB Data Formats .................................................................. 39
Table 6.1 Standard GPIO Pins ........................................................................... 40
Table 7.1 Serial I/O Assignments ....................................................................... 41
Table 8.1 ROM Access Pins .............................................................................. 42
Table 9.1 Absolute Maximum Ratings ................................................................ 43
Table 9.2 DC Characteristics and Recommended Operating Conditions .......... 43
Table 9.3 Supply Current and Voltage ............................................................... 45
Table 9.4 Thermal Characteristics ..................................................................... 46
Table 9.5 DAC Characteristics ........................................................................... 46
Table 10.1 Maximum Clock Rates ....................................................................... 47
Table 10.2 PCI_CLK Timing ................................................................................. 48
Table 10.3 VMI_PCLK (VMI Video Capture Mode) Timing .................................. 48
Table 10.4 TV_INCLK (TV out Mode) Timing ...................................................... 48
Table 10.5 GRX_CLK Timing ............................................................................... 48
Table 10.6 MCLKA/MCLKB Timing ...................................................................... 49
Table 10.7 TV_CLK_OUT Timing: TV Out Mode ................................................. 49
Table 10.8 TV_CLK_OUT Timing: LCD Out Mode .............................................. 49
Table 10.9 Reset Timing ...................................................................................... 50
Table 10.10 PCI/AGP Transmitter (output) Timing ................................................ 51
Table 10.11 PCI/AGP Receiver (input) Timing ....................................................... 52
Table 10.12 Frame Buffer Output Timing ............................................................... 53
Table 10.13 Frame Buffer Input Timing .................................................................. 54
Table 10.14 VMI Host Interface Mode A Timing ................................................... 55
Table 10.15 VMI Host Interface Mode B Timing ................................................... 57
Table 10.16 VMI Video In Timing ........................................................................... 59
Table 10.17 Digital RGB Out Timing ...................................................................... 60
Table 10.18 ROM Read Cycle ............................................................................... 61
Table 10.19 ROM Write Cycle ................................................................................ 62

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List of Figures
Figure 2.1 System Block Diagram ................................................................... 11
Figure 3.1 Bus Diagram .................................................................................. 12
Figure 10.1 Clock Input Waveform .................................................................... 47
Figure 10.2 Clock Out Waveform ...................................................................... 49
Figure 10.3 Reset Waveforms .......................................................................... 50
Figure 10.4 PCI/AGP Transmitter Waveforms .................................................. 51
Figure 10.5 PCI/AGP Receiver Waveforms ...................................................... 52
Figure 10.6 Frame Buffer Output Waveforms ................................................... 53
Figure 10.7 Frame Buffer Input Waveforms ...................................................... 54
Figure 10.8 VMI Host Interface Mode A Waveforms ......................................... 55
Figure 10.9 VMI Host Interface Mode B Waveforms ......................................... 57
Figure 10.10 VMI Video In Waveforms ............................................................... 59
Figure 10.11 Digital RGB Out Waveforms .......................................................... 60
Figure 10.12 ROM Read Cycle Waveforms ........................................................ 61
Figure 10.13 ROM Write Cycle Waveforms ........................................................ 62
Figure 11.1 Physical Dimensions ...................................................................... 63
Figure 11.2 Pad Layout ..................................................................................... 64

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1 Introduction
1.1 Scope of Document
This is the Data Book for Voodoo3. This document includes a device overview, pin descriptions, DC and
AC parameters, and additional information necessary to design with Voodoo3.

1.2 Document History

Table 1.1 Document History

Version Date Change from previous version

1.0 Sept. 29, 1998 Initial Version
1.1 Oct 19, 1998 GPIO0/GPIO1 descriptions corrected.
1.2 Oct 20, 1998 Serial Port connections on reference design corrected.
1.3 Nov 11, 1998 Corrected Serial port connections again.
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1.4 Nov 17, 1998 Changed name to Voodoo3.

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1.5 Dec 16, 1998 Changed RSET resistor value to 56.2 ohms
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Feb 16, 1999
Feb 22, 1999
Corrected pllCtrl, AGP_PLL Strapping
Note added to GPIO[0] in pin descriptions, GPIO Notes
1.8 May 5, 99 Changed to new logo, companyname (correct print date)
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1.9 Aug 24, 1999 Added Power Supply Limits, Thermal Characteristics

1.3 Devices Covered

This document covers the production version(s) of Voodoo3 - 250 and Voodoo3 - 333.

1.4 Audience
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This document is tailored to a knowledgeable audience. It is assumed that the reader is familiar with
assembly language programming of Pentium CPU and has a good foundation in computer-generated
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graphics, especially 3D.

Hardware designers intending to use Voodoo3 should have experience in the design of mixed analog-
digital devices with very high bandwidth buses. Some signals have fast edge rates and will behave as
transmission lines, requiring controlled impedance traces and short, direct connections. Experience with
SGRAM/SDRAM arrays and the PCI/AGP bus will be valuable. Designers are encouraged to study the
layout guidelines available from 3dfx Interactive, Inc.

1.5 Conventions
1.5.1 Acronyms
The first appearance of each TLA (Three Letter Acronym) is followed immediately by the definition in
parentheses.
1.5.2 Number Base
Hexadecimal (base 16) numbers use upper case letters ABCDEF. Hexadecimal numbers have a

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

prepended ‘0x’ or an appended ‘h’. The following are examples of hexadecimal numbers: 0x00, 0x3DF,
3DFh, 0x1234, 0x2A. Eight-digit hexadecimal numbers typically contain a space in the middle. For
example 0x0123 4567 is an eight-digit hexadecimal number.
Decimal (base 10) numbers have no special indicator. The following are examples of decimal numbers:
1234, 2380, 42.
Binary (base 2) have an appended ‘b’. The following are examples of binary numbers: 00b, 01b, 101010b.
Octal (base 8) numbers are not used in this document.
The value zero is often written as 0, without any quotes and without indication as to size or base.
1.5.3 Object Grouping
Objects that are grouped together are listed in descending order. A range is indicated with surrounding
square brackets and a colon between the highest and the lowest in the range. A[7:0] means A7, A6, A5,
A4, A3, A2, A1, A0. This convention is used for bits in a register (for example, CR2[7:0]) and for signal pins
(for example, PCI_AD[31:0]).
1.5.4 Abbreviations
The following abbreviations are used in this document.

Table 1.2 Abbreviations

Abbreviation tC l Meaning Note

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Kbyte 1024 bytes
Mbyte
Gbyte
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1,073,741,824 bytes
1024 Kbytes
1024 Mbytes
Hz Hertz frequency
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kHz 1000 Hertz

MHz 1,000,000 Hertz
ms 10-3 second period

us 10-6 second
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ns 10-9 second
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mA 10-3 Ampere current

uA 10-6 Ampere
uF 10-6 Farad capacitance

pF 10-12 Farad
tbd, na To Be Determined, Not Available used interchangeably
Mpixel 1,000,000 pixels

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2 Product Overview
2.1 Introduction
Voodoo3 incorporates leading-edge 3D graphics and extremely fast 128-bit Windows GUI/Video
Acceleration into a single chip.
2.1.1 Voodoo Graphics Compatibility
Since Voodoo3 is upward compatible with Voodoo 3D, hundreds of 3D titles that have been optimized for
acceleration on Voodoo Graphics, Voodoo Rush, Voodoo2, and Voodoo Banshee will run on Voodoo3
without modification. Of course, to take advantage of the Voodoo3 enhanced features, it will be necessary
make changes.
2.1.2 3D Performance and Quality
3dfx Interactive, Inc. is the industry leader in delivering 3D technology for the PC consumer market.
Voodoo3 - 333 will continue this heritage, delivering 333 Mtexels/sec and over 6 million triangles per
second single-cycle multi-texturing 3D performance1. The design philosophy behind all products of 3dfx
Interactive, Inc. is to provide advanced 3D features with the universal requirement of all serious game
developers: no degradation in performance and quality. As an example, Voodoo3 provides per-pixel
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level-of-detail MIP mapping and per-pixel atmospheric effects such as fog and haze. Other solutions that
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provide these features at all do so on a per-polygon basis, yielding an inferior image.
2.1.3 Optimized for Pentium II and AGP-2X Platform
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Voodoo3 is the only solution to fully exploit the processing power the Pentium II, including direct
hardware handling of out-of-order writes. From the very beginning, Voodoo3 was designed to maximize the
performance of the Pentium Pro and Pentium II I/O architecture. The AGP interface is tuned for optimal 3D
performance, and supports sideband addressing for very fast texture downloading and full 2X 133 MHz
AGP bus operation.
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2.1.4 Windows GUI/Video Acceleration

Voodoo3 - 333 is a 166 MHz (125 for the -250 product) single-cycle GUI accelerator with 128-bit frame
buffer interface. Even the VGA core is 128 bits. The design philosophy has been to implement the
Microsoft GDI (Graphics Device Interface) in hardware for outstanding windows acceleration. Voodoo3
supports the new features of Windows98 (for example, multi-monitor support) and is PC99 compliant.
2.1.5 DVD Acceleration
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The video architecture of Voodoo3 is optimized for software DVD acceleration. This optimization includes
large FIFOs, YUV 4:2:0 planar to packed pixel conversion with AGP bus-mastering, automatic double-
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buffering, and alpha blending for sub-picture support.

2.2 Feature List

2.2.1 General Features
• Two texels per clock
• Fully integrated 128-bit VGA/2D/3D/Video Accelerator
• 2X AGP with sideband addressing
• Fully software-compatible with 3Dfx Voodoo Banshee
• Floating point depth buffer (W buffer)
• Ultimate 3D experience with 333 Mtexels/sec and 6 million triangles/sec for - 333 product,
• 250 Mtexels and 4 million triangles/sec for - 250 product
• Hardware support for Out-of-order writes

1. The -250 product will deliver 250 Mtexel/sec and over 4 million triangles per second.

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• Hardware DVD acceleration

• Digital video output for NTSC and PAL TV-out support
• DFP or VESA FPDI LCD support through external ASIC
• Full VMI (includes the host port) for Hardware DVD decoding or digital video capture
• HDTV resolution of 2132 x 1600 at 60 Hz with 350 MHz (-333 product) RAMDAC
• Supports 4-, 8-, 16-Mbyte SGRAM or 16-Mbyte SDRAM frame buffer
• PC99 rev 1.0 compliant
• VESA DDC2B support
2.2.2 2D Acceleration
• 333 MHz (250 for -250 product) single-cycle 128-bit Windows GUI acceleration
• Fully-featured 128-bit BitBlt Engine: Windows GDI in hardware
• Acceleration for Bresenham line draw, 2-edge polygon fill, scissor/rectangle clippers, 256 ROPs
• Source and destination chroma-keying for DirectDraw
• SGRAM color expansion support and single-cycle block writes
• Accelerated 8-, 16-, 24 (packed)-, 32-bpp modes
2.2.3 3D Acceleration
• Dual texture units: Two texels per-pixel per-clock
• Full hardware setup of triangle parameters
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Support for multi-triangle strips and fans
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• 16-bit integer and floating-point Z-buffering with biasing
• Transparency and chroma-key with dedicated color mask
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Alpha blending of source and destination pixels
Sub-pixel and sub-texel correction to 0.4 x 0.4 resolution
24-bit color dithering to native 16-bit RGB
Per-pixel atmospheric fog with programmable fog zones
• Full-scene polygon-based edge anti-aliasing
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• Dynamic environment mapping

• Perspective correct (true divide-per-pixel) 3D texture mapping and Gouraud shading
• Single-cycle bump mapping
• Single-cycle Trilinear Mip-mapping
• Anisotropic filtering
• True per-pixel LOD (level-of-detail) MIP mapping with biasing and clamping
• RGB modulation combines textures and shaded pixels
• Texture compositing for multi-texture special effects
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• Support of 14 texture map formats

• 8-bit paletted textures with full bilinear filtering
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• Texture compression through narrow-channel YAB format

2.2.4 Video Acceleration
• Multiple video window support
• Bilinear horizontal and vertical filtering
• YUV 4:2:2 and YUV 4:2:0 planar support
• De-interlacing using ‘bob’ and ‘weave’
• Automatic page flipping using VBI (Vertical Blanking Interval) for smooth motion video
• Triple 512 x 8 color lookup tables with separate gamma correction for video and graphics
• Separate gamma correction for video and graphics
2.2.5 Host Interface
• AGP 2X interface includes optimized support for sideband addressing
• PCI v2.1 bus interface supports 33 MHz and 66 MHz
• FIFO optimized for high speed bursting of geometry and texture data
• Optimized for Pentium II I/O architecture; out-of-order writes handled in hardware

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• Bi-endian byte-ordering support

2.2.6 Memory System
• Advanced architecture with 3.0 Gbyte/sec (2.7 Gbyte/sec for -250 product) memory bandwidth
• 4 - 16 Mbytes of 166 MHz (125 for -250 product) and faster SGRAM/SDRAM
2.2.7 Process and Package Technology
• Custom IC fabricated in 0.25 micron, 5 metal layer CMOS
• 352-lead (plus 100 thermal ball) 35mm PBGA package
• 2.5 volt power with PCI and 5-volt tolerant I/O
• Built-in Iddq, CRC, and Parametric NAND tree for testability
2.2.8 Software
• Full BIOS and driver compatibility with Voodoo Banshee for a mature, robust solution
• Windows95, Windows98, WindowNT4.0 device drivers
• Extensive 3D API support including Glide 2.X and 3.X, OpenGL ICD, Microsoft D3D
• Support for TV encoders: Chrontel 7004, Brooktree 868/9
• Software DVD support: Quadrant

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MPEG2
Decoder Analog RGB, Syncs
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Monitor
PCI/AGP 2X

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3Dfx 3Dfx LVDS/ LCD

Voodoo LCDfx Panel
TMDS
Voodoo3

12-bit DDR
100 MHz
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128
Digital
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TV TV
Encoder

4-16 Mbytes
SDRAM/SGRAM

Figure 2.1 System Block Diagram

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

3 Pins
3.1 Introduction
The Voodoo3 pins are described in this chapter. Included are pin diagrams, pin tables, and detailed pin
descriptions. Where appropriate, the detailed pin descriptions include board design notes.

3.2 Pin Diagrams

Voodoo3 is available in a 452-lead PBGA (352 leads and 100 thermal balls). Figure 3.1 is a high-level
diagram showing the buses for reference only. Table 3.1 is the detailed pin diagram.

Digital RGB
OUT
Monitor VMI, ROM, DAC PLL
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PCI/AGP Memory A
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Interface Thermal MD[63:0]

Balls
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Memory B
MD[127:64]

Figure 3.1 Bus Diagram

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Table 3.1 Pin Diagram

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A VSYNC IDDQ HSYNC GPIO0 ROMOE VINT VRDY VRW VCS VHD0 DAVSS GREEN VCC_C VHA0 PD6 PD2 PD1 PAVSS0 XIN TBLNK THSYNC TVD8 TVD5 TVD1 MD31 MD3

B INTA RST SDA0 GPIO1 SDC1 ROMCS VRST VDS VHA3 DAVSSR DRSET BLUE VHA2 VVSYNC PD7 PD3 PCLK PAVDD0 PAVSS1 TCLKO TVD11 TVD7 TVD4 TVD2 TVD0 MD1

C PGNT ST0 SDC0 GPIO2 ROMWE VHD6 VHD4 VHD3 VHD1 VBG DAVDDI VHA1 VPCLK VBLNK PD4 PD0 APVSS XOUT PAVDD1 TRST TVD10 TVD6 TVD3 MD2 MD30 MD0

D RBF ST2 ST1 GND SDA1 VHD7 VHD5 VCC VHD2 GND DAVDD RED CLKO VHSYNC VCC_C PD5 GND APVDD VCC TICLK TVSYNC TVD9 GND MD29 MD4 MD5

E SBA2 SBA1 SBA0 SBA3 (E) MD7 MD27 MD6 MD28

F SBA5 SBA4 SBSTB SBA6 (F) MD16 MD20 MD18 MD17

G PAD30 PAD31 SBA7 PAD29 (G) MD19 MD24 MD21 MD26

H PAD26 PAD27 PAD28 VCC (H) VCC MD23 MD25 MD22

J ADSTB1 PAD24 PAD25 PAD23 (J) MDM0 MWEA MD15 MDM2

K PAD21 IDSEL CBE3 GND (K) GND MD14 MRASA MCASA

L PAD20 PAD19 PAD22 PAD17 (L) MD13 MD12 MA_A9 MA_A10

M AVREF CBE2 PAD18 PAD16 (M) MD11 MD10 MA_A1 MA_A0

N FRAME IRDY VCC_C DEVSEL

T_BALL[100:1] (N) MA_A2 MD8 MD9 MA_A3

P VCC_C STOP TDRY PAR [J:V][18:9] (P) MA_A4 MDM3 MA_A5 VCC_C

R PAD14 PAD15 CBE1 PAD13 (R) MA_A6 MDM6 MDM1 MA_A7

T PAD10 PAD11 PAD12 PAD9 (T) MA_A8 MDM4 VCC_C MDSFA

U CBE0 PAD8 VCC_C GND (U) GND MD54 MD53 MD55

V PAD6 PAD7 ADSTB0 PAD5 (V) MCLKA MD52 MD51 MCLKAI

W PAD2 PAD3 PAD4 VCC (W) VCC MD50 MDM5 MDM7

Y MD127 PAD0 PAD1 MD97 (Y) MD41 MD49 MD48 MD40

AA MD126 MD125 MD96 MD98 (AA) MD43 MD45 MD39 MD42

AB MD122 MD124 MD123 MD121 (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (AB) MD44 MD47 MD38 MD37

AC MD111 MD110 MD120 GND MCLKBI MD116 MD115 VCC MD118 GND MA_B0 MA_B10 MCASB MD76 MD87 MD85 GND MD90 VCC MD68 MD65 MD62 GMD MD36 MD35 MD46

AD MD108 MD109 MD100 MD104 MD113 MD114 MA_B7 MA_B5 MA_B3 MA_B1 MDM12 VCC_C MWEB MRASB MDM10 MD86 MD84 MD83 MD80 MD92 MD93 MD64 MD32 MD60 MD57 MD56

AE MD101 MD106 MD103 MDM15 MD102 MD112 MA_B8 MA_B6 MA_B4 MA_B2 MDM9 MA_B9 (nc) MD75 MDM8 MD78 MD88 MD82 MD71 MD69 MD66 MD63 MD95 MD61 MD59 MD34

AF MD99 MD107 MD105 MDM13 MCLKB MDSFB MD117 MD119 MDM14 MDM11 MD73 MD72 MD74 VCC_C MD77 MD79 MD89 MD81 MD70 MD91 MD67 MD94 MD33 MCS1 MCS0 MD58

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3.3 Pin Tables

The following tables contain pin names, pin number, pin type, and a brief description. The pins are
organized into the groups shown in Table 3.2.
Within each group, the pins are listed in alphabetical order, higher number first. Because of space
limitations in the pin diagram (Table 3.1), it was necessary to abbreviate some pin names. The abbreviated
names are in the second column of each table.

Table 3.2 Pin Table Summary

Group Table Link

PCI Interface Table 3.3 Section 3.4.1
AGP Interface Table 3.4 Section 3.4.2
Frame Buffer Memory Table 3.5 Section 3.4.3
Monitor Interface Table 3.6 Section 3.4.4
VMI Interface Table 3.7 Section 3.4.5
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Digital RGB Out Table 3.8 Section 3.4.6

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Miscellaneous Table 3.9 Section 3.4.7
Power and Ground op Table 3.10 Section 3.4.8
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Table 3.3 PCI Interface Signals

Abbr.
Name Position Type Description
Name
PCI_AD31 PAD31 G2 I/O PCI Address and Data Bus
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PCI_AD30 PAD30 G1 I/O PCI Address and Data Bus

PCI_AD29 PAD29 G4 I/O PCI Address and Data Bus
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PCI_AD28 PAD28 H3 I/O PCI Address and Data Bus

PCI_AD27 PAD27 H2 I/O PCI Address and Data Bus
PCI_AD26 PAD26 H1 I/O PCI Address and Data Bus
PCI_AD25 PAD25 J3 I/O PCI Address and Data Bus
PCI_AD24 PAD24 J2 I/O PCI Address and Data Bus
PCI_AD23 PAD23 J4 I/O PCI Address and Data Bus
PCI_AD22 PAD22 L3 I/O PCI Address and Data Bus
PCI_AD21 PAD21 K1 I/O PCI Address and Data Bus
PCI_AD20 PAD20 L1 I/O PCI Address and Data Bus

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.3 PCI Interface Signals (Continued)

Abbr.
Name Position Type Description
Name
PCI_AD19 PAD19 L2 I/O PCI Address and Data Bus
PCI_AD18 PAD18 M3 I/O PCI Address and Data Bus
PCI_AD17 PAD17 L4 I/O PCI Address and Data Bus
PCI_AD16 PAD16 M4 I/O PCI Address and Data Bus
PCI_AD15 PAD15 R2 I/O PCI Address and Data Bus
PCI_AD14 PAD14 R1 I/O PCI Address and Data Bus
PCI_AD13 PAD13 R4 I/O PCI Address and Data Bus
PCI_AD12 PAD12 T3 I/O PCI Address and Data Bus
PCI_AD11
tC l PAD11 T2 I/O PCI Address and Data Bus
No ntia
y
PCI_AD10 PAD10 T1 I/O PCI Address and Data Bus
PCI_AD9
PCI_AD8
op PAD9
PAD8
T4
U2
I/O
I/O
PCI Address and Data Bus
PCI Address and Data Bus
PCI_AD7 PAD7 V2 I/O PCI Address and Data Bus
Do fide

PCI_AD6 PAD6 V1 I/O PCI Address and Data Bus

PCI_AD5 PAD5 V4 I/O PCI Address and Data Bus
PCI_AD4 PAD4 W3 I/O PCI Address and Data Bus
PCI_AD3 PAD3 W2 I/O PCI Address and Data Bus
n

PCI_AD2 PAD2 W1 I/O PCI Address and Data Bus

PCI_AD1 PAD1 Y3 I/O PCI Address and Data Bus
Co

PCI_AD0 PAD0 Y2 I/O PCI Address and Data Bus

PCI_CBE3 CBE3 K3 Input PCI Command and Byte Enables
PCI_CBE2 CBE2 M2 Input PCI Command and Byte Enables
PCI_CBE1 CBE1 R3 Input PCI Command and Byte Enables
PCI_CBE0 CBE0 U1 Input PCI Command and Byte Enables
PCI_CLK PCLK B17 Input PCI Clock
PCI_DEVSEL DEVSEL N4 I/O PCI Device Select
PCI_FRAME FRAME N1 Input PCI Transfer Frame
PCI_GNT_N PGNT C1 Input PCI Bus Grant

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.3 PCI Interface Signals (Continued)

Abbr.
Name Position Type Description
Name
PCI_IDSEL IDSEL K2 Input PCI Initialization Device Select
PCI_INTA_N INTA B1 Output PCI Interrupt Request
PCI_IRDY_N IRDY N2 Input PCI Initiator Ready
PCI_PAR PAR P4 I/O PCI Bus Parity
PCI_RESET_N RST B2 Input PCI System Reset
PCI_STOP_N STOP P2 Output PCI Transfer Stop
PCI_TRDY_N TRDY P3 I/O PCI Target Ready

tC l
Table 3.4 AGP Interface Signals
No ntia
y
Abbr.
Name

AGP_AD_STB1
op Name
ADSTB1
Position

J1
Type

Input
Description

AD Bus Strobe 1
AGP_AD_STB0 ADSTB0 V3 Input AD Bus Strobe 0
Do fide

AGP_RBF_N RBF D1 Output AGP Read Buffer Full

AGP_SB_STB SBSTB F3 Output AGP Sideband Strobe
AGP_SBA7 SBA7 G3 Output AGP Sideband Address Bus
AGP_SBA6 SBA6 F4 Output AGP Sideband Address Bus
n

AGP_SBA5 SBA5 F1 Output AGP Sideband Address Bus

APG_SBA4 SBA4 F2 Output AGP Sideband Address Bus
Co

AGP_SBA3 SBA3 E4 Output AGP Sideband Address Bus

AGP_SBA2 SBA2 E1 Output AGP Sideband Address Bus
AGP_SBA1 SBA1 E2 Output AGP Sideband Address Bus
AGP_SBA0 SBA0 E3 Output AGP Sideband Address Bus
AGP_ST2 ST2 D2 Input AGP Status Bus
AGP_ST1 ST1 D3 Input AGP Status Bus
AGP_ST0 ST0 C2 Input AGP Status Bus
AGP_VREF AVREF M1 Wire AGP Voltage Reference

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.5 Frame Buffer Memory Signals

Abbr.
Name Position Type Description
Name
MA_A10 MA_A10 L26 Output Frame Buffer Port A Address
MA_A9 MA_A9 L25 Output Frame Buffer Port A Address
MA_A8 MA_A8 T23 Output Frame Buffer Port A Address
MA_A7 MA_A7 R26 Output Frame Buffer Port A Address
MA_A6 MA_A6 R23 Output Frame Buffer Port A Address
MA_A5 MA_A5 P25 Output Frame Buffer Port A Address
MA_A4 MA_A4 P23 Output Frame Buffer Port A Address
MA_A3
tC l MA_A3 N26 Output Frame Buffer Port A Address
No ntia
y
MA_A2 MA_A2 N23 Output Frame Buffer Port A Address
MA_A1
MA_A0
op MA_A1
MA_A0
M25
M26
Output
Output
Frame Buffer Port A Address
Frame Buffer Port A Address
MA_B10 MA_B10 AC12 Output Frame Buffer Port B Address
Do fide

MA_B9 MA_B9 AE12 Output Frame Buffer Port B Address

MA_B8 MA_B8 AE7 Output Frame Buffer Port B Address
MA_B7 MA_B7 AD7 Output Frame Buffer Port B Address
MA_B6 MA_B6 AE8 Output Frame Buffer Port B Address
n

MA_B5 MA_B5 AD8 Output Frame Buffer Port B Address

MA_B4 MA_B4 AE9 Output Frame Buffer Port B Address
Co

MA_B3 MA_B3 AD9 Output Frame Buffer Port B Address

MA_B2 MA_B2 AE10 Output Frame Buffer Port B Address
MA_B1 MA_B1 AD10 Output Frame Buffer Port B Address
MA_B0 MA_B0 AC11 Output Frame Buffer Port B Address
MCAS_A MCACA K26 Output Frame Buffer Port A CAS
MCAS_B MCASB AC13 Output Frame Buffer Port B CAS
MCLKA MCLKA V23 Output Frame Buffer Port A Clock Out
MCLKA_IN MCLKAI V26 Input Frame Buffer Port A Clock Feedback
MCLKB MCLKB AF5 Output Frame Buffer Port B Clock Out

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.5 Frame Buffer Memory Signals (Continued)

Abbr.
Name Position Type Description
Name
MCLKB_IN MCLKBI AC5 Input Frame Buffer Port B Clock Feedback
MCS_1 MCS1 AF24 Output Frame Buffer Bank 1 Chip Select
MSC_0 MCS0 AF25 Output Frame Buffer Bank 0 Chip Select
MD127 MD127 Y1 I/O Frame Buffer Data Bus
MD126 MD126 AA1 I/O Frame Buffer Data Bus
MD125 MD125 AA2 I/O Frame Buffer Data Bus
MD124 MD124 AB2 I/O Frame Buffer Data Bus
MD123 MD123 AB3 I/O Frame Buffer Data Bus
MD122
tC l MD122 AB1 I/O Frame Buffer Data Bus
No ntia
y
MD121 MD121 AB4 I/O Frame Buffer Data Bus
MD120
MD119
op MD120
MD119
AC3
AF8
I/O
I/O
Frame Buffer Data Bus
Frame Buffer Data Bus
MD118 MD118 AC9 I/O Frame Buffer Data Bus
Do fide

MD117 MD117 AF7 I/O Frame Buffer Data Bus

MD116 MD116 AC6 I/O Frame Buffer Data Bus
MD115 MD115 AC7 I/O Frame Buffer Data Bus
MD114 MD114 AD6 I/O Frame Buffer Data Bus
n

MD113 MD113 AD5 I/O Frame Buffer Data Bus

MD112 MD112 AE6 I/O Frame Buffer Data Bus
Co

MD111 MD111 AC1 I/O Frame Buffer Data Bus

MD110 MD110 AC2 I/O Frame Buffer Data Bus
MD109 MD109 AD2 I/O Frame Buffer Data Bus
MD108 MD108 AD1 I/O Frame Buffer Data Bus
MD107 MD107 AF2 I/O Frame Buffer Data Bus
MD106 MD106 AE2 I/O Frame Buffer Data Bus
MD105 MD105 AF3 I/O Frame Buffer Data Bus
MD104 MD104 AD4 I/O Frame Buffer Data Bus
MD103 MD103 AE3 I/O Frame Buffer Data Bus

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.5 Frame Buffer Memory Signals (Continued)

Abbr.
Name Position Type Description
Name
MD102 MD102 AE5 I/O Frame Buffer Data Bus
MD101 MD101 AE1 I/O Frame Buffer Data Bus
MD100 MD100 AD3 I/O Frame Buffer Data Bus
MD99 MD99 AF1 I/O Frame Buffer Data Bus
MD98 MD98 AA4 I/O Frame Buffer Data Bus
MD97 MD97 Y4 I/O Frame Buffer Data Bus
MD96 MD96 AA3 I/O Frame Buffer Data Bus
MD95 MD95 AE23 I/O Frame Buffer Data Bus
MD94
tC l MD94 AF22 I/O Frame Buffer Data Bus
No ntia
y
MD93 MD93 AD21 I/O Frame Buffer Data Bus
MD92
MD91
op MD92
MD91
AD20
AF20
I/O
I/O
Frame Buffer Data Bus
Frame Buffer Data Bus
MD90 MD90 AC18 I/O Frame Buffer Data Bus
Do fide

MD89 MD89 AF17 I/O Frame Buffer Data Bus

MD88 MD88 AE17 I/O Frame Buffer Data Bus
MD87 MD87 AC15 I/O Frame Buffer Data Bus
MD86 MD86 AD16 I/O Frame Buffer Data Bus
n

MD85 MD85 AC16 I/O Frame Buffer Data Bus

MD84 MD84 AD17 I/O Frame Buffer Data Bus
Co

MD83 MD83 AD18 I/O Frame Buffer Data Bus

MD82 MD82 AE18 I/O Frame Buffer Data Bus
MD81 MD81 AF18 I/O Frame Buffer Data Bus
MD80 MD80 AD19 I/O Frame Buffer Data Bus
MD79 MD79 AF16 I/O Frame Buffer Data Bus
MD78 MD78 AE16 I/O Frame Buffer Data Bus
MD77 MD77 AF15 I/O Frame Buffer Data Bus
MD76 MD76 AC14 I/O Frame Buffer Data Bus
MD75 MD75 AE14 I/O Frame Buffer Data Bus

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.5 Frame Buffer Memory Signals (Continued)

Abbr.
Name Position Type Description
Name
MD74 MD74 AF13 I/O Frame Buffer Data Bus
MD73 MD73 AF11 I/O Frame Buffer Data Bus
MD72 MD72 AF12 I/O Frame Buffer Data Bus
MD71 MD71 AE19 I/O Frame Buffer Data Bus
MD70 MD70 AF19 I/O Frame Buffer Data Bus
MD69 MD69 AE20 I/O Frame Buffer Data Bus
MD68 MD68 AC20 I/O Frame Buffer Data Bus
MD67 MD67 AF21 I/O Frame Buffer Data Bus
MD66
tC l MD66 AE21 I/O Frame Buffer Data Bus
No ntia
y
MD65 MD65 AC21 I/O Frame Buffer Data Bus
MD64
MD63
op MD64
MD63
AD22
AE22
I/O
I/O
Frame Buffer Data Bus
Frame Buffer Data Bus
MD62 MD62 AC22 I/O Frame Buffer Data Bus
Do fide

MD61 MD61 AE24 I/O Frame Buffer Data Bus

MD60 MD60 AD24 I/O Frame Buffer Data Bus
MD59 MD59 AE25 I/O Frame Buffer Data Bus
MD58 MD58 AF26 I/O Frame Buffer Data Bus
n

MD57 MD57 AD25 I/O Frame Buffer Data Bus

MD56 MD56 AD26 I/O Frame Buffer Data Bus
Co

MD55 MD55 U26 I/O Frame Buffer Data Bus

MD54 MD54 U24 I/O Frame Buffer Data Bus
MD53 MD53 U25 I/O Frame Buffer Data Bus
MD52 MD52 V24 I/O Frame Buffer Data Bus
MD51 MD51 V25 I/O Frame Buffer Data Bus
MD50 MD50 W24 I/O Frame Buffer Data Bus
MD49 MD49 Y24 I/O Frame Buffer Data Bus
MD48 MD48 Y25 I/O Frame Buffer Data Bus
MD47 MD47 AB24 I/O Frame Buffer Data Bus

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.5 Frame Buffer Memory Signals (Continued)

Abbr.
Name Position Type Description
Name
MD46 MD46 AC26 I/O Frame Buffer Data Bus
MD45 MD45 AA24 I/O Frame Buffer Data Bus
MD44 MD44 AB23 I/O Frame Buffer Data Bus
MD43 MD43 AA23 I/O Frame Buffer Data Bus
MD42 MD42 AA26 I/O Frame Buffer Data Bus
MD41 MD41 Y23 I/O Frame Buffer Data Bus
MD40 MD40 Y26 I/O Frame Buffer Data Bus
MD39 MD39 AA25 I/O Frame Buffer Data Bus
MD38
tC l MD38 AB25 I/O Frame Buffer Data Bus
No ntia
y
MD37 MD37 AB26 I/O Frame Buffer Data Bus
MD36
MD35
op MD36
MD35
AC24
AC25
I/O
I/O
Frame Buffer Data Bus
Frame Buffer Data Bus
MD34 MD34 AE26 I/O Frame Buffer Data Bus
Do fide

MD33 MD33 AF23 I/O Frame Buffer Data Bus

MD32 MD32 AD23 I/O Frame Buffer Data Bus
MD31 MD31 A25 I/O Frame Buffer Data Bus
MD30 MD30 C25 I/O Frame Buffer Data Bus
n

MD29 MD29 D24 I/O Frame Buffer Data Bus

MD28 MD28 E26 I/O Frame Buffer Data Bus
Co

MD27 MD27 E24 I/O Frame Buffer Data Bus

MD26 MD26 G26 I/O Frame Buffer Data Bus
MD25 MD25 H25 I/O Frame Buffer Data Bus
MD24 MD24 G24 I/O Frame Buffer Data Bus
MD23 MD23 H24 I/O Frame Buffer Data Bus
MD22 MD22 H26 I/O Frame Buffer Data Bus
MD21 MD21 G25 I/O Frame Buffer Data Bus
MD20 MD20 F24 I/O Frame Buffer Data Bus
MD19 MD19 G23 I/O Frame Buffer Data Bus

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.5 Frame Buffer Memory Signals (Continued)

Abbr.
Name Position Type Description
Name
MD18 MD18 F25 I/O Frame Buffer Data Bus
MD17 MD17 F26 I/O Frame Buffer Data Bus
MD16 MD16 F23 I/O Frame Buffer Data Bus
MD15 MD15 J25 I/O Frame Buffer Data Bus
MD14 MD14 K24 I/O Frame Buffer Data Bus
MD13 MD13 L23 I/O Frame Buffer Data Bus
MD12 MD12 L24 I/O Frame Buffer Data Bus
MD11 MD11 M23 I/O Frame Buffer Data Bus
MD10
tC l MD10 M24 I/O Frame Buffer Data Bus
No ntia
y
MD9 MD9 N25 I/O Frame Buffer Data Bus
MD8
MD7
op MD8
MD7
N24
E23
I/O
I/O
Frame Buffer Data Bus
Frame Buffer Data Bus
MD6 MD6 E25 I/O Frame Buffer Data Bus
Do fide

MD5 MD5 D26 I/O Frame Buffer Data Bus

MD4 MD4 D25 I/O Frame Buffer Data Bus
MD3 MD3 A26 I/O Frame Buffer Data Bus
MD2 MD2 C24 I/O Frame Buffer Data Bus
n

MD1 MD1 B26 I/O Frame Buffer Data Bus

MD0 MD0 C26 I/O Frame Buffer Data Bus
Co

MDM15 MDM15 AE4 Output Frame Buffer Data Bus Mask

MDM14 MDM14 AF9 Output Frame Buffer Data Bus Mask
MDM13 MDM13 AF4 Output Frame Buffer Data Bus Mask
MDM12 MDM12 AD11 Output Frame Buffer Data Bus Mask
MDM11 MDM11 AF10 Output Frame Buffer Data Bus Mask
MDM10 MDM10 AD15 Output Frame Buffer Data Bus Mask
MDM9 MDM9 AE11 Output Frame Buffer Data Bus Mask
MDM8 MDM8 AE15 Output Frame Buffer Data Bus Mask
MDM7 MDM7 W26 Output Frame Buffer Data Bus Mask

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.5 Frame Buffer Memory Signals (Continued)

Abbr.
Name Position Type Description
Name
MDM6 MDM6 R24 Output Frame Buffer Data Bus Mask
MDM5 MDM5 W25 Output Frame Buffer Data Bus Mask
MDM4 MDM4 T24 Output Frame Buffer Data Bus Mask
MDM3 MDM3 P24 Output Frame Buffer Data Bus Mask
MDM2 MDM2 J26 Output Frame Buffer Data Bus Mask
MDM1 MDM1 R25 Output Frame Buffer Data Bus Mask
MDM0 MDM0 J23 Output Frame Buffer Data Bus Mask
MDSF_A MDSFA T26 Output Frame Buffer A Special Function
MSDF_B
tC l MDSFB AF6 Output Frame Buffer B Special Function
No ntia
y
MRAS_A MRASA K25 Output Frame Buffer Port A RAS
MRAS_B
MWE_A
op MRASB
MWEA
AD14
J24
Output
Output
Frame Buffer Port B RAS
Frame Buffer Port A Write Enable
MWE_B MWEB AD13 Output Frame Buffer Port B Write Enable
Do fide

Table 3.6 Monitor Signals

Abbr.
Name Position Type Description
Name
n

BLUE BLUE B12 Output DAC Analog Blue

DAC_RSET DRSET B11 Wire DAC Full Scale Set
Co

GREEN GREEN A12 Output DAC Analog Green

HSYNC HSYNC A3 Output Horizontal Sync to Monitor
RED RED D12 Output DAC Analog Red
VSYNC VSYNC A1 Output Vertical Sync to Monitor

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.7 VMI Interface Signals

Abbr.
Name Position Type Description
Name
VMI_BLANK VBLNK C14 I/O External VMI Blank Signal
VMI_CS_N VCS A9 I/O External VMI Chip Select
VMI_DS_N VDS B8 I/O External VMI Data Strobe
VMI_HA3 VHA3 B9 Output VMI Host Port Address Bus
VMI_HA2 VHA2 B13 Output VMI Host Port Address Bus
VMI_HA1 VHA1 C12 Output VMI Host Port Address Bus
VMI_HA0 VHA0 A14 Output VMI Host Port Address Bus
VMI_HD7
tC l VHD7 D6 I/O VMI Host Port Data Bus
No ntia
y
VMI_HD6 VHD6 C6 I/O VMI Host Port Data Bus
VMI_HD5
VMI_HD4
op VHD5
VHD4
D7
C7
I/O
I/O
VMI Host Port Data Bus
VMI Host Port Data Bus
VMI_HD3 VHD3 C8 I/O VMI Host Port Data Bus
Do fide

VMI_HD2 VHD2 D9 I/O VMI Host Port Data Bus

VMI_HD1 VHD1 C9 I/O VMI Host Port Data Bus
VMI_HD0 VHD0 A10 I/O VMI Host Port Data Bus
VMI_HSYNC VHSYNC D14 I/O VMI Horizontal Sync
n

VMI_INT_N VINT A6 I/O VMI Interrupt

VMI_PCLK VPCLK C13 I/O VMI Pixel Clock
Co

VMI_PD7 VPD7 B15 I/O VMI Pixel Bus

VMI_PD6 VPD6 A15 I/O VMI Pixel Bus
VMI_PD5 VPD5 D16 I/O VMI Pixel Bus
VMI_PD4 VPD4 C15 I/O VMI Pixel Bus
VMI_PD3 VPD3 B16 I/O VMI Pixel Bus
VMI_PD2 VPD2 A16 I/O VMI Pixel Bus
VMI_PD1 VPD1 A17 I/O VMI Pixel Bus
VMI_PD0 VPD0 C16 I/O VMI Pixel Bus
VMI_RDY_N VRDY A7 I/O VMI Ready

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.7 VMI Interface Signals (Continued)

Abbr.
Name Position Type Description
Name
VMI_RESET_N VRST B7 I/O VMI Reset
VMI_RW_N VRW A8 I/O VMI Host Port Read/Write
VMI_VSYNC VVSYNC B14 I/O VMI Vertical Sync

Table 3.8 Digital RGB Interface Signals

Abbr.
Name Position Type Description
Name
TV_BLANK TBLNK A20 I/O Digital RGB Blank
TV_CLK_OUT tC l TCLKO B20 I/O Digital RGB Clock Out
No ntia
y
TV_DATA11 TVD11 B21 IO Digital RGB Data Bus
TV_DATA10
TV_DATA9
op TVD10
TVD9
C21
D22
IO
IO
Digital RGB Data Bus
Digital RGB Data Bus
TV_DATA8 TVD8 A22 IO Digital RGB Data Bus
Do fide

TV_DATA7 TVD7 B22 IO Digital RGB Data Bus

TV_DATA6 TVD6 C22 IO Digital RGB Data Bus
TV_DATA5 TVD5 A23 IO Digital RGB Data Bus
TV_DATA4 TVD4 B23 IO Digital RGB Data Bus
n

TV_DATA3 TVD3 C23 IO Digital RGB Data Bus

TV_DATA2 TVD2 B24 IO Digital RGB Data Bus
Co

TV_DATA1 TVD1 A24 IO Digital RGB Data Bus

TV_DATA0 TVD0 B25 IO Digital RGB Data Bus
TV_HSYNC THSYNC A21 I/O Digital RGB HSYNC
TV_INCLK TICLK D20 Input Digital RGB Clock In
TV_RESET TRST C20 I/O Digital RGB Reset
TV_VSYNC TVSYNC D21 I/O Digital RGB VSYNC

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.9 Miscellaneous Pins

Abbr.
Name Position Type Description
Name
CLK_OUT CLKO D13 Output Clock Out
GPIO_2 GPIO2 C4 Input General Purpose I/O Bus
GPIO_1 GPIO1 B4 Output General Purpose I/O Bus
GPIO_0 GPIO0 A4 I/O General Purpose I/O Bus
ROM_CS_N ROMCS B6 Output ROM Chip Select
ROM_OE_N ROMOE A5 Output ROM Output Enable
ROM_WE_N ROMWE C5 Output ROM Write Enable
SDA1
tC l SDA1 D5 I/O VMI (Feature Connector)
No ntia
y
SDA0 SDA0 B3 I/O DDC (Monitor Connector)
SDC1
SDC0
op SCK1
SCK0
B5
C3
I/O
I/O
VMI (Feature Connector)
DDC (Monitor Connector)
XIN XIN A19 Analog Crystal In
Do fide

XOUT XOUT C18 Analog Crystal Out

Unused AE13 Unused No Connect
n
Co

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.10 Power and Ground Pins

Abbr.
Name Position Type Description
Name
AGP_PLL_VDD APVDD D18 Power AGP_PLL Power
AGP_PLL_VSS APVSS C17 Ground AGP_PLL Ground
DAC_AVDD DAVDD D11 Power DAC Power
DAC_AVDD_I DAVDDI C11 Power DAC Power
DAC_AVSS DAVSS A11 Ground DAC Ground
DAC_AVSS_R DVSSR B10 Ground DAC Ground
GND12 GND D10 Ground Digital Ground
GND11
tC l GND D17 Ground Digital Ground
No ntia
y
GND10 GND D23 Ground Digital Ground
GND9
GND8
op GND
GND
K23
U23
Ground
Ground
Digital Ground
Digital Ground
GND7 GND AC23 Ground Digital Ground
Do fide

GND6 GND AC17 Ground Digital Ground

GND5 GND AC10 Ground Digital Ground
GND4 GND AC4 Ground Digital Ground
GND3 GND U4 Ground Digital Ground
n

GND2 GND K4 Ground Digital Ground

GND1 GND D4 Ground Digital Ground
Co

IDDQ IDDQ A2
PLL_AVDD1 PAVDD1 C19 Power Phase Locked Loop Power
PLL_AVDD0 PAVDD0 B18 Power Phase Locked Loop Power
PLL_AVSS1 PAVSS1 B19 Ground Phase Locked Loop Ground
PLL_AVSS0 PAVSS0 A18 Ground Phase Locked Loop Ground
Thermal Balls T_BALL J:V 18:9 Ground Thermal Control (100 pins)
VBG VBG C10
VCC8 VCC D8 Power Digital Power
VCC7 VCC D19 Power Digital Power

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

Table 3.10 Power and Ground Pins (Continued)

Abbr.
Name Position Type Description
Name
VCC6 VCC H23 Power Digital Power
VCC5 VCC W23 Power Digital Power
VCC4 VCC AC19 Power Digital Power
VCC3 VCC AC8 Power Digital Power
VCC2 VCC W4 Power Digital Power
VCC1 VCC H4 Power Digital Power
VCC_CORE9 VCC_C P26 Power Digital Power
VCC_CORE8 VCC_C A13 Power Digital Power
VCC_CORE7
tC l VCC_C D15 Power Digital Power
No ntia
y
VCC_CORE6 VCC_C T25 Power Digital Power
VCC_CORE5
VCC_CORE4
op VCC_C
VCC_C
AF14
AD12
Power
Power
Digital Power
Digital Power
VCC_CORE3 VCC_C U3 Power Digital Power
Do fide

VCC_CORE2 VCC_C P1 Power Digital Power

VCC_CORE1 VCC_C N3 Power Digital Power
n
Co

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

3.4 Pin Descriptions

The following sections are the detailed, formal pin descriptions. These descriptions are organized exactly
the same as the tables.
3.4.1 PCI Interface
The pins on the PCI interface connect directly to the corresponding pins on the PCI bus. These pins are
organized so that short, direct traces can be run to the connector.
Name Description
PCI_AD[31:0] PCI Address and Data: This multiplexed, bidirectional bus transfers address and data
during any memory or I/O transaction. The address is on the bus during the clock phase in
which PCI_FRAME is active. For I/O, this is a byte address; for configuration and memory
transactions, this is a DWORD address. During the data phase(s), PCI_AD[7:0] contain
the least significant byte and PCI_AD[31:24] contain the most significant byte. Write data
is stable and valid when PCI_IRDY_N is asserted and read data is stable and valid when
PCI_TRDY_N is asserted. Data is transferred during those clocks in which both
PCI_IRDY_N and PCI_TRDY_N are asserted.

PCI_CBE[3:0] PCI Bus Command and Byte Enables: These multiplexed pins transfer the bus

tC l
command and byte enables for any transaction. During the address phase, these pins are
No ntia
driven by the initiator with the bus command. During data phase(s) these pins are used as

y
byte enables. Byte Enables are valid for the entire data cycle and specify the byte lanes
that carry meaningful data. PCI_CBE0 is associated with PCI_AD[7:0]; PCI_CBE3 is

PCI_CLK
op
associated with PCI_AD[31:24].

PCI Clock: The clock provides timing for all transactions on PCI. All PCI timing is defined
with respect to the rising edge of this clock. Voodoo3 supports 66 MHz PCI Clock.
Do fide

PCI_DEVSEL PCI Bus Device Select: When a device drives this signal active, it indicates the device
has decoded the address on the bus as belonging to itself. This signal is a sustained Tri-
State output as defined in the PCI specification.

PCI_FRAME PCI Bus Cycle Frame: This signal is driven by the initiator to indicate the beginning and
duration of an access. PCI_FRAME is asserted to indicate a bus transaction is beginning.
While PCI_FRAME is active, data transfers continue. When PCI_FRAME is deasserted,
the transaction is in the final data phase.
n

PCI_GNT_N PCI Bus Grant: This input indicates to the agent that bus access is granted. This is a
Co

point-to-point signal; each master has its own GNT. This pin is used without PCI bus
request (REQ#) for AGP mastership.

PCI_IDSEL PCI Bus Initialization Device Select: This input is a chip select in lieu of the upper 24
address lines during configuration read and write cycles. This signal is replaced with AD16
when Voodoo3 is configured for AGP.

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 Voodoo3 High Performance Graphics Engine for 3D Game Acceleration

3.4.1 PCI Interface (cont)

Name Description
PCI_INTA_N PCI Bus Interrupt Request: This open-collector output is driven low when Voodoo3 is
requesting an interrupt. This pin is always connected to INTA#.

PCI_IRDY_N PCI Bus Initiator Ready: This active-low signal indicates the initiating agent’s ability to
complete the current data phase of the transaction. A data phase is completed on any
clock during which both PCI_IRDY_N and PCI_TRDY_N are sampled active. During a
write, PCI_IRDY_N indicates that valid data is present on PCI_AD[31:0]. During a read,
PCI_IRDY_N indicates the bus master is ready to accept data. Wait cycles are inserted
until both PCI_IRDY_N and PCI_TRDY_N are asserted together.

PCI_PAR PCI Bus Parity: This signal provides even parity across PCI_AD[31:0] and PCI_CBE[3:0].
Parity generation is required for all PCI agents. Voodoo3 does not check parity.

PCI_RESET_N PCI Reset: This active-low signal initializes the Voodoo3 to a known state. On the rising
edge of PCI_RESET_N, the chip reads configuration information from the VMI address
and data buses. See Chapter 4. Also, subsystem and subsystem vendor information is

tC l
loaded from four bytes of the ROM into PCI2C. See the description of PCI2C in the SW
No ntia
Programming Guide.

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PCI_STOP_N PCI Bus Stop Request: This active-low signal indicates the target is requesting the

PCI_TRDY_N
op
master to stop the current transaction. This signal is a sustained Tri-State output as
defined in the PCI specification.

PCI Bus Target Ready: This active-low signal indicates the target’s ability to complete the
current data phase of the transaction. A data phase is completed on any clock during
Do fide

which both PCI_IRDY_N and PCI_TRDY_N are sampled active. During a write,
PCI_TRDY_N indicates that the target is ready to accept data. During a read,
PCI_TRDY_N indicates valid data is present on PCI_AD[31:0]. Wait cycles are inserted
until both PCI_IRDY_N and PCI_TRDY_N are asserted together. This signal is a
sustained Tri-State output as defined in the PCI specification.
n
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3.4.2 AGP Interface

The pins on the AGP interface connect directly to the corresponding pins on the AGP bus. These pins are
organized so that short, direct traces can be run to the connector.
Name Description
AGP_AD_STB1 AGP AD Bus Strobe 1: This input provides timing for 2X data transfer mode on
AD[31:16].

AGP_AD_STB0 AGP AD Bus Strobe 2: This input provides timing for 4X data transfer mode on AD[15:0].

AGP_RBF_N AGP Bus Read Buffer Full: When this active-low output is asserted, the arbiter is not
allowed to initiate the return of low priority read data to the master.

AGP_SB_STB: AGP Sideband Strobe: This output provides timing for SBA[7:0] and is always driven by
the AGP master. When the Sideband Strobes have been idle, a synchronization cycle
must be performed before a request can be enqueued.

AGP_SBA[7:0] AGP Bus Sideband Address Port: This bus provides an additional bus to pass address
and command from the master to the target.

AGP_ST[2:0]
tC l
AGP Bus Status: This bus provides information from the arbiter to the Voodoo3 on what it
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may do. This bus has meaning only when PCI_GNT_N is asserted.

AGP_VREF AGP Voltage Reference: This input supplies the switching threshold for the AGP
op
receivers. This input is derived from VDDQ3.3 on the AGP interface through a voltage
divider network. See the schematic diagram of the reference design.
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3.4.3 Frame Buffer Memory

This group of pins provide the interface to the SGRAM/SDRAM frame buffer. The A and B ports connect to
the SGRAM/SDRAMs providing MD[63:0] and MD[127:64], respectively. Doubling up on control lines
reduces the loading and makes for a tighter layout. MCS0 and MCS1 connect to two banks of four devices
each.
Name Description
MA_A[10:0] Memory Address A Bus: This multiplexed bus supplies the address to the SGRAM/
SDRAMs providing MD[63:0].
The exact connections of the MA lines to the SGRAM/SDRAM inputs depends on the
memory devices, as detailed in the table. The device pin names in this table are Samsung
nomenclature.

8 Mbit 16 Mbit 16 Mbit

Pin
SGRAM SGRAM SDRAM
MA_A/B[8:0] A[8:0] A[8:0] A[8:0]
MA_A/B[9] n/c (BA1 on 16 Mbit) BA1 A[9]

tC l
MA_A/B[10] BA0 (band address) BA1 BA
No ntia
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MCS_0 A10 (MD[127:64])
Bank Select
op
MCS_1 A10 (MD[63:0])

MA_B[10:0] Memory Address B Bus: This multiplexed bus supplies the address to the SGRAM/
SDRAMs providing MD[127:64].
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MCAS_A Memory Column Address Strobe A: This signal supplies CAS to the SGRAM/SDRAMs
providing MD[63:0].

MCAS_B Memory Column Address Strobe B: This signal supplies CAS to the SGRAM/SDRAMs
providing MD[127:64].
n

MCLKA Memory Clock A: This signal supplies the clock to the SGRAM/SDRAMs providing
MD[63:0]. This signal requires one series termination resistor placed as close to the pin as
possible for each SGRAM/SDRAM. The evaluation board uses 0 ohms. In addition, this
Co

pin drives MCLKA_IN. This minimizes clock skew when the SGRAM/SDRAMs are
supplying data to Voodoo3.

MCLKA_IN Memory Clock A Feedback: This input supplies the clock which latches read data from
the SGRAM/SDRAMs providing MD[63:0]. This input must be driven from MCLKA.

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3.4.3 Frame Buffer Memory (cont)

Pin Description
MCLKB Memory Clock B: This signal supplies the clock to the SGRAM/SDRAMs providing
MD[127:64]. This signal requires one series termination resistor placed as close to the pin
as possible for each SGRAM/SDRAM. The evaluation board uses 0 ohms. In addition, this
output drives MCLKB_IN. This minimizes clock skew when the SGRAM/SDRAMs are
supplying data to Voodoo3.

MCLKB_IN Memory Clock B Feedback: This input supplies the clock which latches read data from
the SGRAM/SDRAMs providing MD[127:64]. This input must be driven from MCLKB.

MCS_0 Memory Chip Select 0: This output connects to the first bank of four SGRAM/SDRAMs.

MCS_1 Memory Chip Select 1: This output connects to an optional second bank of SGRAMs.
This pin is not used if the array is SDRAMs.

MD[127:0] Memory Data Bus: This is a 128-bit bidirectional data bus. The evaluation board uses the
following connections for the first bank. The connections to the second bank are the same

tC l
except they use MCS_1.
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Device: U1 U2 U3 U4

op
MD
MDM
[31:0]
[3:0]
[63:32]
[7:4]
[95:64]
[11:8]
[127:96]
[15:12]
Controls, Address A A B B
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Chip Select 0 0 0 0

MDM[15:0] Frame Buffer Data Mask: This bus provides the byte-write mask for the 128-bit data.

MDSF_A Frame Buffer Special Function A: This pin supplies the special function control for the
SGRAMs providing MD[63:0]. This is a no-connect in a SDRAM array.
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MDSF_B Frame Buffer Special Function B: This pin supplies the special function control for the
SGRAMs providing MD[127:64]. This is no-connect in a SDRAM array.
Co

MRAS_A Frame Buffer Row Address Strobe A: This pin supplies RAS for the SGRAM/SDRAMs
providing MD[63:0].

MRAS_B Frame Buffer Row Address Strobe B: This pin supplies RAS for the SGRAM/SDRAMs
providing MD[127:64].

MWE_A Frame Buffer Write Enable A: This pin supplies write enable for the SGRAM/SDRAMs
providing MD[63:0].

MWE_B Frame Buffer Write Enable B: This pin supplies write enable for the SGRAM/SDRAMs
providing MD[127:64].

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3.4.4 Monitor
These pins are the monitor interface.
Bit Description
BLUE Pixel Blue Content: This analog output supplies current corresponding to the blue
content of the pixel being refreshed. This output should have a 75 ohm resistor returned to
DAC_VSS placed as close to the pin as possible. The monitor should supply a 75 ohm
parallel termination for a net impedance of 37.5 ohms. The evaluation board has surge
suppression diodes to VCC and ground and a low-pass filter consisting of a bead and 22
pF capacitor close to the DB-15 connector.

DAC_RSET Video DAC RSET: This pin is used to set the full scale DAC output current. A resistor must
be connected between this pin and DAV_VSS. On the evaluation board, this is 56.2 ohms,
1% tolerance.

GREEN Pixel Green Content: This analog output supplies current corresponding to the green
content of the pixel being refreshed. This output should have a 75 ohm resistor returned to
DAC_VSS placed as close to the pin as possible. The monitor should supply a 75 ohm
parallel termination for a net impedance of 37.5 ohms. The evaluation board has surge
suppression diodes to VCC and ground and a low-pass filter consisting of a bead and 22
tC l
pF capacitor close to the DB-15 connector.
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HSYNC Horizontal Sync: This output supplies horizontal sync to the monitor. This output should

op
have a series termination resistor placed as close to the pin as possible. The evaluation
board uses 47 ohms. The evaluation board has a low-pass filter consisting of a bead and
100 pF capacitor close to the DB-15 connector.

RED Pixel Red Content: This analog output supplies current corresponding to the red content
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of the pixel being refreshed. This output should have a 75 ohm resistor returned to
DAC_VSS placed as close to the pin as possible. The monitor should supply a 75 ohm
parallel termination for a net impedance of 37.5 ohms. The evaluation board has surge
suppression diodes to VCC and ground and a low-pass filter consisting of a bead and 22
pF capacitor close to the DB-15 connector.

VSYNC Vertical Sync: This output supplies vertical sync to the monitor. This output should have a
series termination resistor placed as close to the pin as possible. The evaluation board
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uses 47 ohms. The evaluation board has a low-pass filter consisting of a bead and 100 pF
capacitor close to the DB-15 connector.
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3.4.5 VMI Interface

Bit Description
VMI_BLANK VMI VACTIVE: This input indicates that valid pixel data is being transmitted on
VMI_PD[7:0]. Although transitions in VACTIVE are allowed to support common HREF/
VREF systems, VACTIVE is intended to allow a hardware mechanism for cropping data.

VMI_CS_N VMI Chip Select: This output supplies the chip select for the VMI Host interface.

VMI_DS_N VMI Data Strobe: When the VMI interface is configured for mode A, this is an active-low
data strobe. When the VMI interface is configured for mode B, this is an active-low read
command. This pin also supplies ROM address bit 15.

VMI_HA[3:0] VMI Host Port Address Bus: This bus supplies the address for the VMI host interface
port. This bus also supplies ROM address bits [11:8].

VMI_HD[7:0] VMI Host Port Data Bus: This bidirectional bus transfers data across the VMI host
interface port. This bus is also used as the ROM data bus.

VMI_HSYNC VMI HREF: This input is the horizontal reference from the VMI video port.

tC l
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VMI_INT_N VMI INTREQ#: This active input is the interrupt request from the VMI interface. This pin

y
also supplies ROM address bit 13.

VMI_PCLK

VMI_PD[7:0]
op
VMI PIXCLK: This input is the pixel clock from the VMI video port.

VMI YUV Video Data Bus: This input bus is the pixel data from the VMI video port. This
bus is also the low order eight bits of the ROM address bus.
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VMI_RDY_N VMI DTACK#/READY: When the VMI interface is configured for mode A, this is active
DTACK# (extend transaction). When the VMI interface is configured for mode B, this is
active high READY. This pin also supplies ROM address bit 12.

VMI_RESET_N VMI RESET: This active low signal resets the VMI interface and/or devices to a known
condition.

VMI_RW_N VMI R/W# WR#: When the VMI interface is configured for mode A, this is the read/write
n

indicator. When the VMI interface is configured for mode B, this is an active low write
command. This pin also supplies ROM address bit 14.
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VMI_VSYNC VMI VREF: This input is the vertical reference from the VMI video port.

3.4.6 Digital RGB Interface Signals

This interface supplies digital RGB. It is typically used to drive an LCD encoder or TV encoder, but could be
used for any other application requiring digital RGB.
Pin Description
TV_BLANK TV_BLANK_N: This active low output is the blank signal for the digital RGB out port.

TV_CLK_OUT TV Clock Out: This output supplies the clock for the digital RGB out port.

TV_DATA[11:0] TV Data Out: This 12-bit bus supplies digital RGB data for the digital RGB out port.

TV_HSYNC TV_HSYNC: This pin supplies horizontal sync for the digital RGB out port.

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3.4.6 Digital RGB Interface Signals (cont)

Pin Description
TV_INCLK TV Clock In: This input is the clock for the digital RGB out port for slave mode.

TV_RESET TV_RESET_N: This is a reset for the digital RGB out port.

TV_VSYNC TV_VSYNC: This pin supplies vertical sync for the digital RGB out port.

3.4.7 Miscellaneous Pins

The following pins didn’t fall into any of the other groups.
Pin Description
CLK_OUT Clock Out: This clock is used for testing. This is brought to a test point on the reference
design but is otherwise not connected.

GPIO_[2:0] General Purpose I/O[2:0]: These pins are dedicated for general purpose I/O. The table
indicates how they are assigned on the evaluation board.

tC l Signal
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Name Pin Purpose
Label

op
GPIO_2
GPIO_1
C4
B4
GPIO_2_RD
No connect
INSERT# (Z19) on VMI host connector
-

GPIO_0a A4 ROM_ACTIVE Controls BE on analog switch chip (U3)

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a. This pin is active (high) when the ROM is accessed (PCI10 + 0x00A0 xxxx).

ROM_CS_N ROM Chip Select: This output connects to the CE pin of the ROM.

ROM_OE_N ROM Output Enable: This output connects to the OE pin of the ROM. This pin is active
with ROM_CS_N to read the ROM.
n

ROM_WE_N ROM Write Enable: This output connects to the WE pin of the ROM. This pin is active
with ROM_CS_N for ROM writes (for updating the BIOS).
Co

SDA[1:0] Serial Data[1:0]: These are the data pins of the two I2C interfaces. SDA1 is used for the
feature connector interface, both the TV and xLCD encoders, and the LCD panel
connector. SDA0 is used for the CRT monitor (DDC2B) interface.

SDC[1:0] Serial Clock[1:0]: These are the clock pins of the two I2C interfaces. SDC1 is used for the
feature connector interface, both the TV and xLCD encoders, and the LCD panel
connector. SDC0 is used for the CRT monitor (DDC2B) interface.

XIN Crystal In: This pin connects to one side of the reference oscillator crystal. No external
resistor or capacitors are required. Voodoo3 has internal capacitors. The oscillator is
designed for a 18 pF, parallel resonant crystal. 3dfx Interactive, Inc. recommends a
tolerance of 50 ppm.

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3.4.7 Miscellaneous Pins (cont)

Pin Description
XOUT Crystal Out: This pin connects to one side of the reference oscillator crystal.

Unused No Connect: The following pin is a no connect: AE13

3.4.8 Power and Ground

These are the power and ground pins.
Bit Description
AGP_PLL_VDD AGP_PLL Power: This pin supplies power to the AGP PLL. This supply is decoupled from
V2_5 (2.5V supply) with a bead and then four capacitors: 4.7 uF, 0.1 uF, 0.01 uF, and
0.001 uF. The filters should be close to the pin.

AGP_PLL_VSS AGP_PLL Ground Reference: This pin supplies ground reference to the AGP PLL. It
must be connected directly to the ground plane.

DAC_AVDD/I
tC l
DAC Power: These two pins supply power to the DACs. They are adjacent on the
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package. This supply is decoupled from V2_5 (2.5V supply) with a bead and then four

y
capacitors: 4.7 uF, 0.1 uF, 0.01 uF, and 0.001 uF. The filters should be close to the pins.

DAC_AVSS/R

GND[12:1]
op
DAC Ground Reference: These two pins supply ground reference to the DACs. They
must be connected directly to the ground plane.

Digital Ground Reference: These twelve pins supply ground reference to the digital
circuitry. Each must be connected directly to the ground plane.
Do fide

IDDQ Output Enable Disable: This pin must be pulled to VCC.

PLL_AVDD[1:0] PLL Power: These two pins supply power to the PLLs.This supply is decoupled from
V2_5 (2.5V supply) with a bead and then four capacitors: 4.7 uF, 0.1 uF, 0.01 uF, and
0.001 uF. The filters should be close to the pins.

PLL_AVSS[1:0] PLL Ground Reference: These two pins supply ground reference to the PLLs.
n

Thermal Thermal Pads: These 100 pins must be connected directly to the ground plane. They are
intended to conduct heat out of the chip onto the PC board. These pins are internally
Co

connected to the substrate.

VGB This pin is not connected on the reference design.

VCC[8:1] Digital Power: These eight pins supply power to the digital circuitry. Each must be
connected directly to the power plane. These pins must be well bypassed.

VCC_CORE[9:1]Digital Power: These nine pins supply power to the digital circuitry. Each must be
connected directly to the power plane. These pins must be well bypassed.

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4 Configuration Options
When PCI_RST goes not active, the levels on VMI_HA[3:0] and VMI_HD[7:0] are loaded into a set of
configuration latches. These latches control Voodoo3 behavior. Most of the strapping options can be
sensed by software.
To load a zero into a configuration latch, connect a 4700 ohm resistor between the corresponding pin and
ground. To load a one into a configuration latch, connect a 4700 ohm resistor between the corresponding
pin and 3.3V. Every one of the twelve pins must have a resistor to either power or ground in order to
prevent the pin from floating to threshold.

Table 4.1 Strapping Options

Bit Pin Description Level Readback

11 VMI_HA3 PLL_BYPASS (used with bit 2)
10 VMI_HA2 Memory Type 0: SGRAMs
1: SDRAMs
9 VMI_HA1 SGRAM Init 0: Normal Operation
tC l 1: Test Mode
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8 VMI_HA0 IDSEL Select 0: IDSEL (PCI)

7 VMI_HD7
op Disable PCI IRQ Register
1: PCI_AD16 (AGP)
0: Enable
1: Disable
6 VMI_HD6 SGRAM/SDRAM Size 0: 8 Mbit miscInit1[30]
Do fide

1: 16 Mbit
5 VMI_HD5 SGRAM/SDRAM Count 0: 4 Chips miscInit1[29]
1: 8 Chips
4 VMI_HD4 PCI Device Type 0: VGA miscInit1[28]
1: Other Multimedia
n

3 VMI_HD3 AGP Enable 0: Disable miscInit1[27]

1: Enable
Co

2 VMI_HD2 PCI 66 MHz 0: 33 MHz miscInit1[26]

1: 66 MHz
1 VMI_HD1 BIOS Size 0: 32K miscInit1[25]
1: 64K
0 VMI_HD0 DEVSEL Timing 0: Medium miscInit1[24]
1: Fast

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5 Digital RGB Data Formats

Digital RGB data is clocked on both edges of the clock. Which bit is clocked on each edge is controlled by
vidInFormat[8].

Table 5.1 Digital RGB Data Formats

vidInFormat[8] = 0 vidInFormat[8] = 1
Chrontel Encoder Brooktree Encoder
Pin
Rising Falling Rising Falling
Edge Edge Edge Edge
TV_DATA[11] G0[4] R0[7] R0[7] G0[4]
TV_DATA[10] G0[3] R0[6] R0[6] G0[3]
TV_DATA[9] G0[2] R0[5] R0[5] G0[2]
TV_DATA[8] B0[7] R0[4] R0[4] B0[7]
tC l
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TV_DATA[7] B0[6] R0[3] R0[3] B0[6]
TV_DATA[6] B0[5] G0[7] G0[7] B0[5]
TV_DATA[5]
TV_DATA[4]
op B0[4]
B0[3]
G0[6]
G0[5]
G0[6]
G0[5]
B0[4]
B0[3]
Do fide

TV_DATA[3] G0[0] R0[2] R0[2] G0[0]

TV_DATA[2] B0[2] R0[1] R0[1] B0[2]
TV_DATA[1] B0[1] R0[0] R0[0] B0[1]
TV_DATA[0] B0[0] G0[1] G0[1] B0[0]
n
Co

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6 General Purpose I/O

This chapter covers general purpose I/O. There are three pins that are dedicated to general purpose I/O,
as shown in Table 6.1.

Table 6.1 Standard GPIO Pins

Signal on Register
Name Pin Direction
Eval Board Assignment
GPIO_2 C4 In GPIO_2_RD vidSerialParallelPort[30]
GPIO_1 B4 Out - vidSerialParallelPort[29]
GPIO_0 A4a I/O ROM_ACTIVE

a. This pin is driven active (high) when the ROM is accessed (PCI10 + 0x00A0 xxxx).

tC l
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7 Serial I/O
There are two serial I/O ports on Voodoo3. Each port comprises two open-drain outputs that can be
controlled and sensed with register bits. These ports are similar to I 2C.
By convention, Serial Port 0 is used for DDC (it is wired to the monitor connector).
Serial Port 1 is used for VMI (it is wired to the Feature Connector), the TV encoder and xLCD encoder, and
the panel LCD connector.

The following table shows the pin and register bit assignments for the two serial ports.

Table 7.1 Serial I/O Assignments

vidSerialParallelPort bits
Signal
Pin
Name Enable In Out
SDA1 D5 23 27 25
SDC1 B5 23 26 24
tC l
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SDA0 B3 18 22 20

y
SDC0 C3 18 21 19
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8 ROM Access
By convention, a graphics adapter card includes a BIOS in a ROM. Twenty-three of the 26 pins needed to
access the ROM are multiplexed with VMI pins, as shown in Table 8.1.

Table 8.1 ROM Access Pins

ROM Function Pin Name Pin

A15 VMI_DS_N B8
A14 VMI_RW_N A8
A13 VMI_INT_N A6
A12 VMI_RDY_N A7
A11 VMI_HA3 B9
A10 VMI_HA2 B13
A9 tC l VMI_HA1 C12
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A8 VMI_HA0 A14
A7
A6
op VMI_PD7
VMI_PD6
B15
A15
A5 VMI_PD5 D16
Do fide

A4 VMI_PD4 C15
A3 VMI_PD3 B16
A2 VMI_PD2 A16
A1 VMI_PD1 A17
n

A0 VMI_PD0 C16
D7 VMI_HD7 D6
Co

D6 VMI_HD6 C6
D5 VMI_HD5 D7
D4 VMI_HD4 C7
D3 VMI_HD3 C8
D2 VMI_HD2 D9
D1 VMI_HD1 C9
D0 VMI_HD0 A10

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9 DC Specifications
9.1 Absolute Maximum Ratings
Stresses above those listed in Table 9.1 may cause permanent damage to system components. These are
stress ratings only and functional operation at these or any conditions outside those indicated in Table 9.2
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect system
reliability.

Table 9.1 Absolute Maximum Ratings

Symbol Description Rating

TSTG Storage Temperature -40 to 125 degrees C

VIN Input Voltage on any pin -0.5 V to VCC + 0.5 V

VA Power Supply Voltage 3.60 V

IOUT DC output current (per pin) tbd

tC l
No ntia
y
TC Max Case Temperature 105 degrees C

TJ
op
Max Junction Temperature 125 degrees Ca
a. For operation at case temperature above 105 degrees C, consult appl-
ciation note. Maximum junction temperature is 125 degrees C under
any conditions.
Do fide

9.2 DC Characteristics and Recommended Operating Conditions

Table 9.2 DC Characteristics and Recommended Operating Conditions

- 250 - 333
Test
Symbol Description
n

Conditions Min Max Min Max

TC Case Temperature Operating 0°C 100° C 0°C 100° C
Co

VIH Input High Voltage VCC =

VIL Input Low Voltage VCC = 0.0 V 0.8 V 0.0 V 0.8 V

IIH Input High Current VIH = VCC - 10 uA - 10 uA

IIL Input Low Current VIL = -10 uA - -10 uA -

VOH Output High Voltage IOH = 0.9 * VCC - 0.9 * VCC -

VOL Output Low Voltage IOL = - 0.4 V - 0.4 V

IOL Output Leakage 0V ≤ VIN ≤ VCC -10 uA 10 uA -10 uA 10 uA

Current

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Table 9.2 DC Characteristics and Recommended Operating Conditions

- 250 - 333
Test
Symbol Description
Conditions Min Max Min Max
CIN Input Capacitancea All except - 10 pF - 10 pF
XIN, XOUT
CINX Input Capacitance XIN, XOUT tbd tbd tbd tbd

COUT Output Capacitancea - - 10 pF - 10 pF

a. This is not 100% tested, but is periodically sampled.

tC l
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9.3 VCC Limits

Table 9.3 Supply Current and Voltage

Icore IIO Core VCC (volts) I/O VCC (volts)

Device Test Conditions
Typical Typical Min Typ Max Min Typ Max
-250 GRX Clk = 125 MHz 2.00A 0.35A 2.16 2.20 2.27 3.15 3.30 3.45
Core Vcc = 2.20V
I/O Vcc = 3.3V
-333 GRX Clk = 143 MHz 2.47A 0.35A 2.50 2.55 2.63 3.15 3.30 3.45
Core Vcc = 2.55V
I/O Vcc = 3.3V
-333 GRX Clk = 166 MHz 2.94A 0.33A 2.63 2.69 2.77 3.15 3.30 3.45
Core Vcc = 2.69V
I/O Vcc = 3.3V
-XXX GRX Clk = 183 MHz 3.20A 0.36A 2.70 2.76 2.84 3.15 3.30 3.45
Core Vcc = 2.76V
I/O Vcc = 3.3V

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9.4 Package Thermal Characteristics

Table 9.4 Thermal Characteristics

- 250 - 333
Parameter Conditionsa
Degrees C / watt Degrees C / watt
θJA Typical, no heat sink 10.0 n/a
θJA With heat sink n/a 6.0
a. See Application Note to determine actual theta JA and junction temperature.

9.5 DAC Characteristics

Table 9.5 DAC Characteristics

Symbol tC l Parameter MAX Units Conditions Notes

No ntia
y
R Resolution 8 bits
IO
TR
op
Output current
Analog output rise/full time
tbd
tbd
mA
ns
VO < 1V
10% to 90% full scale ab
Do fide

TS Analog output settling time tbd ns 50% FS change to ab

remaining within 2%
TSK Analog output skew tbd ns abcd

FDT DAC-to-DAC correlation tbd % abcd

GI Glitch impulse tbd pV/sec b

n

IL Integral linearity tbd LSB

Co

DL Differential linearity tbd LSB b

a. Load is 50 ohms and 30 pF per analog output.

b. RSET = 147 ohms
c. Outputs loaded identically.
d. About the mid-point of the distribution of the three DAC’s measured at full-scale output.

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10 AC Specifications
In general, these waveforms and tables very closely follow those of the respective specifications.

10.1 Maximum Clock Rates

Table 10.1 shows the maximum rated operational frequencies for Voodoo3.

Table 10.1 Maximum Clock Rates

Maximum Frequency
Clock
-250 -333
GRX 125 MHz 166 MHz
MCLK 125 MHz 166 MHz

tC l
No ntia
y
10.2 Clock Input Timing

2.4 V
op tHIGH

1.5 V
Do fide

0.8 V

tLOW
tCYC
n

Figure 10.1 Clock Input Waveform

Co

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Table 10.2 PCI_CLK Timing

Symbol Parameter Min Max Units

tCYC CLK cycle time 15 30 ns

tHIGH CLK high time 6 - ns

tLOW CLK low time 6 - ns

- CLK slew rate 1.5 4 V/ns

Table 10.3 VMI_PCLK (VMI Video Capture Mode) Timing

Symbol Parameter Min Max Units

tCYC tC l
CLK cycle time 35 - ns
No ntia
y
op
Table 10.4 TV_INCLK (TV out Mode) Timing

Symbol Parameter Min Max Units

Do fide

tCYC CLK cycle time tbd tbd ns

tHIGH CLK high time tbd - ns

tLOW CLK low time tbd - ns

n

Table 10.5 GRX_CLK Timinga

Co

Symbol Parameter Min Max Units

tCYC CLK cycle time tbd tbd ns

tHIGH CLK high time tbd - ns

tLOW CLK low time tbd - ns

a. This clock is used for factory testing. This table is reference only.

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10.3 Clock Out Timing

tHIGH
2.4 V

1.5 V

0.8 V

tLOW
tCYC

Figure 10.2 Clock Out Waveform

Table 10.6 MCLKA/MCLKB Timing

Symbol
tC lParameter Min Max Units
No ntia
y
tCYC CLK cycle time 8.6 - ns

tHIGH

tLOW
op
CLK high time

CLK low time

4

4
-

-
ns

ns
Do fide

Table 10.7 TV_CLK_OUT Timing: TV Out Mode

Symbol Parameter Min Max Units

tCYC CLK cycle time 10 - ns
n

tHIGH CLK high time 5 - ns

Co

tLOW CLK low time 5 - ns

Table 10.8 TV_CLK_OUT Timing: LCD Out Mode

Symbol Parameter Min Max Units

tCYC CLK cycle time 10 - ns

tHIGH CLK high time 5 - ns

tLOW CLK low time 5 - ns

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10.4 Reset Timing

tLOW

PCI_RST

tSU tH

VMI_HA[3:0]
VMI_HD[7:0]

tC l
No ntia
y
Figure 10.3 Reset Waveforms

op
Table 10.9 Reset Timing

Symbol Parameter Min Max Units

tLOW PCI_RST pulse width tbd - PCI_CLK
Do fide

tSU Strapping Resistor Setup 20 - ns

tH Strapping Resistor Hold 20 - ns

n
Co

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10.5 PCI/AGP Transmitter (output) Timing

P_CLK

tON tVALC/D tOFF

Outputs

tC l Figure 10.4 PCI/AGP Transmitter Waveforms

No ntia
y
Table 10.10 PCI/AGP Transmitter (output) Timing

Symbol
tON
op Parameter
Float to active delay
Min
1.0
Max
6
Units
ns
Do fide

tVALC CLK to control signal valid delay 1.0 5.5 ns

tVALD CLK to data valid delay 1.0 6.0 ns

tOFF Active to float delay 1 14 ns

n
Co

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10.6 PCI/AGP Receiver (input) Timing

P_CLK

tSUC/D tH

Inputs

tC l Figure 10.5 PCI/AGP Receiver Waveforms

No ntia
y
Table 10.11 PCI/AGP Receiver (input) Timing

Symbol
tSUC
op Parameter
Control signals setup time to CLK
Min
6.0 -
Max Units
ns
Do fide

tSUD Data setup time to CLK 5.5 - ns

tH Control signals hold time to CLK 0.0 - ns

n
Co

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10.7 Frame Buffer Output Timing

MCLK

tON tVAL tOFF

Outputs

tC l Figure 10.6 Frame Buffer Output Waveforms

No ntia
y
Table 10.12 Frame Buffer Output Timinga

Symbol
tON
op Parameter
Float to active delay (MD[127:0]) tbd
Min Max
tbd
Units
ns
Do fide

tVAL CLK to control signal valid delay - tbd ns

tVAL CLK to address valid delay - tbd ns

tVAL CLK to MD valid delay - tbd ns

tOFF Active to float delay (MD[127:0]) tbd tbd ns

n

a. 115 MHz MCLK, standard BIOS programming.

Co

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10.8 Frame Buffer Input Timing

MCLK_IN

tSU tH

MD Inputs

tC l Figure 10.7 Frame Buffer Input Waveforms

No ntia
y
Table 10.13 Frame Buffer Input Timinga

Symbol
tSU
op Parameter
MD setup time to MCLK_IN
Min
tbd -
Max Units
ns
Do fide

tH MD hold time to MCLK_IN tbd - ns

a. 115 MHz, standard BIOS programming

n
Co

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10.9 VMI Host Interface Mode A Timing

VMI_HA[3:0]

VMI_HD[7:0] Write Data

VMI_R/W

t1 t3
tC l t6
No ntia
y
VMI_DS_N
op t2
t5
t2
t4
Do fide

VMI_DTACK_N
t7
t8
VMI_HD[7:0]
n

Read Data
Co

Figure 10.8 VMI Host Interface Mode A Waveforms

Table 10.14 VMI Host Interface Mode A Timing a

Symbol Parameter Min Max Units

t1 HA, HD, R/W# setup to DS# low 5 - ns
t2 Delay DTACK# low after DS# low 0 13000 ns
t3 HA, HD R/W# hold after DS# high 5 - ns
t4 Delay DS# high after DTACK# low 5 - ns

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Table 10.14 VMI Host Interface Mode A Timing (Continued)a

Symbol Parameter Min Max Units

t5 Delay DTACK# high after DS# high 0 52 ns
t6 Delay DS# low (next cycle) after DTACK# high 5 - ns
t7 (Read cycle) HD setup until DTACK# low 10 - ns
t8 (Read cycle) HD hold after DS# high 0 - ns
a. The timing parameters of VMI interface host cycles are explicitly controlled by bits in the
vidSerialParallelPort register. The timing diagrams and tables are from the VMI specifica-
tion and are included here for convenience.

tC l
No ntia
y
op
Do fide
n
Co

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10.10 VMI Host Interface Mode B Timing

VMI_HA[3:0]

VMI_CS_N

t1 t11 t2
WR#, RD#

t10
t3 t7
tC l t6
No ntia
y
VMI_READY

op t4 t5

VMI_HD[7:0] Write Data

Do fide

t8
VMI_HD[7:0]
Read Data
n

t9
Co

Figure 10.9 VMI Host Interface Mode B Waveforms

Table 10.15 VMI Host Interface Mode B Timing a

Symbol Parameter Min Max Units

t1 HA, CS# setup until WR# or RD# low 10 - ns
t2 HA, CS# hold after WR# or RD# high 0 - ns
t3 Delay READY low after WR# or RD# low - 28 ns
t4 HD setup until WR# low (write cycle) 5 - ns
t5 HD hold after WR# high (write cycle 10 - ns

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Table 10.15 VMI Host Interface Mode B Timing (Continued)a

Symbol Parameter Min Max Units

t6 READY pulse width 0 - ns
t7 WR# high until any command 38 - ns
t8 HD setup until READY active (read cycle) 0 - ns
t9 HD hold after RD# inactive (read cycle) 0 15 ns
t10 Delay WR# or RD# high after READY high 0 100 ns
t11 Read/Write command pulse width 40 - ns
a. The timing parameters of VMI interface host cycles are explicitly controlled by bits in the
vidSerialParallelPort register. The timing diagrams and tables are from the VMI specifica-
tion and are included here for convenience.

tC l
No ntia
y
op
Do fide
n
Co

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10.11 VMI Video In Timing

VMI_PCLK

t1 t2

VMI_BLANK
t3
t4

VMI_PD[7:0]

tC l
No ntia
y
Figure 10.10 VMI Video In Waveforms

op
Table 10.16 VMI Video In Timing

Symbol Parameter Min Max Units

Do fide

t1 VMI_BLANK (VACTIVE) setup to VMI_PCLK high 5 - ns

t2 VMI_BLANK hold after VMI_PCLK high 0 - ns
t3 VMI_PD[7:0] hold after VMI_PCLK high 0 - ns
t4 VMI_PC[7:0] setup to MVI_PCLK high 5 - ns
n
Co

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10.12 Digital RGB Out Timing

TV_INCLK

t6

TV_CLK_OUT
t1
t3

tC l
No ntia
y
TV_DATA[11:0]

opt2
t4
t5
TV_BLANK
Do fide

TV_HSYNC
TV_VSYNC

Figure 10.11 Digital RGB Out Waveforms

n

Table 10.17 Digital RGB Out Timing

Co

Symbol Parameter Min Max Units

t1 Positive Clock Out to next Digital Data valid - tbd ns
t2 Positive Clock Out to current Digital Data invalid tbd - ns
t3 Negative Clock Out to next Digital Data valid - tbd ns
t4 Negative Clock Out to current Digital Data invalid tbd - ns
t5 Clock to Controls delay - tbd ns
t6 Relationship between TV_INCLK and TV_CLK_OUT tbd tbd ns
(Slave Mode only)

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10.13 ROM Read Cycle

t1

MCLK
(reference)

ROM_AD[15:0]
ROM_CS_N
ROM_OE_N

t2
tC l
No ntia
y
ROM_DATA[7:0] op
Figure 10.12 ROM Read Cycle Waveforms
Do fide

Table 10.18 ROM Read Cycle

Symbol Parameter Min Max Units

t1 MCLK Period (Reference) - - ns
n

t2 ROM_AD[15:0] to Data Valid - tbd t1

t2 ROM_CS_N to Data Valid - tbd t1
Co

t2 ROM_OE_N to Data Valid - tbd t1

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10.14 ROM Write Cycle

t1

MCLK
(reference)

ROM_AD[15:0]
ROM_CS_N
ROM_DATA[7:0]

t2 t3 t4
tC l
No ntia
y
ROM_WE_N op
Figure 10.13 ROM Write Cycle Waveforms
Do fide

Table 10.19 ROM Write Cycle

Symbol Parameter Min Max Units

t1 MCLK Period (Reference) - - ns
n

t2 ROM_AD[15:0] to ROM_WE_N active - tbd t1

t2 ROM_CS_N to ROM_WE_N active - tbd t1
Co

t2 ROM_DATA[7:0] to ROM_WE_N_active - tbd t1

t3 ROM_WE_N Active low pulse width - tbd t1
t4 ROM_AD[15:0] hold from ROM_WE_N inactive - tbd t1
t4 ROM_CS_N hold from ROM_WE_N inactive - tbd t1
t4 ROM_DATA[7:0] hold from ROM_WE_N inactive - tbd t1

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11 Package
11.1 Introduction
The Voodoo3 is supplied in a 352-pin 35-mm BGA package with 100 thermal balls (total of 452 balls).

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 (ref) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A A
B B
C C
D D
E E
F F
G Bottom View G
H H
J Top View L2 J
K K
L D3 L
M D2 D1 M
N N
P P
R R
T(S) T(S) T
U U
V V
W L1 W
Z Y
AA
tC l AA
AB
No ntia
AB

y
AC AC
AD AD
AE AE
AF AF
(ref)
D4
op D3
L2
D1
D2
Do fide

A1 A3
A4
30° typ.

A2 C1 (coplanarity)
n

Figure 11.1 Physical Dimensions

Co

Symbol Minimum (mm) Nominal (mm) Maximum (mm)

A1 1.17 ref
A2 0.56 ref
A3 2.20 2.33 2.46
A4 0.50 0.60 0.70
C1 0.15
D1 31.75
D2 34.80 35.00 35.20
D3 30.00 ref
D4 4.00
L1 0.60 0.75 0.90
L2 1.27

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Pads on the PC board may be placed as shown in Figure 11.2.

L2

L2
L1

Figure 11.2 Pad Layout

tC l
Symbol Minimum (mm) Nominal (mm) Maximum (mm)
No ntia
y
L1 0.71

op
L2 1.27
Do fide
n
Co

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