rst_ps8_0_99M

axi_interconnect_0
slowest_sync_clk mb_reset
ext_reset_in bus_struct_reset[0:0]
S00_AXI
aux_reset_in peripheral_reset[0:0]
ACLK
mb_debug_sys_rst interconnect_aresetn[0:0]
ARESETN
dcm_locked peripheral_aresetn[0:0] axi_intc_0
S00_ACLK

S00_ARESETN
Processor System Reset M00_AXI s_axi
M00_ACLK
zynq_ultra_ps_e_0 M01_AXI s_axi_aclk interrupt
M00_ARESETN
M02_AXI s_axi_aresetn irq
M01_ACLK
S_AXI_HP0_FPD M03_AXI intr[2:0]
M01_ARESETN
S_AXI_HP1_FPD
M_AXI_HPM0_FPD M02_ACLK
maxihpm0_fpd_aclk AXI Interrupt Controller
pl_resetn0 M02_ARESETN
saxihp0_fpd_aclk
pl_clk0 M03_ACLK
saxihp1_fpd_aclk
M03_ARESETN
pl_ps_irq0[0:0]

AXI Interconnect
Zynq UltraScale+ MPSoC usp_rf_data_converter_0

s_axi

adc0_clk s12_axis

dac1_clk adc0_clk

TX dac1_clk
m00_axis
vin0_01
clk_wiz_0 vout12 vout12
xlconcat_0 sysref_in
clk_adc0
s_axi_aclk
reset clk_128 clk_dac1
In0[0:0] s_axi_aresetn
clk_in1 locked irq
In1[0:0] dout[2:0] m0_axis_aresetn
In2[0:0] m0_axis_aclk
Clocking Wizard
M_AXIS_MM2S s1_axis_aresetn
Concat s1_axis_aclk
vin0_01 axi_dma_tx axi_smc
sysref_in Zynq Ultrascale+ RF Data Converter
S_AXI_LITE
reset S_AXI_LITE M_AXI_MM2S S00_AXI
reset M00_AXI
s_axi_lite_aclk M_AXIS_MM2S aclk M00_AXI
clk_in1
m_axi_mm2s_aclk mm2s_prmry_reset_out_n aresetn
axi_resetn mm2s_introut
AXI SmartConnect
AXI Direct Memory Access clk_128

axi_resetn[0:0]

mm2s_introut
reset_128
xlconstant_0
slowest_sync_clk mb_reset
ext_reset_in
dout[0:0] ext_reset_in bus_struct_reset[0:0]
aux_reset_in peripheral_reset[0:0]
Constant
mb_debug_sys_rst interconnect_aresetn[0:0]

dcm_locked peripheral_aresetn[0:0]

Processor System Reset

RX

axi_dma_rx

S_AXI_LITE axi_smc
S_AXI_LITE
S_AXIS_S2MM
S_AXIS_S2MM
M_AXI_S2MM S00_AXI
s_axis_s2mm_tlast M00_AXI
s2mm_prmry_reset_out_n aclk M00_AXI
s_axi_lite_aclk
s2mm_introut aresetn
m_axi_s2mm_aclk

axi_resetn
AXI SmartConnect
clk_128
AXI Direct Memory Access
peripheral_aresetn[0:0]

s2mm_introut

clk_wiz_0

reset
reset clk_128
clk_in1
clk_in1 locked

Clocking Wizard

reset_128

slowest_sync_clk mb_reset
ext_reset_in
ext_reset_in bus_struct_reset[0:0]
s_axis_s2mm_tlast1
aux_reset_in peripheral_reset[0:0]
mb_debug_sys_rst interconnect_aresetn[0:0]

dcm_locked peripheral_aresetn[0:0]

Processor System Reset