Microprocessors & Microcontrollers Module 3

MODULE 3

Topics: Signed number arithmetic, String Instructions, 8255 I/O programming, Memory Interfacing.

3.1 Signed Number Arithmetic operations

In signed-operands , the most significant bit is the sign bit.
If it is byte data , D7 bit is sign bit, and if it is word data , D15 bit is sign bit.

Signed Byte data:

Signed Word data:

⮚ Positive numbers
If the sign bit is 0 then the data is positive, else it is negative.
The maximum positive number that can be represented in byte data is +127. ie., 0111 1111.
If the data is larger than +127, then we must use word-sized data.
The maximum positive number that can be represented in byte data is +32767.

⮚ Negative numbers
The magnitude of negative numbers is represented using 2’s complement. The conversion
is done by Assembler. Following steps are used :
• Write the magnitude of the number.
• Invert each bit
• Add 1 to it.
Ex: Represent how -5 is represented in the computer
5 = 0000 0101
Inverted data = 1111 1010
Adding 1 = 1111 1011
So, -5 = 1111 1011
Examples of negative word data:
Microprocessors & Microcontrollers Module 3

⮚ Overflow problem in signed number operations

In 8-bit signed number operations, OF is set to 1 if either of the following two conditions
occurs:
• There is a carry from D6 to D7 but no carry out of D7 ( CF=0).
• There is a carry from D7 (CF=1) but no carry from D6 to D7.
In 16-bit signed number operations, OF is set to 1 if either of the following two
conditions occurs:
• There is a carry from D14 to D15 but no carry out of D15 ( CF=0).
• There is a carry from D15 (CF=1) but no carry from D14 to D15.
Example:

● In the example above; +96 is added to +70 and the result according to the CPU is –90
(5AH).
● The reason is that, the result was more than what AL could handle. Like all other 8-bit
registers, AL could only contain up to +127. The designers of the CPU created the
overflow flag specifically for the purpose of informing the programmer that the result of
the signed number operation is erroneous.
The CPU indicates the existence of the problem by raising the OF (overflow) flag, but it is
up to the programmer to take care of it. The CPU understands only 0s and 1s and ignores the
human convention of positive and negative numbers.

Examples:
Microprocessors & Microcontrollers Module 3

3.2 CBW & CWD

To avoid the problems associated with signed number operations, one can extend
the sign bit of the operand.
⮚ CBW- This instruction converts Signed byte to signed word.
It copies the sign bit in AL to all the bits in AH.
It doesnot affect any flag.
Ex: Before applying CBW, AX = 0000 0000 1001 1010
After applying CBW, AX = 1111 1111 1001 1010
⮚ CWD- This instruction converts Signed word to signed double word.
It copies the sign bit in AX to all the bits in DX..
It doesnot affect any flag.
Ex: Before applying CWD,
DX = 0000 0000 0000 0000
AX = 1010 0000 1001 1010
After applying CWD,
DX = 1111 1111 1111 1111
AX = 1010 0000 1001 1010
Microprocessors & Microcontrollers Module 3

3.3 Arithmetic Shift

The arithmetic shift is used for signed numbers. It is basically the same as the logical shift,
except that the sign bit is copied to the shifted bits. SAR (shift arithmetic right) and SAL
(shift arithmetic left) are two instructions for the arithmetic shift.

• SHL or SAL Shift logical left /Shift Arithmetic Left

These instructions Shift the operand word or byte bit by bit to the left & zeros are
inserted in the space created at LSB’s . The number of shifts may be 1 or may be specified
by reg CL. The operand may be in a register or in memory location but cannot be an
immediate data. All the flags are affected. This operation includes carry flag also. The MSB
which is shifted will be stored in carry flag. Eg: SHL AX, 01

C Reg/ Memory Contents 0

Before SHL, AX = 0001 0010 0011 0001 =1 2 3 1 H

After SHL, AX = 0010 0100 0110 0010 =2 4 6 2H & carry = 0

Eg
: SAL AX, CL it shifts BX contents CL times in left direction if CL=2 then AX becomes 48C4H.

• Shift Arithmetic Right SAR

Reg /Memory contents C

It shifts right the contents of a register or a memory location which is of a byte /word & the MSB
is copied to emptied space..SAR is used with signed numbers, & the sign of the number is not
changed after the shift operation. The shift may be once or more than once (i.e, CL times).

After the shifting the moved out LSB goes to the carry flag, & in the space created at MSB, once
again the previous MSB is copied.

All the flags, except AC flag, are affected. The SAR instruction. is useful for dividing a signed
binary number by a power of 2. When an odd number is shifted, the result will be truncated.

Before After

Eg: SAR CX, 1 CX = FFFC FFFE

Microprocessors & Microcontrollers Module 3

3.4 Signed number division – IDIV

Signed operand must be sign-extended before division takes place using IDIV.

Ex: 8-bit division

MOV AL, -48
CBW
MOV BL,5
IDIV BL ; AL = -9 and AH = -3

Ex: 16-bit division

MOV Ax, -48
CWD
MOV BX,5
IDIV BX ; AX = -9 and DX = -3

3.5 Signed number multiplication -IMUL

IMUL multiplies an 8-bit signed operand by AL & 16-signed operand by AX. The product will
be in AX or DX:AX.
It preserves the sign of the product by sign-extending it into the upper half of the destination
register.(CBW)
Ex: MOV AL,48
MOV BL,4
IMUL BL ; AX = 00C0H and OF =1
OF =1 because AH is not a sign extension of AL.

An application of signed number arithmetic is given in the following Program. It computes the
average of the Celsius temperatures: +13, -10, + 19, +14, -18, -9, +12, -19, and + 16.
Microprocessors & Microcontrollers Module 3

3.6 String manipulation instructions

Following are the string manipulation instructions:
MOVS, LDOS, STOS, SCAS
⮚ MOVS/MOVSB/MOVSW
MOVS Destination String addresss, Source String address
This instruction copies a byte or a word from location in the data segment to a location in the
extra segment.
The offset of the source in the data segment must be in the SI register.
The offset of the destination in the extra segment must be in the DI register.
The number of elements to be moved is put in the CX register so that it can function as a counter.
After the byte or a word is moved, SI and DI are automatically adjusted to point to the next
source element and the next destination element.
If DF is 0, then SI and DI will incremented by 1 after a byte move and by 2 after a word move.
If DF is 1, then SI and DI will be decremented by 1 after a byte move and by 2 after a word
move. MOVS does not affect any flag.
Microprocessors & Microcontrollers Module 3

When using the MOVS instruction, we must indicatethe assembler whether we want to move a
string as byte or as word. This we can do by adding a “B” or a “W” to the MOVS mnemonic.
MOVSB says move a string as bytes; MOVSW says move a string as words.
Ex:
MOV SI, OFFSET SOURCE ;Load offset of start of source string in DS into SI
MOV DI, OFFSET DESTINATION ; Load offset of start of destination string in ES into DI
CLD ;Clear DF to auto increment SI and DI after move
MOV CX, 04H ;Load length of string into CX as counter
REP MOVSB ; Move string byte until CX = 0

⮚ LODS / LODSB / LODSW (LOAD STRING BYTE INTO AL OR STRING WORD

INTO AX)
This instruction copies a byte from a string location pointed to by SI to AL, or a word from a
string location pointed to by SI to AX.
If DF is 0, SI will be automatically incremented (by 1 for a byte string, and 2 for a word string)
to point to the next element of the string.
If DF is 1, SI will be automatically decremented (by 1 for a byte string, and 2 for a word string)
to point to the previous element of the string. LODS does not affect any flag.
Ex:
CLD ; Clear direction flag so that SI is auto-incremented
MOV SI, OFFSET SOURCE ; Point SI to start of string
LODSB SOURCE ; Copy a byte or a word from string to AL or AX

⮚ STOS / STOSB / STOSW (STORE STRING BYTE OR STRING WORD)

This instruction copies a byte from AL or a word from AX to a memory location in the extra
segment pointed to by DI. In effect, it replaces a string element with a byte from AL or a word
from AX.
After the copy, DI is automatically incremented or decremented to point to next or previous
element of the string.
If DF is cleared, then DI will automatically incremented by 1 for a byte string and by 2 for a
word string.
If DI is set, DI will be automatically decremented by 1 for a byte string and by 2 for a word
string. STOS does not affect any flag.
Ex:
MOV DI, OFFSET TARGET
STOSB TARGET
.
“B” added to STOSB mnemonic tells assembler to replace byte in string with byte from AL.
STOSW would tell assembler directly to replace a word in the string with a word from AX.

⮚ SCAS / SCASB / SCASW (SCAN A STRING BYTE OR A STRING WORD)

Microprocessors & Microcontrollers Module 3

SCAS compares a byte in AL or a word in AX with a byte or a word in ES pointed to by DI.

Therefore, the string to be scanned must be in the extra segment, and DI must contain the offset
of the byte or the word to be compared.
If DF is cleared, then DI will be incremented by 1 for byte strings and by 2 for word strings.
If DF is set, then DI will be decremented by 1 for byte strings and by 2 for word strings.
SCAS affects AF, CF, OF, PF, SF, and ZF, but it does not change either the operand in AL (AX)
or the operand in the string.
Ex:
The following program segment scans a text string of 80 characters for a carriage return, 0DH,
and puts the offset of string into DI:
MOV DI, OFFSET STRING
MOV AL, 0DH ;Byte to be scanned for into AL
MOV CX, 80 ;CX used as element counter
CLD ;Clear DF, so that DI auto increments
REPNE SCAS STRING ;Compare byte in string with byte in AL

⮚ CMPS / CMPSB / CMPSW (COMPARE STRING BYTES OR STRING WORDS)

This instruction can be used to compare a byte / word in one string with a byte / word in another
string.
SI is used to hold the offset of the byte or word in the source string, and DI is used to hold the
offset of the byte or word in the destination string.
The AF, CF, OF, PF, SF, and ZF flags are affected by the comparison, but the two operands are
not affected.
After the comparison, SI and DI will automatically be incremented or decremented to point to
the next or previous element in the two strings.
If DF is set, then SI and DI will automatically be decremented by 1 for a byte string and by 2 for
a word string.
If DF is reset, then SI and DI will automatically be incremented by 1 for byte strings and by 2 for
word strings.
The string pointed to by SI must be in the data segment. The string pointed to by DI must be in
the extra segment.
The CMPS instruction can be used with a REPE or REPNE prefix to compare all the elements of
a string.
Ex:
MOV SI, OFFSET FIRST ; Point SI to source string
MOV DI, OFFSET SECOND ; Point DI to destination string
CLD ; DF cleared, SI and DI will auto-increment after compare
MOV CX, 100 ; Put number of string elements in CX
REPE CMPSB ; Repeat the comparison of string bytes until end of string
; or until compared bytes are not equal .
CX functions as a counter, which the REPE prefix will cause CX to be decremented after each
compare.
Microprocessors & Microcontrollers Module 3

The B attached to CMPS tells the assembler that the strings are of type byte. If you want to tell
the assembler that strings are of type word, write the instruction as CMPSW. The REPE
CMPSW instruction will cause the pointers in SI and DI to be incremented by 2 after each
compare, if the direction flag is set.

⮚ REP / REPE / REPZ / REPNE / REPNZ (PREFIX)

(REPEAT STRING INSTRUCTION UNTIL SPECIFIED CONDITIONS EXIST)
REP is a prefix, which is written before one of the string instructions. It will cause the CX
register to be decremented and the string instruction to be repeated until CX = 0.
Ex: The instruction REP MOVSB, for example, will continue to copy string bytes until the
number of bytes loaded into CX has been copied.
REPE and REPZ are two mnemonics for the same prefix. They stand for repeat if equal and
repeat if zero, respectively. They are often used with the Compare String instruction or with the
Scan String instruction. They will cause the string instruction to be repeated as long as the
compared bytes or words are equal (ZF = 1) and CX is not yet counted down to zero. In other
words, there are two conditions that will stop the repetition: CX = 0 or string bytes or words not
equal.
Ex: REPE CMPSB Compare string bytes until end of string or until string bytes not equal.
REPNE and REPNZ are also two mnemonics for the same prefix. They stand for repeat if not
equal and repeat if not zero, respectively. They are often used with the Compare String
instruction or with the Scan String instruction. They will cause the string instruction to be
repeated as long as the compared bytes or words are not equal (ZF = 0) and CX is not yet
counted down to zero.
Ex: REPNE SCASW Scan a string of word until a word in the string matches the word in AX or
until all of the string has been scanned.
The string instruction used with the prefix determines which flags are affected

List of string Instructions

Instruction Mnemonic Destination Source Prefix

Move string byte MOVSB ES: DI DS: SI REP

Move string word MOVSW ES: DI DS: SI REP

Store string byte STOSB ES: DI AL REP

Store string word STOSW ES: DI AX REP

Load string byte LODSB AL DS: SI None

Load string word LODSW AX DS: SI None

Compare string byte CMPSB ES: DI DS: SI REPE/REPNE

Microprocessors & Microcontrollers Module 3

Compare string word CMPSW ES: DI DS: SI REPE/REPNE

Scan string byte SCASB ES: DI AL REPE/REPNE

Scan string word SCASW ES: DI AX REPE/REPNE

Program Examples:
Microprocessors & Microcontrollers Module 3
Microprocessors & Microcontrollers Module 3

3.7 Look up table instruction- XLAT

It is used to find out the codes in case of code conversion problems using look up table
technique. It is a zero operand instruction. The table offset address must be in BX & AL must
contain the displacement value. The data obtained from the address [BX+AL] & stored in AL.
Ex: A table of Hexa decimal numbers from 0 to F may be created as a table. Its segment address
must be in DS register. The decimal i/p numbers between 00 to 16 can be given thru’ keyboard,
& move that data to AL. Then, if we use XLAT instruction, we obtain its equivalent hexa
number in the register AL.
Following Program segment illustrates the usage of XLAT:

MOV AL, DATA ;The i/p data for conversion.

MOV BX, OFFSET Table ; The beginning address of look-up table must be in BX.
XLAT ; Equivalent hexa code in AL

3.8 I/O interface

There are the two different methods to interface I/O devices to the microprocessor.
1. I/O mapped I/O or Isolated I/O
2. Memory mapped I/O
Following is the distinguishing features of both methods:
I/O mapped I/O Memory mapped I/O
• Most commonly used I/O transfer not so common.
technique.
• Separate i/o address space is used. Part of the memory space
is used for i/o addressing also.
• Separate instructions are used to Same instructions of memory
Transfer data from the i/o devices. can be used w.r.t. i/o devices also.
Eg: IN, OUT instructions of 8086 µp
Microprocessors & Microcontrollers Module 3

• Separate control signals are needed No such signals are required.

for i/o read& i/o write. So, reduces the Decoding circuitry.
The complete memory space can be utilized. Since portion of the memory is
used for I/O mapping, total
memory available to applications is
reduced.
• Hardware required is less compare to
memory mapped i/o.

3.9 Programmable Peripheral Interface- 8255

The Intel 8255 is designed for using with Intel microprocessor. It has 24 I/O lines which may be
individually programmed in two groups. The two groups of i/o pins are named as group A &
group B. Each of these groups contains a subgroup of 8 i/o lines called as 8- bit port & another
subgroup of 4 i/o lines called as 4- bit port.
i.e., Group A --contains 8- bit port A + 4-bit port C upper &
Group B --contains 8- bit port B + 4- bit port C lower.
The port A lines are identified by PA0-PA7 & Port C –upper lines are PC4-PC7 & port C lower
lines are PC0-PC3.The port C lower & port C upper can be used together to form another port
called port C.

All of these ports can function independently either as input or as output ports. This can be done
by programming the bits of an internal register of 8255 called CWR (control word register).
The internal block diagram & the pin configuration of 8255 are shown below.

Pin-out of 8255
Microprocessors & Microcontrollers Module 3

The 8-bit data bus buffer is controlled by the read/write control logic. RD, WR, A1, A0, &
RESET are the signals given by the µp to the 8255.
The 8-bit, tri state bidirectional buffer is used to interface the 8255 internal data bus with the
external system data bus. This buffer receives or transmits data upon the execution of
instructions sent by µp. the control word or status information is also transferred through the
buffer.
CS is a chip select line.
A1-A0
there are the address I/p lines & are driven by the µp. these lines along with RD, WR, & CS from the fol

RD WR CS A A0 READ CYCLE
0 1 0 0 0 port A to data bus
0 1 0 0 1 port B to data bus p

0 1 0 1 0 port C to data bus

0 1 0 1 1 CWR to data bus
WRITE cycle
1 0 0 0 0 data bus to port A
1 0 0 0 1 data bus to port B
1 0 0 1 0 data bus to port C
1 0 0 1 1 data bus to CWR.

RESET
A logic high on this line clears the CWR of 8255. All ports are set as i/p ports by default after reset.
PA7-PA0
these are portA lines that act as either latched output or buffered input lines depending upon the contro
PC7-PC4
upper nibble of port C lines. They may act as either o/p latches or I/p buffers lines. This port can also
Microprocessors & Microcontrollers Module 3

PC3-PC0 lower port C lines. Function is same as PC4-PC7.

PB7-PB0
these are port B lines which are used as latched o/p lines or buffered I/p lines like PA7-PA0.
D7-D0 these are the data or control word to / from the µp.

3.9.1 8255 modes of operation

There are two basic modes of operation of 8255:
I/O mode & Bit Set-reset mode (BSR)

In I/O mode we can program all the ports of 8255 in required mode of operation. But in BSR
mode only port C can be used to set/reset its individual bits.
Under I/O mode further there are 3 modes: mode 0, mode 1 & mode2.

Mode 0
simple input or output .Each of the 3 ports can be used in this mode. Data can be simply read from & w

Features of this mode are:

● Two 8-bit ports (A&B) & two 4-bit ports(C upper & C lower) are available. The two 4-
bit ports can be combined used as a third 8-bit port.
● Any port can be used as an input or output port.

● O/P ports are latched & i/p ports are not latched.

● A maximum of 4 ports are available so that overall 16 I/O configurations are possible.

Mode 1 strobe or handshake input / output.

In many applications, valid data is present on an external device only for certain time, & it must
be read at that time. To indicate that there is valid data available, the device sends a strobe signal
on another line to the receiving end. This process is known as strobed input output.
Only port A & port B of 8255 are allowed to function in this mode.
Few of the pins of port C are used for handshake signals.
The strobed data transfer is suitable for low rates of data transfer.
Ex: data from a keyboard to µp.
For a high speed data transfer, the handshake I/O is used. Here, after detecting the strobe signal
(STB), the µp sends an acknowledgement signal to the external device, to indicate that it is ready
to receive next byte of data.
If port A is input port in mode1 then PC3, PC4 & PC5 function as handshake signals.
If port B is i/p port in Mode1 then PC0, PC1,& PC2 function as handshake signals.
If port A is output port in mode1 then PC3, PC6 & PC7 function as handshake signals
& if port B is o/p port in mode1 then PC0, PC1 & PC2 function as handshake signals.

Mode 2
Bidirectional handshake input/output. Only port A can be initialized in mode2. It functions in both the
If port A is used in Mode2, then pins PC3-PC7 are used as handshake lines for PortA . Otherwise
if port B is in mode1 then PC0-PC2 pins are used for handshaking for port B.
Ex: data transfer between µp & floppy disk.

3.9.2 Control word format of 8255

Microprocessors & Microcontrollers Module 3

There are two control word formats in 8255.

● Mode set control word

● Bit set/ reset control word.

The MSB of the control word tells the 8255 which control word has been sent.
MSB 1 indicates mode set & 0 indicates bit set /reset.
Mode set control word is used to set the mode of operation for all the ports.
Bit Set or reset control word is used to set or reset the output on a pin of port C. It is also used to
enable the interrupt output signals for handshake data transfers.
Both control words are sent to the control word register of 8255. The control word formats for
both are as given below:

Mode set control word

3.10 Basic I/O Instructions

IN and OUT Instructions transfer data between an I/O device and the microprocessor's
accumulator (AL)
The I/O address is stored in Register DX as a 16-bit I/O address (variable addressing).
The byte data is stored in AL.
IN AL, DX ; Input Port address in DX & data obtained is stored in AL
OUT DX,AL ; Output port address in DX & Data to be sent is in AL

Example 1: Set portA as input and portB as output , read a byte from portA and
manipulate it and send to prot B. Assume portA =0DC50H

MOV DX,0DC53H
MOV AL 82H
OUT DX,AL ; Initialize Conrol Word PA=input and PB=output
MOV DX,0DC50H
IN AL,DX ; read from input port
ADD AL, 02 ; manipulate data
Microprocessors & Microcontrollers Module 3

MOV DX, 0DC51H

OUT DX,AL ;Send data to output port

Example 2:
Microprocessors & Microcontrollers Module 3

3.11 Memory & Memory Interfacing

• Memory Organization
● The number of bits that a semiconductor memory chip can store is called its capacity. It can
be in the units of K bits (kilobits)/M bits (megabits).
● Memory chips are organized into a number of locations within the IC. Each location can hold
1 bit, 4-bits, 8-bits, or even 16-bits.
● Each memory chip contains 2x locations, where x is the number of address pins on the chip.

● Each location contains y bits, where y is the number of data pins on the chip.

● The entire chip will contain 2x * y bits – the capacity of the chip.

The pin connections common to all memory devices are –

Address Connections: All memory devices have address inputs that select a memory location
within the memory device. Address inputs are always labeled from A0 to An (Note, ‘n’ is one
Microprocessors & Microcontrollers Module 3

less than the total number of address pins). The number of address pins found on a memory
device is determined by the number of memory locations found within it.
Data Connections. All memory devices have a set of data outputs or input/outputs. The device
illustrated in the following Figure has a common set of I/O (input/output) connections.

As shown in the figure above,the memory chips have CS (chip select) pin that must be activated
for memory contents to be accessed. That means, no data can be written into or read form the
memory chip unless CS is activated.
Sometimes, OE (output enable)/RD (read)/WR (write) pins may also be present along with CS
pin.
Numbe of Memory
Address lines
6 64 bytes 2^6 =64
7 128
8 256
9 512
10 1024 (1Kbytes) 2^10=1024
11 2048 (2Kb)
12 4096 (4Kb)
13 8192(8Kb) 2^13 =8192
16 64Kb
201 1Mb 2^20 = 1Mb

Example 1:
A given memory chip has 12 address pins and 8 data pins. Find the memory organization and the
capacity.
Solution:
Memory chip has 12 address lines 212 = 4,096 locations.
Memory chip has 8 data lines Each location hold 8 bits of data.
Thus, the memory organization is 4,096 x 8 = 4K x 8 = 32K bits capacity.

Example 2: A 512K memory chip has 8 data pins. Find the organization.
Solution:
The memory chip has 8 data lines Each location within the chip can hold 8 bits of data.
Given, the capacity of the memory chip = 512K.
Microprocessors & Microcontrollers Module 3

Hence, the locations within the memory chip = 512K / 8 = 64K.

Since, 216 = 64K; the memory chip has 16 address lines.
Hence, the memory organization is: 64K x 8 = 512K bits capacity.

• Memory Address Decoding

Consider a 32K x 8 capacity memory chip. This chip has 15 (215 = 32K) address lines and 8 data
lines.
● Suppose, this memory chip is to be interfaced to x86 microprocessor, which is having 20
address lines and 16 data lines.
● This means that, the microprocessor sends out a 20-bit memory address whenever it reads
or writes data. Hence there is a mismatch that must be corrected.
● The decoder corrects the mismatch by decoding the address pins that do not connect to
the memory component.

• Simple Logic Gates as Address Decoder

The CS (chip select) input pin (in any memory chip) is usually active low and can be activated
using some simple logic gates; such as NAND gate and Inverters. The following Fig. shows
some simple NAND gate decoding for memory chips, along with the address range calculations.
Microprocessors & Microcontrollers Module 3

• Using the 74LS138 as Decoder

● The 74LS138 has 8 NAND gates in it; therefore, a single chip can control 8 blocks of
memory.
● In 74LS138 decoder; the three inputs A, B, C generates eight active low outputs Y0 to
Y7.
● Each Y output can be connected to the CS of memory chip, allowing control of 8
memory blocks by a single 74LS138.
Microprocessors & Microcontrollers Module 3

✔ Consider the following memory decoding diagram. We have, A0-A15 from the CPU, directly
connected to A0-A15 of the memory chip.
✔ A16-A18 are used for the A, B, and C inputs of 74LS138; A19 is controlling G1 pin. G2A and G2B are
grounded.

To enable 74LS138; G2A = 0, G2B = 0; and G1 = 1.

✔ To select Y4; CBA = 100.

✔ This gives the address range (for the memory chip controlled by Y4): C0000H to CFFFFH.
Microprocessors & Microcontrollers Module 3

Q.Explain 74138 decoder configuration to enable the memory address F0000H to F7FFFH
to connect four 8K RAMs.
Soln:
Given Address range is F0000H – F7FFFH with four 8K RAMs.
This Memory range distributed to Each RAM as following:
1st block of Memory RAM1 :
F0000H TO F1FFFH = 1111 0000 0000 0000 0000 To 1111 0001 1111 1111 1111
2nd block of Memory RAM2 :
F2000H TO F3FFFH = 1111 0010 0000 0000 0000 To 1111 0011 1111 1111 1111
3nd block of Memory RAM3 :
F4000H TO F5FFFH = 1111 0100 0000 0000 0000 To 1111 0101 1111 1111 1111
4th block of Memory RAM4 :
F6000H TO F7FFFH = 1111 0110 0000 0000 0000 To 1111 0111 1111 1111 1111
Microprocessors & Microcontrollers Module 3

Out of all the 20 bits in the address , 13 bits are enough to address 8K bytes memory. So, bit 0 to
bit 12 are used for addressing and bits 13,14 and 15 can be used for chip select for 4 RAMs.
000 for RAM1
001 for RAM2
010 for RAM3
011 for RAM4.
Remaining bits 16-19 can be used for enabling 74LS138 decoder. The design is as shown below:

74LS138
Decoder

G2A

G2B
G1
A13 000 RAM1
A14
A15
001 RAM2

ground 010 RAM3

011 RAM4

A16

3.12 Data Integrity In RAM & ROM

When storing data, one major concern is maintaining data integrity – ensuring that, the data
retrieved is the same as the data stored. The same principle applies when transferring data from
one place to another – ensuring that, the data received is the same as the data transmitted.
There are many way to ensure data integrity depending on the type of storage.
● The checksum method is used for ROM

● The parity check method is used for DRAM.

● For mass storage devices such as hard disks and for transferring data on the Internet, the
CRC (Cyclic Redundancy Check) method is employed.

3.12.1 Checksum Byte (for ROM)

During the current surge, or when the PC is turned on, or during operation, the contents of the
ROM may be corrupted.To ensure the integrity of the contents of ROM, every PC must perform
a checksum calculation. The process of checksum will detect any corruption of the contents of
ROM.
The checksum method uses a checksum byte. This checksum byte is an extra byte that is tagged
to the end of a series of bytes of data. To calculate the checksum byte of a series of bytes of data,
the following steps can be taken:
1. Add the bytes together and drop the carries.
Microprocessors & Microcontrollers Module 3

2. Take the 2's complement of the total sum, and that is the checksum byte, which becomes the
last byte of the stored information.
3. To perform the checksum operation, add all the bytes, including the checksum byte. The result must be
zero. If it is not zero, one or more bytes of data have been changed (corrupted).

Checksum Program
When the PC is turned on, one of the first things the BIOS does is to test the system ROM. The
code for such a test is stored in the BIOS ROM. The following code segment shows the program
using the checksum method. In the code all the bytes are added together without keeping the
track of carries. Then, the total sum is ORed with itself to see if it is zero. The zero flag is
expected to be set to high upon return from this subroutine. If it is not, the ROM is corrupted.
Microprocessors & Microcontrollers Module 3

PC BIOS checksum routine

3.12.2 Use of Parity Bit in DRAM Error Detection

DRAM Memory Banks
The arrangement of DRAM chips on the system or memory module board is often referred to as a
memory bank. For ex: the 64K bytes of DRAM can be arranged as one bank of 8 IC chips of 64K x 1
organization, or 4 bank of 16K x 1 organization.
The following Figure shows the memory banks for 640K bytes of RAM using 256K and 1M DRAM
chips. Notice the use of an extra bit for every byte of data to store the parity bit. With the extra parity bit
every bank requires an extra chip of x 1 organization for parity check

Parity Bit Generator/Checker in IBM PC

There are two types of errors that can occur in DRAM chips:
• Hard error – some bits or an entire row of memory cell inside the memory chip get stuck to
high or low permanently, thereafter always producing l or 0 regardless of what you write into
the cell(s).
• Soft error – a single bit is changed from 1 to 0 or from 0 to 1 due to current surge or certain
kinds of particle radiation in the air. Parity is used to detect soft errors.
Including a parity bit to ensure data integrity in RAM is the most widely used method; since, it is
the simplest and cheapest.This method can only indicate if there is a difference between the data
that was written to memory and the data that was read. It cannot correct the error as is the case
with some high-performance computers

74S280 Parity Bit Generator & Checker

Microprocessors & Microcontrollers Module 3

The 74S280 chip has 9 inputs and 2 outputs. Depending on whether an even or odd number of
ones appear in the input, the even or odd output is activated (according to following Table).
As shown in Table, if all 9 inputs have an even number of 1 bits, the even output goes high (as in
cases 1 and 4). If the 9 inputs have an odd number of high bits, the odd output goes high (as in
cases 2 and 3).

Case Inputs Outputs

A–H I Even ODD
1 Even 0 1 0
2 Even 1 0 1
3 Odd 0 0 1
4 Odd 1 1 0

The way the IBM PC uses this chip is as follows:

● In the above Figure (DRAM design and parity bit circuitry for a bank of DRAM), inputs A –
H are connected to the data bus, which is 8 bits, or one byte. The I input is used as a parity bit
to check the correctness of the byte of data read from memory. When a byte of information is
written to a given memory location in DRAM, the even-parity bit is generated and saved on
the ninth DRAM chip as a parity bit with use of control signal MEMW .This is done by
activating the tri-state buffer using MEMW. At this point, I of the 74S280 is equal to zero,
since MEMR high.
● When a byte of data is read from the same location, the parity bit is gated into the I input of
the 74S280 through MEMR. This time the odd output is taken out and fed into a 74LS74. If
there is a difference between the data written and the data read, the Q output (called PCK,
parity bit check) of the 74LS74 is activated and Q activates NMI, indicating that there is a
parity bit error, meaning that the data read is not the same as the data written. Consequently,
it will display a parity bit error message.
● For example, if the byte of data written to a location has an even number of ls, A to H has an
even number of ls, and I is zero, then the even-parity output of 74S280 becomes 1 and is
saved on parity bit DRAM. This is case 1 shown in the above Table. If the same byte of data
is read and there is an even number of ls (the byte is unchanged), I from the ninth bit DRAM,
which is 1, is input to the 74S280, even becomes low, and odd becomes high, which is case 2
in the above Table. This high from the odd output will be inverted and fed to the 74LS74,
making Q low. This means that 𝑄 is high thereby indicating that the written byte is the same
as the byte read and there is no errors occurred.
Microprocessors & Microcontrollers Module 3

● If the number of 1s in the byte has changed from even to odd and the 1 from the saved parity
DRAM makes the number of inputs even (case 4 above), the odd output becomes low, which
is inverted and passed to the 74LS74 D flip-flop. This makes Q = 1 and 𝑄= 0, which signals
the NMI to display a parity bit error message on the screen.

3.13 Memory Cycle Time and Inserting Wait States

• To access an external device such as memory or I/O, the CPU provides a fixed amount of
time called a bus cycle time. During this bus cycle time, the read and write operation of
memory or I/O must be completed.
• The bus cycle time used for accessing memory is often referred to as memory cycle
time(MC). The time from when the CPU provides the addresses at its address pins to when
the data is expected at its data pins is called memory read cycle time.
• The processors such as the 8088/86, the memory cycle time takes 4 clocks, and from 286 to
Pentium, the memory cycle time is only 2 clocks.
• If memory is slow and its access time does not match the MC time of the CPU, extra time
can be requested from the CPU to extend the read cycle time. This extra time is called a
wait state (WS).
The read cycle of 8086/88 MP

It must be noted that, memory access time is not the only factor in slowing down the CPU. The
other factor is the delay associated with signals going through the data and address path.
Delay associated with reading data stored in memory has the following two components:
1. The time taken for address signals to go from CPU pins to memory pins, (going through
decoders and buffers (e.g., 74LS245)); plus the time taken for the data to travel from memory to
CPU, is referred to as a path delay.
2. The memory access time to get the data out of the memory chip. This is the larger (80% of the
read cycle time) of the two components.
The total sum of these two (path delay + memory access time) must equal the memory read cycle
time provided by the CPU.
Microprocessors & Microcontrollers Module 3

74LS138
Decoder

G2A

G2B
G1
A13 000 RAM1
A14
A15
001 RAM2

ground 010 RAM3

011 RAM4

A16

…………………………………. End of Module 3……………………………………..