UNIT -04

CONTROL UNIT
Control of the processor.
Hardwired control unit
 Control unit input
 Control unit logic
Micro programmed control unit
 Micro instruction and its type.
 Architecture of micro programmed control unit.
Micro instruction sequencing
Micro instruction Execution
Application of Hardwired and Micro programmed control unit
RISC and CISC

Control of the processor.

Control Unit :
The unit which directs the operation of the processor & is a part of the CPU is known as Control Unit. It
generates control signals for the operations of a computer.

Examples of devices that require a CU are:

 Control Processing Units(CPUs)
 Graphics Processing Units(GPUs)

Functions of the Control Unit –

1. It coordinates the sequence of data movements into, out of, and between a
processor’s many sub-units.
2. It interprets instructions.
3. It controls data flow inside the processor.

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 4. It receives external instructions or commands to which it converts to sequence of
control signals.
5. It controls many execution units(i.e. ALU, data buffers and registers) contained within a
CPU.
6. It also handles multiple tasks, such as fetching, decoding, execution handling and
storing results.

Types of Control Unit :

There are two types of control units as follows.

1. Hardwired control unit
2. Micro-programmed control unit

HARDWIRED IMPLEMENTATION

In a hardwired implementation, the control unit is essentially a state machine circuit. Its input logic
signals are transformed into a set of output logic signals, which are the control signals.

Control Unit Inputs

The key inputs are the instruction register, the clock, flags, and control bus signals. In the case of the
flags and control bus signals, each individual bit typically has some meaning (e.g., overflow). The other
two inputs, however, are not directly useful to the control unit.

First consider the instruction register. The control unit makes use of the opcode and will perform different
actions (issue a different combination of control signals) for different instructions. To simplify the control
unit logic, there should be a unique logic input for each opcode. This function can be performed by a
decoder, which takes an encoded input and produces a single output. In general, a decoder will have n
binary inputs and 2 n binary outputs. Each of the 2 n different input patterns will activate a single unique
output. Table shown below is an example for n = 4. The decoder for a control unit will typically have to
be more complex than that, to account for variable-length opcodes.

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The clock portion of the control unit issues a repetitive sequence of pulses. This is useful for measuring
the duration of micro-operations. Essentially, the period of the clock pulses must be long enough to allow
the propagation of signals along data paths and through processor circuitry. However, as we have seen,
the control unit emits different control signals at different time units within a single instruction cycle.
Thus, we would like a counter as input to the control unit, with a different control signal being used for
T1 , T2 , and so forth. At the end of an instruction cycle, the control unit must feed back to the counter to
reinitialize it at T1.

With these two refinements, the control unit can be depicted as in figure below.

Control Unit Logic

The table below shows micro-operations and control signals needed to control three of the four phases of
the instruction cycle.

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Let us consider a single control signal, C5. This signal causes data to be read from the external data bus
into the MBR. We can see that it is used twice in Table. Let us define two new control signals, P and Q,
that have the following interpretation:

PQ = 00 Fetch Cycle
PQ = 01 Indirect Cycle
PQ = 10 Execute Cycle
PQ = 11 Interrupt Cycle

Then the following Boolean expression defines C 5 :

That is, the control signal C 5 will be asserted during the second time unit of both the fetch and indirect
cycles.

This expression is not complete. C 5 is also needed during the execute cycle. For our simple example, let
us assume that there are only three instructions that read from memory: LDA, ADD, and AND. Now we
can define C 5 as,

This same process could be repeated for every control signal generated by the processor. The result would
be a set of Boolean equations that define the behavior of the control unit and hence of the processor.

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To tie everything together, the control unit must control the state of the instruction cycle. As was
mentioned, at the end of each subcycle (fetch, indirect, execute, interrupt), the control unit issues a signal
that causes the timing generator to reinitialize and issue T1. The control unit must also set the appropriate
values of P and Q to define the next subcycle to be performed

Micro-programmed Control.

In Microprogrammed Control, the micro-operations are performed by executing a program

consisting of micro-instructions.

The following image shows the block diagram of a Microprogrammed Control

organization.

 The Control memory address register specifies the address of the micro-instruction.
 The Control memory is assumed to be a ROM, within which all control information
is permanently stored.
 The control register holds the microinstruction fetched from the memory.
 The micro-instruction contains a control word that specifies one or more micro-
operations for the data processor.
 While the micro-operations are being executed, the next address is computed in
the next address generator circuit and then transferred into the control address
register to read the next microinstruction.
 The next address generator is often referred to as a micro-program sequencer, as it
determines the address sequence that is read from control memory.

Advantages of Hardwired Control Unit :

Here, we will discuss the advantages of the Hardwired Control Unit as follows.
1. Because of the use of combinational circuits to generate signals, Hardwired Control
Unit is fast.
2. It depends on number of gates, how much delay can occur in generation of control
signals.
3. It can be optimized to produce the fast mode of operation.
4. Faster than micro- programmed control unit.

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Disadvantages of Hardwired Control Unit:

Here, we will discuss the disadvantages of the Hardwired Control Unit as follows.
1. The complexity of the design increases as we require more control signals to be
generated (need of more encoders & decoders)
2. Modifications in the control signals are very difficult because it requires rearranging of
wires in the hardware circuit.
3. Adding a new feature is difficult & complex.
4. Difficult to test & correct mistakes in the original design.
5. It is Expensive.

Difference between Hardwired and Microprogrammed Control Unit:

MICROPROGRAMMED CONTROL
ATTRIBUTES HARDWIRED CONTROL UNIT UNIT

1. Speed Speed is fast Speed is slow

2. Cost of
Implementation More costlier. Cheaper.

Not flexible to accommodate new More flexible to accommodate new

system specification or new system specification or new instruction
3. Flexibility instruction redesign is required. sets.

4. Ability to Handle Difficult to handle complex Easier to handle complex instruction

Complex Instructions instruction sets. sets.

Complex decoding and sequencing

5. Decoding logic. Easier decoding and sequencing logic.

6. Applications RISC Microprocessor CISC Microprocessor

7. Instruction set of
Size Small Large

8. Control Memory Absent Present

9. Chip Area Required Less More

10. Occurrence Occurrence of error is more Occurrence of error is less

Advantages :
1. The main advantage is flexibility.
2. Any change in the control unit can be performed by simply changing the micro-
instruction.
3. Can be easily debugged as compared to hardwired control unit.

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 4. Most micro-instructions are executed sequentially, they don’t require any address field.
5. Reduction of size of control memory.
Disadvantages :
1. Control memory has to be present inside the processor, therefore increases processor
size.
2. This also increases the cost of the processor.

Applications of Microprogrammed Control Unit :

Microprogramming has many advantages like flexibility, simplicity, cost-effectiveness etc.

Therefore, it has a major contribution in the following applications –
1. Development of control units –
Modern processors have very large and complex instruction sets. Microprogramming is
used for making control units of such processors, because it is far less complex and
can be easily modified.
2. High level language support –
Modern high level languages have more advanced and complex data types.
Microprogramming can provide support for such data types directly from the processor
level. Therefore, the language becomes easy to compile and also faster to execute.
3. User tailoring of the control unit –
As the control Unit is developed using software, it can be easily reprogrammed. This
can be used for custom-made modifications of the Control Unit. For this purpose, the
control memory must be writable like RAM or flash ROMs.
4. Emulation –
Emulation is when one processor (say A) is made to emulate or behave like another
processor (say B). To do this, A must be able to execute the instructions of B. If we re-
program the control memory of A, same as that of B, then A will be able to emulate the
behavior of B, for every instruction. This is possible only in microprogrammed control
units.
Used generally when a main processor has to emulate the behavior of a math co-
processor.
5. Improving the operating system –
Microprogramming can be used to implement complex and secure functions of the OS.
This not only makes the OS more powerful and efficient, but more importantly secure,
as it provides the OS a higher degree of protection from malicious virus attacks.
6. Micro-Diagnostics or error debugging –
As Microprogrammed Control Units are software based, debugging an error is far more
easy as compared to doing the same for a complex hardwired control unit. This allows
monitoring, detection and repairs of any kind of system errors in the control unit. It can
also use as a runtime substitute, if the corresponding hardwired component fails.
7. Development of special purpose processors –
All processors are not general purpose. Many applications require special purpose
processors like DSP(Digital Signal Processors) for communication, GPU (Graphic
Processor Unit) for image processing.
They have complex instruction sets and also need to be constantly upgraded.
Microprogrammed control unit is the best choice for them

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MICROINSTRUCTION SEQUENCING:

Sequencing Techniques: Based on the current microinstruction, condition flags, and the
contents of the instruction register, a control memory address must be generated for the next
microinstruction. A wide variety of techniques have been used. We can group them into three
general categories, as illustrated in Figures 16.6 to 16.8. These categories are based on the
format of the address information in the microinstruction:

 Two address fields

 Single address field
 Variable format

1. Dual / Two address field –

Dual address field

 In this approach, micro-instructions are not executed in a sequential manner.

 The instruction register (IR) gives the address of the first micro-instruction.
 Thereafter, each micro-instruction gives the address of the next micro-instruction.
 If it is a conditional micro-instruction, it will contain two address fields.

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  One for the condition to be true and the other for false. Hence, it is called dual address
field.
 The multiplexer will decide the address that will be loaded into the control memory
address register (CMAR) based on the status flags.

Here, lots of control memory is wasted because at least one of the address fields is not required
in many(i.e. for sequential or unconditional) micro-instructions.

2. Single address field –

With some modifications and the added logic, the number of addresses is reduced to one. Here, a
new register called microprogram counter is used. In this case, the next microinstruction address
can be the address of the next sequential address or it can be the address generated using op-code
or it can be the address stored in the address field of the microinstruction.

Single address field.

 In this approach, micro-instructions are executed in a sequential manner.

 The instruction register (IR) gives the address of the first micro-instruction into CMAR.
 Thereafter, the address is simply incremented.
 Hence, every micro-instruction need not carry the address of the next one.
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  This is true so long as the micro-program is executed in a sequential manner.
 For an unconditional branch, the micro-instructions include the branch address. This
address will be loaded into CMAR.
 For a conditional branch, the micro-instruction contains the branch address for true
condition. If the condition is false, the current address in CMAR will be simply
incremented.
 This means even in the worst case, the micro-instruction will carry only one address.
 Hence, it is called single address field.
 The multiplexer will decide the address that will be loaded into the control memory
address register (CMAR) based on the status flags.

This method is commonly used. But the space provided in each micro-instruction in a single
address field is not quite useful if the instructions are executed sequentially.

3. Variable address format –

 In this technique two formats are used. In such a technique, one bit is needed in the
microinstruction to differentiate between control microinstruction or a branching
microinstruction. The first format provides the control microinstruction(i.e. the bits are
used to generate control signals) , while the second format provides the branch logic and
address(there can be conditional or unconditional branch).
 In the first format, the microinstruction contains control signals, then the next
microinstruction address is calculated either by using the op-code of the instruction
register or it is the address of the next microinstruction in sequence. In this approach, an
extra cycle is needed for branch microinstruction.

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 Variable instruction format

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Micro-Instruction Execution

The microinstruction cycle is the basic event on a microprogrammed processor. Each cycle is
made up the two parts: fetch and execute. This section deals with the execution of
microinstruction. The effect of the execution of a microinstruction is to generate control signals
for both the internal control to processor and the external control to processor.

A organization of a control unit is shown in Figure 7.4

Figure 7.4. Microprogrammed Control Unit Organization

RISC Vs CISC

Types Of Processor
RISC
CISC
RISC Processor

RISC stands for Reduced Instruction Set Computer Processor, a microprocessor architecture with a
simple collection and highly customized set of instructions. It is built to minimize the instruction
execution time by optimizing and limiting the number of instructions. It means each instruction cycle
requires only one clock cycle, and each cycle contains three parameters: fetch, decode and execute.

Examples of RISC processors are SUN's SPARC, PowerPC, Microchip PIC processors, RISC-V.

Advantages of RISC Processor

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 1. The RISC processor's performance is better due to the simple and limited number of the
instruction set.
2. It requires several transistors that make it cheaper to design.
3. RISC allows the instruction to use free space on a microprocessor because of its simplicity.
4. RISC processor is simpler than a CISC processor because of its simple and quick design, and it
can complete its work in one clock cycle.

Disadvantages of RISC Processor

1. The RISC processor's performance may vary according to the code executed because subsequent
instructions may depend on the previous instruction for their execution in a cycle.
2. Programmers and compilers often use complex instructions.
3. RISC processors require very fast memory to save various instructions that require a large
collection of cache memory to respond to the instruction in a short time.

RISC Architecture
It is a highly customized set of instructions used in portable devices due to system reliability such as
Apple iPod, mobiles/smartphones, Nintendo DS,

Features of RISC Processor

Some important features of RISC processors are: History of Java

1. One cycle execution time: For executing each instruction in a computer, the RISC processors
require one CPI (Clock per cycle). And each CPI includes the fetch, decode and execute method
applied in computer instruction.
2. Pipelining technique: The pipelining technique is used in the RISC processors to execute
multiple parts or stages of instructions to perform more efficiently.
3. A large number of registers: RISC processors are optimized with multiple registers that can be
used to store instruction and quickly respond to the computer and minimize interaction with
computer memory.
4. It supports a simple addressing mode and fixed length of instruction for executing the pipeline.

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 5. It uses LOAD and STORE instruction to access the memory location.
6. Simple and limited instruction reduces the execution time of a process in a RISC.

CISC Processor

The CISC Stands for Complex Instruction Set Computer, developed by the Intel. It has a large
collection of complex instructions that range from simple to very complex and specialized in the
assembly language level, which takes a long time to execute the instructions. So, CISC approaches
reducing the number of instruction on each program and ignoring the number of cycles per instruction. It
emphasizes to build complex instructions directly in the hardware because the hardware is always faster
than software

Examples of CISC processors are VAX, AMD, Intel x86 and the System/360.

Characteristics of CISC Processor

Following are the main characteristics of the RISC processor:

1. The length of the code is shorts, so it requires very little RAM.

2. CISC or complex instructions may take longer than a single clock cycle to execute the code.
3. Less instruction is needed to write an application.
4. It provides easier programming in assembly language.
5. Support for complex data structure and easy compilation of high-level languages.
6. It is composed of fewer registers and more addressing nodes, typically 5 to 20.
7. Instructions can be larger than a single word.
8. It emphasizes the building of instruction on hardware because it is faster to create than the
software.

CISC Processors Architecture

The CISC architecture helps reduce program code by embedding multiple operations on each program
instruction, which makes the CISC processor more complex. The CISC architecture-based computer is
designed to decrease memory costs because large programs or instruction required large memory space to
store the data, thus increasing the memory requirement, and a large collection of memory increases the
memory cost, which makes them more expensive.

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Advantages of CISC Processors
1. The compiler requires little effort to translate high-level programs or statement languages into
assembly or machine language in CISC processors.
2. The code length is quite short, which minimizes the memory requirement.
3. To store the instruction on each CISC, it requires very less RAM.
4. Execution of a single instruction requires several low-level tasks.
5. CISC creates a process to manage power usage that adjusts clock speed and voltage.
6. It uses fewer instructions set to perform the same instruction as the RISC.

Disadvantages of CISC Processors

1. CISC chips are slower than RSIC chips to execute per instruction cycle on each program.
2. The performance of the machine decreases due to the slowness of the clock speed.
3. Executing the pipeline in the CISC processor makes it complicated to use.
4. The CISC chips require more transistors as compared to RISC design.
5. In CISC it uses only 20% of existing instructions in a programming event.

Difference between the RISC and CISC Processors

RISC CISC
It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.

Simple instruction Complex instruction

Less no of instruction Large no of instruction

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Nearly 1 cycle / instruction 2 or more cycle / instruction

It emphasizes on software to optimize the instruction It emphasizes on hardware to optimize the

set. instruction set.
It is a hard wired unit of programming in the RISC Microprogramming unit in CISC Processor.
Processor.

Fewer addressing mode More addressing mode

It requires multiple register sets to store the instruction. It requires a single register set to store the
instruction.
RISC has simple decoding of instruction. CISC has complex decoding of instruction.

Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.

RISC has more transistors on memory registers. CISC has transistors to store complex
instructions.
The execution time of RISC is very short. The execution time of CISC is longer.

RISC architecture can be used with high-end CISC architecture can be used with low-end
applications like telecommunication, image processing, applications like home automation, security
video processing, etc. system, etc.

It has fixed format instruction. It has variable format instruction.

The program written for RISC architecture needs to take Program written for CISC architecture tends to
more space in memory. take less space in memory.

Example of RISC: ARM, PA-RISC, Power Examples of CISC: VAX, Motorola 68000
Architecture, Alpha, AVR, ARC and the SPARC. family, System/360, AMD and the Intel x86
CPUs.

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