ASL F18 circuits

Christopher I. Daykin MA

email: hiaccelectronics@gmail.com

Jan 2023

The collection of monographs “High Accuracy Electronics” can be found at: -

https://drive.google.com/folderview?id=1TbomXeoBble-IVADaOOmyyLH9le-3wAt
ASL F18 circuits

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 ASL F18 circuits

Contents
1. Introduction and overview
1.1 Bridge configuration
1.2 The active guard circuit
1.3 The quadrature servo
1.4 Bridge current source
1.5 External reference resistor
1.6 Internal zero and unity ratio checks
1.7 Null detector
1.7.1 Low noise pre-amplifier
1.7.2 Amplifier/filter PCB
1.7.3 Phase sensitive detectors and quad servo PCB

2. Power supply
2.1 Main 5V supply
2.2 Main 15-0-15 supply
2.3 Power supplies for the high accuracy voltage followers (HAVFs)
2.4 Relay coil and 5V logic power supplies
2.5 Power supply distribution PCB
2.6 Zener diode supplies
2.7 Miscellaneous stuff

3. Part 1: Carrier generator

3.1 Phase-lock loop PLL1
3.2 Modulator and filter stages
3.3 Phase reversal circuit
3.4 Amplitude control circuit
3.5 Phase reference phase-lock loop PLL2

3. Part 2: V to I and guard amp

3.6 V to I and guard amp module
3.7 Current amplitude fine control
3.8 Voltage to current converter
3.9 Guard amplifier
3.10 Current amplitude coarse control
3.11 Guard amp (carrier) overload detector
3.12 Interface circuits

4. Active guard and the high accuracy voltage followers (HAVFs).

4.1 Active guard
4.2 High accuracy voltage followers

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ASL F18 circuits
5. Part 1: Null detector pre-amp and PCB1
5.1 The low noise pre-amp
5.2 Amplifier and filter PCB1
5.2.1 Band-pass filter BPF1
5.2.2 Switched gain stage (SGS1)
5.2.3 Band-pass filter BPF2
5.2.4 Notch filter NF1
5.2.5 Notch filter NF2
5.2.6 Switched gain stage (SGS2)
5.2.7 MDAC variable gain stage
5.2.8 Band-pass filter BPF3
5.2.9 Pre-amp overload detector
5.2.10 Pre-amp gain decoder
5.2.11 Power supply and other controls via connectors JA1 and JA2
5.2.12 Interface circuits

5. Part 2: Null detector PCB2

5.3 The null detector PCB2
5.3.1 Inverter stage INV1
5.3.2 The synchronous rectifiers
5.3.3 The multiplier
5.3.4 The mutual inductor
5.3.5 Low-pass filters
5.3.6 Residual detector
5.3.7 Meter selector
5.3.8 Differential switched gain stage
5.3.9 Inverter 2
5.3.10 Synchronous rectifier/low-pass filter
5.3.11 Overload detectors
5.4 Interface circuits

6. Ratio transformer, MDAC, negative and simulated capacitors

6.1 Introduction
6.2.1 The ratio transformer (decades 1 to 4)
6.2.2 MDAC (decades 5 to 7)
6.3 Negative and simulated large capacitors
6.4 Interface circuits

7. Adjustments and final checks

7.1 Basic checks (normal configuration)
7.2 External zero ratio check
7.3 External unity ratio check
7.4 External signal generator configuration
7.5 Zero VS and VT checks
7.6 Adjustments
7.6.1 V to I and guard amplifier PCB.
7.6.2 Carrier generator PCB (slot 4 of the card frame)
7.6.3 High accuracy voltage follower PCB.
7.6.4 Pre-amplifier PCB
7.6.5 Amplifier and filter PCB (slot 6)
7.6.6 Amplifier/filter tuning
7.6.7 Null detector PCB2 DC offsets
7.6.8 MDAC module
7.6.9 Negative and simulated capacitors
7.7 Final checks

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 ASL F18 circuits
1. Introduction and overview

1.1 Bridge configuration

The ASL F18 employs a pair of high accuracy voltage followers (HAVFs) [1] to drive the energising windings of a
three-stage ratio transformer [2] in a novel bridge configuration: -

HAVF1
Ratio transformer/MDAC
+

RS VS NP
NS
+
Null
D detector
IB HAVF2
Virtual earth
(VE)

RT VT

Fig. 1.1.1 The F18 bridge configuration

The HAVFs and ratio transformer are depicted here in the conventional way for simplicity. The actual circuits are
rather more subtle. For a thorough understanding it is recommended that the reader study the relevant monographs.

The most sensitive part of the bridge circuit is maintained at local 0V (“virtual earth”) by the active guard circuit - a
high gain block [3].

The full range of ratio is 0.0000000 to 1.2999999. The first five digits are implemented with two stages of ratio
transformer. The lower three digits are implemented with an MDAC plus a two-stage step-down (10000:1)
transformer.

The in-phase component of the bridge output (input to the null detector) is: -

NS N
VD  VS  VT  S I B RS  I B RT
NP NP
RT N S
At null balance VD  0 the resistance ratio is the transformer turns ratio: 
RS N P

The null detector [4] also detects any quadrature imbalance which is automatically reduced to zero by the action of
a quadrature servo in both manual and automatic (in-phase) balance modes.

The bridge operating frequency is selectable 25Hz or 75Hz (60Hz or 90Hz for the USA version) phase locked to
the local power supply. Whereas it is very unlikely that any sub-harmonics are present the relative phase is
reversible so that such interference can be detected.

For more detail see [5].

1. Part 4, monograph 2: “High accuracy voltage followers”.

2. Part 3, monograph 4: “Three-stage RTs”.
3. Part 4, monograph 1: “High gain blocks”.
4. Part 5, monograph 1: “Null detectors – the basics”.
5. Part 3, monograph 7: “An F18 type ratio transformer bridge”.

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ASL F18 circuits
1.2 The active guard circuit

Another innovative feature of the F18 is the use of a high gain block (HGB, two-stage, type 1 [1]) to create a
“virtual earth” point (VE) for the bridge. The HGB, standard resistor and thermometer are configured as an
inverting amplifier. The action of feedback ensures that the inverting input of the HGB is maintained at the primary
0V (P0V) very accurately, setting the bridge potentials relative to local earth. This is much more practicable than a
“Wagner balance” [2]: -

outer VS inner VT
outer
RT
RS
IB VE
±15V
P0V HGB
PSU
±15V IB

Fig. 1.2.1 The active guard circuit

A useful way to remember the coax cable connections for normal operation is “outer conductors to the outer part of
the bridge”. The inner connections (between RS and RT) are sensitive to interference and are shielded by the outer
conductors.

Note that the current returns to the source via the power supply. The area of the loop (and stray flux) thus created is
minimised by a combination of twisted pairs and go/return pairs if PCB tracks.

1.3 The quadrature servo

The F18 has a separate quadrature synchronous rectifier (Quad SR) and automatic null balance (a.k.a. “quadrature
servo”) implemented with an analogue multiplier and a low phase error (ferrite) transformer. The output is added in
series with the output of the ratio transformer/MDAC . For in-depth theory see [3 and 4].

VIN G1 Quad SR Quad phase

Ref.

Integrator
Differentiator
LF
VS VREF V1 R
G2 Multiplier VQ

In-phase V2
0V
Fig. 1.3.1 Quadrature servo

With null balance for both in-phase and quadrature components the phase accuracy, of the amplifier/filter stages
before the synchronous rectifiers, is far less important so that a high degree of filtering is possible (band-pass for 25
or 75Hz and notch filters for supply harmonics).

1. Part 4, monograph 1: “High gain blocks”.

2. Part 3, monograph 7: “An F18 type ratio transformer bridge”. See section 3.
3. Part 5, monograph 1: “Null detectors-the basics”. See section 6.2.
4. Part 1, monograph 6: “Low phase error capacitors and inductors”. See section 3.

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 ASL F18 circuits
1.4 Bridge current source

The bridge current generator circuits are on a PCB in slot 4 of the card frame.

The clock signal, CLK1 at 25 or 75Hz, is generated with a phase-lock loop (PLL). The output of a power
transformer (18V RMS at 50Hz) is first passed through a (passive) band-pass filter (BPF) and then comparator
(Comp) to produce a 50Hz logic signal (±7.5V). The first divider (Div) then provides feedback to generate a 150Hz
logic signal. A second divider then generates CLK1 (divide by 2 or 6): -

TP1 TP11 TP12 TP14

50Hz 50Hz 19.2kHz 150Hz TP16

VCO/
BPF Comp Div Div CLK1
PC2
TP15
TP13
9.6kHz Select
Fig. 1.4.1 Phase-lock loop (PLL1)

The clock signal CLK1 drives a DC to AC modulator/filter to produce a sine wave at the chosen frequency: -

TP9 TP10 TP2 TP3 TP4 TP5 Output/

TP6

Inv
LPF LPF Inv
Inv
DC input
CLK1
Select Select
Fig. 1.4.2 Modulator/filter section

The modulator is a single pole two-way analogue switch, driven by CLK1, and produces a symmetrical square
wave from the DC input (from an integrator: TP9) and its inverse (TP10). The square wave is then converted to a
low distortion sinewave with two second order (Butterworth) low-pass filters (LPF). The natural frequency (-3dB
gain) is selectable so that the total phase shift is a fairly precise 180 deg. The phase integrity, relative to the power
supply, is thus maintained so that the final stage (inverted or not) can be used to detect the presence of sub-
harmonic interference.

The amplitude is controlled by comparison with a reference diode (ZD1: -6.2V) and integrator/feedback loop: -

R25 C25 TP9

TP6 100k 1μF TP4
CLK1

0/180 HWR Mod/

R26//R27
TP8 50k
filter
Phase IC12
control ZD1 LF356
0V Freq
1N821 VR7 R28
select
6V2 100k 220k
Fig. 1.4.3 Amplitude control circuit

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ASL F18 circuits
The half wave rectified current (via HWR and R26 in parallel with R27) plus the AC current via R25 supplies, on
average, the full wave rectified current into the virtual earth node of the integrator stage (IC12). An equal but
opposite current is provided by the adjustable resistance from the (negative) reference voltage.

The DC output of the integrator, together with a 25/75Hz clock and frequency selector logic inputs, result in an
amplitude controlled sine wave at the output (TP4 at ≈3V RMS).

The main oscillator is followed by an MDAC, two-stage high-pass filter (HPF), amplifier (Amp) and a voltage to
current converter (V to I). The 1, 2, 5mA and  2 options are selected by the 12 bit code to the MDAC.

TP3 TP4

IB
MDAC HPF Amp V to I

12 bits ×1.024

Fig. 1.4.4 Bridge current output stages

The voltage to current converter stage is a “Howland current pump” [1 and 2] based on a power op-amp with
positive and negative feedback [1, 2]. Glass encapsulated relays select the ×0.1, ×1 and ×10 options: -

R37
10k ±15V (High)
R7
TP4 10k Power op-amp.
3

R16 R17 R18

3k0 300R 30R

IB

R19 R20 R21

3k0 300R 3k0
0V (High)

Fig. 1.4.5 Voltage to current output stage

Most of the current source circuitry is supplied by a low current ±15V supply. The final (power) stage of the V to I
converter, however, is supplied by a separate high current supply which also supplies the guard amplifier.

The bridge current loop area (and stray flux) is minimised by careful routing of the conductors – a combination of
twisted pairs and go/return pairs of PCB tracks (see fig. 1.2.1).

1. Sheingold D. H.: "Impedance & Admittance Transformations using Operational Amplifiers".

The Lightning Empiricist, Vol. 12, No. 1. (Jan 1964).
2. Part 4, monograph 4: “The Isotech MicroK Bridge”. See section 3.

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 ASL F18 circuits
A second phase-lock loop is used to generate the in-phase and quadrature phase reference logic signals: -

TP6 TP18
fC TP17 4×fC TP19
Quad
TP20
Comp PLL Div
TP21
In-phase
TP22

Fig. 1.4.6 In-phase and quadrature phase reference generator

The comparator (Comp) first converts the carrier signal to logic levels (±7.5V). The phase-lock loop then produces
4 times the input frequency. This is then divided by 4 to produce both in-phase and quadrature phase reference
signals.

1.5 External reference resistor

To take advantage of the accuracy of the F18 the reference resistor the reference resistor needs to be very stable –
typically a “Wilkins” AC/DC transfer standard (in an oil bath for temperature control): -

Fig. 1.5.1 A Wilkins type reference resistor

The reference resistor can be in the range 1Ω to 300Ω, depending on the resistance range of the resistance
thermometer.

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ASL F18 circuits
1.6 Internal zero and unity ratio checks

The F18 has provision for high accuracy zero and unity ratio checks: -

RS VS to HAVFs

Virtual earth
VT
RT

Zero
Unity
Fig. 1.6.1 Zero and unity ratio checks

Zero check: The bridge should balance at a ratio of precisely 0.0000000 (±0.1ppm).

Unity check: The bridge should balance at a ratio of precisely 1.0000000 (±0.1ppm).

The ratio tweek PCB has a trimmer (picture required) for adjusting the meter to read zero in internal or external
unity ratio check configuration.

For adjustments and final checks see section 7.

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 ASL F18 circuits
1.7 The null detector

The null detector consists of three modules:

a). A low noise pre-amplifier with transformer for noise matching in a mumetal box for screening.
b). An amplifier/filter PCB in slot 6 of the card frame.
c). Phase sensitive detectors and quadrature servo in slot 5 of the card frame.

The card frame slots are numbered from right to left, as seen from the top and front. Please check.

1.7.1 Low noise pre-amplifier

The noise matching transformer [1] has three settings: 1, 10 and 100Ω: -

100Ω VOUT

700 R5
10k
10Ω
3000
R6
200 CBA 10R
1Ω
0V
VIN 100

Fig. 1.7.1.1 Low noise pre-amp

The high gain block is a single stage composite amplifier with a matched pair of BJTs (long-tail pair) front-end,
operated at 0.1mA each, for an input noise resistance of approximately 1kΩ [2].

The relay selects gain of ×1 or ×1001 according to a three bit gain control: -

Gain control code [3]

C B A Pre-
SGS1 SGS2 Total
(MSB) (LSB) amp
0 0 0 ×1 ×1 ×1 ×1
0 0 1 ×1 ×10 ×1 ×10
0 1 0 ×1 ×102 ×1 ×102
0 1 1 ×103 ×1 ×1 ×103
3
1 0 0 ×10 ×10 ×1 ×104
1 0 1 ×103 ×102 ×1 ×105
1 1 0 ×103 ×102 ×10 ×106
1 1 1 ×103 ×102 ×102 ×107
Fig. 1.7.1.2 Gain setting truth table [4]

1. Part 3, monograph 5: “Noise matching transformers”. See section 2.

2. Part 5, monograph 2: “Low noise BJT pre-amps”. See section 4.3.
3. The bit labels A, B and C are consistent with the Fairchild CD4051 data sheet.
4. Gain relative to the lowest setting and not including the fine gain control (see next section ).
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ASL F18 circuits
1.7.2 Amplifier/filter PCB

The amplifier/filter PCB card (slot 6) consists of: -

a). Band-pass filter (BPF1: 25Hz or 75Hz selectable).

b). Switched gain stage (SGS1: ×1, ×10 and ×100).
c). Band-pass filter (BPF2: 25Hz or 75Hz selectable).
d). Notch filters (NF1: 50Hz and 150Hz).
e). Notch filters (NF2: 50Hz and 150Hz).
f). Switched gain stage (SGS2: ×1, ×10 and ×100).
h). MDAC fine gain control (12 bit).
i). Band-pass filter (BPF3: 25Hz or 75Hz selectable).

TP1 TP2 TP3 TP6 25

25/75 CBA 25/75 25/75
From 75
Pre-amp
Quad BPF1 SGS1 BPF2 NF1 LSB TP17
TP18
TP19
TP20
MSB
NF2 SGS2 MDAC BPF3
To PSD/
Quad PCB
CBA Gain 25/75
TP9 TP10 TP12 TP13
Fig. 1.7.2.1 Amplifier/filter PCB

The control lines come from the interface PCB (card frame slot 3): -

a). Band-pass filters (BPF1 and BPF2): Logic 1 input selects 75Hz.
b). Switched gain stages: The three control lines are CBA (see fig. 1.7.1.2).
c). MDAC fine gain control: 12 binary bits delivered 4 bits at a time with 2 address lines, chip select and write
control. The gain is variable: up to ×10.

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 ASL F18 circuits
1.7.3 Phase sensitive detectors and quad servo PCB

The PSD/quad servo PCB card (slot 5) consists of: -

a). An inverter (Inv1).

b). In-phase synchronous rectifier (PSD1).
c). Two low-pass filters (LPF1 and LPF2) for the in-phase out-of-balance (including 25Hz notch).
d). Quadrature synchronous rectifier/integrator (PSD2/Int).
e). Analogue multiplier (Mult).
f). Mutual inductor stage (MI).
h). Switched gain stage (SGS) for the reference voltage.
i). Reference voltage synchronous rectifier/low-pass filter (PSD3/LPF) with a second inverter (Inv2).
j). Residual signal full wave rectifier and low-pass filter (FWR).
k). Residual and quadrature overload indicator/drivers (ROID and QOID).
l). Meter selector (analogue switch).

From TP8 Phase TP9 TP11

amp/filter ref.
PCB LPF1
Inv1
PSD1 TP12

LPF2 To ADC (μC PCB)

TP5
QOID To LED
indicator
TP6
PSD2/
Mult MI VQ
Int

TP1 Phase 0V
In-phase
ref.

FWR Quad Meter

M
selector

ROID Residual
To LED
Meter
indicator
From TP4 select
HAVFs
PSD3/
VS SGS Inv2 To ADC (μC PCB)
LPF

TP2 TP3
Gain
Fig. 1.7.3.1 Phase sensitive detector and quad servo PCB

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