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Vnd5050aj e

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0% found this document useful (0 votes)
26 views26 pages

Vnd5050aj e

manual

Uploaded by

leopoldo cortes
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 26

VND5050AJ-E

VND5050AK-E
Double channel high side driver with analog current sense
for automotive applications

Features
General
Max supply voltage VCC 41V
Operating voltage range VCC 4.5 to 36V PowerSSO-12 PowerSSO-24
Max On-State resistance (per ch.) RON 50 mΩ
■ Self limiting of fast thermal transients
Current limitation (typ) ILIMH 18 A
■ Protection against loss of ground and loss of
Off state supply current IS 2 µA(*)
VCC
(*) Typical value with all loads connected ■ Thermal shut down
■ Reverse battery protection (see Figure 24)
Application
■ Electrostatic discharge protection
■ All types of resistive, inductive and capacitive loads
■ Suitable as LED driver
Description
Main
The VND5050AJ-E, VND5050AK-E is a monolithic
■ Inrush current active management by power
limitation device made using STMicroelectronics VIPower
M0-5 technology. It is intended for driving resistive
■ Very low stand-by current
or inductive loads with one side connected to
■ 3.0V CMOS compatible input
ground. Active VCC pin voltage clamp protects the
■ Optimized electromagnetic emission device against low energy spikes (see ISO7637
■ Very low electromagnetic susceptibility transient compatibility table).
■ In compliance with the 2002/95/ec european
directive This device integrates an analog current sense
which delivers a current proportional to the load
Diagnostic Functions current (according to a known ratio) when
■ Proportional load current sense CS_DIS is driven low or left open.
■ High current sense precision for wide range
When CS_DIS is driven high, the CURRENT
currents
SENSE pin is in a high impedance condition.
■ Current sense disable
■ Thermal shutdown indication Output current limitation protects the device in
■ Very low current sense leakage overload condition. In case of long overload
duration, the device limits the dissipated power to
Protections safe level up to thermal shut-down intervention.
■ Undervoltage shut-down Thermal shut-down with automatic restart allows
■ Overvoltage clamp the device to recover normal operation as soon as
■ Load current limitation fault condition disappears..

Order codes
Package Part number (Tube) Part number (Tape & Reel)
PowerSSO-12 VND5050AJ-E VND5050AJTR-E
PowerSSO-24 VND5050AK-E VND5050AKTR-E

April 2006 Rev 2 1/26


www.st.com 26
Contents VND5050AJ-E / VND5050AK-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 15
3.1.1 Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2 Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 µC I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17


4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/26
VND5050AJ-E / VND5050AK-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block Diagram


VCC

VCC UNDERVOLTAGE
CLAMP OUTPUT1
PwCLAMP 1 CURRENT
GND DRIVER 1
SENSE1

INPUT1 ILIM 1 PwCLAMP 2


VDSLIM 1 DRIVER 2
LOGIC OUTPUT2
PwrLIM 1
ILIM 2
OVERTEMP. 1 CURRENT
VDSLIM 2 SENSE2
INPUT2 IOUT1
K1
OVERTEMP. 2
IOUT2
K2
PwrLIM 2

CS_DIS

Table 1. Pin Function


Name Function

VCC Battery connection


OUTPUT1,2 Power output
GND Ground connection. Must be reverse battery protected by an external diode/resistor network
INPUT1,2 Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state
CURRENT
Analog current sense pin, delivers a current proportional to the load current
SENSE1,2
CS_DIS Active high CMOS compatible pin, to disable the current sense pin

Figure 2. Configuration diagram (top view) & suggested connections for unused and n.c. pins
TAB = Vcc
VCC OUTPUT2
GND OUTPUT2
GND 12 N.C. OUTPUT2
1 Vcc OUTPUT2
11 INPUT2
INPUT2 2 OUTPUT2 N.C. OUTPUT2
INPUT1 3 10 OUTPUT2 INPUT1 OUTPUT2
CURRENT SENSE1 4 9 OUTPUT1 N.C. OUTPUT1
8 CURRENT SENSE1 OUTPUT1
CURRENT SENSE2 5 OUTPUT1 N.C. OUTPUT1
CS_DIS 6 7 Vcc CURRENT SENSE2 OUTPUT1
CS_DIS. OUTPUT1
VCC OUTPUT1

TAB = VCC

PowerSSO-12 PowerSSO-24

Connection / Pin Current Sense N.C. Output Input CS_DIS

Floating N.R. X X X X
To Ground Through 1KΩ resistor X N.R. Through 10KΩ resistor 10KΩ
N.R. = Not recommended

3/26
Electrical specifications VND5050AJ-E / VND5050AK-E

2 Electrical specifications

Figure 3. Current and Voltage Conventions


IS

VCC VCC

ICSD IOUT1
OUTPUT1
CS_DIS VOUT1
VCSD
IIN1 CURRENT ISENSE1
SENSE1
INPUT1 VSENSE1
VIN1
IOUT2
IIN2 OUTPUT2
INPUT2 VOUT2
VIN2 ISENSE2
CURRENT
SENSE2
GND VSENSE2

IGND

VFn = VOUTn - VCC during reverse battery condition

2.1 Absolute Maximum Ratings


Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
-VCC Reverse DC supply voltage 0.3 V
-IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
-IOUT Reverse DC output current 12 A
IIN DC input current -1 to 10 mA
ICSD DC current sense disable input current -1 to 10 mA
-ICSENSE DC Reverse CS pin current 200 mA
VCC-41 V
VCSENSE Current sense maximum voltage
+VCC V
Maximum switching energy
EMAX 51 mJ
(L=1.5mH; RL=0Ω; Vbat=13.5V; Tjstart=150°C; IOUT = IlimL(Typ.) )
Electrostatic Discharge (Human Body Model: R=1.5KΩ;
C=100pF) 4000 V
– INPUT 2000 V
VESD – CURRENT SENSE
4000 V
– CS_DIS
– OUTPUT 5000 V
– VCC 5000 V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
Tj Junction operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C

4/26
VND5050AJ-E / VND5050AK-E Electrical specifications

2.2 Thermal Data


Table 3. Thermal Data
Value
Symbol Parameter Unit
PowerSSO-12 PowerSSO-24

Thermal resistance junction-case (Max.)


Rthj-case 2.7 2.7 °C/W
(with one channel ON)
Rthj-amb Thermal resistance junction-ambient (Max.) See Figure 26 See Figure 30 °C/W

2.3 Electrical Characteristics


8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified.
Table 4. Power section
Symbol Parameter Test Conditions Min. Typ. Max. Unit

VCC Operating supply voltage 4.5 13 36 V


VUSD Undervoltage shutdown 3.5 4.5 V
Undervoltage shut-down
VUSDhyst 0.5 V
hysteresis
IOUT=2A; Tj=25°C 50 mΩ
RON On state resistance(2) IOUT=2A; Tj=150°C 100 mΩ
IOUT=2A; VCC=5V; Tj=25°C 65 mΩ
Vclamp Clamp Voltage IS=20mA 41 46 52 V
Off State; VCC=13V; Tj=25°C;
IS Supply current VIN=VOUT=VSENSE=VCSD=0V 2(1) 5(1) µA
On State; VCC=13V; VIN=5V; IOUT=0A 3 6 mA
VIN=VOUT=0V; VCC=13V; Tj=25°C 0 0.01 3
IL(off) Off state output current(2) µA
VIN=VOUT=0V; VCC=13V; Tj=125°C 0 5
VF Output - VCC diode voltage(2) -IOUT=4A; Tj=150°C 0.7 V
(1) PowerMOS leakage included.
(2) For each channel

Table 5. Switching (VCC=13V)


Symbol Parameter Test Conditions Min. Typ. Max. Unit

td(on) Turn-on delay time RL=6.5Ω (see Figure 6) 25 µs


td(off) Turn-off delay time RL=6.5Ω (see Figure 6) 35 µs
dVOUT/dt(on) Turn-on voltage slope RL=6.5Ω see Figure 19 V/µs
dVOUT/dt(off) Turn-off voltage slope RL=6.5Ω see Figure 20 V/µs
Switching energy losses
WON RL=6.5Ω (see Figure 6) 0.24 mJ
during twon
Switching energy losses
WOFF RL=6.5Ω (see Figure 6) 0.2 mJ
during twoff

5/26
Electrical specifications VND5050AJ-E / VND5050AK-E

Table 6. Logic input


Symbol Parameter Test Conditions Min. Typ. Max. Unit

VIL Input low level voltage 0.9 V


IIL Low level input current VIN=0.9V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN=2.1V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
IIN=1mA 5.5 7 V
VICL Input clamp voltage
IIN=-1mA -0.7 V
VCSDL CS_DIS low level voltage 0.9 V
ICSDL Low level CS_DIS current VCSD=0.9V 1 µA
VCSDH CS_DIS high level voltage 2.1 V
ICSDH High level CS_DIS current VCSD=2.1V 10 µA
VCSD(hyst) CS_DIS hysteresis voltage 0.25 V
ICSD=1mA 5.5 7 V
VCSCL CS_DIS clamp voltage
ICSD=-1mA -0.7 V

Table 7. Protections and Diagnostics (1)


Symbol Parameter Test Conditions Min. Typ. Max. Unit

VCC=13V 12 18 24 A
IlimH DC Short circuit current
5V<VCC<36V 24 A
Short circuit current during
IlimL VCC=13V TR<Tj<TTSD 7 A
thermal cycling
TTSD Shutdown temperature 150 175 200 °C
TR Reset temperature TRS + 1 TRS + 5 °C
TRS Thermal reset of STATUS 135 °C
THYST Thermal hysteresis (TTSD-TR) 7 °C
Turn-off output voltage
VDEMAG IOUT=2A; VIN=0; L=6mH VCC-41 VCC-46 VCC-52 V
clamp
Output voltage drop IOUT=0.1A; Tj= -40°C...+150°C
VON 25 mV
limitation (see Figure 7)
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must
limit the duration and number of activation cycles

6/26
VND5050AJ-E / VND5050AK-E Electrical specifications

Table 8. Current Sense (8V<VCC<16V)


Symbol Parameter Test Conditions Min. Typ. Max. Unit

IOUT=0.05A; VSENSE=0.5V;VCSD=0V;
K0 IOUT/ISENSE
Tj= -40°C...150°C 1270 2360 3450
IOUT=1A; VSENSE=0.5V;VCSD=0V;
K1 IOUT/ISENSE Tj= -40°C 1470 2020 2610
Tj= 25°C...150°C 1570 2020 2470
IOUT=2A; VSENSE=4V;VCSD=0V;
K2 IOUT/ISENSE Tj= -40°C 1740 2020 2320
Tj= 25°C...150°C 1790 2020 2250
IOUT=4A; VSENSE=4V;VCSD=0V;
K3 IOUT/ISENSE Tj=-40°C 1880 2010 2160
Tj=25°C...150°C 1900 2010 2120
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj=-40°C...150°C 0 1 µA
Analog sense leakage VCSD=0V; VIN=5V; Tj=-40°C...150°C 0 2 µA
ISENSE0
current
IOUT=2A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj=-40°C...150°C 0 1 µA
Max analog sense
VSENSE IOUT=4A; VCSD=0V 5 V
output voltage
Analog sense output
voltage in
VSENSEH VCC=13V; RSENSE=10KΩ 9 V
overtemperature
condition
Analog sense output
current in
ISENSEH VCC=13V; VSENSE=5V 8 mA
overtemperature
condition
Delay Response time VSENSE<4V, 0.5A<Iout<4A
tDSENSE1H from falling edge of 50 100 µs
ISENSE=90% of ISENSE max (see Figure 4)
CS_DIS pin
Delay Response time VSENSE<4V, 0.5A<Iout<4A
tDSENSE1L from rising edge of 5 20 µs
ISENSE=10% of ISENSE max (see Figure 4)
CS_DIS pin
Delay Response time VSENSE<4V, 0.5A<Iout<4A
tDSENSE2H from rising edge of 80 300 µs
ISENSE=90% of ISENSE max (see Figure 4)
INPUT pin
Delay Response time VSENSE<4V, 0.5A<Iout<4A
tDSENSE2L from falling edge of 100 250 µs
ISENSE=10% of ISENSE max (see Figure 4)
INPUT pin

7/26
Electrical specifications VND5050AJ-E / VND5050AK-E

Figure 4. Current Sense Delay Characteristics

INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L

Figure 5. IOUT/ISENSE Vs. IOUT (see Table 8 for details)

Iout/Isense
4000

max Tj= -40ºC to 150ºC


3500

3000

max Tj=25...150ºC
2500

typical value
2000

min Tj=25...150ºC
1500

min Tj=-40ºC to 150ºC


1000

500

0
0 1 2 3 4 5
Iout (A)

8/26
VND5050AJ-E / VND5050AK-E Electrical specifications

Table 9. Truth table


CONDITIONS INPUT OUTPUT SENSE (VCSD=0V)(1)

L L 0
Normal operation
H H Nominal
L L 0
Overtemperature
H L VSENSEH
L L 0
Undervoltage
H L 0
L L 0
Short circuit to GND
H L 0 if Tj < TTSD
(Rsc ≤ 10 mΩ)
H L VSENSEH if Tj > TTSD
L H 0
Short circuit to VCC
H H < Nominal
Negative output voltage
L L 0
clamp
(1) If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.

Figure 6. Switching characteristics

VOUT
tWon tWoff

90%
80%

dVOUT/dt(on) dVOUT/dt(off)

tr 10% tf
t

INPUT
td(on) td(off)

Figure 7. Output Voltage Drop Limitation


Vcc-Vout

Tj=150oC Tj=25oC

Tj=-40oC

Von

Iout
Von/Ron(T)

9/26
Electrical specifications VND5050AJ-E / VND5050AK-E

Table 10. Electrical Transient Requirements


ISO 7637-2: TEST LEVELS Number of
2004(E) Burst cycle/pulse repetition Delays and
pulses or
III IV time Impedance
Test Pulse test times
1 -75V -100V 5000 pulses 0.5 s 5s 2 ms, 10 Ω
2a +37V +50V 5000 pulses 0.2 s 5s 50 µs, 2 Ω
3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 -6V -7V 1 pulse 100 ms, 0.01 Ω
5b(1) +40V +40V 1 pulse 400 ms, 2 Ω

ISO 7637-2: TEST LEVEL RESULTS


2004(E)
III IV
Test Pulse
1 C C
2a C C
3a C C
3b C C
4 C C
5b(1) C C

CLASS CONTENTS
C All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
E
and cannot be returned to proper operation without replacing the device.

(1) For load dump exceeding the above value a centralized suppressor must be adopted.

10/26
VND5050AJ-E / VND5050AK-E Electrical specifications

Figure 8. Waveforms

NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT

UNDERVOLTAGE

VUSDhyst
VCC VUSD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT

SHORT TO VCC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal <Nominal

OVERLOAD OPERATION
TTSD
Tj TR
TRS

INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
VSENSEH
SENSE CURRENT

current power thermal cycling


limitation limitation
SHORTED LOAD NORMAL LOAD

11/26
Electrical specifications VND5050AJ-E / VND5050AK-E

2.4 Electrical characteristics curves


Figure 9. Off State Output Current Figure 10. High Level Input Current

Iloff (uA) Iih (uA)


1 5

4.5
0.875
Vin=2.1V
Off State 4
0.75 Vcc=13V
Vin=Vout=0V 3.5
0.625
3

0.5 2.5

2
0.375
1.5
0.25
1
0.125
0.5

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 11. Input Clamp Voltage Figure 12. Input High Level

Vicl (V) Vih (V)


7 4

6.8
3.5
Iin=1mA
6.6
3
6.4
2.5
6.2

6 2

5.8
1.5
5.6
1
5.4
0.5
5.2

5 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 13. Input Low Level Figure 14. Input Hysteresis Voltage

Vil (V) Vhyst (V)


2 1

1.8 0.9

1.6 0.8

1.4 0.7

1.2 0.6

1 0.5

0.8 0.4

0.6 0.3

0.4 0.2

0.2 0.1

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

12/26
VND5050AJ-E / VND5050AK-E Electrical specifications

Figure 15. On State Resistance Vs. Tcase Figure 16. On State Resistance Vs. VCC

Ron (mOhm) Ron (mOhm)


100 100

90 90

Iout=2A 80 Tc= 150°C


80
Vcc=13V
70 70
Tc= 125°C
60 60

50 50
Tc= 25°C
40 40

30 30
Tc= - 40°C
20 20

10 10

0 0
-50 -25 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 40

Tc (°C) Vcc (V)

Figure 17. Undervoltage Shutdown Figure 18. ILIMH Vs. Tcase

Vusd (V) Ilimh (A)


16 25

14 22.5
Vcc=13V
12 20

10 17.5

8 15

6 12.5

4 10

2 7.5

0 5
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 19. Turn-on Voltage Slope Figure 20. Turn-off Voltage Slope

(dVout/dt)on (V/ms) (dVout/dt)off (V/ms)


1000 1000

900 900
Vcc=13V Vcc=13V
800 800
RI=6.5Ohm RI=6.5Ohm
700 700

600 600

500 500

400 400

300 300

200 200

100 100

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

13/26
Electrical specifications VND5050AJ-E / VND5050AK-E

Figure 21. STAT_DIS Clamp Voltage Figure 22. Low Level STAT_DIS Voltage

Vsdcl(V) Vsdl(V)
8
14
7
12
6
Isd=1mA
10
5

8
4

6
3

4 2

2 1

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 23. High Level STAT_DIS Voltage

Vsdh(V)
8

0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)

14/26
VND5050AJ-E / VND5050AK-E Application information

3 Application information

Figure 24. Application schematic

+5V

VCC

Rprot CS_DIS

Dld

µC Rprot INPUT
OUTPUT

Rprot
CURRENT SENSE
GND

RSENSE
RGND
CEXT VGND DGND

Note: Channel 2 has the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

3.1.1 Solution 1:
Resistor in the ground line (RGND only). This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600mV / (IS(on)max).
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.

15/26
Application information VND5050AJ-E / VND5050AK-E

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

3.1.2 Solution 2:
A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection


Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 µC I/Os protection:


If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ.
Recommended values: Rprot =10kΩ, CEXT=10nF.

16/26
VND5050AJ-E / VND5050AK-E Package and PCB thermal data

4 Package and PCB thermal data

4.1 PowerSSO-12 thermal data


Figure 25. PowerSSO-12 PC Board

Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2).

Figure 26. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
70

65

60

55

50

45

40
0 2 4 6 8 10
PCB Cu heatsink area (cm^2)

Figure 27. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse


ZTH (˚C/W)
1000

Footprint
100
2 cm2

8 cm2

10

0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)

Pulse Calculation Formula


Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T

17/26
Package and PCB thermal data VND5050AJ-E / VND5050AK-E

Figure 28. Thermal Fitting Model of a Double Channel HSD in PowerSSO-12

Thermal Parameter
Area/island (cm2) Footprint 2 8

R1=R7 (°C/W) 0.7


R2=R8 (°C/W) 2.8
R3 (°C/W) 7
R4 (°C/W) 10 10 9
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1=C7 (W.s/°C) 0.001
C2=C8 (W.s/°C) 0.0025
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9

18/26
VND5050AJ-E / VND5050AK-E Package and PCB thermal data

4.2 PowerSSO-24 thermal data


Figure 29. PowerSSO-24 PC Board

Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2).

Figure 30. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
55

50

45

40

35

30
0 2 4 6 8 10
PCB Cu heatsink area (cm^2)

Figure 31. PowerSSO-24 Thermal Impedance Junction Ambient Single Pulse


ZTH (˚C/W)
1000

100 Footprint

2 cm2

8 cm2

10

0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)

Pulse Calculation Formula


Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T

19/26
Package and PCB thermal data VND5050AJ-E / VND5050AK-E

Figure 32. Thermal Fitting Model of a Single Channel HSD in PowerSSO-12

Thermal Parameter
Area/island (cm2) Footprint 2 8

R1=R7 (°C/W) 0.4


R2=R8 (°C/W) 2
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1=C7 (W.s/°C) 0.001
C2=C8 (W.s/°C) 0.0022
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17

20/26
VND5050AJ-E / VND5050AK-E Package information

5 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.1 Package Mechanical


Figure 33. PowerSSO-12™ Package Dimensions
D
h x 45˚ 0.25 mm
GAUGE PLANE
C

A2 A

B C
SEATING
PLANE L
A1 K
ddd C

12 7

E H

BOTTOM
Y VIEW
1 6
e

Table 11. PowerSSO-12™ Mechanical Data


millimeters
Symbol
Min Typ Max
A 1.250 1.620
A1 0.000 0.100
A2 1.100 1.650
B 0.230 0.410
C 0.190 0.250
D 4.800 5.000
E 3.800 4.000
e 0.800
H 5.800 6.200
h 0.250 0.500
L 0.400 1.270
k 0° 8°
X 1.900 2.500
Y 3.600 4.200
ddd 0.100

21/26
Package information VND5050AJ-E / VND5050AK-E

Figure 34. PowerSSO-24™ Package Dimensions

Table 12. PowerSSO-24™ Mechanical Data


millimeters
Symbol
Min Typ Max
A 2.15 2.47
A2 2.15 2.40
a1 0 0.075
b 0.33 0.51
c 0.23 0.32
D 10.10 10.50
E 7.4 7.6
e 0.8
e3 8.8
G 0.1
G1 0.06
H 10.1 10.5
h 0.4
L 0.55 0.85
N 10deg
X 4.1 4.7
Y 6.5 7.1

22/26
VND5050AJ-E / VND5050AK-E Package information

5.2 Packing information


Figure 35. PowerSSO-12 Tube Shipment (No Suffix)

B
Base Q.ty 100
C
Bulk Q.ty 2000
Tube length (± 0.5) 532
A 1.85
A
B 6.75
C (± 0.1) 0.6

All dimensions are in mm.

Figure 36. PowerSSO-12 Tape And Reel Shipment (Suffix “TR”)

REEL DIMENSIONS

Base Q.ty 2500


Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm. End

Start

Top No components Components No components


cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

23/26
Package information VND5050AJ-E / VND5050AK-E

Figure 37. PowerSSO-24 Tube Shipment (No Suffix)

Base Q.ty 49
Bulk Q.ty 1225
C
Tube length (± 0.5) 532
B
A 3.5
B 13.8
C (± 0.1) 0.6
All dimensions are in mm.
A

Figure 38. PowerSSO-24 Tape And Reel Shipment (Suffix “TR”)

REEL DIMENSIONS
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 100
T (max) 30.4

TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2
End
All dimensions are in mm.

Start

Top No components Components No components


cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

24/26
VND5050AJ-E / VND5050AK-E Revision history

6 Revision history

Table 13. Document revision history


Date Revision Changes

30-Mar-2006 1 Initial release.


14-Apr-2006 2 PowerSSO-24 dimensions table update.

25/26
VND5050AJ-E / VND5050AK-E

Please Read Carefully:

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