ACE

Engineering College
An Autonomous Institution
(NBA ACCREDITED B.TECH COURSES: EEE, ECE, MECH & CSE, ACCORDED NAAC ‘A’GRADE)
Ghatkesar, Hyderabad- 501 301

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

COMPUTER ORGANIZATION AND ARCHITECTURE (CS304PC) – 20 Batch

UNIT – 1

1.Discuss the functional units of Digital computer?

Answer:
Digital Computer is a fast electronic calculating machine that accepts digitized input information,
processes it according to a list of internally stored instructions, and produces the resulting output
information.
The below figure shows block diagram of digital computer:

Central Processing Unit (CPU):

 Performs all operations in the computer
 Controls operation of system by issuing timing and control signals
 Contains ALU which does all computations(arithmetic, logic and shift operations) on data
 Contains registers for storing data, control circuits for fetching and executing instructions

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 Memory:
– Is a storage area
– Storage for instructions and data (no distinction).
– It is called Random Access Memory (RAM) because CPU can access any location in memory
at random and retrieve the binary info within a fixed interval of time.

Input and Output Processor (IOP):

– Contains electronic circuits for communicating and controlling the (interface) transfer of
information between computer and outside world, e.g. keyboard, printer, scanner, mass
storage, etc.

Computer system is divided into two functional entities: hardware and software
– Hardware: Lowest level in a computer. It comprises all of the physical parts (electronic and
electromechanical devices) of a computer.
– Software: Sequences of instructions and data that make computers do useful work.

Three viewpoints for hardware:

1. Computer Organization
2. Computer Design
3. Computer Architecture

Computer organization:
 It is concerned with the way the hardware components operate and the way they are connected
together to form the computer system.( interconnection of h/w to form the computer system)

Computer design:
 It is concerned with the hardware design of the computer.
 Computer design is concerned with the determination of what hardware should be used and how
the parts should be connected.
 This aspect is referred to as computer implementation.

Computer architecture:
 It is concern with the structure and behavior of the computer perceived by the user.
 It Includes instruction format, instruction set, and techniques for addressing memory.
 It is also concern with specifications of the various functional modules like processor and
memory, and structuring them.

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2.Draw the Bus System for four registers and explain. (or) Demonstrate
construction of common Bus System with Multiplexers.
Answer:

A digital computer has many registers, and paths must be provided to transfer information from one register
to another.

 A more efficient scheme for transferring information between registers in a multiple-register

configuration is a common bus system.
 A bus structure consists of a set of common lines, one for each bit of a register, through which
binary information is transferred one at a time.
 Control signals determine which register is selected by the bus during each transfer.

There are two ways to construct Common Bus

1.By using Multiplexers

2.By using three- state gates

Common Bus Using Multiplexers:

The below figure shows construction of common bus between registers using Multiplexers:

– A multiplexer (or mux), also known as a data selector, is a device that selects between several analog
or digital input signals and forwards it to a single output line.
– Each register has four bits, numbered 0 through 3. The bus consists of four 4 x 1 multiplexers each
having four data inputs, 0 through 3, and two selection inputs, S1 and S0.

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 – Output 1 of register A is connected to input 0 of MUX 1 because this input is labeled A1.
– The bits in the same significant position in each register are connected to the data inputs of one
multiplexer to form one line of the bus.
– Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of the
registers, and similarly for the other two bits.

Bus selection

– The two selection lines S1 and S0 are connected to the selection inputs of all four multiplexers.
– The selection lines choose the four bits of one register and transfer them into the four-line common
bus.

 In general, a bus system will multiplex k registers of n bits each to produce an n-line common bus.
 The number of multiplexers needed to construct the bus is equal to n, the number of bits in each
register.
 The size of each multiplexer must be k x 1 since it multiplexes k data lines.
 The transfer of information from a bus into one of many destination registers can be accomplished by
connecting the bus lines to the inputs of all destination registers and activating the load control of the
particular destination register selected.
BUS ← C, R1 ← BUS
R1 ← C
 The content of register C is placed on the bus, and the content of the bus is loaded into register R 1 by
activating its load control input.

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3.Explain the Memory Reference Instructions LDA, STA, BUN, and BSA.
Write the microoperations.
Answer:

LDA: Load to AC

 Transfers the memory word specified by the effective address to AC.

 Microoperations for this instruction:

D2T4: DR  M[AR] Read operand

D2T5: AC  DR, SC  0 Load into DR
STA: Store AC
 Stores the content of AC into the memory word specified by effective address.
 Microoperation for this instruction:

D3T4: M[AR]  AC, SC  0

BUN: Branch Unconditionally

 Transfers the program control to the instruction specified by the effective address.
 Allows to specify the instruction out of sequence.
 Program branches (jumps) unconditionally.
 Microoperation for this instruction:

D4T4: PC  AR, SC  0

BSA: Branch and Save Return Address

 This instruction is useful for branching to a portion of the program called a subroutine or
procedure.
 When executed, the BSA instruction stores the address of the next instruction in sequence
(which is available in PC) into a memory location specified by the effective address.
 Microoperation for this instruction:

D5T4: M[AR]  PC, AR  AR + 1

D5T5: PC  AR, SC  0

A numerical example that demonstrates how this instruction is used with a subroutine is shown in nelow
Figure.

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 – The BSA instruction is assumed to be in memory at address 20.
– The I bit is 0 and the address part of the instruction has the binary equivalent of 135.
– After the fetch and decode phases, PC contains 21, which is the address of the next instruction in
the program (referred to as the return address).
– AR holds the effective address 135. This is shown in part (a) of the figure.
– The BSA instruction performs the following numerical operation:
M[135] 21, PC 135 + 1 = 136
– The result of this operation is shown in part (b) of the figure.
– The return address 21 is stored in memory location 135 and control continues with the subroutine
program starting from address 136.
– The return to the original program (at address 21) is accomplished by means of an indirect BUN
instruction placed at the end of the subroutine.
– When this instruction is executed, control goes to the indirect phase to read the effective address at
location 135, where it finds the previously saved address 21.
– When the BUN instruction is executed, the effective address 21 is transferred to PC .
– The next instruction cycle finds PC with the value 21, so control continues to execute the
instruction at the return address.

Subroutine Call

 The BSA instruction performs the operation / function referred to as a subroutine call.

 The indirect BUN instruction at the end of the subroutine performs the function referred to as
subroutine return.

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4. Explain about Stored program organization? What is the difference
between a direct and an indirect address instruction? How many
references to memory are needed for such type of instruction to
bring an operand into a processor register?
Answer:

 The ability to store and execute instructions is called Stored-Program organization, is the important
property of a general-purpose computer.

 Below figure shows the concept

 The simplest way to organize a computer is to have one processor register and an instruction code
format with two parts.
 The first part specifies the operation to be performed and the second specifies an address.
 The memory address tells the control where to find an operand in memory.
 This operand is read from memory and used as the data to be operated on together with the data
stored in the processor register.

 There are three Addressing Modes used for address portion of the instruction code:
1. Immediate: the operand is given in the address portion (constant).
2. Direct: the address points to the operand stored in the memory.
3. Indirect: the address points to the pointer (another address) stored in the memory that
references the operand in memory.

 One bit of the instruction code can be used to distinguish between direct & indirect addresses.
 The instruction code format shown in Figure.

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  It consists of a 3-bit operation code, a 12-bit address, and an indirect address mode bit designated
by I.
 The mode bit is 0 for a direct address and 1 for an indirect address.

Figure: Demonstration of direct and indirect address.

 For direct address one reference is needed, for indirect address two references are needed to access
the memory word.
 Effective address: the address of the operand in a computation-type instruction or the target address
in a branch-type instruction.
 The pointer can be placed in a processor register instead of memory as done in commercial
computers

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5. Discuss about the following
i. Instruction Cycle
ii. Applications of Logic microoperations
iii. Instruction set completeness
Answer:
i. Instruction Cycle

 In the basic computer each instruction is executed by going through a cycle, called Instruction
Cycle.
 Instruction Cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.

 After step 4, the control goes back to step 1 to fetch, decode and execute the next instruction.
 This process continues unless a HALT instruction is encountered.

Fetch and Decode

The Microoperations for the fetch and decode phases

T0: AR←PC The address of the instruction is moved to AR.

T1: IR←M[AR], PC←PC+1

The instruction is fetched from the memory to IR, and the PC is incremented.

T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11), I←IR(15)

After fetch and decode, instruction type is determined and instruction is executed.

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 ii. Applications of Logic microoperations
Logic microoperations can be used to change bit values, delete a group of bits, or insert new bit
values into a register .

1. Selective-set : The selective-set operation sets to 1, the bits in register A where there are
corresponding 1's in register B. It does not affect bit positions that have 0's in B. The OR
microoperation can be used to selectively set bits of a register.

2. Selective-complement: The selective-complement operation complements bits in A where

there are corresponding l's in B . It does not affect bit positions that have 0's in B . The exclusive-
OR microoperation can be used to selectively complement bits of a register.

3. Selective-clear : The selective-clear operation clears to 0, the bits in A, only where there are
corresponding 1's in B.

4. Mask (Delete): The mask operation is similar to the selective-clear operation except that the
bits of A are cleared only where there are corresponding 0' s in B. The mask operation is an
AND microoperation.
5. Clear: The clear operation compares the words in A and B and produces an all 0' s result if
the two numbers are equal. This operation is achieved by an exclusive-OR microoperation

6. Insert: The insert operation inserts a new value into a group of bits. This is done by first
masking the bits to be replaced and then ORing them with the bits to be inserted.

iii. Instruction set completeness

The set of instructions are said to be complete if the computer includes a sufficient number of
instructions in each of the following categories:

1.Arithmetic, logical, and shift instructions

• ADD, CMA (Complement AC), INC (increment AC)
• CIR, CIL
• AND, CMA, CLA (clear AC)
•
2. Instructions for moving information to and from memory and processor registers
• LDA (Load AC), STA (Store AC)

3. Program control instructions together with instructions that check status

• BUN (Branch Unconditional),
• BSA (Branch and Save return address),
• ISZ (Increment and skip if zero) with
• 4 skip instructions (SPA, SNA, SZA, SZE)

4. Input and output Instructions

• INP, OUT

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