EMBEDDED SYSTEM (EE 3401)

BY
DR. SUPRATIM GUPTA

National Institute of Technology Rourkela

Odisha - 769008
CHAPTER – 3: MEMORY INTERFACING

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MICROCOMPUTER SYSTEM
Features
Input / Output
• 2K Bytes EPROM
ALU Register Array
• 256 Bytes RAM
System Bus • 1 Timer/Counter
• 4 8-bit I/O port
Memory
• 1 6-bit I/O port
Control Unit
ROM RAM • 4 Interrupt levels
• Serial in / Serial out ports
Microprocessor
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THE 8085 PIN DIAGRAM

Microprocessor
GENERAL MEMORY STRUCTURE

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EPROM RAM
MEMORY INTERFACING: BASIC SIGNALS
1. Selection of the chip : Enables us to page the memories

2. Identification of group of registers in the chip (A8-A15 or part of that):

No. relates to width of memory 8, 16, so on; Decided by signal values on
Address Lines

3. Enable the input buffer by / output buffer : Access data from /

places data on data bus (AD0-AD7).
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THE MEMORY CHIPS

2764 7
8755A
THE MEMORY CHIPS: RAM

8156 8
THE MEMORY CHIPS: RAM

8156 6264 9
MEMORY INTERFACE WITH 8085

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ADDRESS DECODER: 8205

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ADDRESS DECODER: 74LS138

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MEMORY INTERFACE WITH 8085

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MEMORY INTERFACE WITH 8085

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MEMORY TYPES

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CHAPTER – 3: PARALLEL & SERIAL INTERFACING

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 8085 I/O STRUCTURE

Programmed I/O Interrupt I/O Direct Memory Access

Block Transfer Cycle Stealing Demand

Standard I/O Memory mapped I/O
DMA DMA Transfer DMA
Address: 8-bit Address: 16-bit
(AD7-AD0) (AD15-AD0)

External Internal

Maskable Non-maskable Software generated Due to exceptional

condition 17
8085 I/O STRUCTURE

• Programmed I/O: In programmed I/O the data transfer is accomplished

through an I/O port and controlled by software.

• Interrupt driven I/O: In interrupt driven I/O, the I/O device will interrupt
the processor, and initiate data transfer.

• Direct memory access (DMA): In DMA, the data transfer between memory
and I/O can be performed by bypassing the microprocessor.
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 PROGRAMMABLE PERIPHERAL INTERFACE: 8255

• Chip for interfacing

devices via parallel
communication –all
data bus signal
transferred at one
clock period.

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PROGRAMMABLE PERIPHERAL INTERFACE: 8255

1 1 1 0 0

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8255 IN STANDARD I/O CONFIGURATION

Sl.No Opcode Operand Hex Code Affected Flags

1. IN 8-bit DB No Flag
port
add.
2. OUT 8-bit D3 No Flag
port
add.

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8255 IN STANDARD I/O CONFIGURATION

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Port/ Register
1 1 1 1 1 1 0 0 PORT A

0 1 PORT B
1 0 PORT C
=0 1 1 Control Register

FC PORT A

FD PORT B

FE PORT C

FF Control Register
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8255 IN MEMORY MAPPED I/O CONFIGURATION
Sl.No Opcode Operand Hex Code Affected
Flags
1. STA 16-bit Add. 32 No Flag
2. LDA 16-bit Add. 3A No Flag

3. SHLD 16-bit Add. 22 No Flag

4. LHLD 16-bit Add. 2A No Flag

Reg. Hex
Pair Code
5. STAX B/D Reg. BC 02 No Flag
pair

DE 12
6. LDAX B/D Reg. BC 0A No Flag
pair 23
DE 1A
8255 IN MEMORY MAPPED I/O CONFIGURATION
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8
=0 1 X X X X X X X

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Port/ Register
X X X X X X 0 0 PORT A

0 1 PORT B
1 0 PORT C
1 1 Control Register

8000 PORT A

8001 PORT B

8002 PORT C

8003 Control Register 24

8255: AND SIGNAL GENERATION

Standard I/O Configuration

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8255: AND SIGNAL GENERATION

Memory Mapped I/O Configuration

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8255: CONTROL WORD

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8255: CONTROL WORD

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8255: CONTROL WORD FOR BSR MODE

This mode works only for Port C

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8255 IN MODE 1: INPUT CONFIGURATION

INTEA PC4

INTEB PC2

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8255 IN MODE 1: OUTPUT CONFIGURATION

INTEA PC6

INTEB PC2

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8255 IN MODE 2: OUTPUT CONFIGURATION

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ASSIGNMENTS

• Design a 8085 microprocessor based circuit to connect 8 push buttons & 8-

LEDs in memory mapped I/O configuration of 8255. The base address of this
configuration is CXXX H. Draw the circuit and write a code in assembly
language of 8085 to glow each LED –one to one mapped with push button.
Test your program in simulator
• Repeat the above problem in standard I/O configuration of 8255 with base
address as 9X H.

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34
8255: KEY BOARD INTERFACING

PC0 35
 ROBUST KEYBOARD OPERATIONS: HUMAN FACTORS

• To guard against bouncing of push button or accidental key press

• To guard against multiple & simultaneous key press and release in arbitrary
sequence
• To guard against key press and held for longer duration
• To guard against rapid key press
ROBUST KEYBOARD OPERATIONS: BOUNCING
ROBUST KEYBOARD OPERATIONS: HARDWARE SOLUTION
ROBUST KEYBOARD OPERATIONS: HARDWARE SOLUTION

Inverting Schmitt Trigger Operation

Schmitt Trigger

Output Voltage Vs. Input Voltage

 ROBUST KEYBOARD OPERATIONS: HARDWARE SOLUTION
Inverting Schmitt Trigger Operation
ROBUST KEYBOARD OPERATIONS: HARDWARE SOLUTION

Starting with the switch open

• The capacitor will charge
via and
• In time, will charge and will
reach within of .
• Therefore the output of the
inverting Schmitt trigger will be a
logic 0.
ROBUST KEYBOARD OPERATIONS: HARDWARE SOLUTION

Now close the switch

• The capacitor will discharge
via .
• In time, will discharge
and will reach 0 .
• Therefore the output of the
inverting Schmitt trigger will be
a logic 1.
 ROBUST KEYBOARD OPERATIONS: SOFTWARE SOLUTION

• De-bounce/Accidental Key hit: To wait until a time interval –longer than the manufacturer’s
specification –lapses during both key press & release.

• Multiple Key press: To use only a valid key patterns –all other patterns will be ignored; the first
valid key patterns will be accepted

• Key Hold: To identify valid key press if the same valid pattern exists after the de-bounce delay

• Rapid Key hit: Keys are scanned at a rate faster than human reaction time
THE ALGORITHM FOR KEYBOARD INTERFACE

• Step1: Check if any key is pressed else return to main routine

• Step 2: Provide a time delay for de-bouncing (generally 20ms)

• Step 3: Check if same switch is remained pressed else return to main routine

• Step 4: Check if valid key pattern is pressed else return to main routine

• Step 5: Act on the key pressed and return to main routine

 ROBUST KEYBOARD OPERATIONS: SOFTWARE SOLUTION

• Key scanning via polling: May sluggish, but usable for small keypad & less
number of multi-task environment

• Key scanning via interrupt: CPU will scan keys when interrupted; Optimal for
large key board & larger number of multi-tasking environment
KEYBOARD CONFIGURATION: LEAD-PER-KEY
KEYBOARD CONFIGURATION: MATRIX
KEYBOARD CONFIGURATION: CODED KEYBOARD
8255 INTERFACE WITH 7-SEGMENT DISPLAY
8255 INTERFACE WITH 74LS244 OCTAL BUFFER
8255 INTERFACE WITH 74LS244 OCTAL BUFFER
8255 Characteristics
8255 INTERFACE WITH 74LS244 OCTAL BUFFER
7-Segment LED Characteristics
8255 INTERFACE WITH 74LS244 OCTAL BUFFER
74LS244 Characteristics
 THE ALGORITHM FOR 7-SEGMENT LED DISPLAY

• Step1: Get the content to be displayed in Hex

• Step 2: Convert the HEX number to BCD

• Step 3: Use index addressing –Base address + index (the nibbles of BCD no.) -to a look up
table for fetching code for 7-Segment LEDs

• Step 4: Send the code to Port where the unit(s) is (are) connected
HEX TO BINARY CODED DECIMAL CONVERSION

• Let us consider radix ‘ ’ system of number representation

• If we put we get decimal system

for we get hexadecimal system
for we get binary system

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HEX TO BINARY CODED DECIMAL CONVERSION
• Let us consider a decimal number and its hexadecimal representation as
.

× × × × ×
 Step 1: in both the system and a
remainder
× × × ×
 Step 2: in both the system and a remainder

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HEX TO BINARY CODED DECIMAL CONVERSION
• Alternative Approach for same number .

or in general form
After every unit operation we need to adjust the overflow in the nibbles beyond 9 or
AC is generated

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HEX TO BINARY CODED DECIMAL CONVERSION
• Alternative Approach for same number .

Doubling : 0000 1001

0000 1001
DAA 0001 1000 = 18H but in decimal
0001 0010
system representation
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 INDEX ADDRESSING FOR DISPLAY CODE RETRIEVAL

10 ; For 9
⋮ ; For 2 - 8
79 ; For 1
LUTB: 40 ; For 0
RET
OUT 81H
MOV A, M ;Get the code from the memory
MOV L, A
ADD L
Display: LXI H, LUTb ; Store the base address of LUT
MOV A, B ; Get the number /character to be displayed in A
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EPROM
INDEX ADDRESSING FOR DISPLAY CODE RETRIEVAL
A B
10 8013
10
13
XX
09 09
⋮
H L
79 800B
LUTb: 40 800A XX
80 13
0A
XX
RET 8009
OUT 81H 8007
Program Counter
MOV A, M 8006
MOV L, A 8005 8009
8006
8007
8001
8000
8004
8005
ADD L 8004
Display: LXI H, LUTb 8001 PORT B OF 8255
MOV A, B 8000 XX
10

EPROM PROGRAMMING MODEL 60

INTERFACING MULTIPLE 7-SEGMENT LEDS WITH 8255

Draw the circuit with octal buffer with necessary

changes
ADC INTERFACING: ADC0809

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ADC0809: SPECIFICATIONS

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ADC0809: SPECIFICATIONS

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ADC INTERFACING

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ADC INTERFACING WITH 8255 IN MODE 0 & BSR
+5V

OE ALE VCC

IN0 PA D7-D0 AD7-AD0

ADC0809 8255 Micro-Computer

with 8085 𝜇P
EOC PC0 𝐶𝑆 A7
C A1 A1
B SC PC7 A0 A0 ALE
A
Vref- Vref+ 74LS373

+5V

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 ADC INTERFACING: ALGORITHM

• Step 1: Configure 8255: port A as input port

(mode 0) & port C for BSR
• Step2: Send a Pulse to PC7 (SC signal to ADC)
• Step 3: Read PC0 (EOC) for high
• Step 4: Read PA (Digital Data)
• Step 5: Repeat step 2-3 for next samples

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ADC INTERFACING: DETERMINING SAMPLING FREQUENCY

Other Lines can be checked

• EOC
• ALE 68

• OE (if connected)
ADC INTERFACING: DETERMINING SAMPLING FREQUENCY

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𝒇𝑪𝒍𝒌:𝑨𝑫𝑪 𝒇𝑺𝒂𝒎𝒑𝒍𝒆 𝒇𝑪𝒍𝒌:𝑨𝑫𝑪
𝑺𝒂𝒎𝒑𝒍𝒆 𝑵 and the signal bandwidth is 𝟐 𝟐𝑵
ADC INTERFACING: BIPOLAR SIGNAL
+5V

OE ALE VCC
D7-D0
IN0 PA

ADC0809 8255
EOC PC0 𝐶𝑆 A7
C A1 A1
B SC PC7 A0 A0
A
Vref- Vref+

+5V
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DAC INTERFACING: DAC0808

𝐴 𝐴 𝐴 𝑉 𝐴 𝐴 𝐴
𝐼 =𝐼 + + …+ 𝐼 = + + …+
2 4 256 𝑅 2 4 256
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DAC INTERFACING: DAC0808

𝐴 𝐴 𝐴
𝐼 =𝐼 + + …+
𝑅 2 4 256

𝑉 𝐴 𝐴 𝐴
𝑅 𝐼 = + + …+
𝑅 2 4 256

𝑉 𝐴 𝐴 𝐴
𝑉 = + + …+ 𝑅
𝑅 2 4 256

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DAC INTERFACING WITH 8255 IN MODE 0 & BSR
+5V

OE ALE VCC

IN0 PA D7-D0 AD7-AD0

ADC0809 8255 Micro-Computer

with 8085 𝜇P
EOC PC0 𝐶𝑆 A14
C A1 A1
B SC PC7 A0 A0 ALE
A
Vref- Vref+ PB 74LS373

+5V I0
DAC0809
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DAC INTERFACING: BIPOLAR OUTPUT SIGNAL

PA D7-D0 AD7-AD0

8255 Micro-Computer
with 8085 𝜇P
PC0 𝐶𝑆 A14
A1 A1
PC7 A0 A0 ALE
PB 74LS373

DAC0809
I0
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