Calibre xRC

Fast, accurate rule-based parasitic Calibre xRC signoff-quality rule decks in

extraction industry-standard SVRF format exist for
practically every manufacturing process
imaginable.

Hierarchical extraction reduces

simulation time
Parasitic extraction tools can potentially
generate a huge volume of data, impact-
ing overall processing time including
Benefits High-performance rule-based parasitic extraction and simulation of these very
• Full-chip performance – combines the extraction with industry-proven large netlists. The Calibre xRC product
performance of the Calibre hierarchical accuracy accelerates extraction and simulation in
and multi-threaded architecture with a Calibre® xRC parasitic extraction gives several ways:
compact netlist to boost throughput of designers rapid, accurate, and compre- • Leverages Calibre hierarchical design
large designs and maintain rapid feed- hensive feedback, increasing confidence processing, greatly accelerating turn-
back within custom design that manufactured devices will function around time particularly for designs
environments. Multiple process corner according to design. It seamlessly inte- that include regular arrays (e.g., mem-
analysis does not require complete grates with all major design flows ories), and multiple instances of
design re-run. because it is a constituent element of the hierarchical cells;
industry-proven Calibre physical verifica-
• Proven accuracy – Advanced extrac- •
tion suite. With countless successful
tion and process models correlate
tapeouts to its name, foundry-qualified
closely with field solver results; propri-
etary reduction algorithm maintains
integrity of parasitic data. Reduces
need for prohibitive design margins by
incorporating manufacturing depen-
dent effects (e.g., in-die variation) into
parasitic models.
• Rule deck availability – Availability of
foundry-certified signoff rule decks in
SVRF format ensures Calibre xRC para-
sitic extraction can meet your design
needs regardless of process or foundry
choice.
• Easy flow integration – Calibre xRC
exchanges native database informa-
tion with Calibre nmLVS, Calibre PERC,
Calibre xRC is fully integrated into the Calibre verification suite for seamless creation of netlists
and Calibre xACT 3D products.
and parasitic debugging in the design environment using Calibre RVE. xCalibrate is used by
Upstream design integration using foundries to create extraction rule files, and the same rule files can be used by Calibre xRC,
Calibre xL, Calibre xACT 3D and Calibre xACT 3D Reference.

siemens.com/software
Calibre xRC

Calibre Interactive, CalibreView and • Scales across multiple cores or CPUs seamless data exchange and analysis
Calibre RVE enables GUI-driven using the Calibre multi-threaded using a combination of LVS, rule-based
launch, back annotation, and cross- architecture; parasitic extraction, and field-solver–
probing for all popular layout based parasitic extraction. This integra-
• Accelerates time-to-simulation by pro-
environments. tion also
viding sets of compact, transistor-level
parasitic data that can be back-anno- helps the clear definition of the boundary
Benefits continued
tated and simulated while the between the device model and the para-
Support for all major transistor-
extraction process is still running on sitic tool, eliminating double counting of
based and cell-based simulation and
other parts of the design; parasitics and ensuring that there are no
analysis netlist formats ensures
missed effects.
compatibility with downstream digi- • Combines mixed-level data (transistor-
tal, custom, and mixed-signal flows. level, gate-level, and hierarchical), in a
Accelerates mixed-signal and
single parasitic extraction run;
custom design
• Generates multiple netlists including Tight integration between the design
any mixture of resistance, intrinsic environment, Calibre nmLVS, Calibre xRC
capacitance, and coupling capacitance parasitic extraction, and simulation and
and based on multiple process corners analysis tools streamlines data handling
without requiring a complete re-run; between upstream design creation envi-
ronments and downstream post-layout
• Generates compact netlists that
analysis. The synergistic pairing of hierar-
accelerate simulation without
chical Calibre nmLVS with Calibre xRC
sacrificing accuracy.
parasitic extraction gives analog/mixed-
signal designers several performance and
Engines precisely model
analysis benefits for full-chip, mixedsig-
advanced effects
nal design:
The Calibre xRC capacitance engine’s
proven close correlation with field solver • Enhanced accuracy for custom devices
and silicon data provides the greatest through intentional device recognition
contribution to the overall accuracy of with exact device parameters;
the product. The engine incorporates
• Ease of operation in a mixed-signal
precise, specific models for vias, con-
environment with concurrent transis-
tacts, and poly-to-contact area, which are
tor-level and gate-level parasitic device
particularly susceptible to esoteric but
extraction;
significant capacitance effects. Designers
can control modeling around devices • Acceleration of custom debug through
very accurately because of the product’s seamless backannotation of simulation
close integration into Calibre LVS and results to the source schematic. The
Calibre xACT 3D. The product’s resistance optional Calibre results viewing envi-
engine delivers improved fracturing, ronment (RVE) enables automated
including precise width and resistor loca- re-simulation directly from within the
tion for electromigration analysis. It design layout environment. It allows
enables device pin handling and custom- designers to examine resistance,
ized control over gate-region extraction. intrinsic capacitance, and coupling
The engine’s algorithms are hierarchical capacitance (R, C, RCC) data in a graph-
and correlate closely with resistance ical environment, and it facilitates
field-solver values. back-annotation and netlisting.
Designers who are using Calibre PERC
Integration with Calibre Platform
reliability checking can drive electrostatic
ensures efficient data handling
discharge analysis directly from Calibre
Calibre xRC parasitic extraction is fully
xRC resistance data. Designers can search
integrated into the Calibre physical verifi-
for specific topologies, identify pins and
cation suite along with Calibre nmLVS
ports of interest, extract parasitic
(layout vs. schematic), and the Calibre
xACT 3D field solver. This facilitates
resistances between these pins and designers to incorporate GDS metal fill or solutions. Our reputation depends on it,
ports, and compare point-to-point resis- transistor-level cell models without and we depend on our reputation. At
tance against constraints. Designers can requiring a full GDS stream-out from every node, Calibre has provided, and
then display violations using Calibre RVE. place-and-route. will continue to provide, pioneering tech-
nologies and tools that ensure you can
Calibre xRC operates seamlessly within
Integrated with multiple design flows continue to deliver your products on time
multiple schematic and layout environ-
The product’s flexible data model enables with the quality you need.
ments for easy debugging, and it gener-
multiple diverse design flows and styles
ates standard netlist formats, including
including analog, memory, ASIC, and The Calibre nm platform
Hspice, Eldo, Spectre, Calibreview, DSPF,
mixed signal. The Calibre nm platform, the industry’s
and SPEF. Calibre xRC drives fast, SPICE-
leading physical verification platform, is
Calibre xRC parasitic extraction supports level accurate, hierarchical, and flat cir-
known for delivering best-in-class perfor-
all popular upstream design tools cuit simulation and static-timing,
mance, accuracy, and reliability. A pow-
because it directly reads hierarchical and signal-integrity, and IR-drop analysis.
erful hierarchical engine is at the heart of
flat layout data in standard formats Calibre xRC can optimize hierarchical
the Calibre tool suite, providing solutions
including GDS, annotated GDS, LEF/DEF, netlist data for use with the Synopsys
for physical verification, parasitic extrac-
and Milkyway. The optional Calibre HSIM signal and power net analysis tool.
tion, resolution enhancement, mask data
Interactive product enables interactive
The parasitic reduction capability of prep, lithofriendly design, and design for
extraction driven from a graphical user
Calibre xRC is based on a proprietary manufacturing. Complete Calibre rule
interface (GUI), integrated into standard
combination of AWE and S-parameter files and extensive coverage of Calibre
layout environments including Siemens
techniques with custom control of processes for DRC and DFM are available
place-and-route tools, Pyxis custom lay-
thresholds and tolerances. at all major semiconductor foundries.
out and Calibre DESIGNrev, Cadence
Virtuoso and Encounter, Synposys The Calibre parasitic database provides
Milkway and IC Compiler, Seiko System customizable parasitic models per net
SX9000, and SpringSoft Laker. (for example, R only, RCC, RCCLM), to
enable different analysis flows, including
In digital flows, Calibre xRC establishes
noise, timing, power, and signal
connectivity information directly from
integrity.
LEF/DEF or annotated GDS design data.
This saves time and effort by eliminating
Calibre commitment to innovation
the need for an additional LVS run.
Calibre leads the way for one powerful
Calibre xRC enhances gatelevel extraction
reason – our constant and ongoing com-
accuracy because it supports a mixture of
mitment to innovation. We know that
LEF/DEF and GDS information. This allows
when you’re ready to move to the next
node, your tools need to be ready as
well. You need the confidence that
comes from knowing we’ve been work-
ing far in advance to identify the chal-
lenges and develop effective, proven

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