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VLSI Module 2 Part1

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Krishnapriyasudhakaran Krishna
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83 views21 pages

VLSI Module 2 Part1

Uploaded by

Krishnapriyasudhakaran Krishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECT 304 VLSI

MODULE 2
Static CMOS Logic
Design
Initial topics
SYLLABUS

 Module 2: Static CMOS Logic Design MOSFET Logic Design - NMOS Inverter
(Static analysis only), basic logic gates, CMOS logic, Static and transient
analysis of CMOS inverter, Switching power dissipation and delays. Realization
of logic functions with static CMOS logic, Pass transistor logic, and
transmission gate logic
MOS inverter:
Logic symbol , truth table & Ideal Voltage
Transfer Characteristics (VTC) (DC Chara.)
Generalised Circuit of an NMOS inverter
Resistive Load Inverter

 The basic structure of a


resistive load inverter is shown
in the figure given below. Here,
enhancement type nMOS acts as
the driver transistor. The load
consists of a simple linear
resistor RL. The power supply of
the circuit is VDD and the drain
current ID is equal to the load
current IR.
Resistive Load Inverter

 Circuit Operation:
 When the input of the driver transistor is less than threshold voltage
VTH (Vin < VTH), driver transistor is in the cut – off region and does not
conduct any current. So, the voltage drop across the load resistor is
ZERO and output voltage is equal to the VDD.
 Now, when the input voltage increases further, driver transistor will
start conducting the non-zero current and nMOS goes in saturation
region.
 Contd.
 Increasing the input voltage further, driver transistor will enter into the linear
region and output of the driver transistor decreases.
Voltage Transfer Characteristics (VTC)/Static
Characteristics/ DC characteristics of
inverter with resistive load
NMOS inverter with active load

 In this type, instead of resistor , a transistor is used as the load.


 The load can be
 Enhancement mode n-MOSFET
 Depletion mode n-MOSFET
NMOS inverter with enhancement mode
MOSFET as the load
Gate of the load MOSFET is
connected to VDD
NMOS inverter with DEPLETION mode
MOSFET as the load

Gate of the load MOSFET is connected to its


source.
Ie, VGS is kept 0V.
Since it is a depletion mode MOSFET, it is ON
even when VGS =0V.
Depletion mode MOSFET is indicated with
thicker line in place of channel in its symbol.
CMOS inverter
VTC/ Static/DC characteristics of CMOS
inverter with critical points & regions of
operation
Critical voltages in VTC
Noise Margin and Noise Immunity
 Noise Margin: Ability of the gate to tolerate fluctuations of the voltage
levels.
 Noise Immunity: The circuit's ability to tolerate noise signals is
referred to as the noise immunity
Calculation
of VM
(midpoint
voltage, also
known as
threshold
voltage of
CMOS
inverter)

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