Sequential circuit design

Finite State Machines

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Finite State Machines
 Definition
 State transition graphs
• Moore model
• Mealy model
 VHDL description

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Finite State Machines
 Synchronous sequential circuits:

Inputs Outputs

Combinational
circuit

Present Next
state state

State
(flip-flops)
Clk

 “State” block is made of flip-flops, synchronous with the

same clock signal
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Finite State Machines
 The behavior of a synchronous circuit can be represented by a
Finite State Machine (FSM)
 A state machine has the following elements:
• X = Inputs
• Y = Outputs
• Z = States (flip-flop values, they change every clock edge)
• δ = State functions (combinational functions, acting as flip-flop inputs)
• λ = Output functions (combinational functions, generating the outputs)

 A state machine can be defined as an event sequence in

discrete time. State (Z) changes with every event. State change
is defined by state functions (δ)

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Moore model
 Outputs are a function of the state (not inputs)
 Moore State Machine:
• Z = δ (X, Z)
• Y = λ (Z)
 Structure of a Moore circuit:

Inputs
Output Functions Outputs
(COMB)

State Functions State

(COMB) (SEQ)

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Moore model
 Clock and Reset do not appear in state machine
representations. Their relation with the state
machine is:
• Every clock edge a state change or transition is produced
• Reset activation makes the state machine to take its initial state

 Moore state machine outputs change only when

there is a state change
• Outputs are synchronized with the clock

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Moore model
 A FSM can be represented using a State Transition
Graph (STG):
• Every state is represented by a node
• Every transition is represented by an arrow
• Input values producing the transition are represented over the
corresponding arrow
• In a Moore model, outputs are represented inside the
corresponding state node

 State Transition Graph (Moore): Input 1 State 2

Output 2
State 1
Output 1
Input 2
State 3
Output 3

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Mealy model
 Outputs are functions of the state and the inputs
 Mealy FSM:
• Z = δ (X, Z)
• Y = λ (X, Z)
 Mealy circuit structure:
Inputs
Output Outputs
functions
(COMB)

State
State
functions
(SEQ)
(COMB)

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Mealy model
 Mealy state transition graph:
• Every state is represented by a node
• Every transition is represented by an arrow
• Input values producing the transition are represented over
the corresponding arrow
• In a Mealy model, outputs are represented over the
corresponding transition arrow
Input 1 /
Output 1
State 2

State 1

State 3
Input 2 /
Output 2

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Mealy model
 Same as Moore model, clock an reset are
not represented in the STG, they are implicit
 In Mealy state machines, outputs can change
anytime. An input change can produce an
output change:
• Outputs are not (necessarily) synchronized with
clock
• Although outputs are not in sync with clock, the
circuit is still synchronous, as every flip-flop is
synchronized with clock
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Synchronous Sequential Circuits
 Example: design a synchronous sequential circuit to
detect a sequence of three or more consecutive
ones in a serial input
 Input is read every rising clock edge
 Output activates when the right sequence is detected

X Z

Clk
Reset

 Input-output sample sequence:

 X:001101111100111
 Z:000000011100001

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State Transition Graphs
 Solution: Mealy

1/0 S1

0/0 S0 0/0 1/0

0/0 S2

1/1

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State Transition Graphs
 Solution: Moore

0 1
S0/0 S1/0
0
0 1
0
S3/1 S2/0
1
1

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VHDL: State Machines
 States: declared as enum type
• TYPE state_t IS (s0, s1, s11);
• Declare signals for present and next state
 Sequential part:
• Sequential process
• Asynchronous initialization to initial state
• Synchronous state update (present state updated with next
state)
 Combinacional part:
• Generates next state and outputs
• Combinational process depending on state (case)

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VHDL example: Moore machine
 Write VHDL description

‘0’ ‘0’

‘1’ ‘1’
s0 / ‘0’ s1 / ‘0’ s11 / ‘1’
‘1’

‘0’

ENTITY fsm is
PORT( clk: in std_logic;
reset: in std_logic;
a: in std_logic;
z: out std_logic);
END fsm;

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VHDL example: Moore machine
ARCHITECTURE moore OF fsm IS PROCESS (state, a)
TYPE state_t IS (s0, s1, s11); BEGIN
SIGNAL state, next_state: state_t; CASE state IS
BEGIN WHEN s0 =>
PROCESS (clk, reset) z <= '0';
BEGIN IF a = '0' THEN
IF reset = '1' THEN next_state <= s0;
state <= s0; ELSE
ELSIF rising_edge(clk) THEN next_state <= s1;
state <= next_state; END IF;
END IF; WHEN s1 =>
END PROCESS; z <= '0';
.... IF a = '0' THEN
next_state <= s1;
ELSE
next_state <= s11;
END IF;
WHEN s11 => ...
z <= ‘1';
....
END CASE;
END PROCESS;
END moore;

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VHDL example: Mealy machine

‘0’ / ‘0’
‘0’ / ‘0’

‘1’ / ‘0’
S0 S1

‘1’ / ’1’
ENTITY fsm is
PORT( clk: in std_logic;
reset: in std_logic;
a: in std_logic;
z: out std_logic);
END fsm;

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VHDL example: Mealy machine
ARCHITECTURE mealy OF fsm IS PROCESS (state, a)
TYPE state IS (s0, s1); BEGIN
SIGNAL state, next_state: estado; CASE state IS
BEGIN WHEN s0 =>
PROCESS (clk, reset) z <= '0';
BEGIN IF a = '0' THEN
IF reset = '1' THEN next_state <= s0;
state <= s0; ELSE
ELSIF rising_edge(clk)THEN next_state <= s1;
state <= next_state; END IF;
END IF; WHEN s1 =>
END PROCESS; IF a = '0' THEN
.... z <= '0';
next_state <= s1;
ELSE
z <= '1';
next_state <= s0;
END IF;
END CASE;
END PROCESS;
...

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