S a mp le Soke tious CprE 281: Digital Logic Midterm 1: Friday Sep 22, 2017 ‘Student Name: Student ID Number: Lab Section: Mon 9-12(N) Tue 11-2(U) Wed 8-11(J) Thur 11-2(Q) Fri 11-2(G) (circle one) Mon 12-3(P) Tue 2-5(M) Wed 11-2(W) Thur 11-2(V) Tue 2-5(Z) Wed 6-9(T) Thur 2-5(L) Thur 5-8(K) 1, True/False Questions (10 x Ip each = 10p) (a) [ forgot to write down my name, student ID, and lab section. RUE (FALSE) (b) A 2-to-1 multiplexer can be built using only OR and NOT gates. Gaury FALSE (c) Itis not possible to build a NOT gate with a 2-to-1 multiplexer. TRUE (Gatsby (@) The minimum expression for f{x,y)=Xm(0,1,3)+D(2) is 1. FALSE GRoB)y FALSE TRUE /| Gauby FALSE TRUE 0 (i) The *K’ in K-map stands for ‘Kilobyte.” TRUE (j) K-2S0 is stronger than C-3P0. GRuey FALSE 2. Three-Variable K-map (5p) Draw the K-map and derive the minimum SOP expression for f(a,b,e) = II MQ, 4, 5). This pro€lem has two sole hms, =m (0, 4,36 ¥) 2, ab c\ 222 q(t || 0 i ( °° j_ _ ce \ f= ae+bcer+a€ feabe ac+aG (selehon a +) ( Solution #2)3. Minimization (3 x Sp each = 15p) (a) Draw the truth table for the Boolean function f(x, y,z)=xZ+x(z+y) BtyY ® (2+) x y2| xz| + Ovo\| ot \ \ | gol|oy}t | | I ao'\0)\o}r 0 oO oO o1!l|ol. \ ( l foe.)hUhUl \ 0 \ EO: 0lo I 0 0 (®t) tlolo O \ rilpojg|4 0 oO (b) Draw the K-map for this function and derive the minimum cost POS expression. uu 7 2\_22_ 21 o| \ c ft fe (xt Fez) (x42) (c) Draw the circuit diagram for the minimum cost POS expression. K a t+ _) > (xtF¥+2z) [—) >4, Number Conversions (5 x 4p each = 20p) (a) Convert 2435 to decimal Lx 54 Ux 5 4 BxS% UXLTt YxS 43x ae OS = 4340 (b) Convert 19339 to binary Ats3)/ 2p= 1G 4 96/2 = 48 O 48/2 = 24 0 24/2 = 12 0 42/2- 6 O 44000004, 6/z= 3 0 3/22 464 igeeee On et 4 (©) Convert DC5By6¢ to binary 1104 1440004044014, Whe be OO ES Dd ie 5S & (d) Find the value of the base x in the following equation: 12x = 10112 wa de Xe 2exs 14, 9 the soyry | ¥+ 25 44 — (¢) Compute the following sum and write the answer in octal: e dang 11010012 + 81i1¢ 2s > a bo palling £0 Bina © Ott oAlo04 + G1 0100 DiD04 = ae a ; pe eee ) convert 4 5 4,¢+2 © 45 = B52, te Ata5. Verilog to Cireuit (2 x Sp each = 10p) (a) Draw the circuit diagram that corresponds to the Verilog module shown below. Label all inputs and outputs. module mystery (A, B, C, D, F); input A, B, C, Ds output F; assign F = (A & B) | (~B & C)| D; endmodule (b) Redraw the circuit from (a) using only NAND gates. 5k D6. Circuit to Circuit Conversion (3 x Sp each = 15p) (a) Write the expression for the function F given by this circuit (don't simplify it yet). Ps eeasoaa |) e % [pf Fs RY + K+ x7 Db D 7 (b) Use the theorems of Boolean algebra to simplify the expression from part (a). > oe ff he ( De Morgan's ) = Kt + KAY (repeeted & ) a = ete Ye xv (feo ¥) = K+ (44+x)7 ( Theorem 5) uo — _ a a xty (De Morgan's ) ao (©) Draw the circuit for your expression from part (b). Label all inputs and outputs. alalais simp i fes bo a MAWD, ‘—De7. Derive the minimum SOP expression using a K-map (3 x 5p each = 15p) (a) Draw the K-map for the following function F(a,b,c,d)=Zm(1, 3, 8, 9, 10, 12, 14, 15) + D(2, 4, 5, 11) a6 \ ‘ _ eg\ 22 et Oe ad of | d éd i \ i (b) Use the K-map to derive the minimum-cost SOP expression for the function F. Ss ade 6d+ ac (©) Draw the circuit diagram for the minimum expression from part (b). ao 6 Cd ry8. NAND/NOR Logic (2 x Sp Op) (a) Using onl sates, dri ¢ logic circuit that corresponds to the truth table shown below. Hint: Start by writing and then modifying the expression for F. XY(FO a SO > <—RY Fe xy¥t+xy=s XY t KY 2 KY OXY “xy x x oD =) (b) Draw the circuit that corresponds to the following K-map using only NOR gates. > {9. Joint Optimization (3 x Sp each = 1Sp) The outputs f and g of a two-output circuit are specified with the following expressions: f(a, b,c, d) = Em(1, 4, 5, 8, 15) + D(O, 2, 6, 9) (a, b, ¢, d) =EZm(0, 4, 5, 10, 15) + D(2, 8, 9, 11) (a) Draw the K-map for f and the K-map for 6 eb op! _at 6= alg esi 1 (b) Derive the jointly optimized SOP expressions for f and g such that the two expressions share two implicants. Note that these are not necessarily prime implicants. 4- a6o+ abed t OE 5° GbE. abed t Bd (©) Draw the diagram for the jointly optimized circuit. Indicate which logic gates are shared by drawing arrows that point to them. Label all inputs and outputs. Oo & c d Gee oe10. Minimization with Theorems (15p) Use the theorems of Boolean algebra to simplify the following Boolean function £0, Xp y, Z=Y(V + 2) + (+ wy (xz + xz))z+ (xy + x Fy) +z) + y(ztWx( WZ) oY ~~ & 8 Se > Simplify A,B,C, and D separate and they Ou bine te portek rese Gls, he y (Y+2z)2 y¥t ye = v2 = Be (Frwy (x2 + x))2 = J2+ wy (x (2+2))a > a STR t WYK! = Ya (44 wx) = Ya u~~—" a Co xFs Ke = xv e RTE = ORIHE “4 Fe At BtCED = yet Yer Yar v2 (1% repeated 3 bmas) ye+y2 =. (+92 TZ »Question ‘Max | Score 1 True/False 10 2. Three-variable K-map | __ 5 3. Minimization 15. 4, Number Conversions | 20 5. Verilog to Circuit 6. Circuit to Cireuit 7. SOP with K-Map 8. NANDINOR Logic 10 9. Joint Optimization [| 15| 10. Minimization 15 TOTAL: 130)