Fig. 11.10.1 Code generation from DAG Let us understand how effective it is to generate code using DAG instead of ies three address code sequence: Rearranging Order ‘The order of three address code affects the cost of the object code being generated, jn the sense that by changing the order in which computations are done we can obtain . object code with minimum cost. For example > tysatb tyacd tenet, teat+ts For the expression (a+b)+(e+(c-d)) A DAG can be constructed for the above sequence as followsFig. 11.10.1 Code generation from DAG Let us understand how effective it is to generate code using DAG instead of ies three address code sequence: Rearranging Order ‘The order of three address code affects the cost of the object code being generated, jn the sense that by changing the order in which computations are done we can obtain . object code with minimum cost. For example > tysatb tyacd tenet, teat+ts For the expression (a+b)+(e+(c-d)) A DAG can be constructed for the above sequence as followspa Heuristic Ordering ‘The heuristic ordering algorithm is as follows. 1) Obtain all the interior nodes. Consider these interior nodes as unlisted interior 2) while( unlisted interior nodes remain) f ) pitk up,gn unlisted node n,whose parents have been listed list ny 5) while(the leftmost child m of n { 6) list m; 7) n=m; } has no unlisted parent AND is not leaf | First we will draw a DAG for some given expression. A lapis te Geet ontCompiter Design a Consider « DAG ax shown in the FIs: 11.10.2. Fig. 11.10.3 DAG The DAG is first numbered from top to bottom and from left to right. Then consider the unlisted interior nodes 1 234568. Initially the only node with unlisted parent is 1 <. set n=1 by line 4) of algorithm Rg aN eigamment’of7 is andl parent of 2 te 1 whic is Wed. Hence tse 2 “set n=2 by line 7) of algorithm 4234568 Now we will find the leftmost node of 2 and that is 6. But 6 has unlisted parent 5 Hence we can not select 6. We therefore can switch to 3. The parent of n=3 Pesta 56S, The left of 3 is 4. As parent of 4 is 3 and that is listed hence list 4. Left of 4 is 5 which has listed parent(i.e. 4) hence list 5. Similarly list 6 42S £5) 6 8 ‘As now only 8 is remaining from the unlisted interior nodes we will list it, Hence the resulting list is 1 2 3 4 5 6 8. Then the order of computation is decided by reversing this list. We get the order of evaluation as 8 6 5 4 3 2 1.That also means that we have to perform the computations at these nodes in the given order 3 is 1 which is listed one. Hence list 3 set TECHNICAL PUBLICATIONS” An up thrust for knowledgeallocates the continuous block of “ “a records or other data object This ate when js ivi activation ends. This deallocated located cuted manager agement can be done by (tree) space can be f peop me list for the free blocks and when er memory is appended in the linked he Memory is deallocated most suitable block of memory from the Ji a for allocation of block. inked list. 12. use best between Static, Stack and Heap Allocation _ In stack allocation, stack is_ used to manage runtime mate: memory allocation. _ Data structures and data Data structures and data objects can be created objects can be created dynamically. = __ dynamically.Compiler Design 11-92 is called global register allocation. A Oa, allocation of variables to specific registers that is consistent across the block Following are the strategies adopted while doing the global register a} * The global register allocation has @ strategy of storing the most 4.8 variables in fixed registers throughout the loop. recventy ty * Another strategy is to assign some fixed number of global tegistors most active values in each inner loop. "© hog te * The registers not already allocated may be used to hold values local 10 tne * In certain languages like C or Bliss programmer can do the "he using register declaration. Enz Usage Count The usage count is the count for the use of some variable x in some any basic block, The usage count gives the idea about how Many units of ‘hed iy Saved by selecting a specific variable for global register allocation. Thy, mt b formula for usage count for the Loop L. in some basic block B can be given ‘ SY (use(x,B) + 2* live(X,B)) blockBin L where use(x,B) is number of times x used in block B Prior to any definition live(x,B) =1 is x is live on exit from B; otherwise live(x)=0. tray For example : Fig. 11.7.4 Consider a block B1, B2, B3, B4 and count the usage count for block B in fllowsg loop L ‘The usage count for block B1 for variable a is 0 ee19-13 1) = 0 818 defined in BL bef A fore use, po i . ee ais live on exit of BI hence I (use(@.B1) + 2" live(aby) = 9 ive(a,B1)=1 count for block B2 and 183 F 3 for vari reg) = usela,B2) = 1 ete et “sais used in B 1 ai ) = P*live(a,B2) = 0 wnt Pa before definion @ is not live on exit of BI and B2 > use(a,B) = i Bint A use(a,B) +2 ‘live - > ve(ab) = 242 = 4 the usage count of a is 4. That means i sa rginsnncton 8 compiler can save 4 units of cost by Register Assignment for Outer Loop ger that there are two loops LI is outer 100} : : yp and L2 is an inner loop. And ‘on of variable a is to be done to some register. The approximate ats is as a Loop L1 Fig. 11.7.2 Nested loops following criteria should be adopted for register assignment for outer loop 1) Ifais allocated in loop L2 then it should not be alocated in Ll - 2. 2) If a is allocated in in L1 and it is not allocated in L2 then store a on a entrance to L2 and load a while leaving L2. 3) Ifa is allocated in L2 and not in L1 then load a on entrance of L2 and store aon exite from L2. > aaCode 11-14 Compiler Design Register Ass! ignment Graph Coloring for 1 is allocated for it. Thus we go on allocag, ing As we encounter the variable, the registe . But a time may come when a re it. But register 5 vid that we visi the registers for the variables pied. In such a situation we May sded for computation but all the registers are oct) nee r computal free for reusability. Again from the heap of allocated need to make some registers : registers which register is can be freed 1s a big question. To solve this problem a graph coloring technique is used. The graph coloring, works in two passes: ‘The working is as given below instruction i8 selected for register allocation, 1. In the first pass the specific machine For each variable a symbolic register is allocated. In the second pass the register inference graph is prepared. In register inference graph each node is a symbol an edge connects two nodes where ic registers and one is live at a point where other is defined. nique is applied for this register inference graph usin, assumed to be number of assignable registers. In gra ' odes can have same color. Hence in mae ing principle each node (actually a Variable) that no two symbolic registers can interfere n Then a graph coloring tec! k-color. The k-colors can be coloring technique no two adjacent n\ inference graph using such graph colo is assigned the symbolic registers so with each other with assigned physical registers. y Simple Code Generation Algorithm aa In this section we will discuss the method of generating target code from three address statement. « In this method computed results can be kept in registers as long as possible. For example xe aab; : : The corresponding target code is ADEE Here R; holds value of a Here cost =2 OR POY dspace, A ie Bodo valve of » PR Sa Here cost =2 * The code generator algori gorithm use: i and addresses for names. s descriptors to keep track of register contents 1. A register descriptor i iptor is used to keep tr wh ¥ : p track of what is curr is i © register descriptors show that initially all the registers a ee oo . As the leCode 11-14 Compiler Design Register Ass! ignment Graph Coloring for 1 is allocated for it. Thus we go on allocag, ing As we encounter the variable, the registe . But a time may come when a re it. But register 5 vid that we visi the registers for the variables pied. In such a situation we May sded for computation but all the registers are oct) nee r computal free for reusability. Again from the heap of allocated need to make some registers : registers which register is can be freed 1s a big question. To solve this problem a graph coloring technique is used. The graph coloring, works in two passes: ‘The working is as given below instruction i8 selected for register allocation, 1. In the first pass the specific machine For each variable a symbolic register is allocated. In the second pass the register inference graph is prepared. In register inference graph each node is a symbol an edge connects two nodes where ic registers and one is live at a point where other is defined. nique is applied for this register inference graph usin, assumed to be number of assignable registers. In gra ' odes can have same color. Hence in mae ing principle each node (actually a Variable) that no two symbolic registers can interfere n Then a graph coloring tec! k-color. The k-colors can be coloring technique no two adjacent n\ inference graph using such graph colo is assigned the symbolic registers so with each other with assigned physical registers. y Simple Code Generation Algorithm aa In this section we will discuss the method of generating target code from three address statement. « In this method computed results can be kept in registers as long as possible. For example xe aab; : : The corresponding target code is ADEE Here R; holds value of a Here cost =2 OR POY dspace, A ie Bodo valve of » PR Sa Here cost =2 * The code generator algori gorithm use: i and addresses for names. s descriptors to keep track of register contents 1. A register descriptor i iptor is used to keep tr wh ¥ : p track of what is curr is i © register descriptors show that initially all the registers a ee oo . As the le11-15 ot tion for the block progresses ts es, ses generation fc 8 the registers. will hold the values of ress descripto add iptor stores the location where the current value of the name can 4 ‘ : pe found at run time. The information ab. | fable and is used to access the variables A 1h Hoe Re a aa ‘qhe modes of operand addressabilit - " ty are as given bel | gi used to indicate value of operand in amt thas! Ris used to indicate value of operand in register. Code Generation Addrossin Attributes: 0 Storage mode Location / Register Fig. 11.8.1 Address descriptor | js indicates that the address of operand is stored in storage i.e. indirect accessing. IR indicates that the address of operand is stored in register ie. indirect accessing. The address descriptor has following fields. The attributes mean type of the operand. It generally refers to the name of temporary variables. The addressing mode indicates whether the addresses are of type *S1/R,1S'/IR’- The third field is location field which indicates whether the address is in storage location or in register. « Similarly the register descriptor can be shown as below. Operand ‘Status descriptors ee Fig. 11.8.2 Register descriptor By using register descriptors we can keep track of the registers which are currently occupied. The status field is of Boolean type which is used to check whether the register is occupied with some data or not. When the status field holds the value ‘True’ then operand descriptors fields contains the pointer to the operand descriptor who is having the latest value in the register. EE11-15 ot tion for the block progresses ts es, ses generation fc 8 the registers. will hold the values of ress descripto add iptor stores the location where the current value of the name can 4 ‘ : pe found at run time. The information ab. | fable and is used to access the variables A 1h Hoe Re a aa ‘qhe modes of operand addressabilit - " ty are as given bel | gi used to indicate value of operand in amt thas! Ris used to indicate value of operand in register. Code Generation Addrossin Attributes: 0 Storage mode Location / Register Fig. 11.8.1 Address descriptor | js indicates that the address of operand is stored in storage i.e. indirect accessing. IR indicates that the address of operand is stored in register ie. indirect accessing. The address descriptor has following fields. The attributes mean type of the operand. It generally refers to the name of temporary variables. The addressing mode indicates whether the addresses are of type *S1/R,1S'/IR’- The third field is location field which indicates whether the address is in storage location or in register. « Similarly the register descriptor can be shown as below. Operand ‘Status descriptors ee Fig. 11.8.2 Register descriptor By using register descriptors we can keep track of the registers which are currently occupied. The status field is of Boolean type which is used to check whether the register is occupied with some data or not. When the status field holds the value ‘True’ then operand descriptors fields contains the pointer to the operand descriptor who is having the latest value in the register. EE17-16 Compter Desion oration using wg oeTReES wn of Operator OPS rand and operand? and ger ol neNeTAte Algorithm for code gene pression algorithm Read the ex in the form code using following ee weed addresamode = ‘R) it (operator = ‘+ fh Q to‘ADD eer JRO"): else iffopera' omen SUB operand2,R0": eise if(operator = '*") “Generate MUL operand2. RO"); else ee ='f) tato('DIV operand2,RO') mode = ‘R’) ) } else if we oe if (operator = +) Generate(‘ADD n pameaat RO’); else if(operator = ‘~') Generate(‘SUB operand1,RO0'); else if(operator = “*" Generate(' s else iffoperator = '/') F Generate(‘DIV operand1,R0"); ) MUL operand RO"); else Generate(‘MOV operand2,RO0); if (operator = '+') Generate(‘ADD operand2,R0'); else iffoperator = ‘-’) Generate(‘SUB operand2,RO'); else if(operator = ‘*") Generate(‘MUL operand2,RO'); else if(operator = ‘/') Generate('DIV operand2,R0'); a Example We will generate code for following expression x := (a + b)*(c~d) + (/f) « (a +b)) The corresponding three address code can be given aseae coe Generation thm the sequence target code can be ots the simple code generation algort as sence using cade generrion agar JO" THe DoE ression Generate the code seq expression w:=(A-Br(A-9+A-9 3 address code for given exp! solution : We will write the t):=A-B tp:=A-C tg:etitte {n= 3 to ; ~ -eanais. An up trust for knowledgeeae coe Generation thm the sequence target code can be ots the simple code generation algort as sence using cade generrion agar JO" THe DoE ression Generate the code seq expression w:=(A-Br(A-9+A-9 3 address code for given exp! solution : We will write the t):=A-B tp:=A-C tg:etitte {n= 3 to ; ~ -eanais. An up trust for knowledgeMOV CCR), . Fig. 11.9.1 P Le te tor i Let us understand the code generator genera r concept with the help of example.