6 Future ARM TrustZone&Secure Element
6 Future ARM TrustZone&Secure Element
TRUSTZONE &
SECURE
ELEMENT
Secure Block
TPM
External Flash Internal Flash MCU / MPU
Flash Flash MCU / MPU
MCU / MPU / MPU
Secure Block
FPGA Firewall
MCU / MPU / Trustzone
FPGA QSPI /
Flash External Secure
Flash Flash
OSPI
Element MCU / MPU
Very Low attack level Low attack level (not Low level of SW attacks TPM
Trustzone
connected, not easily
reachable)
High level of physical
Secure attacks
Element
Higher Cost
TPM use cases
Full security companion (TCG
use cases)
Gateway
Network Equipment
Secure Element
Communication use cases
1 USD Complex Authentication (TLS)
Identity
Certificate / Key Store Communication Devices
Simple Gateway
Authenticator
Simple use case optional
Authentication
Identity accessories
Lower Cost
Simple use cases & Complex use cases &
limited Memory Size CONFIDENTIAL AND PROPRIETARY
Big Memory Size 4
SECURE ELEMENT TYPICAL ARCHITECTURE
communication
provisioning
(Private) Cloud
/ Internet
provisioning HSM
Manufacturing / Assembly
Device
provisioning
(Private) Cloud
/ Internet SE provisioning
Component
delivery
List of
Manufactured Component
devices assembly
ID
Manufacturing / Assembly
Device
Your
Device
▪ Pro ▪ Cons
▪ Provisioning options ▪ Memory limitation
▪ ARM Technology
▪ Available on Cortex-A and Cortex-M23 / 33 / 35 / 55
▪ Optional ARM Feature : not all Cortex A or M xx have Trustzone enabled.
▪ Concept are the same on MCU & MPU but SW implementation is different.
▪ Separate execution of
Non-Secure (NS) and
Secure code.
▪ Interrupts can be
executed from Secure or
NS.
▪ TrustZone can be
propagated into internal
peripherals and memories
to give access to only
Secure world to some Cortex M4 / M7
registers or memory area.
CONFIDENTIAL AND PROPRIETARY 11
RAM ISOLATION
▪ https://tf-m-user-guide.trustedfirmware.org/index.html
CONFIDENTIAL AND PROPRIETARY 13
TRUSTZONE ON CORTEX-M
Development in NS
looks like a different
OS is running only in
Function table to communicate OS.
NS world
between NS & Secure World. Not Most of the time
possible to call directly any Secure separate binary.
function. CONFIDENTIAL AND PROPRIETARY 14
MBEDTLS WITH TFM
PSA API
mbedTLS Mbed Crypto
UDP/TCP/IP Stack
Secure Storage Drivers
Connectivity driver
AES / PKA
Accelerator
OS NS
▪ OP-TEE is an implementation of
a secure monitor for Cortex A.
▪ Pro ▪ Cons
▪ Good SW Isolation between Secure & ▪ Trustzone is an enabler, depends on
non-Secure vendor implementation
▪ Same API for all vendor ▪ Ramp up effort and debugging more
complex
▪ Data flow stays in MCU/MPU
Optiga Authenticate S Optiga Trust Charge Optiga Authenticate ECC204 / 206 SHA10x
Optiga Authenticate I2C, SWI, 64 bytes,
I2C/SWI/GPO I2C NFC 384 bytes,
ON powered by SWI option
125 / 256 / 625 bytes 10 kB I2C powered by SWI option
SWI HW Protection (JIL)
EAL6+ EAL6+ 8kB RNG
powered by SWI option ECC-256 sign
ECC 163 / 193 ECC P256 NFC field pin Symmetric authentication
256 bytes SHA 256
up to 120°C SHA-2 ECC NIST P256 using SHA 256
ECC 163 RNG
RNG AES 128 Several Packages for non
MAC Several Packages for non
Qi Certificate Chain electronics devices
500µA max electronics devices
130 nA sleep SHA106: SWI, 2 pins, 200
ECC206: 2 pin package nA sleep
Qi Certificate Chain SHA105: I2C
SHA104: SWI, 3 pins,
Signature only 130nA
MbedTLS OpenSSL
CCC
Qi 1.3
Optiga TPM SLB9672 Optiga TPM AT97SC3205 SW TPM ST33GTPMA ST33TPHF2X ST33KTPM2X
FW16 SLI/SLM9670 FW13.11 SPI / I2C / LPC Software TPM AEC-Q100 SPI / I2C SPI / I2C
50 kB AEC-Q100 FIPS 140-2 emulating TCG SPI / I2C EAL4+ / FIPS140-2 level 3 EAL4+ / FIPS140-3*
SPI 50 kB 2kB interface EAL4+ / FIPS140-2 level 3 TCG 2.0 rev 1.38 TCG 2.0 rev 1.59
EAL4+ / FIPS140-2 level 3 SPI TCG 1.2 TCG 2.0 rev 1.38 ECC P256/384 ECC P256/384
TCG 2.0 rev 1.59 EAL4+ / FIPS140-2 level 3 RSA ECC P256/384 ECC BN256 ECC BN256
ECC P256/384 TCG 2.0 rev 1.38 AES ECC BN256 RSA 1024/2048/3072 RSA 1024/2048/3072/4096
ECC BN256 ECC P256/384 SHA RSA 1024/2048/3072 AES 128/192/256 AES 128/192/256
RSA 1024/2048/3072/4096 ECC BN256 RNG AES 128/192/256 TDES 192 SHA 1/256/384
AES 128/192/256 RSA 1024/2048 TDES 192 SHA 1/256/384 3x EK / EK Certificates
SHA2-384 SHA1/256 SHA 1/256/384 3x EK / EK Certificates
FPGA TPM
4x EK / EK Certificates RNG 3x EK / EK Certificates
PQC
RNG
Post Quantum FW Update
MCXN
SESIP/PSA L3
ES
Basic STM32U0 LPC55S36 STM32U585 RA8 STM32N6
PSA L1 / SESIP L3* PSA/SESIP L3 SESIP/PSA L3 PSA L2+SE
Physical STM32WBA RW610 ES
Attacks SESIP/PSA L3 STM32L4 STM32L5 STM32H573 PSOC EDGE
SESIP/PSA L3 PSA L1 / SESIP L3* PSA L1 / SESIP L3 SESIP/PSA L3
Apollo 5 SAML11 PIC32CM PIC32CK PIC32CZ i.MX RT1180
Advanced PSA L2 HSM HSM SESIP/PSA L2
HSM
Logical
Attacks LPC55S1 PSoC 64S
SESIP/PSA L2 PSA L2
KW45
STM32L4+ i.MX RT
Logical STM32G4 SESIP/PSA L1 PSA L1
Attacks Apollo 4 PSA L1 RA6Mx STM32H7
PSA L1 SESIP L1
LPC55S0 PSA L1
RSL15 SESIP/PSA L1 PSoC 64Bx
PSA L1 PSA L1
STM32G0
PSA L1
DA16xxx
PSA L1
Feature Set
ES: Engineering Sample * Only secure boot CONFIDENTIAL AND PROPRIETARY 27
MPU WITH SECURITY FOR MASS MARKET
PCI / PSA / SESIP Processors
SAMA5D29 STM32MP135 STM32MP2 i.MX95
AECQ-100 Grade 2
SiP with Secure Element : TA100 SESIP L3 PSA L1 UNDER NDA SESIP/PSA L3* FIPS 140-3 L2***
Symetric crypto with SCA EDGELock Enclave
Basic ECC / RSA with SCA
RNG
V2X Accelerator
Physical Trustzone
Secure boot / encrypted
Attacks Tamper pin
Unique ID
Resistant Voltage/Temp/Frequency detection
QSPI decryption
RAM enc. /dec.
Secure storage with HUK
Feature Set
CONFIDENTIAL AND PROPRIETARY 28
(*) target, not certified (**) pre-certified (***) FIPS: iMX93 only FIPS 140-3 Level 2: Evidence of the physical attack (no resistance)
ANY QUESTION ?