US 2013 0200327A1

(19) United States

(12) Patent Application Publication (10) Pub. No.: US 2013/0200327 A1
WANG et al. (43) Pub. Date: Aug. 8, 2013
(54) RESISTIVE MEMORY ARRANGEMENT AND Publication Classification
A METHOD OF FORMING THE SAME
(51) Int. Cl.
(71) Applicant: Agency for Science, Technology and HOIL 45/00 (2006.01)
Research, Singapore (SG) (52) U.S. Cl.
CPC ................ HOIL 45/04 (2013.01); HOIL 45/16
(72) Inventors: Xinpeng WANG. Singapore (SG); (2013.01); Y10S 977/943 (2013.01); Y10S
Xiang LI. Singapore (SG); Navab 977/762 (2013.01); B82Y 10/00 (2013.01)
SINGH, Singapore (SG); Guo-Qiang USPC 257/4; 438/382; 977/943; 977/762; 977/840
Patrick LO, Singapore (SG)
(57) ABSTRACT
(73) Assignee: AGENCY FOR SCIENCE,
TECHNOLOGY AND RESEARCH, According to embodiments of the present invention, a resis
Singapore (SG) tive memory arrangement is provided. The resistive memory
arrangement includes a nanowire, and a resistive memory cell
(21) Appl. No.: 13/745,993 including a resistive layer including a resistive changing
material, wherein at least a section of the resistive layer is
(22) Filed: Jan. 21, 2013 arranged covering at least a portion of a Surface of the nanow
ire, and a conductive layer arranged on at least a part of the
(30) Foreign Application Priority Data resistive layer. According to further embodiments of the
present invention, a method of forming a resistive memory
Jan. 20, 2012 (SG) ............................... 2012OO484-2 arrangement is also provided.

250
R

Form a resistive layer including a resistive changing

material, wherein at least a section of the resistive layer is 254
arranged covering at least a portion of a Surface of the
nanowire

Form a conductive layer on at least a part of the resistive 256

layer
Patent Application Publication Aug. 8, 2013 Sheet 1 of 10 US 2013/0200327 A1

104b.

106a 106b

116

FIG 1B
Patent Application Publication Aug. 8, 2013 Sheet 2 of 10 US 2013/0200327 A1

138a 138b.

FIG. 1C

150

13 la m 13 1C 153
{ 151
FIG D
N N
S-N-152

157 Resistive layer 155

BE 156

FIG 1E
Patent Application Publication Aug. 8, 2013 Sheet 3 of 10 US 2013/0200327 A1

202 208 2O3

site/ Conductive layer

FIG. 2A

220 222 226 221

Resistive memory arrangement A ce. A

Plurality of resistive memory cells Plurality of nanowires
204.206
y Plurality of conductive lines

FIG. 2B

250

Form a nanowirc 252

Form a resistive layer including a resistive changing

material, wherein at least a section of the resistive layer is 254
arranged covering at least a portion of a surface of the
nanowire

Form a conductive layer on at least a part of the resistive 256

layer

FIG. 2C
Patent Application Publication Aug. 8, 2013 Sheet 4 of 10 US 2013/0200327 A1

FIG. 3B

FIG. 3C

FIG. 3D
Patent Application Publication Aug. 8, 2013 Sheet 5 of 10 US 2013/0200327 A1

FIG. 4A FIG. 4B

FIG. 4C FIG. 4D
Patent Application Publication Aug. 8, 2013 Sheet 6 of 10 US 2013/0200327 A1

FIG. 5A

FIG. 5B

N
|

Š
||
FIG. 5C
Patent Application Publication Aug. 8, 2013 Sheet 7 of 10 US 2013/0200327 A1

FIG. 6A FIG. 6B

718 700
716 R 71.4

Buried Oxide 706 Buried Oxide

from top from bottom

FIG. 7A FIG 7B
Patent Application Publication Aug. 8, 2013 Sheet 8 of 10 US 2013/0200327 A1

R y
818 810 808 718
716 708 714 710 830 832

804
806 Buried Oxide 706 Buried Oxide

Logic part Memory part

FIG. 8
Patent Application Publication Aug. 8, 2013 Sheet 9 of 10 US 2013/0200327 A1

FIG. 9C

972 964 -- r 971

Buried Oxide
E-E cross sectional view top view
Patent Application Publication Aug. 8, 2013 Sheet 10 of 10 US 2013/0200327 A1

1000

1002
R 1004

1200

R 1116
1114
1112 u/
N-1NE

FIG 10
US 2013/0200327 A1 Aug. 8, 2013

RESISTIVE MEMORY ARRANGEMENT AND 131a sandwiched between the bit line, BL, 136a and the
A METHOD OF FORMING THE SAME word line, WL, 138a, a second one bit cell arrangement
CROSS-REFERENCE TO RELATED
131b sandwiched between the bit line, BL, 136b and the
APPLICATION
word line, WL, 138a, a third one bit cell arrangement 131c
sandwiched between the bit line, BL 136a and the word line,
0001. This application claims the benefit of priority of WL, 138b, and a fourth one bit cell arrangement 131d
Singapore patent application No. 201200484-2, filed 20 Jan. sandwiched between the bit line, BL, 136b and the word
2012, the content of which is hereby incorporated by refer line, WL, 138b. As a non-limiting example, the third bit
ence in its entirety for all purposes. cell arrangement 131c includes the RRAM 132c electrically
coupled to the diode 133c, where the diode 133c is arranged
TECHNICAL FIELD or formed over or on top of the RRAM 132c, vertically,
0002 Various embodiments relate to a resistive memory between BL 136a and WL. 138b. FIG. 1D shows a sche
arrangement and a method of forming the resistive memory matic top view of the 1D-1R memory structure 130 of FIG.
arrangement. 1C, illustrating a period or pitch of 2F (F refers to the mini
mum feature size) between adjacent one bit cell arrangements
BACKGROUND (e.g. between the first one bit cell arrangement 131a and the
third one bit cell arrangement 131c), thereby realizing a cell
0003. As the physical limitation of scaling NAND flash arrangement size of 4F footprint.
memory is being reached in the near future, several classes of
materials which demonstrate bi-stable resistances have been 0008 FIG.1E shows a schematic cross sectional view of a
studied for high density non-volatile memory (NVM) appli 1D-1R memory cell arrangement 150. The memory cell
cations for the next generation. Among them, transition arrangement 150 includes a stack arrangement of a p-doped
metal-oxide (TMO) based resistive random access memory layer (P-type) 151 and an n-doped layer (N-type) 152, which
(RRAM) cells attract lots of attention owing to their fast collectively form a diode 153, which may be equivalent to the
Switching, excellent reliability (retention & endurance), good diode 133 of FIG. 1C. The memory cell arrangement 150
scalability and CMOS (complementary metal-oxide-semi further includes a top electrode (TE) 154, a resistive layer 155
conductor) compatibility. Therefore, RRAM is a promising and a bottom electrode (BE) 156, which collectively form a
candidate for high density NVM. RRAM cell 157, which may be equivalent to the RRAM 132
of FIG. 1C.
0004 FIG. 1A shows a schematic perspective view of a
generalized 2x2 array cross-bar memory structure 100, 0009 Considering the fabrication technology for the tra
wherein one bit cell arrangement (e.g. as represented by the ditional transistor, stacked 1T-1R (RRAM) structures for high
dotted rectangle 101) of the array 100 consists of a RRAM density applications are not very suitable due to their high
cell (1R) only, sandwiched between the conductive word lines temperature processes, which make it difficult to form three
(WL) and bit lines (BL). For example, the array 100 includes dimensional (3-D) multi-stacks, and large unit cell sizes,
a RRAM 102a, of the bit cell 101, sandwiched between the bit which is determined by the transistor.
line, BL 104a and the word line, WL. 106a, and a RRAM 0010. Therefore, the vertical cross-bar architecture has
102b sandwiched between the bit line, BL, 104b and the attracted a lot of interest for high density 3-dimensional (3D)
word line, WL. 106b. integration, with RRAM cells (and diodes) sandwiched
0005. In order to eliminate the cross-talk interference from between the word and bit lines, realizing a cell arrangement
neighbouring RRAM cells in an array structure and to avoid
the read error effect, a selector (or rectifying element), imple size of 4F (Frefers to the minimum feature size) footprint, as
mented either by 1 D (diode) or by 1T (transistor), is required illustrated in FIGS. 1C and 1D. Furthermore, the vertical
in each cell. 1D-1R cross-bar architecture may have a 4F/n footprint,
0006 FIG. 1B shows a schematic of a generalized 3x3 where n is the number of stacked layers. Nevertheless, the
array 1T-1R (a transistoranda RRAM cell) memory structure requirements for the diode selector, including high forward
110. For a 1T-1R memory configuration, each cell arrange current density, high on/off current ratio, low processing tem
ment 111 includes a RRAM 112 electrically coupled with a perature and high CMOS compatibility, have been found to be
transistor 113. The transistor 113 includes a first source? drain very difficult to be met simultaneously in the vertical 1D-1R
terminal 114, which may be electrically coupled to a terminal architecture. For example, the diode stack (material) is not
of the RRAM 112, a second source? drain terminal 115 and a CMOS friendly. Furthermore, the current (density or area)
needs to be increased for the diode to meet the RRAM switch
gate terminal 116. As shown in FIG. 1B for the memory ing requirements. In addition, the current through the diode
structure 110, as a non-limiting example, the one bit cell may not be big enough to trigger the RRAM Switching with
arrangement (e.g. as represented by the dotted circle 111a) size scaling.
includes the RRAM 112a electrically coupled to the transis
tor 113a, where the cell arrangement 111a is electrically 0011. In addition, as illustrated in FIG. 1C, the RRAM
coupled between the bit line, BL2, 117 and the source line, (1R) (e.g. 132c) and the diode (1D) (e.g. 133c) are stacked
SL2, 118. The gate terminal of the transistor 113a is electri vertically in between WL (e.g. 138b) and BL (e.g. 136a) in the
cally coupled to the word line, WL2, 119. conventional 1D-1R cross-bar architecture. Moreover, the
0007 FIG. 1C shows a schematic of a generalized 2x2 critical dimensions for both the RRAM and the diode are
array 1D-1R memory structure 130 having a cross-bar archi exactly the same, which means that the size of the diode has
tecture. For a 1D-1R memory configuration, each cell to scale together with that of the RRAM cell. This means that
arrangement 131 includes a RRAM 132 electrically coupled as the size of the RRAM cell is increased or decreased, the
with a diode selector 133. As shown in FIG. 1C, the 2x2 array size of the diode needs to correspondingly increase or
memory structure 130 includes a first one bit cell arrangement decrease by the same amount.
US 2013/0200327 A1 Aug. 8, 2013

SUMMARY 0026 FIG. 3C shows a schematic perspective view of a

resistive memory arrangement, according to various embodi
0012. According to an embodiment, a resistive memory mentS.
arrangement is provided. The resistive memory arrangement 0027 FIG. 3D shows a schematic cross sectional view of
may include a nanowire, and a resistive memory cell includ the resistive memory arrangement of the embodiment of FIG.
ing a resistive layer including a resistive changing material, 3C taken along the line B-B'.
wherein at least a section of the resistive layer is arranged 0028 FIG. 4A shows a schematic top view of a resistive
covering at least a portion of a Surface of the nanowire, and a memory arrangement, according to various embodiments.
conductive layer arranged on at least a part of the resistive 0029 FIG. 4B shows a schematic cross sectional view of
layer. the resistive memory arrangement of the embodiment of FIG.
0013. According to an embodiment, a resistive memory 4A taken along the line C-C".
arrangement is provided. The resistive memory arrangement 0030 FIG. 4C shows a schematic perspective view of a
may include a plurality of nanowires, and a plurality of resis resistive memory arrangement, according to various embodi
tive memory cells, wherein each resistive memory cell of the mentS.
plurality of resistive memory cells includes a resistive layer 0031 FIG. 4D shows a schematic cross sectional view of
including a resistive changing material, wherein at least a the resistive memory arrangement of the embodiment of FIG.
section of the resistive layer is arranged covering at least a 4C taken along the line D-D'.
portion of a surface of a respective nanowire of the plurality of 0032 FIGS. 5A to 5C show schematic cross sectional
nanowires, and a conductive layer arranged on at least a part views of respective resistive memory arrangements, accord
of the resistive layer, and a plurality of conductive lines elec ing to various embodiments.
trically coupled to the plurality of nanowires and the plurality 0033 FIGS. 6A and 6B show schematic cross sectional
of resistive memory cells. views of respective resistive memory arrangements with
0014. According to an embodiment, a method of forming multi stacked resistive memory cells, according to various
a resistive memory arrangement is provided. The method may embodiments.
include forming a nanowire, forming a resistive layer includ 0034 FIGS. 7A and 7B show schematic cross sectional
ing a resistive changing material, wherein at least a section of views of respective resistive memory arrangements, accord
the resistive layer is arranged covering at least a portion of a ing to various embodiments.
Surface of the nanowire, and forming a conductive layer on at 0035 FIG. 8 shows a schematic cross sectional view of a
least a part of the resistive layer. parallel integration of a resistive memory arrangement with a
logic CMOS device, according to various embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS 0036 FIG. 9A shows a schematic perspective view of a
0015. In the drawings, like reference characters generally Vertical integration of a resistive memory arrangement with a
refer to like parts throughout the different views. The draw logic CMOS device, according to various embodiments.
ings are not necessarily to scale, emphasis instead generally 0037 FIG.9B shows a schematic perspective view of an
being placed upon illustrating the principles of the invention. array of resistive memory arrangements with logic CMOS
In the following description, various embodiments of the devices, based on the embodiment of FIG.9A.
invention are described with reference to the following draw 0038 FIG.9C shows a schematic cross sectional view of a
ings, in which: Vertical integration of a resistive memory arrangement with a
0016 FIG. 1A shows a schematic perspective view of a logic CMOS device, according to various embodiments.
generalized 2x2 array cross-bar memory structure. 0039 FIG. 10 shows a schematic cross sectional view of a
fabrication process for forming a resistive memory arrange
0017 FIG. 1B shows a schematic of a generalized 3x3 ment, according to various embodiments.
array 1T-1R memory structure.
0018 FIG. 1C shows a schematic of a generalized 2x2 DETAILED DESCRIPTION
array 1D-1R memory structure.
0019 FIG. 1D shows a schematic top view of the 1D-1R 0040. The following detailed description refers to the
memory structure of FIG. 1C. accompanying drawings that show, by way of illustration,
0020 FIG.1E shows a schematic cross sectional view of a specific details and embodiments in which the invention may
1D-1R memory cell arrangement. be practiced. These embodiments are described in sufficient
0021 FIG. 2A shows a schematic block diagram of a detail to enable those skilled in the art to practice the inven
resistive memory arrangement, according to various embodi tion. Other embodiments may be utilized and structural, logi
mentS. cal, and electrical changes may be made without departing
from the scope of the invention. The various embodiments are
0022 FIG.2B shows a schematic block diagram of a resis not necessarily mutually exclusive, as some embodiments
tive memory arrangement, according to various embodi can be combined with one or more other embodiments to
mentS. form new embodiments.
0023 FIG. 2C shows a flow chart illustrating a method of 0041 Embodiments described in the context of one of the
forming a resistive memory arrangement, according to vari methods or devices are analogously valid for the other
ous embodiments. method or device. Similarly, embodiments described in the
0024 FIG. 3A shows a schematic perspective view of a context of a method are analogously valid for a device, and
resistive memory arrangement, according to various embodi Vice versa.
mentS. 0042. Features that are described in the context of an
0.025 FIG. 3B shows a schematic cross sectional view of embodiment may correspondingly be applicable to the same
the resistive memory arrangement of the embodiment of FIG. or similar features in the other embodiments. Features that are
3A taken along the line A-A". described in the context of an embodiment may correspond
US 2013/0200327 A1 Aug. 8, 2013

ingly be applicable to the other embodiments, even if not (diode free) stack or arrangement may beformed Surrounding
explicitly described in these other embodiments. Further a vertical nanowire, laterally integrated around the Vertical
more, additions and/or combinations and/or alternatives as nanowire.
described for a feature in the context of an embodiment may 0055 An additional diode selector or extrinsic diode,
correspondingly be applicable to the same or similar feature when fabricated, may be formed adjacent to the nanowire
in the other embodiments. and/or the RRAM cell, and may surround the nanowire and
0043. In the context of various embodiments, the articles extend laterally from the side or circumference of the nanow
“a”, “an and “the as used with regard to a feature or element ire. Therefore, the RRAM cell may beformed over the diode,
includes a reference to one or more of the features or ele where both the RRAM cell and the diode extend laterally
mentS. from the side or circumference of the nanowire, at least Sub
0044. In the context of various embodiments, the phrase stantially perpendicular to a longitudinal axis of the nanow
“at least substantially” may include “exactly' and a reason ire. In other words, a 1D+1 R stack or arrangement may be
able variance. formed Surrounding a vertical nanowire, laterally integrated
0045. In the context of various embodiments, the term around the vertical nanowire.
"about as applied to a numeric value encompasses the exact 0056. The RRAM cells and the resistive memory arrange
value and a reasonable variance. ments, including 1D--1R or 1R architectures, of various
0046. As used herein, the term “and/or includes any and embodiments may be fully CMOS compatible. The RRAM
all combinations of one or more of the associated listed items. cells and the resistive memory arrangements of various
0047. As used herein, the phrase of the form of “at least embodiments may be fabricated based on the 32 nm technol
one of A or B may include A or B or both A and B. Corre ogy node and beyond.
spondingly, the phrase of the form of “at least one of A or B or 0057 The resistive memory arrangements of various
C, or including further listed items, may include any and all embodiments may be employed for all non-volatile memory
combinations of one or more of the associated listed items. (NVM) application related areas, suitable for both stand
0.048 Various embodiments relate to semiconductor alone and embedded NVMapplications, for example for data
memory devices and methods of fabricating such devices in storage related applications, requiring density and endurance,
high density. e.g. for cell-phones, tablets, for code storage related applica
tions, requiring density and Scalability, e.g. for computers,
0049 Various embodiments provide resistive random cell-phones, and for embedded NVM related applications,
access memory (RRAM) cells and/or arrangements for high requiring ease to embed, e.g. for microcontrollers, field-pro
density non-volatile memory (NVM) applications and meth grammable gate arrays (FPGAs).
ods of fabricating the RRAM cells and/or arrangements. 0058. The resistive memory arrangements of various
0050. Various embodiments may provide resistive embodiments may have a 1D+1 R or a 1R only configuration
memory arrangements having a 1R(RRAM memory cell) Surrounding a nanowire, with a small footprint, down to 4F
architecture, a 1D (diode)+1 R(RRAM memory cell) archi (F is the minimum feature size), thereby providing the highest
tecture or a 1T (transistor)+1R(RRAM memory cell) archi density. This means that various embodiments may provide
tecture. The selector (1D or 1T) may enable proper switching RRAM cell and vertical nanowire integration with a small
of the intended resistive memory cell to minimise or prevent footprint, down to 4F, which may be desirable for high
read error effect. The 1D may be a nanowire-based diode and density NVM applications.
the 1T may be a nanowire-based transistor. 0059. Different from the conventional vertical cross-bar
0051 A RRAM cell may have a metal-insulator-metal architecture, the respective areas or sizes for the RRAM cell
(M-I-M) configuration. A diode may be formed of a pnjunc (1R) and/or the selector (e.g. diode, 1D), when present, in this
tion. In various embodiments, one of the metal layers of the integration scheme, may be controlled separately and flex
M-I-M structure may be a common layer to the RRAM cell ibly, providing more space to reach the required drive current,
and the diode, meaning that the common metal layer is part of Is for RRAM Switching, so that the drive current
the diode, as either the n-doped layer or the p-doped layer of required for reversible switching may be tuned and reached
the diode. In various embodiments, a separate pnjunction of more easily. This means that there may be a balance of the
the diode may be provided to the M-I-M structure. current provided by 1D and the drive current required by 1R.
0052 Various embodiments may provide nanoelectronic In addition, various embodiments pave the way for integrat
(Nano-E), non-volatile memory (NVM) based on the integra ing the RRAM stacks having vertical nanowires of various
tion of phase change random access memory (PCRAM) and embodiments, with vertical nanowire CMOS devices, which
resistive random access memory (RRAM) cells with ultra is very desirable for embedded NVMapplications.
scaled vertical silicon (Si) nanowire devices. 0060 Various embodiments may provide a memory unit
0053 Various embodiments may provide a RRAM inte cell or arrangement having a two-terminal RRAM cell, with
gration scheme, which integrates RRAM cells on top of ver or without an extra diode selector. In various embodiments,
tical nanowires, for example a RRAM cell may be stacked on one or more memory unit cells may at least Substantially
top of a vertical nanowire. Surround a vertical nanowire, where the nanowire may be
0054 Various embodiments may provide a RRAM inte formed by a standard Vertical top-down process.
gration scheme (e.g. a lateral integration scheme), which 0061. In various embodiments, the materials for the
integrates RRAM cells around vertical nanowires, with or nanowires may include but not limited to silicon (Si), germa
without an extra selector (e.g. diode), depending on the nium (Ge) or III-V semiconductors including one or more
switching properties of the RRAM stacks. This may mean group III elements (e.g. aluminum (Al), gallium (Ga) or
that a RRAM cell may be formed surrounding a nanowire. indium (In)) and one or more group V elements (e.g. nitrogen
The RRAM cell may extend laterally from the side or periph (N), arsenic (As) or antimony (Sb)), which may therefore
eral surface or circumference of the nanowire. Therefore, 1R enable the nanowire to serve as (1) a bottom electrode for the
US 2013/0200327 A1 Aug. 8, 2013

RRAM cells, or (2) one component of an additional diode including a resistive layer 204 including a resistive changing
selector, or (3) one contact electrically connected with an material, wherein at least a section of the resistive layer 204 is
additional diode. arranged covering at least a portion of a Surface of the nanow
0062. In various embodiments where the nanowire mate ire 202, and a conductive layer (e.g. an electrode) 206
rials serve as the bottom electrode (BE) of the RRAM cell, a arranged on at least a part of the resistive layer 204. In FIG.
thin resistive layer having transition metal oxide(s), including 2A, the line represented as 207 is illustrated to show the
but not limited to hafnium oxide (H?O), titanium oxide relationship between the resistive layer 204 and the conduc
(TiO), aluminium oxide (Al2O), tantalum oxide (Ta-Os), tive layer 206, which may include electrical coupling and/or
nickel oxide (NiO, tungsten oxide (WO), with or without mechanical coupling, and the line represented as 208 is illus
dopants, may be deposited around the nanowire to serve as the trated to show the relationship between the nanowire 202 and
Switching dielectric. The resistive layer may be a single layer the resistive memory cell 203, which may include electrical
or have a multilayer structure consisted by one or more tran coupling and/or mechanical coupling.
sition metal oxides, including the materials as described 0070. In various embodiments, the nanowire 202 may be
above. part of the resistive memory cell 203.
0063 Subsequently, a metal layer or a conductive layer of (0071. In the context of various embodiments, the term
a material including but not limited to platinum (Pt), tungsten “resistive memory cell may include a memory cell of any
(W), nickel (Ni), aluminium (Al), titanium nitride (TiN). kind which may be switched between two or more states
tantalum nitride (TaN), hafnium nitride (HfN), aluminium exhibiting different resistivity values.
nitride (AIN), or tungsten nitride (WN) may be deposited and 0072. In the context of various embodiments, the resistive
patterned to serve as the top electrode (TE) of the RRAM cell. changing material may change its resistance as a result of a
0064. In various embodiments of a resistive memory change in its resistivity.
arrangement having a RRAM cell (resistive memory cell)
with an extra diode selector, the nanowire materials may serve 0073. In the context of various embodiments, the term
as one component (e.g. first part) of the diode, with the other “covering may include embodiments where the section of
component (e.g. second part) of the diode, besides also serv the resistive layer 204 may be arranged directly on or over the
ing as the bottom electrode of the RRAM cell, formed around portion of the surface of the nanowire 202 for covering the
the nanowire. The materials for the other component of the portion of the Surface, and/or may be arranged with interven
diode may include but not limited to highly doped Si, Ge, and ing layer(s) in between the section of the resistive layer 204
III-V semiconductors, or their alloys, including but not lim and the portion of the surface of the nanowire 202.
ited to nickel silicide (NiSi), titanium silicide (TiSi.), cobalt 0074. In various embodiments, the nanowire 202 may
silicide (CoSi.), nickel-platinum silicide (NiPtSi), nickel ger have a longitudinal axis, and wherein the Surface of the
manide (NiGe) and nickel-germanosilicide (NiGeSi). Subse nanowire 202 may be arranged at least Substantially parallel
quently, a thin resistive layer as described above, followed by to a plane which intersects the longitudinal axis. The Surface
a metal layer as described above may be deposited and pat may for example be an end Surface, e.g. a top end Surface.
terned to form 1 D+1 R memory unit cells. Therefore, the section of the resistive layer 204 may cover an
0065. In various embodiments, the silicide material may end surface of the nanowire 204.
be formed, for example by depositing a metal layer on a 0075. In various embodiments, the entire resistive layer
silicon (Si) nanowire, which are then subjected to a heat 204 may be arranged on the surface of the nanowire 202
treatment, for example using a rapid thermal annealing pro which is arranged at least Substantially parallel to a plane
cess, in order to form a metal silicide. which intersects the longitudinal axis. Therefore, the resistive
0066. In various embodiments of a resistive memory layer 204 may be stacked on top of the nanowire 204. In this
arrangement having a RRAM cell (resistive memory cell) context, the resistive layer 204 may have a height of between
with an extra diode selector, the nanowire materials may serve about 0.1 nm and about 2 um, for example between about 0.1
as a contact electrically connected with the diode, which may nm and about 1.5um, between about 0.1 nm and about 1 um,
be formed around the nanowires. Subsequently, a thin resis between about 0.1 nm and about 500 nm, between about 0.1
tive layer as described above, followed by a metal layer as nm and about 100 nm, between about 0.1 nm and about 10
described above may be directly deposited and patterned to nm, between about 10 nm and about 1 lum, between about 10
form 1 D+1 R memory unit cell arrangements. Optionally, nm and about 100 nm or between about 100 nm and about 1
another metal layer or conductive layer may be first formed um. It should be appreciated that the height for the resistive
before the deposition of the resistive layer and the metal layer layer 204 may be flexible.
as described above. 0076. In various embodiments, the nanowire 202 may
0067. In various embodiments, the respective sizes or have a longitudinal axis, and wherein at least a portion of the
dimensions for the RRAM cell and the diode selector, when resistive layer 204 (e.g. a portion of the section of the resistive
present, may be controlled separately and flexibly by tuning layer 204) may be arranged around the longitudinal axis and
or changing the nanowire dimension (e.g. length), and/or the at least substantially surrounding the nanowire 202. In other
contact area of the top electrode (e.g. conductive layer) and/or words, the resistive memory arrangement 200 may include a
the diode around the nanowire. nanowire 202. The resistive memory arrangement 200 further
0068. In various embodiments, any one or each RRAM includes a resistive memory cell (e.g. RRAM cell) 203, a
cell may have two Switching modes, which is either unipolar portion of which may at least substantially surround the
or bipolar. nanowire 202, where at least a portion of the resistive layer
0069 FIG. 2A shows a schematic block diagram of a 204 may be arranged around the longitudinal axis and at least
resistive memory arrangement 200, according to various substantially surrounding the nanowire 202. In various
embodiments. The resistive memory arrangement 200 embodiments, a portion of the resistive layer 204 may at least
includes a nanowire 202, and a resistive memory cell 203 substantially surround the nanowire 202 throughout the entire
US 2013/0200327 A1 Aug. 8, 2013

length of the nanowire 202. In various embodiments, the example based on pattering and etching, so as to form a
resistive layer 204 may cover an end (e.g. top end) of the nanowire monolithically integrated with the substrate.
nanowire 202. I0086. In various embodiments, the nanowire 202 may be
0077. In various embodiments, by forming or providing at doped.
least a portion of the resistive layer 204 arranged around the 0087. In the context of various embodiments, the nanow
longitudinal axis and at least Substantially Surrounding the ire 202 may include a semiconductor material, including but
nanowire 202. Such a configuration is similar to a gate all not limited to silicon (Si), germanium (Ge) and a III-V semi
around (GAA) nanowire architecture. Here, the resistive conductor. The III-V semiconductor may include one or more
layer 204 or at least the portion of the resistive layer 204 group III elements (e.g. aluminum (Al), gallium (Ga) or
arranged at least Substantially Surrounding the nanowire 202 indium (In)) and one or more group V elements (e.g. nitrogen
may be referred to as a “gate' in terms of the GAA architec (N), arsenic (As) or antimony (Sb)).
ture. 0088. In the context of various embodiments, the nanow
0078. In the context of various embodiments, the term ire 202 may include silicon. As non-limiting examples, the
'surround may mean “encircle” and/or may mean an nanowire 202 may include a silicon nanowire, a polysilicon
arrangement completely around a circumference or a perim nanowire (i.e. polycrystalline silicon nanowire) and a silicon
eter of a structure (e.g. nanowire 202). germanium nanowire. However, it should be appreciated that
0079. In various embodiments, the conductive layer 206 any silicon-based nanowires may be provided.
may be arranged confined within a boundary or height of the I0089. In various embodiments, the resistive layer 204 may
resistive layer 204. be a single layer or may include a multilayer arrangement.
0080. In various embodiments, at least a portion of the 0090. In the context of various embodiments, the resistive
conductive layer 206 may be arranged at least substantially changing material may include a transition metal oxide,
surrounding the portion of the resistive layer 204 which at including but not limited to hafnium oxide (H?O), titanium
least substantially surrounds the nanowire 202. This means oxide (TiO), aluminium oxide (Al2O), tantalum oxide
that at least a portion of the conductive layer 206 may at least (TaOs), nickel oxide (NiO) tungsten oxide (WO) or any
combination thereof.
substantially surround the nanowire 202. Here, the conduc
tive layer 206 or at least the portion of the conductive layer 0091. In the context of various embodiments, the resistive
206 arranged at least Substantially Surrounding the portion of changing material may include a dopant (i.e. doped), for
the resistive layer 204 around the nanowire 202 may also be example including but not limited to germanium (Ge), tellu
referred to as a "gate” in terms of the GAA architecture. rium (Te), antimony (Sb), silver (Ag), indium (In), chromium
0081. In various embodiments, the portion of the resistive (Cr), nitrogen (N), selenium (Se), tin (Sn), silicon (Si), bis
layer 204 may be arranged at least Substantially Surrounding muth (Bi) or any combination thereof.
a partial portion of the nanowire 202. This means that the 0092. In the context of various embodiments, the conduc
resistive layer 204 or the portion of the resistive layer 204 may tive layer 206 may include a metal, for example including but
not necessary surround the nanowire 202 throughout the not limited to platinum (Pt), tungsten (W), nickel (Ni), alu
entire length of the nanowire 202. minum (Al), a nitride alloy or any combination thereof. The
nitride alloy may include but not limited to titanium nitride
0082 In various embodiments, the resistive layer 204 and (TiN), tantalum nitride (TaN), hafnium nitride (HfN), alumi
the conductive layer 206 may be arranged at least substan num nitride (AIN), tungsten nitride (WN) or any combination
tially coplanar relative to each other. This may mean that at thereof.
least one respective Surface (e.g. atop surface and/or a bottom 0093. In the context of various embodiments, the nanow
surface) of the resistive layer 204 and the conductive layer ire 202 may have a diameter or a cross sectional dimension of
206 may be arranged in the same plane or flushed with each between about 10 nm and about 200 nm, for example between
other.
about 10 nm and about 100 nm, between about 10 nm and
0083. In various embodiments, the resistive memory about 50 nm or between about 50 nm and about 200 nm. The
arrangement 200 may exhibit a self-rectifying effect or term "cross sectional dimension' may mean a dimension of a
behaviour. This may mean that the resistive memory arrange cross section of the nanowire 202 defined along a transverse
ment 200 may behave as a diode, thereby providing an intrin axis (perpendicular to the longitudinal axis) of nanowire 202.
sic diode. In various embodiments, the resistive layer 204 and 0094. In the context of various embodiments, the nanow
the conductive layer 206 may define an intrinsic diode. In ire 202 may have a length of between about 100 nm and about
various embodiments, the resistive layer 204 and the nanow 2 um, between about 100 nm and about 1 um, between about
ire 202 may define an intrinsic diode. This may mean that a 100 nm and about 500 nm, or between about 500 nm and
separate diode or rectifying element may not be necessarily about 2 Lim.
provided for the resistive memory arrangement 200. 0095. In the context of various embodiments, the portion
0084. In the context of various embodiments, the nanow of the resistive layer 204 arranged around the longitudinal
ire 202 may serve as a conducting channel. axis and at least Substantially Surrounding the nanowire 202
0085. In the context of various embodiments, the resistive may have a height of between about 0.1 nm and about 2 um,
memory arrangement 200 may further include a substrate for example between about 0.1 nm and about 1.5um, between
from which the nanowire 202 may extend monolithically. about 0.1 nm and about 1 um, between about 0.1 nm and about
This means that the substrate and the nanowire 202 may be a 500 nm, between about 0.1 nm and about 100 nm, between
monolithic (single) structure. The nanowire 202 may extend about 0.1 nm and about 10 nm, between about 10 nm and
continuously from the substrate. The nanowire 202 may about 1 lum, between about 10 nm and about 100 nm or
extend at least Substantially perpendicular to a surface of the between about 100 nm and about 1 lum. It should be appreci
Substrate. As a non-limiting example, a Substrate may be ated that the height for the portion of the resistive layer 204 at
provided and portions of the substrate may be removed, for least substantially surrounding the nanowire 202 may be flex
US 2013/0200327 A1 Aug. 8, 2013

ible. In various embodiments, the resistive layer 204 or a ductivity type are of an n-conductivity type such that a mate
portion thereof may fully cover the nanowire 202, e.g. equal rial doped with Such doping atoms may be n-doped.
to the length of the nanowire 202. This may mean that where 0103) The term “p-doped may mean a host material that
the nanowire 202 extends from a substrate, the resistive layer is doped with doping atoms that may accept weakly-bound
204 or a portion thereof may contact the substrate directly. In outer electrons from the host material, thereby creating
various embodiments, the resistive layer 204 or a portion vacancies left behind by the electrons, known as holes. Such
thereofmay bearranged towards atop portion of the nanowire doping atoms are also generally referred to as acceptoratoms.
202, for example with a layer height of about 0.1 nm. 0104. The term “n-doped may mean a host material that
0096. In the context of various embodiments, the resistive is doped with doping atoms that may provide extra conduc
layer 204 may have a thickness of between about 3 nm and tion electrons to the host material, thereby resulting in an
about 15 nm, for example between about 3 nm and about 10 electrically conductive n-doped host material with an excess
nm, between about 3 nm and about 5 nm or between about 5 number of mobile electrons (negatively charged carriers).
nm and about 15 nm. The resistive layer 204 may be a single Such doping atoms are also generally referred to as donor
layer or may have a multilayer structure, e.g. bi-layer or atOmS.
tri-layer or more, where the multilayer structure of the resis 0105. In the context of various embodiments, where the
tive layer 204 may have a total thickness as described above. host material may be for example silicon, which is a Group IV
0097. In the context of various embodiments, the conduc element, the host material may be doped or implanted with
tive layer 206 may have a height of between about 0.1 nm and Group III doping atoms or elements, for example boron (B),
about 2 um, for example between about 0.1 nm and about 1.5 aluminium (Al) or gallium (Ga), to form a p-doped material,
um, between about 0.1 nm and about 1 um, between about 0.1 or doped or implanted with Group V doping atoms or ele
nm and about 500 nm, between about 0.1 nm and about 100 ments, for example phosphorus (P), arsenic (AS) or antimony
nm, between about 0.1 nm and about 10 nm, between about (Sb), to forman n-doped material.
10 nm and about 1 um, between about 10 nm and about 100 0106. In the context of various embodiments, doping may
nm or between about 100 nm and about 1 lum. It should be be carried out with a dopant concentration of between about
appreciated that the height for the conductive layer 206 may 1x10'7/cm to about 5x10'/cm.
be flexible. In various embodiments, the height of the con 0107. In various embodiments, the core portion may be
ductive layer 206 or a portion thereof may correspond to or at p-doped and the peripheral portion may be n-doped or the
least substantially similar to the height of the resistive layer core portion may be n-doped and the peripheral portion may
204 or a portion thereof that at least substantially surrounds be p-doped.
the nanowire 202. 0108. In various embodiments, the core portion and the
0098. In the context of various embodiments, the conduc peripheral portion of the nanowire 202 may define a diode.
tive layer 206 may have a thickness of between about 10 nm 0109. In various embodiments, the resistive memory
and about 50 nm, for example between about 10 nm and about arrangement 200 may further include a second conductive
30 nm, between about 10 nm and about 20 nm or between layer (e.g. an electrode) in between the nanowire 202 and the
about 30 nm and about 50 nm The conductive layer 206 may resistive layer 204, wherein at least a portion of the second
be a single layer or may have a multilayer structure, e.g. conductive layer may be arranged around the longitudinal
bi-layer or tri-layer or more, where the multilayer structure of axis and at least Substantially surrounding the nanowire 202.
the conductive layer 206 may have a total thickness as In various embodiments, the second conductive layer may be
described above. part of the resistive memory cell 203.
0099. In the context of various embodiments, the term 0110. In various embodiments, the resistive layer 204 and
"nanowire' may mean a nanostructure extending, for the second conductive layer may be arranged at least Substan
example in a longitudinal direction, with dimensions in the tially coplanar relative to each other. This may mean that at
order of nanometers, and may be used interchangeably with least one respective Surface (e.g. a top surface and/or a bottom
the terms "nanorod”, “nanopillar”, “nanocolumn”, “nano surface) of the resistive layer 204 and the second conductive
tube' and the likes. layer may be arranged in the same plane or flushed with each
0100. In various embodiments, the nanowire 202 may other.
include a core portion and a peripheral portion at least Sub 0111. In various embodiments, the resistive layer 204 and
stantially Surrounding the core portion, wherein the core por the second conductive layer may define an intrinsic diode.
tion may be doped with doping atoms of a first conductivity 0.112. In the context of various embodiments, the second
type, wherein the peripheral portion may be doped with dop conductive layer may include a metal, for example including
ing atoms of a second conductivity type, and wherein the but not limited to platinum (Pt), tungsten (W), nickel (Ni).
second conductivity type is different from the first conduc aluminum (Al), a nitride alloy or any combination thereof.
tivity type. The nitride alloy may include but not limited to titanium
0101. In the context of various embodiments, the core nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN),
portion may have a diameter or a cross sectional dimension of aluminum nitride (AIN), tungsten nitride (WN) or any com
between about 5 nm and about 100 nm, for example between bination thereof.
about 5 nm and about 50 nm, between about 5 nm and about 0113. In the context of various embodiments, the second
20 nm, between about 20 nm and about 100 nm, or between conductive layer may have a thickness of between about 5 nm.
about 50 nm and about 100 nm. and about 10 nm, for example between about 5 nm and about
0102. In the context of various embodiments, the doping 8 nm or between about 8 nm and about 10 nm.
atoms of the first conductivity type/the second conductivity 0114. In various embodiments, the resistive memory
type may be of a p-conductivity type such that a material arrangement 200 may further include a peripheral layer in
doped with Such doping atoms may be p-doped while the between the nanowire 202 and the resistive layer 204,
doping atoms of the second conductivity type? the first con wherein at least a portion of the peripheral layer may be
US 2013/0200327 A1 Aug. 8, 2013

arranged around the longitudinal axis and at least Substan and about 10 nm, for example between about 5 nm and about
tially surrounding the nanowire 202, wherein the nanowire 8 nm or between about 8 nm and about 10 nm.
202 may be doped with doping atoms of a first conductivity 0.125. In the context of various embodiments, the resistive
type, wherein the peripheral layer may be doped with doping memory arrangement 200 may further include a transistor
atoms of a second conductivity type, and wherein the second having a first Source? drain terminal, a second source/drain
conductivity type is different from the first conductivity type. terminal and a gate terminal, wherein the first source/drain
The first conductivity type and the second conductivity type terminal may be electrically coupled to the resistive memory
may be as described above. cell 203. In various embodiments, the nanowire 202 may be
0115. In various embodiments, the nanowire 202 may be electrically coupled to a bit line as well as also serving as a
p-doped and the peripheral layer may be n-doped or the contact to the first Source/drain terminal. The gate terminal
nanowire 202 may be n-doped and the peripheral layer may may be coupled to a word line.
be p-doped. 0.126 In the context of various embodiments, the resistive
0116. In various embodiments, the nanowire 202 and the memory arrangement 200 may further include a logic circuit
peripheral layer may define a diode. electrically coupled to the nanowire 202 and/or the resistive
0117. In the context of various embodiments, the periph memory cell 203. The logic circuit may be integrated and/or
eral layer may include a material including but not limited to embedded with the resistive memory arrangement 200, and/
silicon (Si), germanium (Ge), a III-V semiconductor and an or provided separate from the resistive memory arrangement
alloy thereof. The alloy may include but not limited nickel 200. The logic circuit may include a transistor having a first
silicide (NiSi), titanium silicide (TiSi), cobalt silicide (CoSi), Source/drain terminal, a second source/drain terminal and a
nickel-platinum silicide (NiPtSi), nickel germanide (NiGe) gate terminal.
and nickel-germanosilicide (NiGeSi). 0127. In the context of various embodiments, the term
0118. In the context of various embodiments, the periph “source/drain terminal of a transistor may refer to a source
eral layer may have a thickness of between about 2 nm and terminal or a drain terminal. As the Source terminal and the
about 10 nm, between about 2 nm and about 8 nm, between drainterminal of a transistor are generally fabricated Such that
about 2 nm and about 5 nm or between about 5 nm and about these terminals are geometrically symmetrical, these termi
10 nm. nals may be collectively referred to as source/drain terminals.
0119. In various embodiments, the resistive memory In various embodiments, a particular source? drain terminal
arrangement 200 may further include a first peripheral layer may be a “source' terminal or a "drain' terminal depending
in between the nanowire 202 and the resistive layer 204, on the voltage to be applied to that terminal. Accordingly, the
wherein at least a portion of the first peripheral layer may be terms “first source? drain terminal and 'second source? drain
arranged around the longitudinal axis and at least Substan terminal” may be interchangeable.
tially Surrounding the nanowire 202, and a second peripheral 0128. In the context of various embodiments, the term
layer in between the first peripheral layer and the resistive “coupled may include electrical coupling and/or mechanical
layer 204, wherein at least a portion of the second peripheral coupling. In the context of various embodiments, the term
layer may be arranged around the longitudinal axis and at “coupled may include a direct coupling and/or an indirect
least Substantially Surrounding the portion of the first periph coupling. For example, two devices being coupled to each
eral layer, wherein the first peripheral layer may be doped other may mean that there is a direct coupling path between
with doping atoms of a first conductivity type, wherein the the two devices and/or there is an indirect coupling path
second peripheral layer may be doped with doping atoms of a between the two devices, e.g. via one or more intervening
second conductivity type, and wherein the second conductiv devices.
ity type is different from the first conductivity type. The first 0129. In the context of various embodiments, the resistive
conductivity type and the second conductivity type may be as memory arrangement 200 may include a plurality of resistive
described above. memory cells 203 spaced apart from each other along a length
0120 In various embodiments, the first peripheral layer of the nanowire 202, wherein each resistive memory cell 203
may be p-doped and the second peripheral layer may be of the plurality of resistive memory cells 203 includes a
n-doped or the first peripheral layer may be n-doped and the resistive layer 204 including a resistive changing material,
second peripheral layer may be p-doped. wherein at least a portion of the resistive layer 204 may be
0121. In various embodiments, the first peripheral layer arranged around the longitudinal axis and at least Substan
and the second peripheral layer may define a diode. tially Surrounding the nanowire 202, and a conductive layer
0122. In the context of various embodiments, at least one 206 arranged on at least a part of the resistive layer 204.
of the first peripheral layer or the second peripheral layer may 0.130. In other words, a plurality of stack arrangements,
include a material including but not limited to silicon (Si), where each stack arrangement includes a resistive layer 204
germanium (Ge), a III-V semiconductor and an alloy thereof. and a conductive layer 206, thereby defining a resistive
The alloy may include but not limited nickel silicide (NiSi), memory cell 203, may be arranged or formed along the length
titanium silicide (TiSi), cobalt silicide (CoSi), nickel-plati of the nanowires 202. The plurality of resistive memory cells
num silicide (NiPtSi), nickel germanide (NiGe) and nickel 203 are spaced apart from each other with a gap defined
germanosilicide (NiGeSi). between two adjacent resistive memory cells 203.
0123. In the context of various embodiments, the first 0.131. In the context of various embodiments, it should be
peripheral layer may have a thickness of between about 5 nm. appreciated that there are embodiments where the resistive
and about 10 nm, for example between about 5 nm and about layer 204 or a portion thereof may surround the nanowire 202
8 nm or between about 8 nm and about 10 nm. throughout the entire length of the nanowire 202, or the resis
0124. In the context of various embodiments, the second tive layer 204 only covers an end (e.g. top end or top end
peripheral layer may have a thickness of between about 5 nm. surface) of the nanowire 202.
US 2013/0200327 A1 Aug. 8, 2013

0132 FIG.2B shows a schematic block diagram of a resis the nanowire 302. The peripheral layer 304 may behave as a
tive memory arrangement 220, according to various embodi rectifier and/or provide rectifying effect, and therefore may
ments. The resistive memory cell arrangement 220 includes a be or may form a diode (1D) on its own or may, together with
plurality of nanowires 221, and a plurality of resistive the nanowire 302, form a diode. Therefore, an additional or
memory cells 222, wherein each resistive memory cell 222 of separate diode may be provided for the resistive memory cell
the plurality of resistive memory cells 222 includes a resistive 3OO.
layer 204 including a resistive changing material, wherein at 0143. The RRAM cell (1R) 306 may be formed or
least a section of the resistive layer 204 is arranged covering arranged around the longitudinal axis 301 of the nanowire
at least a portion of a surface of a respective nanowire 221 of 302, at least substantially surrounding the peripheral layer
the plurality of nanowires 221, and a conductive layer 206 304 and the nanowire 302. The RRAM cell 306 may be
arranged on at least a part of the resistive layer 204, and a formed over or on the peripheral surface 305 or circumfer
plurality of conductive lines 224 electrically coupled to the ence of the peripheral layer 304. The RRAM cell 306 may be
plurality of nanowires 221 and the plurality of resistive formed in contact with the peripheral layer 304. The RRAM
memory cells 222. In FIG. 2B, the line represented as 226 is cell 306 may be formed at least substantially surrounding a
illustrated to show the relationship between the plurality of partial portion of the nanowire 302 and the peripheral layer
nanowires 221, the plurality of resistive memory cells 222 304. The RRAM cell 306 may include a resistive layer and a
and the plurality of conductive lines 224, which may include conductive layer (e.g. as a top electrode (TE)) as will be
electrical coupling and/or mechanical coupling. described later.
0.133 Each nanowire 221, each resistive memory cell 222, 0144. Therefore, the RRAM cell 306 may extend laterally
and the resistive layer 204 and conductive layer 206 of each from the side or circumference of the nanowire 302. The
resistive memory cell 222 may be as correspondingly additional diode selector or extrinsic diode including the
described in the context of the resistive memory arrangement peripheral layer 304, may beformed adjacent to the nanowire
200 of FIG. 2A. 302 and/or the RRAM cell 306, surrounding the nanowire
0134. In various embodiments, the plurality of conductive 302 and extends laterally from the peripheral surface 303 or
lines 224 may include a plurality of first conductive lines, circumference of the nanowire 302. Therefore, the RRAM
wherein a respective first conductive line of the plurality of cell 306 may beformed over the diode, where both the RRAM
first conductive lines is electrically coupled to the respective cell 306 and the diode including the peripheral layer 304
nanowire 221, and, and a plurality of second conductive lines, extend laterally from the peripheral surface 303 or circum
wherein a respective second conductive line of the plurality of ference of the nanowire 302, at least substantially perpen
second conductive lines is electrically coupled to a respective dicular to the longitudinal axis 301. In other words, a 1D+1R
memory cell 222 of the plurality of resistive memory cell 222. stack may be formed surrounding the vertical nanowire 302.
The plurality of first conductive lines may be bit lines (BLS). (0145 The RRAM cell (1R)306 and the 1D including the
0135 FIG.2C shows a flow chart 250 illustrating a method peripheral layer 304 may be stacked laterally in between a
of forming a resistive memory arrangement, according to word line (WL) and a bit line (BL). This may allow control of
various embodiments. the respective sizes of the RRAM cell 306 and the selector
0136. At 252, a nanowire is formed. The nanowire may (i.e. diode) separately and flexibly by tuning the dimension or
have a longitudinal axis. size of the nanowire diameter, D, the RRAM cell height,
0.137. At 254, a resistive layer including a resistive chang H, and the diode height, H, to reach the drive current,
ing material is formed, wherein at least a section of the resis Ist required for reversible Switching. Also, such a con
tive layer is arranged covering at least a portion of a surface of figuration or structure may pave the way to integrate one or
the nanowire. more such resistive memory arrangements 300 with vertical
0.138. At 256, a conductive layer is formed on at least apart nanowire CMOS devices, which may be desirable for embed
of the resistive layer. ded non-volatile memory (NVM) applications.
0.139. In various embodiments, at 254, the resistive layer 0146 FIG. 3C shows a schematic perspective view of a
may be patterned, for example using lithography process. resistive memory arrangement 320, according to various
0140. In various embodiments, at 256, the conductive embodiments, while FIG. 3D shows a schematic cross sec
layer may be patterned, for example using lithography pro tional view of the resistive memory arrangement 320 taken
CCSS, along the line B-B'. The resistive memory arrangement 320
0141 FIG. 3A shows a schematic perspective view of a includes a nanowire 322 and a RRAM cell (resistive memory
resistive memory arrangement 300, according to various cell)326. The nanowire 322 may act as a contact, for example
embodiments, while FIG. 3B shows a schematic cross sec as a bottom electrode (BE) for the RRAM cell326.
tional view of the resistive memory arrangement 300 taken 0147 The RRAM cell (1R) 326 may be formed or
along the line A-A. The resistive memory arrangement 300 arranged around the longitudinal axis 321 of the nanowire
includes a nanowire 302, a peripheral layer 304 and a RRAM 322, at least substantially surrounding the nanowire 322. The
cell (resistive memory cell)306. The nanowire 302 may act as RRAM cell 326 may be formed over or on the peripheral
a contact, for example as a bottom electrode (BE) for the surface 323 or circumference of the nanowire 322. The
RRAM cell 306. RRAM cell 326 may be formed in contact with the nanowire
0142. The peripheral layer 304 may beformed or arranged 322. The RRAM cell326 may beformed at least substantially
around the longitudinal axis 301 of the nanowire 302, at least surrounding a partial portion of the nanowire 302. The
substantially surrounding the nanowire 302. The peripheral RRAM cell 306 may include a resistive layer and a conduc
layer 304 may beformed over or on the peripheral surface 303 tive layer (e.g. as a top electrode (TE)) as will be described
or circumference of the nanowire 302. The peripheral layer later.
304 may be formed throughout the length of the nanowire (0.148. Therefore, the RRAM cell326 may extend laterally
302. The peripheral layer 304 may be formed in contact with from the peripheral surface 323 or circumference of the
US 2013/0200327 A1 Aug. 8, 2013

nanowire 322, at least substantially perpendicular to the lon the nanowire 402. The conductive layer 410 may act as a
gitudinal axis 321. In other words, a 1R stack may be formed contact, for example as a top electrode (TE) for the RRAM
surrounding the vertical nanowire 322. cell 406. As illustrated in FIG. 4B, the conductive layer 410
014.9 The arrangement of the nanowire 322 and the may be confined within the boundary or height of the resistive
RRAM cell 326, and therefore the resistive memory arrange layer 408, and forming a stack structure.
ment 320, may show or exhibit self-rectifying properties or 0154 The RRAM cell 406, and therefore also the resistive
behaviour, e.g. a 1R configuration showing self-rectifying layer 408 may be formed at least substantially surrounding a
behaviour. The RRAM cell 326 may exhibit or possess self partial portion of the nanowire 402. This also means that the
rectifying properties or behaviour and therefore may behave conductive layer 410 at least substantially surrounds the par
as a diode, thereby providing an intrinsic diode. This means tial portion of the nanowire 402. The conductive layer 410
that the resistive memory arrangement 320 may exhibit or may be formed over or on the resistive layer 408. The con
possess self-rectifying properties. Furthermore, in addition or ductive layer 410 may be formed in contact with the resistive
alternatively, the nanowire 322 may be configured as a diode, layer 408. The resistive layer 408 and the conductive layer
for example by forming respective n-doped portion/region 410 may be arranged or formed at least Substantially coplanar
and p-doped portion/region. Therefore, a separate diode may relative to each other, as illustrated in FIG. 4B.
not be necessary for the resistive memory arrangement 320, (O155 Therefore, the RRAM cell 406 may extend laterally
although it is not precluded that an additional or separate from the peripheral surface 403 or circumference of the
diode, for example as described in the context of the resistive nanowire 402, at least substantially perpendicular to the lon
memory arrangement 300, may be provided. gitudinal axis 401. In other words, a 1R stack may be formed
0150. The RRAM cell (1R)326, with the intrinsic diode, surrounding the vertical nanowire 402.
may allow separate and flexible control in tuning the dimen 0156 The stack arrangement of the nanowire 402, the
sion or size of the nanowire diameter, D, the RRAM cell resistive layer 408 and the conductive layer 410, may show or
height, H, and the diode height, H, to reach the drive exhibit self-rectifying properties, thereby behaving as a
current, I, required for reversible Switching. Also, such a diode. In various embodiments, the resistive layer 408 and the
configuration or structure may pave the way to integrate one conductive layer 410 may form or define an intrinsic diode. In
or more such resistive memory arrangements 320 with verti further embodiments, the resistive layer 408 and the nanowire
cal nanowire CMOS devices, which may be desirable for 402 may form or define an intrinsic diode.
embedded non-volatile memory (NVM) applications. 0157 FIG. 4C shows a schematic perspective view of a
0151. In various embodiments of resistive memory resistive memory arrangement 450, according to various
arrangements including 1 R only (e.g. resistive memory embodiments while FIG. 4D shows a schematic cross sec
arrangement 320) or 1D+1 R (e.g. resistive memory arrange tional view of the resistive memory arrangement 450 taken
ment 300), the RRAM cell (e.g. 306, 326) and the peripheral along the line D-D'. The resistive memory arrangement 450
layer 304 may be directly formed around the nanowire (e.g. includes a nanowire 402 and a RRAM cell 406 having a
302,322) with no or a little, if any, planar space occupied. As resistive layer 408 and a conductive layer 410, which may be
shown in FIGS. 3A to 3D, there may be 2 stack structures, as described in the context of the resistive memory arrange
depending on the switching properties of the RRAM cells, i.e. ment 400, except that the nanowire 402 of the resistive
with an extra diode selector (e.g. resistive memory arrange memory arrangement 450 includes a core portion/region (e.g.
ment 300, FIGS. 3A and 3B) or without an extra diode selec region 1) 452 and a peripheral portion/region (e.g. region 2)
tor (e.g. resistive memory arrangement 320, FIGS. 3C and 454 at least substantially surrounding the core portion 452.
3D). For the resistive memory arrangement 320, the RRAM The core portion 452 may be p-doped or n-doped (P/N-type)
cell 326 with the nanowire 322 as a bottom electrode, may while the peripheral portion 454 may be n-doped or p-doped
possess self-rectifying properties to avoid or minimise any (N/P-type). In other words, the core portion 452 may be
read error effect. p-doped while the peripheral portion 454 may be n-doped or
0152 FIG. 4A shows a schematic top view of a resistive the core portion 452 may be n-doped while the peripheral
memory arrangement 400, according to various embodi portion 454 may be p-doped. Therefore, by having the core
ments, while FIG. 4B shows a schematic cross sectional view portion 452 and the peripheral portion 454 respectively doped
of the resistive memory arrangement 400 taken along the line with doping atoms different or opposite conductivity types,
C-C". The resistive memory arrangement 400 may be similar n-doped region and p-doped region may beformed within the
to the resistive memory arrangement 320 (FIGS. 3C and 3D), nanowire 402, thereby forming a diode within the nanowire
where the corresponding or like features of the resistive 402.
memory arrangement 400 may be as described in the context 0158 FIG. 5A shows a schematic cross sectional view of
of the resistive memory arrangement 320. The resistive a resistive memory arrangement 500, according to various
memory arrangement 400 includes a nanowire 402 and a embodiments. The resistive memory arrangement 500
RRAM cell (resistive memory cell) 406. The nanowire 402 includes a nanowire 502 and a RRAM cell (resistive memory
may act as a contact, for example as a bottom electrode (BE) cell) 506. The nanowire 502 may be doped, for example
for the RRAM cell 406. n-doped (N-type) or p-doped (P-type).
0153. The RRAM cell 406 may include a resistive layer 0159. The RRAM cell (1R) 506 may be formed or
408 arranged around the longitudinal axis 401 of the nanow arranged around the longitudinal axis 501 of the nanowire
ire 402 and at least Substantially Surrounding the nanowire 502, at least substantially surrounding the nanowire 502. The
402, and a conductive layer 410 arranged at least substantially RRAM cell 506 may include a resistive layer 508 arranged
surrounding the resistive layer 408. The resistive layer 408, around the longitudinal axis 501 of the nanowire 502 and at
and therefore also the RRAM cell 406 may beformed over or least Substantially Surrounding the nanowire 502, and a con
on the peripheral surface 403 or circumference of the nanow ductive layer 510 arranged at least substantially surrounding
ire 402. The resistive layer 408 may beformed in contact with the resistive layer 508. The conductive layer 510 may act as a
US 2013/0200327 A1 Aug. 8, 2013

contact, for example as a top electrode (TE) for the RRAM includes a nanowire 502, a peripheral layer 522 and a RRAM
cell 506. As illustrated in FIG. 5A, the conductive layer 510 cell (resistive memory cell) 506. The resistive memory
may be confined within the boundary or height of the resistive arrangement 520 may be similar to the resistive memory
layer 508, and forming a stack structure. The resistive layer arrangement 300 (FIGS. 3A and 3B). The peripheral layer
508 and the conductive layer 510 may be arranged or formed 522 may act as a contact, for example as a bottom electrode
at least Substantially coplanar relative to each other. (BE) for the RRAM cell 506.
0160 The resistive memory arrangement 500 further 0166 The peripheral layer 522 may beformed or arranged
includes a second conductive layer 512 formed or arranged around the longitudinal axis 501 of the nanowire 502, at least
around the longitudinal axis 501 of the nanowire 502, at least substantially surrounding the nanowire 502. The peripheral
substantially surrounding the nanowire 502. The second con layer 522 may beformed over or on the peripheral surface503
ductive layer 512 may be formed over or on the peripheral or circumference of the nanowire 502. The peripheral layer
surface 503 or circumference of the nanowire 502. The sec 522 may be formed throughout the length of the nanowire
ond conductive layer 512 may be formed throughout the 502. The peripheral layer 522 may be formed in contact with
length of the nanowire 502. The second conductive layer 512 the nanowire 502.
may be formed in contact with the nanowire 502. The second (0167. The nanowire 502 may be p-doped orn-doped (P/N-
conductive layer 512 may form part of the RRAM cell 506. type) while the peripheral layer 522 may be n-doped or
The RRAM cell 506 may act as a contact, for example as a p-doped (N/P-type). In other words, the nanowire 502 may be
bottom electrode (BE) for the resistive memory arrangement p-doped while the peripheral layer 522 may be n-doped or the
SOO. nanowire 502 may be n-doped while the peripheral layer 522
(0161. As illustrated in FIG.5A, the resistive layer 508, and may be p-doped. Therefore, by having the nanowire 502 and
therefore also the RRAM cell 506, may beformed or arranged the peripheral layer 522 respectively doped with doping
around the longitudinal axis 501 of the nanowire 502, at least atoms different or opposite conductivity types, n-doped
substantially surrounding the second conductive layer 512 region and p-doped region formed within the nanowire 502
and the nanowire 502. The resistive layer 508, and therefore and the peripheral layer 522 may form or define a diode (1D).
also the RRAM cell 506, may be formed over or on the Therefore, the nanowire 502 may serve as one component of
peripheral surface 513 or circumference of the second con the diode.
ductive layer 512. The resistive layer 508 may be formed in (0168 The RRAM cell (1R) 506 may be formed or
contact with the second conductive layer 512. The conductive arranged around the longitudinal axis 501, at least Substan
layer 510 may be formed in contact with the resistive layer tially surrounding the peripheral layer 522 and the nanowire
SO8. 502. The RRAM cell 506 may include a resistive layer 508
(0162. The RRAM cell 506, and therefore also the resistive arranged around the longitudinal axis 501 and at least Sub
layer 508, may be formed at least substantially surrounding a stantially surrounding the nanowire 502, and a conductive
partial portion of the nanowire 502 and the second conductive layer 510 arranged at least substantially surrounding the
layer 512. This also means that the conductive layer 510 at resistive layer 508. The resistive RRAM cell 506 may further
least Substantially Surrounds the partial portion of the nanow optionally include a second conductive layer 512 formed or
ire 502. The resistive layer 508 and the conductive layer 510 arranged around the longitudinal axis 501, at least Substan
may be arranged or formed at least Substantially coplanar tially surrounding the nanowire 502. The second conductive
relative to each other, as illustrated in FIG. 5A. layer 512 is arranged in between the nanowire 502 and the
(0163 Therefore, the RRAM cell 506 may extend laterally resistive layer 508. The second conductive layer 512 may be
from the peripheral surface 503 or circumference of the formed over or on the peripheral surface 523 or circumfer
nanowire 502. The second conductive layer 512 may be ence of the peripheral layer 522. The second conductive layer
formed adjacent to the nanowire 502 and/or the RRAM cell 512 may be formed in contact with the peripheral layer 522.
506, surrounding the nanowire 502 and extends laterally from The resistive layer 508 may be formed in contact with the
the peripheral surface 503 or circumference of the nanowire second conductive layer 512. The conductive layer 510 may
502. Therefore, the RRAM cell 506 may be formed over the be formed in contact with the resistive layer 508.
second conductive layer 512, where both the RRAM cell 506 (0169. As illustrated in FIG. 5B, the conductive layer 510
and the second conductive layer 512 extend laterally from the may be confined within the boundary or height of the resistive
peripheral surface 503 or circumference of the nanowire 502, layer 508. The resistive layer 508 and the conductive layer
at least Substantially perpendicular to the longitudinal axis 510 may be arranged or formed at least substantially coplanar
501. In other words, a 1R stack may be formed surrounding relative to each other. The resistive layer 508 and the second
the vertical nanowire 502. conductive layer 512 may be arranged or formed at least
0164. The stack arrangement of the nanowire 502, the substantially coplanar relative to each other. The resistive
resistive layer 508, the conductive layer 510 and the second layer 508, the conductive layer 510 and the second conductive
conductive layer 512, may show or exhibit self-rectifying layer 512 may form a stack structure.
properties, thereby behaving as a diode. In various embodi 0170 The conductive layer 510 may act as a contact, for
ments, the resistive layer 508 and the conductive layer 510 example as a top electrode (TE) for the RRAM cell 506. The
may form or define an intrinsic diode. In further embodi second conductive layer 512 may act as a contact, for example
ments, the resistive layer 508 and the second conductive layer as a bottom electrode (BE) for the RRAM cell 506.
512 may form or define an intrinsic diode. In yet further (0171 The RRAM cell 506, and therefore also the resistive
embodiments, the resistive layer 508 and the nanowire 502 or layer 508, may be formed at least substantially surrounding a
the nanowire core may form or define an intrinsic diode. partial portion of the nanowire 502 and the peripheral layer
0165 FIG. 5B shows a schematic cross sectional view of a 522. This also means that the conductive layer 510 and the
resistive memory arrangement 520, according to various second conductive layer 512 may at least substantially sur
embodiments. The resistive memory arrangement 520 round the partial portion of the nanowire 502.
US 2013/0200327 A1 Aug. 8, 2013

(0172. Therefore, the RRAM cell 506 may extend laterally (0177. The RRAM cell (1R) 506 may beformed over or on
from the peripheral surface 503 or circumference of the the peripheral surface 545 or circumference of the second
nanowire 502. The peripheral layer 522 may be formed adja peripheral layer 544. The RRAM cell (1R) 506 may be
cent to the nanowire 502 and/or the RRAM cell 506, Sur formed in contact with the second peripheral layer 544.
rounding the nanowire 502 and extends laterally from the (0178. Therefore, the RRAM cell 506 may extend laterally
peripheral surface 503 or circumference of the nanowire 502. from the peripheral surface 503 or circumference of the
Therefore, the RRAM cell 506 may be formed over the nanowire 502. The first peripheral layer 542 and the second
peripheral layer 522, where both the RRAM cell 506 and the peripheral layer 544 may be formed adjacent to the nanowire
peripheral layer 522 extend laterally from the peripheral Sur 502 and/or the RRAM cell 506, surrounding the nanowire
face 503 or circumference of the nanowire 502, at least Sub 502 and extends laterally from the peripheral surface 503 or
stantially perpendicular to the longitudinal axis 501. In other circumference of the nanowire 502. Therefore, the RRAM
words, a 1D+1 R stack may be formed surrounding the verti cell 506 may beformed over the first peripheral layer 542 and
cal nanowire 502. the second peripheral layer 544, where the RRAM cell 506,
0173 FIG.5C shows a schematic cross sectional view of a the first peripheral layer 542 and the second peripheral layer
resistive memory arrangement 540, according to various 544 extend laterally from the peripheral surface 503 or cir
embodiments. The resistive memory arrangement 540 may cumference of the nanowire 502, at least substantially per
be as described in the context of the resistive memory pendicular to the longitudinal axis 501. In other words, a
arrangement 520, except that the peripheral layer 522 of the 1D+1 R stack may be formed surrounding the vertical nanow
resistive memory arrangement 520 is replaced by a two-layer ire 502.
peripheral structure 541 arranged around the longitudinal 0179 Various embodiments may also provide three-di
axis 501 of the nanowire 502, at least substantially surround mensional (3-D) multi stacks of RRAM cells for a resistive
ing the nanowire 502 in the resistive memory arrangement memory arrangement, with either a 1R architecture or a
540. In addition, the nanowire 502 may be undoped of the 1D--1R architecture, based on the embodiments of FIGS. 3A
resistive memory arrangement 540. The resistive memory to 3D, 4A to 4D and 5A to 5C. The three-dimensional (3-D)
arrangement 540 may be similar to the resistive memory cell multi stacks may be implemented or arranged around the
300 (FIGS. 3A and 3B). same nanowire, for example, for high density 3-D multi
0.174. The two-layer peripheral structure 541 includes a stacked RRAM applications. The number of multi-stacked
first peripheral layer 542 formed or arranged in between the RRAM cells around a nanowire may be two, three, four, five
nanowire 502 and the resistive layer 508, being arranged or any higher number of RRAM cells around the nanowire,
around the longitudinal axis 501 and at least substantially thereby offering 3-D capability.
surrounding the nanowire 502. The first peripheral layer 542 0180 FIG. 6A shows a schematic cross sectional view of
may be formed over or on the peripheral surface 503 or a resistive memory arrangement 600 with a multi or plurality
circumference of the nanowire 502. The first peripheral layer of stacked resistive memory cells 506a, 506b, according to
542 may be formed throughout the length of the nanowire various embodiments. The resistive memory arrangement
502. The first peripheral layer 542 may be formed in contact 600 may be based on the embodiments of FIG. 5B or 5C, and
with the nanowire 502. having, as a non-limiting example, a nanowire 502 which
(0175. The two-layer peripheral structure 541 further may be as described in the context of the embodiment of FIG.
includes a second peripheral layer 544 in between the first 5B or 5C, a peripheral layer 522 or 541 which may be as
peripheral layer 542 and the resistive layer 508, the second described in the context of the embodiments of FIGS. 5B and
peripheral layer 544 being arranged around the longitudinal 5C respectively, and two RRAM cells, e.g. a first RRAM cell
axis 501 and at least substantially surrounding the first 506a and a second RRAM cell 506b arranged spaced apart
peripheral layer 542. The second peripheral layer 544 may be from each other along the length of the nanowire 502. It
formed over or on the peripheral surface 543 or circumfer should be appreciated that any higher number of RRAM cells
ence of the first peripheral layer 542. The second peripheral may be provided, spaced apart from each other.
layer 544 may beformed throughout the length of the nanow 0181. The first RRAM cell 506a includes a resistive layer
ire 502. The second peripheral layer 544 may be formed in 508a and a conductive layer 510a, and the second RRAM cell
contact with first peripheral layer 542. The first peripheral 506b includes a resistive layer 508b and a conductive layer
layer 542 and the second peripheral layer 544 may be 510b. Each of the resistive layers 508a, 508b may be as
arranged or formed at least Substantially coplanar relative to described in the context of the resistive layer 508 of the
each other. embodiments of FIG.5B or 5C. Each of the conductive layers
0176 The first peripheral layer 542 may be p-doped or 510a, 510b may be as described in the context of the conduc
n-doped (P/N-type) while the second peripheral layer 544 tive layer 510 of the embodiments of FIG.5B or 5C. It should
may be n-doped or p-doped (N/P-type). In other words, the be appreciated that while not shown, the second conductive
first peripheral layer 542 may be p-doped while the second layer 512 as described in the context of the embodiments of
peripheral layer 544 may be n-doped or the first peripheral FIG. 5B or 5C may be formed in the respective first RRAM
layer 542 may be n-doped while the second peripheral layer cell 506a and the second RRAM cell 506b.
544 may be p-doped. Therefore, by having the first peripheral 0182 FIG. 6B shows a schematic cross sectional view of a
layer 542 and the second peripheral layer 544 respectively resistive memory arrangement 620 with a multi or plurality of
doped with doping atoms of different or opposite conductiv stacked resistive memory cells 406a, 406b, according to vari
ity types, n-doped region and p-doped region formed within ous embodiments. The resistive memory arrangement 620
the first peripheral layer 542 and the second peripheral layer may be based on the embodiment of FIGS. 4A and 4B, and
544 may form or define a diode (1D). Therefore, the nanowire having, as a non-limiting example, a nanowire 402 which
502 may serve as a contact (e.g. as a bottom electrode (BE)) may be as described in the context of the embodiment of
electrically connected with the diode. FIGS. 4A and 4B, and two RRAM cells, e.g. a first RRAM
US 2013/0200327 A1 Aug. 8, 2013

cell 406a and a second RRAM cell 406b arranged spaced and contact with the substrate 704 directly. The resistive
apart from each other along the length of the nanowire 402. It memory arrangement 720 may further include a passivation
should be appreciated that any higher number of RRAM cells layer 712 at least substantially surrounding the bottom end
may be provided, spaced apart from each other. region of the nanowire 702 and the RRAM cell 708. A contact
0183. The first RRAM cell 406a includes a resistive layer (e.g. a contact pad) 714, for example made of metal, may be
408a and a conductive layer 410a, and the second RRAM cell formed on or over the passivation layer 712, and extending
506b includes a resistive layer 408b and a conductive layer through a through via 715 and electrically coupled to the
410b. Each of the resistive layers 408a, 408b may be as bottom end region of the nanowire 702 or the substrate 704.
described in the context of the resistive layer 408 of the The contact 714 may be electrically coupled to a bit line (BL).
embodiments of FIGS. 4A and 4.B. Each of the conductive A contact (e.g. a contact pad)716, for example made of metal,
layers 410a, 410b may be as described in the context of the may be formed on or over the passivation layer 712, and
conductive layer 410 of the embodiments of FIGS. 4A and extending through a through via 718 and electrically coupled
4B. to the RRAM cell 708. The contact 716 may be electrically
0184. It should be appreciated any one of the resistive coupled to a word line (WL).
memory arrangements 300,320,400,450,500,520,540 may 0189 The process flow of various embodiments, for
be provided with a plurality of resistive memory cells spaced example for the embodiment of FIG. 7A, may be compatible
apart from each other along the length of the respective with vertical gate all around (GAA) nanowire CMOS tech
nanowire. nology. Therefore, it may be possible to integrate the memory
0185. In various embodiments, during fabrication of the unit cells or resistive memory cells or resistive memory
resistive memory arrangements of various embodiments, dif arrangements with logic CMOS devices (e.g. Vertical nanow
ferent fabrication methods may be employed to obtain or ire CMOS devices) within one chip for embedded memory
form an electrical contact between the nanowires and the bit applications. Hence, in various embodiments, different
lines (BL). Different contact modes may be formed, for approaches may be employed for integrating the resistive
example from the top of the nanowire as illustrated for the memory arrangements of various embodiments with logic
resistive memory arrangement 700 of FIG. 7A, or from the CMOS devices for embedded memory applications, for
bottom of the nanowire as illustrated for the resistive memory example integrating them in parallel within one chip as illus
arrangement 720 of FIG. 7B, where the resistive memory trated in FIG. 8, or to integrate them vertically on the same
arrangement 700 and the resistive memory arrangement 720 nanowire within one chip as illustrated in FIGS. 9A and 9C.
may be based on the embodiments of FIGS. 3A to 3D, 4A to Depending on the design rule and specific RRAM switching
4D, 5A to 5C, 6A and 6B. This provides more integration properties, there may be several options to get or form a
choices for different RRAM stacks. contact between nanowires and bit lines (BLS), for example
0186 Each of the resistive memory arrangements 700 from the top of the nanowire and/or from the bottom of the
(FIG.7A), 720 (FIG. 7B) includes a nanowire 702 extending nanowire.
from a substrate 704 having a buried oxide layer 706. Each of 0.190 FIG. 8 shows a schematic cross sectional view of a
the resistive memory arrangements 700, 720 further includes parallel integration of a resistive memory arrangement
a RRAM cell 708, where a portion of the RRAM cell 708 at (memory part) 800 with a logic CMOS device (logic part)
least substantially surrounds the nanowire 702. The RRAM 850, according to various embodiments, where the stack(s) or
cell 708 has at least a resistive layer and a conductive layer. structure(s) around the respective nanowires 702, 802, for the
Therefore, at least a portion of the resistive layer may be resistive memory arrangement 800 and the logic CMOS
arranged at least Substantially Surrounding the nanowire 702. device 850, may be at least substantially similar. The overall
In various embodiments, each of the resistive memory structures for the resistive memory arrangement 800 and the
arrangements 700, 720 may show or exhibit self-rectifying logic CMOS device 850 may be at least substantially similar
properties or behaviour, e.g. a 1R configuration showing self as well. The resistive memory arrangement 800 and the logic
rectifying behaviour. CMOS device 850 may be arranged or embedded in parallel
0187. The resistive memory arrangement 700 may further and separately in a single chip (e.g. a system-on-ship), and
include a passivation layer (e.g. insulation oxide) 710 at least may be electrically coupled to each other in the chip. As a
Substantially surrounding the top end region of the nanowire non-limiting example, electrical coupling between the resis
702, and another passivation layer (e.g. insulation oxide) 712 tive memory arrangement 800 and the logic CMOS device
at least Substantially Surrounding the bottom end region of the 850 may be carried out at the module (or block) level.
nanowire 702, at least a portion of the RRAM cell 708 and the 0191 The resistive memory arrangement 800 may be as
passivation layer 710. A contact (e.g. a contact pad) 714, for described in the context of the resistive memory arrangement
example made of metal, may be formed on or over the top of 700 of FIG. 7A, with the addition of a further contact (e.g. a
the nanowire 702, where the contact 714 may be electrically contact pad) 830, for example made of metal, which may be
coupled to a bit line (BL). A contact (e.g. a contact pad) 716, formed on or over the passivation layer 712, and extending
for example made of metal, may be formed on or over the through a through via 832 and electrically coupled to the
passivation layer 712, and extending through a through via bottom end region of the nanowire 702 or the base layer 704.
718 and electrically coupled to the RRAM cell 708. The In various embodiments, the resistive memory arrangement
contact 716 may be electrically coupled to a word line (WL). 800 may show or exhibit self-rectifying properties or behav
0188 For the resistive memory arrangement 720, at least a iour, e.g. a 1R configuration showing self-rectifying behav
portion of the RRAM cell 708 may be arranged at least iour. Any one of or each of the contacts 714, 830 may enable
substantially surrounding the nanowire 702 and over the top electrical coupling between the nanowire 702 and a bit line
of the nanowire 702. It should be appreciated that the RRAM (BL). In various embodiments, the resistive memory arrange
708 may be formed at least substantially along the length of ment 800 may further include a transistor (1T), for example to
the nanowire 702, pushing down the RRAM 708 all the way form a 1T+1 R architecture, as will be described later with
US 2013/0200327 A1 Aug. 8, 2013

reference to FIGS. 9A and 9C, and which may have a similar lines, SL1981, SL2982, SL3983, SL4984. As a non-limiting
structure as shown for the embodiments of FIGS. 9A and 9C. example, the single unit cell 94.0a is coupled to BL4964,
(0192. The logic CMOS device 850 may have an at least WL4974 and SL4984, while the single unit cell 940b is
Substantially similar structure or configuration, and/or mate coupled to BL2962, WL4974 and SL4984. The source
rial system as that of the resistive memory arrangement 800. terminal/contact of the respective single unit cell (e.g. 940a,
(0193 The logic CMOS device 850 includes a nanowire 940b) is coupled to a source line. The gate terminal/contact of
802 extending from a substrate 804 having a buried oxide the respective single unit cell (e.g. 940a, 940b) is coupled to
layer 806. The logic CMOS device 850 further includes a a word line. The drain terminal/contact of the respective
logic circuit 808 at least substantially surrounding the nanow single unit cell (e.g. 940a, 940b) and a bit line may overlap
ire 802. together. The memory array 960 shows a period or pitch of 2F
(0194 The logic CMOS device 850 may further include a (F refers to the minimum feature size) between adjacent
passivation layer (e.g. insulation oxide) 810 at least Substan single unit cells, thereby realizing a cell arrangement size of
tially surrounding the top end region of the nanowire 802, and 4F footprint.
another passivation layer (e.g. insulation oxide) 812 at least (0199 FIG.9C shows a schematic cross sectional view of a
Substantially Surrounding the bottom end region of the Vertical integration of a resistive memory arrangement with a
nanowire 802, the logic circuit 808 and the passivation layer logic CMOS device, according to various embodiments. The
810. A contact (e.g. a contact pad) 814, for example made of respective resistive memory arrangements of the embodi
metal, may be formed on or over the top of the nanowire 802. ments of FIGS. 3A to 3D, 4A to 4D,5A to 5C, 6A and 6B, and
A contact (e.g. a contact pad) 816, for example made of metal, 7A and 7B may be employed.
may be formed on or over the passivation layer 812, and 0200. As a non-limiting example, the integrated resistive
extending through a through via 818 and electrically coupled memory arrangement 900 includes a nanowire 902, a RRAM
to the logic circuit 808. A further contact (e.g. a contact pad) cell 908 at least substantially surrounding the nanowire 902,
820, for example made of metal, which may be formed on or and a logic circuit 909 at least substantially surrounding the
over the passivation layer 812, and extending through a nanowire 902, where the RRAM cell 908 and the logic circuit
through via 822 and electrically coupled to the bottom end 909 may be arranged spaced apart from each other along the
region of the nanowire 802 or the base layer 804. length of the nanowire 902. The nanowire 902 extends from a
0.195 The logic circuit 808 may include, for example, a substrate 904 having a buried oxide layer 906. The RRAM
transistor (e.g. MOSFET) having a gate terminal that at least cell 908 may have at least a resistive layer and a conductive
substantially surrounds the nanowire 802, thereby providing layer, where at least a portion of the resistive layer may at least
a gate all around (GAA) nanowire transistor. substantially surround the nanowire 902. The logic circuit
0.196 FIG. 9A shows a schematic perspective view of a 909 may include or may be, for example, a transistor (e.g.
Vertical integration of a resistive memory arrangement with a MOSFET, e.g. n/p-channel MOSFET) having a source (S)
logic CMOS device in the form of a transistor 944, according terminal, a drain (D) terminal and a gate (G) terminal, thereby
to various embodiments, thereby providing a 1T+1R resistive providing a 1T+1 R resistive memory arrangement. The inte
memory arrangement 940. The integrated resistive memory grated resistive memory arrangement 900 represents a single
arrangement 940 represents a single unit 1T+1 R arrange unit 1T+1 R arrangement. The gate terminal may at least
ment. The transistor 944 may be a gate all around n/p-channel substantially surround the nanowire 902, thereby providing a
(GAA NP) MOSFET. The integrated resistive memory gate all around (GAA) nanowire transistor or GAA vertical
arrangement 940 includes a nanowire 946 and a RRAM cell transistor. In this way, in one embodiment, the RRAM cell
942 stacked on top of the nanowire 946. This may mean that 908 may be arranged over the nanowire transistor (e.g. in a
the RRAM cell 942 may be arranged on top of the nanowire vertical stack), and the vertical nanowire for the resistive
946, e.g. on top of a top end surface of the nanowire 946. For memory cell 908 and the nanowire transistor is the same
example, the nanowire 94.6 may have a longitudinal axis, and Vertical nanowire structure (i.e. the resistive memory cell and
wherein RRAM cell 942 may be stacked on top or over a the nanowire transistor share one common continuous verti
surface of the nanowire 202 that is arranged at least substan cal nanowire).
tially parallel to a plane which intersects the longitudinal axis. 0201 The integrated resistive memory arrangement 900
The entire RRAM cell 942 may be stacked on top of the may further include a passivation layer (e.g. insulation oxide)
nanowire 946. The RRAM cell 942 may exhibit self-rectify 912 at least substantially surrounding the nanowire 902, the
ing property or behaviour, for example for embedded RRAM cell 908 and the logic circuit 909.
memory applications. 0202 The integrated resistive memory arrangement 900
(0197) A gate (G) terminal 948 of the transistor 944 is may further include a first contact (e.g. a contact pad)920 and
arranged with at least a portion at least Substantially Sur a second contact (e.g. a contact pad)922, for example made of
rounding the nanowire 946, thereby providing a GAA con metal, which may be electrically coupled to the nanowire 902,
figuration. The gate terminal 948 is connected to a gate con for example electrically coupled to the top of the nanowire
tact 950. A source (S) terminal 952 is coupled to one end of 902. The first contact 920 may be electrically coupled to a bit
the nanowire 946, where a source contact 954 is connected to line (BL) and the second contact 922 may be electrically
the source terminal 952. A drain (D) contact 956 is connected coupled to a drain terminal of the GAA nanowire transistor.
to the other end of the nanowire 946 and the RRAM cell 942. 0203 The integrated resistive memory cell 900 may fur
0198 FIG.9B shows a schematic perspective view of an ther include a third contact (e.g. a contact pad) 924 and a
array 960 of resistive memory arrangements with logic fourth contact (e.g. a contact pad)926, for example made of
CMOS devices, based on the embodiment of FIG.9A. The metal, which may be formed on or over the passivation layer
memory array 960 includes 4x4 1T+1 R coupled to four bit 912, and extending through one or more through Vias (e.g.
lines, BL1961, BL2962, BL3963, BL4964, four word lines, 928) and electrically coupled to the logic circuit 909. The
WL1971, WL2972, WL3973, WL4974, and four source third contact 924 and the fourth contact 926 may be respec
US 2013/0200327 A1 Aug. 8, 2013

tively electrically coupled to a source terminal and a gate ments makes it possible to fabricate high performance
terminal of the GAA nanowire transistor. Si-based diode without any damage to the pre-existing
0204 Referring to the top view of the integrated resistive Structures.
memory cell 900, the first contact (e.g. D/BL contact)920 and 0213 (3) The lateral self-rectifying RRAM stack of
the second contact (e.g. D/BL contact) 922 are illustrated as various embodiments may be implemented directly
overlapping together. It should be appreciated that they may without an increase of unit cell size. In contrast, conven
be arranged in parallel vertically and not on the same plane. tional devices may employ additional transistors to Sup
The reference numeral 901 a represents a source line, the press the interference from neighbouring cells, thereby
reference numeral 901b represents a word line while the increasing the device area.
reference numeral 901c represents the overlapped D and BLs. 0214 (4) The GAA architecture of various embodi
In addition, it should be appreciated that the drain (D) termi ments may provide more flexibility to control the areas
nal may not be required, for example similar to the embodi of 1D and 1RRAM separately.
ment of FIG. 7B, where the RRAM cells may fully cover the 0215 (5) The lateral 1D+1RRAM stack of various
top of nanowires. embodiments provides a higher potential for high den
0205 Therefore, vertical GAA nanowire transistors may sity, and also adds flexibility to control the areas of 1D
be integrated with the resistive memory arrangements of vari and 1RRAM separately.
ous embodiments vertically on the same nanowires, where 0216 While the invention has been particularly shown and
one electrode of a RRAM cell may share the same nanowire described with reference to specific embodiments, it should
(e.g. silicon nanowire) with the drain region (D) of a MOS be understood by those skilled in the art that various changes
FET, for embedded memory applications. in form and detail may be made therein without departing
0206 FIG.10 shows a schematic cross sectional view of a from the spirit and scope of the invention as defined by the
fabrication process 1000 for forming a resistive memory appended claims. The scope of the invention is thus indicated
arrangement, according to various embodiments. A substrate by the appended claims and all changes which come within
may be provided. The substrate may be patterned and por the meaning and range of equivalency of the claims are there
tions of the substrate may be removed, for example by etch fore intended to be embraced.
ing, to define a nanowire. As a result, a structure 1002 may be 1. A resistive memory arrangement comprising:
obtained, the structure 1002 having a nanowire 1004 extend a nanowire; and
ing monolithically from the substrate 1006. a resistive memory cell comprising:
0207. A passivation layer (e.g. insulation oxide) may be a resistive layer comprising a resistive changing mate
deposited over the structure 1002. The passivation may be rial, wherein at least a section of the resistive layer is
patterned and part of the passivation layer may be removed to arranged covering at least a portion of a Surface of the
leave a passivation layer towards the bottom or base region of nanowire; and
the nanowire 1004 on the substrate 1006. A resistive layer, a conductive layer arranged on at least a part of the
followed by a conductive layer may then be deposited. As a resistive layer.
result, a structure 1100 may be obtained, having a passivation 2. The resistive memory arrangement as claimed in claim
layer 1112, a resistive layer 1114 and a conductive layer 1116. 1, wherein the nanowire has a longitudinal axis, and wherein
0208. The resistive layer 1114 and the conductive layer the Surface of the nanowire is arranged at least Substantially
1116 may be patterned and portions of the resistive layer 1114 parallel to a plane which intersects the longitudinal axis.
and the conductive layer 1116 may then be removed, for 3. The resistive memory arrangement as claimed in claim
example on the end sides of the resistive layer 1114 and the 1, wherein the nanowire has a longitudinal axis, and wherein
conductive layer 1116. As a result, a structure 1200 may be at least a portion of the resistive layer is arranged around the
obtained. longitudinal axis and at least Substantially Surrounding the
0209 Further processing of the structure 1200 may be nanowire.
further carried out, where necessary. Doping processes may 4. The resistive memory arrangement as claimed in claim
also be carried out. In addition, it should be appreciated that 3, wherein at least a portion of the conductive layer is
other layers, for example a second conductive layer, a periph arranged at least Substantially Surrounding the portion of the
eral layer, etc. may be deposited and processes (e.g. etched) at resistive layer.
any stage of the fabrication process 1000. Therefore, the 5. The resistive memory arrangement as claimed in claim
fabrication process 1000 begins with formation of a nanowire 3, wherein the portion of the resistive layer is arranged at least
followed by deposition of the layers. The layers may be to Substantially surrounding a partial portion of the nanowire.
form a resistive memory cell, or a resistive memory cell and a 6. The resistive memory arrangement as claimed in claim
diode. 1, wherein the nanowire is doped.
0210 Various embodiments may provide one or more of 7. The resistive memory arrangement as claimed in claim
the following advantages: 1, wherein the nanowire comprises a semiconductor material.
0211 (1) The lateral 1D+1 RRAM stack of various 8. The resistive memory arrangement as claimed in claim
embodiments not only minimizes the interference from 1, wherein the nanowire has a diameter of between about 10
neighbouring cells, but also increases the current by nm and about 200 nm.
increasing the diode area, without penalty on the 9. The resistive memory arrangement as claimed in claim
1D-1RRAM unit area. 1, wherein the nanowire has a length of between about 100 nm
0212 (2) Silicon (Si) based diodes offer the highest and about 2 um.
performance, but the high fabrication temperature is still 10. The resistive memory arrangement as claimed in claim
problematic, especially over metal layers (e.g. NiSi or 1, further comprising a substrate from which the nanowire
Cu). The lateral 1D--1RRAM stack of various embodi extends monolithically.
US 2013/0200327 A1 Aug. 8, 2013

11. The resistive memory arrangement as claimed in claim conductivity type, and wherein the second conductivity
1, wherein the nanowire comprises a core portion and a type is different from the first conductivity type.
peripheral portion at least Substantially surrounding the core 17. The resistive memory arrangement as claimed in claim
portion, wherein the core portion is doped with doping atoms 1, further comprising a transistor having a first source/drain
of a first conductivity type, wherein the peripheral portion is terminal, a second source? drain terminal and a gate terminal,
doped with doping atoms of a second conductivity type, and wherein the first source/drain terminal is electrically coupled
wherein the second conductivity type is different from the to the resistive memory cell.
first conductivity type. 18. The resistive memory arrangement as claimed in claim
12. The resistive memory arrangement as claimed in claim 1, comprising
1, further comprising a second conductive layer in between a plurality of resistive memory cells spaced apart from each
the nanowire and the resistive layer, wherein at least a portion other along a length of the nanowire, each resistive
of the second conductive layer is arranged around the longi memory cell comprising
tudinal axis and at least Substantially Surrounding the nanow a resistive layer comprising a resistive changing mate
ire.
13. The resistive memory arrangement as claimed in claim rial, wherein at least a portion of the resistive layer is
1, further comprising a peripheral layer in between the arranged around the longitudinal axis and at least
nanowire and the resistive layer, wherein at least a portion of Substantially Surrounding the nanowire; and
the peripheral layer is arranged around the longitudinal axis a conductive layer arranged on at least a part of the
and at least Substantially Surrounding the nanowire, wherein resistive layer.
the nanowire is doped with doping atoms of a first conduc 19. A resistive memory arrangement comprising:
tivity type, wherein the peripheral layer is doped with doping a plurality of nanowires; and
atoms of a second conductivity type, and wherein the second a plurality of resistive memory cells, wherein each resistive
conductivity type is different from the first conductivity type. memory cell of the plurality of resistive memory cells
14. The resistive memory arrangement as claimed in claim comprises
13, wherein the peripheral layer comprises a material selected a resistive layer comprising a resistive changing mate
from the group consisting of silicon, germanium, a III-V rial, wherein at least a section of the resistive layer is
semiconductor and any alloy thereof. arranged covering at least a portion of a Surface of a
15. The resistive memory arrangement as claimed in claim respective nanowire of the plurality of nanowires; and
14, wherein the alloy is selected from the group consisting of
nickel silicide, titanium silicide, cobalt silicide, nickel-plati a conductive layer arranged on at least a part of the
num silicide, nickel germanide and nickel-germanosilicide. resistive layer; and
16. The resistive memory arrangement as claimed in claim a plurality of conductive lines electrically coupled to the
1, further comprising: plurality of nanowires and the plurality of resistive
a first peripheral layer in between the nanowire and the memory cells.
resistive layer, wherein at least a portion of the first 20. A method of forming a resistive memory arrangement,
peripheral layer is arranged around the longitudinal axis the method comprising:
and at least Substantially Surrounding the nanowire; and forming a nanowire;
a second peripheral layer in between the first peripheral forming a resistive layer comprising a resistive changing
layer and the resistive layer, wherein at least a portion of material, wherein at least a section of the resistive layer
the second peripheral layer is arranged around the lon is arranged covering at least a portion of a Surface of the
gitudinal axis and at least Substantially Surrounding the nanowire; and
portion of the first peripheral layer,
wherein the first peripheral layer is doped with doping forming a conductive layer on at least a part of the resistive
atoms of a first conductivity type, wherein the second layer.
peripheral layer is doped with doping atoms of a second