A 13.

56MHz Receiver SoC for Multi-Standard RFID

Reader
Min-Woo Seo, Yong-Chang Choi, Young-Han Kim and Hyung-Joun Yoo

Abstract – A HF (13.56MHz) RFID receiver RFID system and generate the required specifications.
architecture SoC (System on Chip) is proposed. The After that, a compatible 13.56MHz RFID receiver SoC
receiver can be used in the standards of ISO/IEC 14443 architecture is proposed for reader system. Following the
type A/B, 15693, and 18000-3. Before designing the experiments of test board adopting commercial parts, the
circuit, standard analysis is processed. And also, we did receiver circuit was fabricated as a chip level using 0.18um
a previous measurement for preparing implementation CMOS technology.
as a chip level. That is, a RFID transceiver test board The remainder of this paper is as follows. In section II,
using commercial components was configured and configurations and experiments as a board level test are
tested. Through the board experiments, we checked the introduced. The brief introduction of the standard analysis
possibilities of operation of designed receiver. Based on is in section III, the receiver of the system are introduced in
the experiment results, the multi-standard 13.56MHz section VI. Section V presents measurement results of the
RFID receiver SoC was designed and fabricated using fabricated chip. Lastly Conclusions are in section VI.
TSMC 0.18um CMOS technology. The test results
show that designed receiver system as a chip level can II. CONFIGURATION OF TEST BOARD FOR RFID
be operated properly in multiple standard conditions. TRANSCEIVER
I. INTRODUCTION To confirm the possibility of implementing RFID
transceiver system as a chip level, board level tests were
As demands of user about wireless communication going ahead before circuit simulation. A block diagram of
have increased from a voice transmission service to a the RFID system is shown in Fig. 1. The diagram is applied
complex multimedia service, the volumes of data rates of to both board level and chip level design. When we are
wireless system also have been swelled. In case of the configuring the board, commercial components like tags
distribution industry, producers want to read and write and antennas are adopted for compatibility with other
information about their merchandises more and more. commercial RFID reader chips. A digital FPGA boards are
Therefore, a management system using RFID is preferred used to generate coded signals like modified miller and
rather than using a conventional barcode system. At the NRZ. Through this test, we can check the total operation of
beginning of the RFID readers, a standalone RFID system entire RFID Transceiver system.
is mainly used because of its weak battery time due to large
power consumption, weight and size of the reader. But as
the application ranges of RFID are expanded and the
communication technology is developed, consumer’s
requests for mobile RFID reader system are having
extended more and more. [1]
Depending on the RFID carrier frequency, readable
distance and applications, system characteristics and
required specifications of the RFID systems can be
variously changed. For example, 13.56 MHz RFID system Fig. 1. Block diagram of the RFID system.
utilizes passive tags that do not have its own power supply
like battery and can be used as a near far communications In transmitter (TX), to mix a modulation signal with
(NFC) defined in multiple standards : ISO-14443, 15693 a 13.56MHz carrier signal, an analog switch is adopted.
and 18000-3 [2]-[4]. And a 13.56MHz clock signal can be made with crystal
Though there are many kinds of structures about oscillator, capacitor, invertors and resistors. Based on the
RFID transceiver reported in [5]-[7], it is significant to standard, digital baseband signal can be made by using
design a transceiver test board using discrete components digital controller, a FPGA board.
for implementing as a chip level. Combining tests between From this test, we can conclude that this proto-type
digital baseband and analog front-end can help designing RFID system can communicate in a half-duplex mode and
transceiver SoC more perfectly. inductive coupling between reader and tag antenna is well
In this paper, we are mainly focused on the receiver operated.
architecture. First, we introduce standards of 13.56MHz But during the verification, some considerations are
founded. First, peak to peak voltage (VPP) of the TX output
Min-Woo Seo, Yong-Chang Choi, Young-Han Kim and
is not quite large enough to wake up the tag. To settle this
Hyung-Joun Yoo are with the School of Engineering, Information
and Communications University, South Korea, E-mail: matter, the output of the transmitter should be composed as
minune@icu.ac.kr, sky-cyc@icu.ac.kr, ekmyph@icu.ac.kr a differential structure rather than single-ended output.
hjyoo@icu.ac.kr Through this process, higher level of VPP is transferred to

978-1-4244-2540-2/08/$25.00 ©2008 IEEE

antenna and more power can be offered to the tag by system is half-duplex mode. The reader (interrogator) uses
resonance of external capacitor and antenna. a 13.56 MHz carrier frequency of the industrial, scientific
Furthermore, an additional sub-circuit for generating and medical band (ISM) for transferring data and energy.
reference voltage of a comparator is to be added in receiver. For 14443 type-A system, the reader transmits 100%
In the board experiment, to tune the reference voltage of amplitude shift keying (ASK) modulated data encoded in
the comparator, external power supply is used. And the modified miller. For 14443 type-B system, a 10% ASK
tuning range is considerably wide because of the variation signal coded in non-return to zero (NRZ) is used to transfer
of the response signal from the tag due to the distance data and seamless power to passive tag.
between the transceiver and the tag and different standards.
In implementation as a chip level, a circuit that fixes a TABLE I.
reference voltage of the comparator is to be added. SPECIFICATIONS OF THE RFID STANDARDS
And ESD protection and ground isolation between
the digital part and analog part is necessary to prevent ISO standard 14443A 14443B 15693 18000-3
clock noise for reliability in operation. Carrier
13.56 MHz · 7 KHz
frequency
Data coding ASK 100%
ASK 10% PPM
(Reader to Modified
NRZ (1 out of 256, 1 out of 4)
Tag) Miller
Data coding
OOK BPSK One or two subcarrier
(Tag to
Manchester NRZ-L Manchester
Reader)
6.62 / 6.67 kbps
Data rate 106kbps
26.48 / 26.69 kbps
Subcarrier
847.5kHz 423.75 / 484.28 kHz
Frequency
Read range ~5cm 5~20cm

IV. RECEIVER OF THE DESIGNED TRANSCEIVER

Fig. 2. Configuration and experiment of test board.
The proposed receiver structure is made up of
III. STANDARD ANALYSIS FOR RECEIVER DESIGN envelope detector (ED), variable gain amplifier (VGA),
low pass filter and comparator as shown in Fig. 4. To
As shown in table I, in order to transmit data signals demodulate the load modulated response signal from the
from reader to tag supporting many standards, various tag, the ED detect the envelope of the received signal
modulation indexes are needed [2] ~ [4]. That is, a firstly. Sallen-key 2nd low pass filter is adopted to reduce
additional circuit for controlling modulation index is the ripple voltage output generated during peak detection.
necessary in transmitter structure. Before filtering the signal, envelope signal is amplified by
For low power consumption and higher efficiency, using VGA. The gain of the VGA can be selected by
load modulation with subcarrier is adopted in signal digital bits (D0, D1). After filtering a high frequency noise,
transferring from a tag to a reader. The modulation with the the signal is transmitted to the digital controller by passing
subcarrier is operated by subcarrier using different coded through a comparator. For hysteresis effect and high speed
data. According to standards, the subcarrier frequency is operation, preamp stage and positive feedback latch stage
different and obtained by the binary division of the carrier are included in the comparator. For ESD protection, a poly
frequency. For the HF (13.56MHz) RFID systems, the resistor is connected in front of the envelope detector and
subcarrier frequencies 847 kHz (13.56MHz / 16) and 424 each pad has diodes for preventing surge voltage incoming
kHz (13.56 MHz /32) are used. Modulation with subcarrier to the circuit.
signal is used to switch the load resistance on and off.

Fig. 4. Proposed receiver circuit. (Simplified model)

Fig. 3. Illustration of communication signal between
reader (PCD) and tag (PICC) [2]. A. Envelope detector consideration

Fig. 3 shows the signal illustration and modulation To demodulate ASK signal, envelope detector (ED) is
index between reader (PCD) and passive tag (PICC) in the widely used for detecting envelope because it is simple and
standard 14443 A and B. the communication mode of the cost effective. But there is a trade-off relation between
ripple voltage (ǻV) and a time (Tdrop) for output voltage to As shown in Fig. 7, at low frequency, the signal is
go to much small value when discharge of a capacitor is directly buffered to the output because capacitors are
begun. These two terms are expressed as appeared as open circuits. At high frequency, where
capacitors are shown as short circuits, the signal is shunted
V peak to ground at the amplifier’s input. This input is amplified to
'V (1) the output and the signal does not appear at amplifier’s
f cW output.

{ tdrop / W } V peak
Vdrop V peak e o tdrop W ˜ (2)
Vdrop

Where fc is carrier frequency and W is time constant. As

shown in Fig. 5, when ǻV is low, Tdrop is increased; slope
of the falling voltage is become slow-moving which makes
output of comparator having duty cycle more than 50%.
Large duty cycle makes digital controller hard to find the
Fig. 7. Low-Pass Sallen-Key circuit
position of logic level where the transition is happened.
Thus selecting proper time constant is necessary. We can
find optimal time constant by comparing Fig.6 and pause
time defined in the standard [2] ~ [4].

Fig. 8. Simulated result of the designed filter

C. Determination on VREF for digitally controlled

Comparator
Fig. 5. Ripple voltage and negative peak clipping of the
envelope detector (ED) From the test board experiments, we can confirm that
levels of VREF are to be predetermined. For commercial
usage, internal tuning reference circuit is necessary. To fix
the VREF of the comparator decided by digital part, binary
weighted resistor type 4bit Digital to Analog Converter
(DAC) is designed. Since digital input data stream is 4bit,
we can obtain 16 levels of voltage between high and low
threshold voltage by equations (4), (5). From (4), (5) we
can set levels of VREF by properly determined Bin. In this
manner, internally circuited VREF can be controlled by
selecting digital bit (D2 ~ D5) in Fig. 4 and need not an
external control unit for tuning. Thus, demodulation can be
done rapidly and accurately.
Fig. 6. Selection of W : Graphical description of (1), (2) Bin b1 2 1  b2 2 2  b3 2 3  b4 2 4 (4)
where fc is 13.56MHz, Vpeak is 0.54V, Vdrop is 0.2V

B. Sallen key low pass filter § RF · (5)

Vout ¨ VREF ¸ Bin
© R ¹
In order to eliminate the high frequency of the output
of the ED output, low pass filter (LPF) is adopted. When
considering smaller area and higher power for filtering, we
adopted sallen-key architecture. Transfer function is in (3).
K
H( f ) (3)
S ( R1 R2 C1C 2 )  S ( R1C1  R2 C1  R1C 2 (  K ))  1
2

1 R3  R4
where f c and K
2S R1 R2C1C2 R3 Fig. 9. Binary weighted Resistor Type 4bit DAC
Fig. 10. Simulated Result of Binary weighted Resistor 4bit
DAC. Large glitch is occurred during transition between
0111 and 1000.
Fig. 13. Waveforms of response signal, ED output and
V. MEASUREMENT RESULTS comparator in the receiver part.

Obtained specifications, we firstly design a test board VI. CONCLUSION

of the system. After that, we implement TX and RX part as
a chip level in order to verify proposed RFID system with In this paper, a 13.56MHz multi-standard receiver
connecting FPGA board to make command data and SoC was designed and fabricated. Previously to chip
commercial tags. The chip was designed and fabricated by implementation, the RFID system test board is designed
using TSMC 0.18um 1 poly 6-meteal CMOS technology. using commercial parts like analog switch for transmitter,
The die photos of the chips are in Fig 11. The chip size is antenna, op-amp, and comparator.
0.54mm Ƿ 0.54mm and 0.68mmǷ0.6mm respectively. From this demo board, we can check the potential
From the experiment, we could awake commercial problems during designing the receiver as a chip level.
13.56MHz RFID tags as shown in Fig. 12. After that, implementation as a chip level is processed
based on these check points. For supporting various
standards in 13.56MHz RFID system, circuits for
controlling reference voltage and gain of VGA are added
in receiver. In order to less sensitive to various response
signal level from the tag, a certain voltage is to be applied
to the receiver after eliminating DC voltage at VGA input.
In measurement using various commercial tags with FPGA
board, we can confirm that this receiver chip works well.

Fig. 11. photograph of the TX(left) and RX(right) chip ACKNOWLEDGEMENT

In Fig. 13, the response signal from the tag are This work was sponsored by Ministry of Knowledge
demodulated and transmitted to the digital part. The Economy of South Korea, Component and Material
Waveform RX_in in Fig. 13 is same as load modulated Development Project and by Advanced Digital Chips Inc.
response signal (upper) in Fig. 12. After demodulating the
RX signal, peak voltage of the RX is converted to the
REFERENCES
digital pulse.
The measured results demonstrated that the circuit has [1] K. Klaus Finkenzeller and J. Wiley, RFID Handbook: J.
met the standard specifications. Wiley & Sons, 2003.
[2] International standard ISO/IEC 14443, International
Standardization Organization, April 2003.
[3] ISO/IEC FDIS 18000-3: RFID for item management-Air
interface, Part 3 - Parameters for air interface
communications at 13.56 MHz, April 2003.
[4] International standard ISO/IEC 15693, International
Standardization Organization, April 2003.
[5] S. Chen, V. Thomas, “Optimization of Inductive RFID
Technology,” Proc. IEEE Int. Symp. Electronics and the
Environment 2001, Denver, CO, pp. 82–87.
[6] N. G. Choi, H. J. Lee, S. H. Lee and S. J. Kim, “Design of
a 13.56MHz RFID System,” in ICACT 2006, Korea, vol. 1,
pp 840-843 .
[7] S. Meillère, H. Barthélemy, M. Martin, “13.56 MHz
CMOS transceiver for RFID applications,” Analog
Fig. 12. Wake up (lower) signal generated by the FPGA Integrated Circuits and Signal Processing archive, vol. 49,
board and antenna output in TX part and the response pp 249-256, December 2006.
signal (upper) of the commercial tag.