What is setup time? Setup time is defined as the minimum amount of time BEFORE the clock’s active edge by which the data must be stable for it to be latched correctly, Any violation in this required time causes incorrect data to be captured and is known as a setup violation. What is hold time? Hold time is defined as the minimum amount of time AFTER the clock's active edge during which the data must be stable. Any violation in this required time causes incorrect data to be latched and is known as a hold violation. Advertisement For more information on the intra-flop aspects of setup and hold time, see Understanding the basics of setup and hold time Advertisement PARTNER CONTENT a] uc san ngincring Advanced Pee ec vnces mien Enenserne, Packaging ‘Adoption of for Drives New 09.24.2004 7775" 99.00.2004" 99.19.2004 Setup and hold time equationsLet's first define clock-to-Q delay (Tenersea). In a positive edge triggered flip-flop, input signal is captured on the positive edge of the clock and corresponding output is generated after a small delay called the Tussssea. The flip flop can only do the job correctly if the data at its input does not change for some time before the clock edge (Toxss) and some time after the clock edge (T,4,)- Again, the clock signal which circulates via clock tree throughout the design has its own variability termed as skew. From Figure 1 below, we derive equations for setup time and hold time. Figure 1 shows two talking flops, the first being the launching flop and the second is obviously the capturing flop. We shall derive equation for setup time for the capturing flop and equation for hold time for the launching flop. However, the derived equations will be true for either of the flops or for that matter any flops in the design Insertion Delay Toso Figure 1 Two talking flops scenario In the diagram above, at time zero FF1 is to process D2 and FF2 is to process D1. Time taken for the data D2 to propagate to FF2, counting from the clock edge at FF1, is invariably = Tay +T.n and for FF2 to successfully latch it, this D2 has to be maintained at D of FF2 for Tug time before the clock tree sends the next positive edge of the clock to FF2. Hence to fulfil the setup time requirement, the formula should be like the following.Teag* Toant* Tuts Tar + Toe (1) Let's have a look at the timing diagram below to have a better understanding of the setup and hold time. Tha uk reactng FAL i setup | Tone caxreactng t FR wt stew). Toen Figure 2 Setup and hold timing diagram Now, to avoid the hold violation at the launching flop, the data should remain stable for some time (Trax) after the clock edge. The equation to be satisfied to avoid hold violation looks somewhat like below: Teas Ton = Tras * Toten @) ‘As seen from the above two equations, it can be easily judged that positive skew is good for setup but bad for hold. The only region where the input can vary is the ‘valid input window’ as shown in Figure 3.§Toeup Figure 3 Valid input window Example setup and hold time formulas Consider Figure 4 consisting of two talking flops. Based on the timing details provided, we can find out the maximum frequency at which this circuit could work without timing violations. Ta=3ns Tha 4ns ‘lock insertion Delay = 2ns Teen = 25008 Figure 4 Timing details for two talking flops does not constrain the maximum Since clock insertion delay is common to clock inputs for both flip-flops, operating frequency for the given setup.lt can be seen that this circuit does not violate the hold constraint as givenin equation (2). Intuitively, we can look at equation (1) as follows: (Time available for data to travel from FF1 to FF2) 2 (Time needed for data to travel from FF1 to FF2) Telk + Tskew 2 Te2q + Teomb + Ts2 Telk + 0.25ns 2 0.1ns + 5ns + 3ns Telk > 7.85ns Thus a minimum Clock Period of 7.85 ns is required to prevent setup violation. This translates to a maximum, operating frequency of 127.4 MHz From the above example itis clear that to improve the maximum operating frequency, any of the following steps can be taken 1, Decrease Tcomb between talking flops. 2. Increase Tskew if there is scope to do so. 3, Select flops with lower Te2q and Tsetup. Another way of looking at this is, reducing the operating frequency of the system helps mitigate setup violations, if any, Impact of setup/hold constraints on clock to Q delaySince latching circuit in a Flip-Flop is a back to back inverter (op of one inverter is ip to the other inverter, as shown in Figure 5), the //O characteristic, as shown in Figure 6, is derived from the characteristic of single inverter. For the purpose of explanation, let's say OV corresponds to logic LOW and SV corresponds to logic HIGH. As seen from the adjacent diagram, if any value other than a perfect OV or SV is given as input to this back-to-back inverter, it will take some latching cycles to produce a stable inverted o/p. This delay accounts for the C2Q delay. Figure 5 Back-to-back inverters for latching action— _— Figure 6 10 characteristics If such delays accumulate over flops it may so happen that a data signal is missed by the clock edge at which it was supposed to be captured,