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Classical Method and One-Hot Method Design

This is a brief discussion of Classical and One-hot method GCD Processor design from John P. Hayes' book

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43 views7 pages

Classical Method and One-Hot Method Design

This is a brief discussion of Classical and One-hot method GCD Processor design from John P. Hayes' book

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CL1FF -クリフ
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Since a subtraction always follows a swap, all next-state entries in the

second row are S2. The corresponding active outputs are the two register-
load signals Load XR and Load YR, along with Swap, which route the outputs
of XR and YR to YR and XR, respectively. The next states for S 2 are the same
as those for S0; the active outputs are Subtract, which routes the output XR –
YR of the subtracter to XR, and Load XR.

Classical method. The major steps of the classical design method are as
follows:

1. Construct a P-row state table that defines the desired input-output


behavior.

2. Select the minimum number p of D-type flip-flops and assign a p-bit binary
code to each state.

3. Design a combinational circuit C that generates the primary output signals


{zi} and the secondary outputs {Di} that must be applied to the flip-flops.

We now apply this method to the design of the control unit CU for the gcd
processor. We have already constructed the necessary state table (Figure
5.7). Since there are four states, we require two flip-flops, whose outputs
D1D0 = y1y0 define CU's internal states. We assign the binary patterns to the
four states in the following obvious way:

We note in passing that the state assignment pattern affects the complexity
of the circuit in subtle ways. At this point we can construct a binary version
of the state table, the excitation table, as shown in Figure 5.8. The D flip-
flop's characteristic equation Di+ (t + 1) = Di (t) defines the inputs D1+ and
D0+ to the flip-flops. CU's combinational logic C can now be derived from the
excitation table using any available manual or auto- matic method. Suppose,
for instance, that we use two-level sum-of-products (SOP) minimization. It is
easily checked that C is defined by the following SOP equations, which lead
directly to the design of Figure 5.9. Note that all gates in an AND-OR SOP
circuit can be changed to NANDs to produce a NAND-NAND realization of the
original function.
One-hot method. While the classical design method minimizes a control
unit's memory elements, its effect on the amount of combinational logic C is
less obvious. Furthermore, control units designed by this technique tend to
have a complicated, "random" structure, which makes design debugging and
subsequent maintenance of the circuit difficult. An alternative approach that
simplifies the design process and gives C a regular and predictable structure,
is the one-hot method, so called because its binary state assignment always
contains a single 1 the “hot" bit—while all the remaining bits are 0. Thus the
state assignment for a four-state machine like the gcd processor takes the
following form:
A NAND implementation of these equations appears in Figure 5.10. Note that
the asynchronous Reset line must set D 0 to 1 and all other state variables to
0.

The steps of the one-hot design method for a Moore machine can be
summarized as follows:

1. Construct a P-row state table that defines the desired input-output


behavior.
2. Associate a separate D-type flip-flop D i with each state Si and assign
the P-bit one—hot binary code D1, D2, …, Di-1, Di, Di+1, …, Dp = 0, 0, …,
0, 1, 0, …, 0 to Si.
3. Design a combinational circuit C that generates the primary and
secondary output signals {Di} and {zk}, respectively. Di+ is defined by
the logic equation
XR> XRY D1 DD0
0 R

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