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Taxichip Integrated Circuits: Transparent Asynchronous Transmitter/Receiver Interface

TAXIchipTM Integrated Circuits Transparent Asynchronous Transmitter/Receiver Interface

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0% found this document useful (0 votes)

22 views127 pages

Taxichip Integrated Circuits: Transparent Asynchronous Transmitter/Receiver Interface

TAXIchipTM Integrated Circuits Transparent Asynchronous Transmitter/Receiver Interface

Uploaded by

محمد خدائی

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TAXIchipTM Integrated Circuits

Transparent Asynchronous
Transmitter/Receiver Interface
Am7968/Am7969-125
Am7968/Am7969-175

Data Sheet
and
Technical Manual
1994
 1994 Advanced Micro Devices, Inc.

Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.

This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or fitness
for a particular application. AMD assumes no responsibility for the use of any circuitry other than the circuitry in an AMD product.

The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice.
AMD assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the
information included herein. Additionally, AMD assumes no responsibility for the functioning of undescribed features or parameters.

Trademarks
AMD and the AMD logo are registered trademarks of Advanced Micro Devices, Inc.
TAXIchip and TAXI are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
TABLE OF CONTENTS

Am7968/Am7969 TAXIchip Integrated Circuits

Am7968/Am7969 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Am7968/Am7969 Technical Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.1 The Am7968 TAXITM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.2 The Am7969 TAXI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Chapter 2 Using the TAXIchip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.1 Data and Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.2 Operational Modes: Local, Cascade and Test . . . . . . . . . . . . . . . . . . . . . . . . 53

Chapter 3 Data Encoding, Violation and Syncs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.2 Violation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3 TAXI PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 4 Clock Generation and Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.1 TAXI Transmitter Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.1.1 Local Mode Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2 TAXI Receiver Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.1 Cascade Mode Receivers (Am7969-125 only) . . . . . . . . . . . . . . . . . . 61

Chapter 5 Interfacing with the Serial Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1 Very Short Link, DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.2 Terminated, DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 Terminated, AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.4 Baseline Wander and the AC Coupling Capacitor . . . . . . . . . . . . . . . . . . . . . 64
5.5 Interfacing to Fiber Optic Transmitters/Receivers . . . . . . . . . . . . . . . . . . . . . 66
5.5.1 DC-Coupled TAXl-Fiber Optic Transceiver Interface . . . . . . . . . . . . . 66
5.5.2 AC-Coupled TAXl-Fiber Optic Transceiver Interface . . . . . . . . . . . . . 68
5.6 Interfacing to Coaxial Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.7 Interfacing to Twisted-Pair Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Chapter 6 Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.1 Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.1 Rules for Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.2 Layout using Fiber Optic Data Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table of Contents iii

AMD

Chapter 7 Cascade Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.1 Transmit Cascaded Data with a Single TAXI Transmitter . . . . . . . . . . . . . . . 76
7.2 Receivers In Cascade Mode: Connections (Am7969-125 only) . . . . . . . . . . . 79
7.3 Auto-Repeat Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3.1 Receiver Connections in Auto-Repeat Configuration . . . . . . . . . . . . . 81
7.3.2 Timing Limitations of the Auto-Repeat Configuration . . . . . . . . . . . . . 84
7.4 Unbalanced Configuration (Am7968/Am7969-125 only) . . . . . . . . . . . . . . . . 85

Chapter 8 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.1 Transmitter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.2 Receiver Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3 Timing Relationships in Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Appendix A Optical Components Manufacturers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Appendix B Error Detection Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Appendix C TAXI TIPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

iv Table of Contents
FINAL

Am7968/Am7969 Advanced
Micro
TAXIchipTM Integrated Circuits Devices
(Transparent Asynchronous Xmitter-Receiver Interface)

DISTINCTIVE CHARACTERISTICS
■ Parallel TTL bus interface ■ Easy interface with fiber optic data links
— Eight Data and four Command Pins ■ 32–140 Mbps (4–17.5 Mbyte/s) data
— or nine Data and three Command Pins throughput
■ Asynchronous input using STRB/ACK
— or ten Data and two Command Pins
■ Automatic MUX/DEMUX of Data and Command
■ Transparent synchronous serial link
■ Complete on-chip PLL, Crystal Oscillator
— +5 V ECL Serial I/O
■ Single +5 V supply operation
— AC or DC coupled
■ 28-pin PLCC or DIP or LCC
— NRZI 4B/5B, 5B/6B encoding/decoding
■ Drive coaxial cable or twisted pair directly

GENERAL DESCRIPTION
The Am7968 TAXIchip Transmitter and Am7969 The speed of a TAXIchip system is adjustable over a
TAXIchip Receiver Chipset is a general-purpose inter- range of frequencies, with parallel bus transfer rates of
face for very high-speed (4–17.5 Mbyte/s, 40–175 4 Mbyte/s at the low end, and up to 17.5 Mbyte/s at the
Mbaud serially) point-to-point communications over co- high end. The flexible bus interface scheme of the
axial or fiber-optic media. The TAXIchip set emulates a TAXIchip set accepts bytes that are either 8, 9, or
pseudo-parallel register. They load data into one side 10 bits wide. Byte transfers can be Data or Command
and output it on the other, except in this case, the “other” signaling.
side is separated by a long serial link.

BLOCK DIAGRAM
Am7968
Data Command
N M

Strobe (STRB) Strobe &

Input Latch
Acknowledge (ACK Acknowledge

X1
Oscillator Encoder Latch
and
X2 Clock Gen.
Clock (CLK)

Data Encoder
Data Mode Select (DMS)

Media (SEROUT+) Serial Out +

Shifter Interface
Test Serial In Serial Interface (SEROUT–) Serial Out –
(TSERIN)
Test/Local Select (TLS)
07370F-1
Note:
N can be 8, 9, or 10 bits; total of N + M = 12.

Publication# 07370 Rev. F Amendment /0

Issue Date: April 1994
AMD

BLOCK DIAGRAM (continued)

Am7969
(X1)
Oscillator
and
Serial In+ (SERIN+) Media Clock Gen.
Shifter
Serial In– (SERIN–) Interface (X2)

PLL Clock
Generator
Decoder Latch

(DMS) Data Mode Select

Data Decoder Byte Sync (CNB) Catch Next Byte

Logic (IGM) I-Got-Mine

Output Latch (CLK) Clock

N M (DSTRB) Data Strobe

(VLTN)
Violation Data Command
Note: (CSTRB) Command Strobe
N can be 8, 9, or 10 bits Total of N + M = 12 07370F-2

CONNECTION DIAGRAMS
Top View
Am7968

DIPs LCC/PLCC

1 28
SEROUT+

ACK DI5
SEROUT-

STRB 2 27 DI4
STRB
ACK
DI5
DI4
DI3

SEROUT+ 3 26 DI3
SEROUT– 4 25 DI2
4 3 2 1 28 27 26
VCC2 (ECL) 5 24 DI1
6 23 VCC2 (ECL) 5 25 DI2
VCC1 (TTL) DI0
7 22 VCC1 (TTL) 6 24 DI1
VCC3 (CML) GND1 (TTL)
RESET 8 21 GND2 (CML) VCC3 (TTL) 7 23 DI0

DMS 9 20 X1 RESET 8 22 GND1 (TTL)

TLS 10 19 X2 DMS 9 21 GND2 (CML)

TSERIN 11 18 CLK TLS 10 20 X1

CI0 12 17 DI6 TSERIN 11 19 X2
CI1 13 16 DI7 12 13 14 15 16 17 18
07370F-4
DI9/CI2 14 15 DI8/CI3
CI0
CI1
DI9/CI2
DI8/CI3
DI7
DI6
CLK

07370F-3

Note:
Pin 1 is marked for orientation.

2 Am7968/Am7969
AMD

CONNECTION DIAGRAMS (continued)

Top View
Am7969
DIPs LCC/PLCC

DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO3 1 28 DO4
DO2 2 27 DO5
4 3 2 1 28 27 26
DO1 3 26 DO6
4 25 IGM 5 25 DO7
DO0 DO7
5 24 RESET 6 24 CNB
IGM CNB
6 23 VCC1 (TTL) 7 23 X2
RESET X2
7 22 VCC2 (CML) 8 22 X1
VCC1 (TTL) X1
8 21 GND2 (CML) SERIN+ 9 21 GND2 (CML)
VCC2 (CML)
SERIN+ 9 20 GND1 (TTL) SERIN- 10 20 GND1 (TTL)
SERIN– 10 19 CLK DMS 11 19 CLK
DMS 11 18 DO8/CO3 12 13 14 15 16 17 18
DSTRB 12 17 DO9/C02

DSTRB
CSTRB
VLTN
CO0
CO1
DO9/CO2
DO8/CO3
CSTRB 13 16 CO1 07370F-6

VLTN 14 15 CO0

07370F-5

Note:
Pin 1 is marked for orientation.

LOGIC SYMBOLS

Am7968 Am7969

TLS DMS RESET CNB DMS RESET

12 2 2 12
DIn/CIm SEROUT+ SERIN+ DOn/COm

VLTN
STRB
ACK DSTRB
X1 X1
CSTRB
X2 X2
IGM

TSERIN CLK CLK

07370F-7 07370F-8
VCC = Power Supply (3) VCC = Power Supply (2)
GND = Ground (2) GND = Ground (2)

Am7968/Am7969 3
AMD

ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is
formed by a combination of:

AM7968
AM7969 –125 D C

TEMPERATURE RANGE
C = Commerical (0°C to +70°C)

PACKAGE TYPE
D = 28-Pin Ceramic DIP (CD 028)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)

SPEED OPTION
-125 = Max Serial Encoded
Transmission Rate is 125 MHz
-175 = Max Serial Encoded
Transmission Rate is 175 MHz

DEVICE NUMBER/DESCRIPTION
Am7968 TAXIchip Transmitter
Am7969 TAXIchip Receiver

Valid Combinations Valid Combinations

AM7968-125 Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AM7969-125 AMD sales office to confirm availability of specific
DC, JC
AM7968-175 valid combinations and to check on newly released
AM7969-175 combinations.

4 Am7968/Am7969
AMD

MILITARY ORDERING INFORMATION

CPL Products
AMD products for Aerospace and Defense applications are available in several packages and operating ranges. CPL (Controlled
Products List) products are compliant with MIL-STD-883C requirements with exceptions for VCC or operating temperature. The
order number (Valid Combination) is formed by a combination of:

AM7968
AM7969 -125 /L K C

C = Controlled Product List

TEMPERATURE RANGE
K = –30°C to 125°C
M = –55°C to 125°C

PACKAGE TYPE
D = 28-Pin Ceramic DIP (CD 028)
L = 28-Pin Ceramic Leadless Chip
Carrier (CL 028)

SPEED OPTION
-125 = Max Serial Encoded Transmission
Rate is 125 MHz

DEVICE NUMBER/DESCRIPTION
Am7968 – TAXIchip Transmitter (Local Mode only)
Am7969 – TAXIchip Receiver (Local Mode only)

Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.

Group A Tests
Group A tests consist of Subgroups
1, 2, 3, 7, 8, 9, 10, 11.

Valid Combinations
Pkg Temps (TC) VCC CPL Part Number SMD Part Number APL Part Number

LCC –30°C to 125°C 4.5 V to 5.5 V AM7968-125/LKC

LCC –55°C to 125°C 4.75 V to 5.5 V 5962-9052701M3A AM7968-125V/B3A

DIP –30°C to 125°C 4.5 V to 5.5 V AM7968-125/DKC

DIP –55°C to 125°C 4.75 V to 5.5 V 5962-9052701MXA AM7968-125V/BXA

LCC –30°C to 125°C 4.5 V to 5.5 V AM7969-125/LKC

LCC –55°C to 125°C 4.75 V to 5.5 V 5962-9052801M3A AM7969-125V/B3A

DIP –30°C to 125°C 4.5 V to 5.5 V AM7969-125/DKC

DIP –55°C to 125°C 4.75 V to 5.5 V 5962-9052801MXA AM7969-125V/BXA

Am7968/Am7969 5
AMD

PIN DESCRIPTION Command. When it is wired to VCC, the Am7968

Transmitter will assume Data to be nine bits wide, with
Am7968 TAXIchip Transmitter three bits of Command. If DMS is left floating (or termi-
ACK nated to 1/2 VCC), the Am7968 will assume Data to be
Input-Strobe Acknowledge (TTL Output) ten bits wide, with two bits of Command.
ACK High signifies that the Am7968 is ready to accept
new Data and Command. The timing of ACK’s response
GND1, GND2
Ground Pins
to STRB depends on the condition of the Input Latch (in
given CLK cycle). GND1 is a TTL I/O Ground and GND2 is an internal
Logic and Analog Ground.
If the Input Latch is empty, data is immediately stored
and ACK closely follows STRB. If the Input Latch con- RESET
tains previously stored data when STRB is asserted, PLL RESET (Input)
ACK is delayed until the next falling edge of CLK. Note This pin is normally left open, but can be momentarily
that for ACK to rise STRB must maintain HIGH for both grounded to force the internal PLL to reactivate lock.
of the above conditions. This allows for correction in the unlikely occurrence of
PLL lockup on application of power.
CI0 – CI1
Parallel Command In (TTL Inputs) RESET has an internal pull-up resistor which causes it
These two inputs accept parallel command information to float high when left unconnected (50 K ohm nominal).
from the host system. If one or more command bits are
If this board is driven by a board Reset signal, an open
logic “1”, the command bit pattern is latched, encoded,
drain (or open collector) style output should be used to
and transmitted in place of any pattern on the
insure the High level signal is at VCC.
Data inputs.

CLK SEROUT+, SEROUT–

Differential Serial Data Out (Differential Open Emit-
Clock (TTL I/O)
ter ECL Outputs)
CLK is an I/O pin that supplies the byte-rate clock refer-
These differential ECL outputs generate data at ECL
ence to drive all internal logic. When TLS is connected to
voltage levels referenced to +5.0 V. When connected to
ground (Local mode), CLK is enabled as a free-running
appropriated pull down resistors, they are capable of
(byte-rate) clock output which runs at the Crystal Oscil-
driving 50-Ω terminated lines, either directly or through
lator frequency; this output can be used to drive the X1
isolating capacitors.
input of TAXIchip Receivers or other system logic. In
Test mode CLK becomes an input. In Test Mode 1 CLK STRB
is a Byte rate input and in Test Mode 2 it is a Bit Input Strobe Signal (TTL Input)
rate input.
A rising edge on the STRB input causes the Data (DI0 –
DI0 – DI7 DI9) or the Command (CI0 – CI3) inputs to be latched
Parallel Data In (TTL Inputs) into the Am7968 Transmitter. The STRB signal is nor-
mally taken LOW after ACK has risen.
These eight inputs accept parallel data from the host
system, to be latched, encoded and transmitted. TLS
Test/Local Select (Input)
DI8/CI3
Parallel Data (8) In or Command (3) In (TTL Input) TLS input determines the mode of operation. When TLS
is wired to GND, the Am7968 Transmitter assumes a
DI8/CI3 input is either Data or Command, depending
Local mode connection to the media. It will output NRZI
upon the state of DMS.
encoded data, and will enable its CLK output driver. The
DI9/CI2 TLS pin should always be grounded during normal
Parallel Data (9) In or Command (2) In (TTL Input) operation.

DI9/CI2 input is either Data or Command, depending When TLS is wired to VCC (Test Mode 1),the serial data
upon the state of DMS. is NRZ, CLK becomes an input, and ACK timing is modi-
fied. This mode is only used for Automatic Test Equip-
DMS ment (ATE) testing at full speed.
Data Mode Select (Input)
When this input is left unconnected, it floats to an inter-
Data Mode Select input determines the Data pattern
mediate level which puts the Am7968 Transmitter into
width. When it is wired to GND, the Am7968 Transmitter
its Test Mode 2. In Test Mode 2, the internal clock
will assume Data to be eight bits wide, with four bits of

6 Am7968/Am7969
AMD

multiplier is switched out, and the internal logic is X1, X2

clocked directly from the CLK pin. Test Mode 2 is in- Crystal Oscillator Inputs (Inputs)
cluded to ease Automatic Test Equipment (A.T.E.) test-
The two crystal input pins connect to an internal parallel
ing by making the internal logic of the Transmitter
mode oscillator which operates at the fundamental fre-
synchronous to the external clock instead of the
quency of the external crystal. The byte rate matches
internal PLL.
the crystal frequency. During normal operation, the byte
TSERIN rate is set by the crystal frequency.
Test Serial Input (Pseudo ECL Input) Alternatively, X1 can be driven by an external TTL fre-
This pin is left unconnected in Local Mode operation. quency source. In multiple TAXI systems this external
TSERIN can be used to input serial data patterns into source could be another Am7968’s CLK output.
the Shifter in Test Mode 1 operation.

VCC1, VCC2, VCC3

Power Supply
VCC1, VCC2, and VCC3 are +5.0 volt nominal power sup-
ply pins. VCC1 powers TTL I/O, VCC2 powers ECL and
VCC3 powers internal Logic and Analog circuitry.

Am7968/Am7969 7
AMD

Am7969 TAXIchip Receiver DO0 – DO7

Parallel Data Out (TTL Outputs)
CLK
Clock (TTL Output) These eight outputs reflect the most recent Data re-
ceived by the Am7969 Receiver.
This is a free-running clock output which runs at the byte
rate, and is synchronous with the serial input. It falls at DO8/CO3
the time that the Decoder Latch is loaded from the Parallel Data (8) Out or Command (3) Out
Shifter, and rises at mid-byte. The CLK output of the Re- (TTL Output)
ceiver is not suitable as a frequency source for another
TAXI Transmitter or Receiver. It is intended to be used DO8/CO3 output will be either a Data or Command bit,
by the host system as a clock synchronous with the re- depending upon the state of DMS.
ceived data.
DO9/CO2
CNB Parallel Data (9) Out or Command (2) Out
Catch Next Byte Input (TTL Input) (TTL Output)
If this input is connected to the CLK output, the Receiver DO9/CO2 output will be either a Data or Command bit,
will be in the Local mode, and each received byte will be depending upon the state of DMS.
captured, decoded and latched to the outputs.
DSTRB
If the CNB input is HIGH, it allows the Am7969 Receiver Output Data Strobe (TTL Output)
to capture the first byte after a sync. The Am7969 Re- The rising edge of this output signals the presence of
ceiver will wait for another sync before latching the data new Data on the DO0 – DO9 lines. Data is valid just be-
out, and capturing another. If CNB is toggled LOW, it will fore the rising edge of DSTRB.
react as if it had decoded a sync byte.
GND1, GND2
In Cascade mode, CNB input is typically connected to Ground
an upstream Am7969’s IGM output. The first Am7969
Receiver in line will have its CNB input connected to
GND1 is a TTL I/O Ground, GND2 is an internal Logic
and Analog Ground.
VCC.

For Am7969-175 applications, an inverter is required IGM

between CLK and CNB for speeds above 140 MHz. See I-Got-Mine (TTL Output)
Figure 3 and Timing Specifications T47A, T47B, T48, This pin signals cascaded Am7969 Receivers that their
and T49. upstream neighbor has captured its assigned data byte.
IGM falls at the mid-byte when the first half of a sync
CO0 – CO1 byte is detected in the Shifter. It rises at mid-byte when it
Parallel Command Out (TTL Output) detects a non-sync pattern. During Local mode opera-
These two outputs reflect the most recent Command tion the IGM signal is undefined.
data received by the Am7969 Receiver.
RESET
CSTRB PLL RESET (Input)
Command Data Strobe (TTL Output) This pin is normally left open, but can be momentarily
The rising edge of this output signals the presence of grounded to force the internal PLL to reactivate lock.
new Command data on the CO0 – CO3 lines. Command This allows for correction in the unlikely occurance of
bits are valid just before the rising edge of CSTRB. PLL Lockup on application of power.

DMS RESET has an internal pull-up resistor (50 K nominal)

Data Mode Select (Input) which causes it to float high when left unconnected.
DMS selects the Data pattern width. When it is wired to If this board is driven by a board Reset signal, an open
GND, the Am7969 Receiver will assume Data to be drain (or open collector) style output should be used to
eight bits wide, with four bits of Command. When it is insure the High level signal is at VCC.
wired to VCC the Am7969 Receiver will assume Data to
be nine bits wide, with three bits of Command. If DMS is SERIN+, SERIN–
left floating (or terminated to 1/2 VCC), the Am7969 Re- Differential Serial Data In (ECL Inputs)
ceiver will assume Data to be ten bits wide, with two bits Data is shifted serially into the Shifter. The SERIN+ and
of Command. SERIN– differential ECL inputs accept ECL voltage

8 Am7968/Am7969
AMD

swings, which are referenced to +5.0 V. When SERIN– same time DOi or COi change and will be followed by
is grounded, the Am7969 is put into Test Mode; SERIN+ either DSTRB or CSTRB. This pin goes LOW when the
becomes a single-ended ECL input, the PLL clock gen- next valid byte is decoded.
erator is bypassed, and X1 determines the bit rate
(rather than the byte rate). Both pins have internal pull X1, X2
down resistors which cause unterminated inputs to Crystal Oscillator Inputs (Inputs)
stay low. These two crystal input pins connect to an internal paral-
lel/mode oscillator which oscillates at the fundamental
VCC1, VCC2 frequency external crystal. During normal operation, the
Power Supply byte rate is set by the crystal frequency. Alternatively,
VCC1 and VCC2 are +5.0 volt nominal power supply pins. X1 can be driven by an external frequency source. In
VCC1 powers TTL I/O, and VCC2 powers internal Logic multiple TAXI systems, this external source could be a
and Analog circuitry. TAXI Transmitter’s CLK output or an external TTL fre-
quency source.
VLTN
Violation (TTL Output)
The rising edge of this output indicates that a transmis-
sion error has been detected. It changes state at the

Am7968/Am7969 9
AMD

FUNCTIONAL DESCRIPTION information remains unchanged. If a Command pattern

is sent to the output latch or if Sync is received, CSTRB
System Configuration is pulsed and Data outputs remain in their previous
The TAXIchip system provides a means of connecting state. Reception of a Sync pattern clears the Command
parallel data systems over a serial link (Figure 2). In outputs to all 0’s, since Sync is a legal command.
LOCAL Mode (normal operation mode) each TX/RX
pair is connected over a serial link which can be a Fiber Noise-induced bit errors can distort transmitted bit pat-
Optic or Copper Media (Figure 3). terns. The Am7969 Receiver logic detects most noise-
induced transmission errors. Invalid bit patterns are
The Am7968 Transmitter accepts inputs from a sending recognized and indicated by the assertion of the viola-
host system using a simple STRB/ACK handshake. tion (VLTN) output pin. This signal rises to a logic “1”
Parallel bits are saved by the Am7968’s input latch on state at the same time that Data or Command outputs
the rising edge of a STRB input. The input latch can be change and remains HIGH until a valid pattern is
updated on every CLK cycle; if it still contains previously detected by the Data Decoder. The error detection
stored data when a second STRB pulse arrives, Data is method used in the Receiver cannot identify bit
stored in the input latch, and the second ACK response errors which transform one valid Command or Data pat-
is delayed until the next CLK cycle. tern to another. Fault-sensitive systems should use ad-
ditional error checking mechanisms to guarantee
The inputs to an Am7968 Transmitter can be either Data
message integrity.
or Command and may originate from two different parts
of the host system. A byte cycle may contain Data or Am7968 Transmitter
Command, but not both. Data represents the normal
The Transmitter accepts messages from its parallel in-
data channel message traffic between host systems.
put pins (Command or Data). Once latched into an
Commands can come from a communication control
Am7968, a parallel message is encoded, serialized, and
section of the host system. Commands occur at a rela-
shifted out to the serial link. The idle time between trans-
tively infrequent rate but have priority over Data. Exam-
mitted bytes (evident by lack of STRB) is filled with
ples include communication specific commands such
Sync bytes.
as REQUEST-TO-SEND or CLEAR-TO-SEND; or
application specific commands such as MESSAGE- Am7969 Receiver
ADDRESS-FOLLOWS, MESSAGE-TYPE-FOLLOWS,
INITIALIZE YOUR SYSTEM, ERROR, RETRANSMIT, Receivers accept differential signals on the SERIN+/
HALT, etc. SERIN– input pins. This information, previously
encoded by an Am7968 Transmitter, is loaded into
The Am7968 Transmitter switches between Data and a decoder.
Command by examining Command input patterns. All
0s on Command input pins cause information on the When serial patterns are received, they are decoded
Am7968’s Data input pins to be latched into the device and routed to the appropriate outputs. If the received
on the rising edge of STRB. All other Command patterns message is a Command, it is stored in the output latch,
cause a Command symbol to be sent in response to an appears at the Command output pins, and CSTRB is
input strobe. The pattern on the Data inputs is ignored pulsed; Data output pins continue holding the last Data
when a Command symbol is sent. In either case, if there byte and DSTRB stays inactive. If a Data message fol-
is no STRB before the next byte boundary, a Sync sym- lows the reception of a Command, Command output
bol will be transmitted. The sync pattern maintains link pins continue holding the previous Command byte and
synchronization and provides an adequate signal transi- CSTRB stays inactive. The command outputs will retain
tion density to keep the Receiver Phase-Locked-Loop their states until another Command signal is received
(PLL) circuits in lock. It was chosen for its unique pattern (Sync is considered to be a valid command which, when
which never occurs in any Data or Command mes- decoded, sets Command outputs to “0” and issues a re-
sages. This feature allows Sync to be used to establish sulting CSTRB).
byte boundaries.
Byte Width
The Sync pattern utilized by TAXIchip set keeps the The TAXIchip set has twelve parallel interface pins
automatic gain control (AGC) fiber-optic transceiver cir- which are designated to carry either Command or Data
cuits in their normal range because the pattern has zero bits. The Data Mode Select (DMS) pin on each chip can
DC offset. be set to select one of three modes of operation: eight
Data and four Command bits, nine Data and three Com-
The Am7969 Receiver detects the difference between
mand, or ten Data and two Command. This allows the
Data and Command patterns and routes each to the
system designer to select the byte-width which best
proper Output Latch. When a new Data pattern enters
suits system needs.
the output latch, DSTRB is pulsed and Command

10 Am7968/Am7969
AMD

Am7968 Encoder/Am7969 Decoder pattern during each clock cycle in which no new Data or
Command messages are being transmitted.
To guarantee that the Am7969’s PLL can stay locked
onto an incoming bit stream, the data encoding scheme Cascade Mode (for –125 only)
must provide an adequate number of transitions in each
data pattern. This implies a limit on the maximum time For very wide parallel buses, TAXI Receiver’s (commer-
allowed between transitions. The TAXIchip set encod- cial temperature parts only) can be Cascaded. The
ing scheme is based on the ANSI X3T9.5 (FDDI) com- Am7969 Receivers all have their SERIN+ and SERIN–
mittee’s 4-bit/5-bit (4B/5B) code. pins connected to the media (or an optical data link).
IGM of each Am7969 is connected to CNB of its down-
An ANSI X3T9.5 system used an 8-bit parallel data pat- stream neighbor or is left unconnected on the Receiver
tern. This pattern is divided into two 4-bit nibbles which farthest downstream. CNB of the first Receiver is tied
are each encoded into a 5-bit symbol. Of the thirty-two HIGH, making this device the only Receiver in the chain
patterns possible with these five bits, sixteen are chosen that can act on the first non-Sync pattern in a message
to represent the sixteen input Data patterns. Some of (see below).
the others are used as Command symbols. Those re-
maining represent invalid patterns that fail either the Each TAXIchip Receiver monitors the serial link and a
run-length test or DC balance tests. special acknowledgment scheme is used to direct sym-
bols into each of the Am7969s. When a Catch-Next-
Transmitters in 8-bit mode use two 4B/5B encoders to Byte (CNB) input is HIGH, the Receiver will capture the
encode eight Data bits into a 10-bit pattern. In 9-bit next non-Sync symbol from the serial link. At this point,
mode, Transmitters use one 5B/6B encoder and one the device forces its I-Got-Mine (IGM) pin HIGH to tell
4B/5B encoder to code nine Data bits into an 11-bit pat- the downstream Receiver to capture the next symbol.
tern. In 10-bit mode, two 5B/6B encoders are used to The Receiver then waits for the Sync symbol or for its
change ten bits of Data into a 12-bit pattern (see Tables CNB to be set LOW before transferring the message to
1 and 2 for encoding patterns). its output latch. IGM is forced LOW whenever a Sync
byte is detected or when CNB goes LOW. This IGM-
The Am7968 Transmitter further encodes all symbols CNB exchange continues down the chain until the last
using NRZI (Non Return to Zero, Invert on Ones). NRZI Receiver captures its respective byte. The next byte to
represents a “1” by a transition and a “0” by the lack of appear on the serial link will be a Sync symbol which is
transition. In this system a “1” can be a HIGH-to-LOW or detected by all of the cascaded Am7969s. On the follow-
LOW-to-HIGH transition. This combination of 4B/5B ing Clock cycle their messages are transferred to the
and NRZI encoding ensures at least two transitions per output latch of each device and sent to the receiving
symbol and permits a maximum of three consecutive host. IGM pins on all Receivers are also set LOW when
non-transition bit times. The Am7969 then uses the the first half of the Sync symbol is detected.
same method to decode incoming symbols so that the
whole encoding/decoding process is transparent to Asynchronous Operation
the user.
Inputs to the Am7968 Transmitter Input Latch can be
Most Serially transmitted data patterns with this code asynchronous to its internal clock. Data STRB will latch
will have the same average amount of HIGH and LOW data into the Am7968 Transmitter and an internal clock
times. This near DC balance minimizes pattern-sensi- will transfer the data to the Encoder Latch at the first
tive decoding errors which are caused by jitter in AC- byte boundary. Data can be entered at any rate less
coupled systems. than the maximum transfer rate without regard to actual
byte boundaries. As data rates approach the TAXI
Operational Modes BYTE RATE, care must be taken to insure that the 2
In normal operational mode, a single Transmitter/ BYTE FIFO inside TAXI Transmitter is not over filled.
Receiver pair is used to transfer 8, 9, or 10 bits of parallel STRB/ACK handshake will assure that every byte is
Data over a private serial link. (On the Am7968, the TLS transferred correctly. At higher byte rates, where delays
pin is tied to ground and TSERIN is left unconnected). and setup/hold times make the STRB/ACK handshake
On the Am7969, CNB must be connected to the CLK impractical, STRB should be synchronized with CLK.
output. The Am7969 Receiver continuously deserial-
Synchronous Operation
izes the incoming bit stream, decodes the resulting pat-
terns, and saves parallel data at its output latches (see The Transmitter may be strobed synchronous by tying
Figure 3). the strobe to the input clock. When doing this a provision
should be make to inhibit the strobe periodically to en-
Local mode provides a fast and efficient parallel sure proper byte alignment. In the absence of a strobe,
throughout because data can be transferred on every Syncs will be transmitted on the serial link which will al-
clock cycle. On the other hand, it is not necessary for the low the receiver to re-align the byte boundaries. In addi-
host to match the byte rate set by the Transmitter’s crys- tion it is essential that the delay between the falling edge
tal oscillator; the Am7968 automatically sends a Sync
Am7968/Am7969 11
AMD

of the internal byte clock (CLK) and the rising edge of data) from having clocks which are too narrow, the out-
strobe does not violate tBB specification shown in the put logic will stretch an output pulse when the pulse
SWITCHING CHARACTERISTICS Section. would have been less than a byte-time long. The data
being processed just prior to this re-acquisition of sync
The internal byte clock controls the flow of data from the will be lost. The Sync symbol, and all subsequent data
input register through the shift register. The falling edge will be processed correctly.
of the internal byte clock delineates the end of one byte
from the start of the next. Due to various tolerances in TAXI User Test Modes
the PLL, the period of the internal byte clock may vary TLS input can be used to force the Am7968 Transmitter
slightly. This effect may cause a shift in the location of into either of the two Test modes. If TLS is open or termi-
the byte boundary with respect to the falling edge of the
nated to approximately VCC/2 (Test Mode 2), the internal
clock. This variation may move the byte boundary and
VCO is switched out and everything is clocked directly
therefore creates a window during which the part should
from the CLK input. The serial output data rate will be at
not be strobed. This window called the t6 window, is the CLK bit rate and not at 10X, 11X, or 12X, as is the
shown in the figure below. If the part is strobed during case in normal operation. Test Mode 2 will allow testing
the t6 window data will not be lost however, a sync may of the logic in the Latches, Encoder, and Shifter without
be added and the transmitter latency will be increased having to first stabilize the PLL clock multiplier. In Test
by one byte time. Mode 1 (TLS wired to VCC), the PLL is enabled and the
chip operates normally, except that the output is an NRZ
stream (CLK is an input & ACK function is slightly modi-
Strobe Stayout Area
(t6 window) fied). This will allow testing of all functions at full rate
without needing to perform match loop tests to accom-
modate the data inversion characteristics of NRZI.
Differential SERIN+/SERIN– inputs can be used to
force the Am7969 Receiver into its Test mode. This will
CLK
allow testing of the logic in the Latches, Decoder, and
Shifter without having to first stabilize the the PLL. If
–9/8(t1/n) + 9 ns
SERIN– is tied to ground, the internal VCO is switched
20 ns
out and X1 becomes the internal bit rate clock. The serial
data rate will be at the CLK bit rate, not at 10X, 11X, or
07370F-9 12X, as is the case in normal operation. In this mode,
Nominal Byte
Boundary SERIN+ becomes a single-ended serial data input with
nominal 100K ECL threshold voltages (Referenced to
+5 volts).
Sync Acquisition
These Test Mode switches make the parts determinate,
In case of errors which cause Am7969 Receivers to lose
synchronous systems, instead of statistical, asynchro-
byte/symbol sync, and on power-up, internal logic de-
nous ones. An automatic test system will be able to
tects this loss-re-acquisition of sync and modifies the
clock each part through the functional test patterns at
CLK output. CLK output is actually a buffered version of
any rate or sequence that is convenient. After the logic
the signal which controls Data transfers inside the
has been verified, the part can be put back into the nor-
Am7969 Receiver on byte boundaries. Byte boundaries
mal mode, and the PLL functions verified knowing that
move when the Am7969 Receiver loses, and re-
the rest of the chip is functional.
acquires sync. To protect slave systems (which may use
this output as a clock synchronous with the incoming

12 Am7968/Am7969
AMD

Oscillator frequency (1st harmonic) and at all odd harmonics of

The Am7968 and Am7969 contain an inverting amplifier this frequency (even harmonic resonance is not me-
intended to form the basis of a parallel mode oscillator. chanically possible). Unless otherwise constrained,
The design of this oscillator considered several factors crystal oscillators operate at their fundamental
related to its application. frequencies.

The first consideration is the desired frequency accu- A typical crystal specification for use in this circuit is:
racy. This may be subdivided into several areas. An os- Fundamental Frequency 3.3 MHz–17.5 MHz ± 0.1%
cillator is considered stable if it is insensitive to
Resonance: Mode Parallel
variations in temperature and supply voltage, and if it is
unaffected by individual component changes and aging. Load Capacitor (Correlation) 30 pF
The design of the TAXIchip set is such that the degree to Operating Temperature Range 0°C to 70°C
which these goals are met is determined primarily by the Temperature Stability ±100 ppm
choice of external components. Various types of crystal Drive Level (Correlation) 2 mW
are available and the manufacturers’ literature should Effective Series Resistance 25 Ω (max)
be consulted to determine the appropriate type. For Holder Type Low profile
good temperature stability, zero temperature coefficient
Aging for 10 years ±10 ppm
capacitors should be used (Type NPO).
It is good practice to ground the case of the crystal to
The mechanism by which a crystal resonates is electro- eliminate stray pick-up and keep all connections as
mechanical. This resonance occurs at a fundamental short as possible.

RESET
Am7968 or, Am7969
Power On RESET (Optional)
X1 X2

C C

07370F-10
C* = 220 pF for 4.0–12.5 MHz crystal, 150 pF for a 12.5–17.5 MHz Crystal.
*C determined by crystal specifications and trace capacities. Values shown are typical.
Figure 1. Connections for 4.0 MHz–17.5 MHz

Am7968/Am7969 13
AMD

Table 1. TAXIchip Encoder Patterns

4B/5B Encoder Scheme 5B/6B Encoder Scheme

4-Bit 5-Bit 5-Bit 6-Bit
HEX Binary Encoded HEX Binary Encoded
Data Data Symbol Data Data* Symbol
0 0000 11110 00 00000 110110
1 0001 01001 01 00001 010001
2 0010 10100 02 00010 100100
3 0011 10101 03 00011 100101
4 0100 01010 04 00100 010010
5 0101 01011 05 00101 010011
6 0110 01110 06 00110 010110
7 0111 01111 07 00111 010111
8 1000 10010 08 01000 100010
9 1001 10011 09 01001 110001
A 1010 10110 0A 01010 110111
B 1011 10111 0B 01011 100111
C 1100 11010 0C 01100 110010
D 1101 11011 0D 01101 110011
E 1110 11100 0E 01110 110100
F 1111 11101 0F 01111 110101

* Note:
HEX data is parallel input data which is represented by the 4- or 5-bit binary data listed in the column to the immediate right
of HEX data. Binary bits are listed from left to right in the following order.
8-Bit Mode: D7, D6, D5, D4, (4-Bit Binary), and D3, D2, D1, D0, (4-Bit Binary)
9-Bit Mode: D8, D7, D6, D5, D4, (5-Bit Binary), and D3, D2, D1, D0, (4-Bit Binary)
10-Bit Mode: D8, D7, D6, D5, D4, (5-Bit Binary), and D9,D3, D2, D1, D0, (5-Bit Binary)
Serial bits are shifted out with the most significant bit of the most significant nibble coming out first.

14 Am7968/Am7969
AMD

Table 2. TAXIchip Command Symbols

Am7968 Transmitter Am7969 Receiver
Command Input Command Output
Encoded
HEX Binary Symbol Mnemonic HEX Binary
8-Bit Mode
0 0000 XXXXX XXXXX Data No Change No Change
(Note 2) (Note 2)
No STRB No STRB 11000 10001 JK (8-bit Sync) 0 0000
(Note 1) (Note 1)
1 0001 11111 11111 I I 1 0001
2 0010 01101 01101 TT 2 0010
3 0011 01101 11001 TS 3 0011
4 0100 11111 00100 IH 4 0100
5 0101 01101 00111 TR 5 0101
6 0110 11001 00111 SR 6 0110
7 0111 11001 11001 SS 7 0111
8 (Note 3) 1000 00100 00100 HH 8 1000
9 1001 00100 11111 HI 9 1001
A (Note 3) 1010 00100 00000 HQ A 1010
B 1011 00111 00111 RR B 1011
C 1100 00111 11001 RS C 1100
D (Note 3) 1101 00000 00100 QH D 1101
E (Note 3) 1110 00000 11111 QI E 1110
F (Note 3) 1111 00000 00000 QQ F 1111
9-Bit Mode
0 000 XXXXXX XXXXX Data No Change No Change
(Note 2) (Note 2)
No STRB No STRB 011000 10001 LK (9-bit Sync) 0 000
(Note 1) (Note 1)
1 001 111111 11111 I’I 1 001
2 010 011101 01101 T’T 2 010
3 011 011101 11001 T’S 3 011
4 100 111111 00100 I’ H 4 100
5 101 011101 00111 T’R 5 101
6 110 111001 00111 S’R 6 110
7 111 111001 11001 S’S 7 111
10-Bit Mode
0 00 XXXXXX XXXXXX Data No Change No Change
(Note 2) (Note 2)
No STRB No STRB 011000 100011 LM (10-bit Sync) 0 00
(Note 1) (Note 1)
1 01 111111 111111 I’I’ 1 01
2 10 011101 011101 T’T’ 2 10
3 11 011101 111001 T’S’ 3 11

Notes:
1. Command pattern Sync cannot be explicitly sent by Am7968 Transmitter with any combination of inputs and STRB,
but is used to pad between user data.
2. A strobe with all Os on the Command input lines will cause Data to be sent. See Table 1.
3. While these Commands are legal data and will not disrupt normal operation if used occasionally, they
may cause data errors if grouped into recurrent fields. Normal PLL operation cannot be guaranteed if one or more
of these commands is continuously repeated.

Am7968/Am7969 15
AMD

Am7968 Transmitter Functional Block CLK (input is multiplied by ten (8-bit mode), eleven (9-bit
Description mode), or twelve (10-bit mode), using the internal PLL to
create the bit rate.
(Refer to page 1)
Crystal Oscillator/Clock Generator The working frequency can be varied between 3.3 MHz
and 17.5 MHz. The crystal frequency required to
The serial link speed is derived from a master frequency
achieve the maximum 175 Mbaud on the serial link, and
source (byte rate). This source can either be the built-in
the resultant usable data transfer rate will be:
Crystal Oscillator, or a clock signal applied through the
X1 pin. This signal is buffered and sent to the CLK out-
put when Am7968 Transmitter is in Local mode.

Crystal Am7968-125 Input and Am7969-125 Internal

Mode Frequency Maximum Parallel Throughput Divide Ratio
8-Bit 12.50 MHz 80 ns/pattern (100 Mbit/sec) 125/10
9-Bit 11.36 MHz 88 ns/pattern (102 Mbit/sec) 125/11
10-Bit 10.42 MHz 96 ns/pattern (104 Mbit/sec) 125/12
Crystal Am7968-175 Input and Am7969-175 Internal
Mode Frequency Maximum Parallel Throughput Divide Ratio
8-Bit 17.50 MHz 57.1 ns/pattern (140 Mbit/sec) 175/10
9-Bit 15.90 MHz 62.8 ns/pattern (143 Mbit/sec) 175/11
10-Bit 14.58 MHz 68.5 ns/pattern (145 Mbit/sec) 175/12

Input Latch Data Encoder

The Am7968’s Input Latch accommodates asynchro- Encodes twelve data inputs (8, 9, 10 Data bits or 4, 3, 2
nous strobing of Data and Command by being divided Command inputs) into 10, 11, or 12 bits. The Command
into two stages. data inputs control the transmitted symbol. If all Com-
mand inputs are LOW, the symbol for the Data bits will
If STRB is asserted when both stages are empty, Data be sent. If Command inputs have any other pattern then
or Command bits are transferred directly to the second the symbol representing that Command will be
stage of the Input Latch and ACK rises shortly after transmitted.
STRB. This pattern is now ready to move to the Encoder
Latch at the next falling edge of CLK. Shifter
An input pattern is strobed into the first stage of the Input The Shifter is parallel-loaded from the Encoder at the
Latch only when the second stage is BUSY (contains first available byte boundary, and then shifted until the
previously stored data). The Transmitter will be BUSY next byte boundary. The Shifter is being serially loaded
when STRB is asserted a second time in a given CLK at all times. As data is being shifted out of the Transmit-
cycle. Contents of the first stage are not protected from ter, the shifter fills from the LSB. If parallel data is avail-
subsequent STRBs within the same CLK cycle. At the able at the end of the byte, it is parallel-loaded into the
falling edge of CLK, previously stored data is transferred Shifter and begins shifting out during the next clock cy-
from the second stage to the Encoder Latch and the new cle. Otherwise, the serially loaded data fills the next
data is clocked into the second stage of the Input Latch. byte. The serial data which loads into the Shifter is gen-
If in Local mode, ACK will rise at this time. erated by an internal state machine which generates a
repeating Sync pattern.
Encoder Latch
Media Interface
Input to the Encoder Latch is clocked by an internal sig-
nal which is synchronous with the shifted byte being The Media Interface is differential ECL, referenced to
sent on the serial link. Whenever a new input pattern is +5 V. It is capable of driving lines terminated with 50 Ω to
strobed into the Input Latch, the data is transferred to the (VCC - 2.0) volts.
Encoder Latch at the next opportunity.

16 Am7968/Am7969
AMD

Am7969 Receiver Functional Block when the first byte after a Sync symbol is transferred.
Description Parallel outputs are made on a byte boundary, after
(Refer to page 1) CNB falls, or when Sync is detected.
Crystal Oscillator/Clock Generator The I-Got-Mine (IGM) signal will fall when the first half of
The data recovery PLL in the Am7969 must be supplied a Sync is detected in the Shifter or when CNB goes
with a reference frequency at the expected byte rate of LOW. It will remain LOW until the first half of a non-Sync
the data to be recovered. The source of this frequency byte is detected in the Shifter, whereupon it will rise (as-
can either be the built-in Crystal Oscillator, or an exter- suming that the CNB input is HIGH). A continuous
nal clock signal applied through the X1 pin. The refer- stream of normal data or command bytes will cause IGM
ence frequency source is then multiplied by ten (8-bit to go HIGH and remain HIGH. A continuous stream of
mode), eleven (9-bit mode) or twelve (10-bit mode) us- Sync’s will cause IGM to stay LOW. IGM will go HIGH
ing an internal PLL. during the byte before data appears at the output. This
feature could be used to generate an early warning of in-
Media Interface coming data.
SERIN+, SERIN– inputs are to be driven by differential
ECL voltages, referenced to +5 V. Serial data at these Decoder Latch
inputs will serve as the reference for PLL tracking. Data is loaded from the Shifter to this latch at each
symbol/byte boundary. It serves as the input to the
PLL Clock Generator Data Decoder.
A PLL Clock recovery loop follows the incoming data
and allows the encoded clock and data stream to be de- Data Decoder
coded into a separated clock and data pattern. It uses Decodes ten, eleven, or twelve data inputs into twelve
the crystal oscillator and clock generator to predict the outputs. In 8-bit mode, data is decoded into either an
expected frequency of data and will track jittered data 8-bit Data pattern or a 4-bit Command pattern. In 9-bit
with a characteristically small offset frequency. mode, data is decoded into either a 9-bit Data pattern or
a 3-bit Command pattern. In 10-bit mode, data is de-
Shifter coded into either a 10-bit Data pattern or a 2-bit Com-
The Shifter is serially loaded from the Media Interface, mand pattern.
using the bit clock generated by PLL.
The decoder separates Data symbols from Command
Byte Sync Logic symbols, and causes the appropriate strobe output to
The incoming data stream is a continuous stream of be asserted.
data bits, without any significant signal which denotes Parallel Output Latch
byte boundaries. This logic will continuously monitor the
data stream, and upon discovering the reserved code Output Latch will be clocked by the byte clock, and will
used for Am7969 Receiver Sync, will initialize a reflect the most recent data on the link. Any Data pattern
synchronous counter which counts bits, and indicates will be latched to the Data outputs and will not affect the
byte boundaries. status of the Command outputs. Likewise, any Com-
mand pattern will be latched to the Command outputs
The logic signal that times data transfers from the Shif- without affecting the state of the Data outputs.
ter to the Decoder Latch is buffered and sent to the CLK
output. CLK output from the Receiver is not suitable as a Any data transfer, either Data or Command will be syn-
frequency source for another TAXI Transmitter or Re- chronous with an appropriate output strobe. However,
ceiver. It is intended to be used by the host system as a there will be CSTRBs when there is no active data on the
clock synchronous with the received data. This output is link, since Sync is a valid Command code.
synchronous with the byte boundary and is synchronous Any pattern which does not decode to a valid Command
with the Receiver’s internal byte clock. or Data pattern is flagged as a violation. The output of
Byte Sync Logic is responsible for generating the inter- the decoder during these violations is indeterminate and
nal strobe signals for Parallel Output Latches. It also will result in either a CSTRB or DSTRB output when the
generates the IGM (I-Got-Mine) signal in Test mode indeterminate pattern is transferred to the output latch.

Am7968/Am7969 17
AMD

Command M M Command
Source Command Command Destination
Signals Signals

STRB CSTRB
Message
Transfer VLTN Data Path
Control Am7968 Am7969 Control
Logic ACK Transmission DSTRB Logic
Media

Data N N Data
Source Destination
Data Data
Signals Signals

07370F-11

Note:
N can be 8, 9, or 10 bits of parallel data; total of N + M = 12.

Figure 2. TAXIchip System Block Diagram

18 Am7968/Am7969
AMD

Message Transfer Control Logic Message Transfer Control Logic

Data Command Data Command

Source Source Source Source

8 4 9 3

DI0 – DI7 CI0 – CI3 STRB ACK DI0 – DI8 CI0 – CI2 STRB ACK
SEROUT+ SEROUT+
SEROUT– TAXI TX #1 SEROUT– TAXI TX #2
(Note
(Note1)1)
TLS DMS X1 X2 CLK X1 X2
TLS DMS CLK

*
(Note 2)
3.3 MHz to
17.5 MHz

To Other Stages
(Note 4) (Note 4)

3.3 MHz to 3.3 MHz to

17.5 MHz 17.5 MHz
* *

SERIN+ SERIN– X1 X2 DMS CLOCK SERIN+ SERIN– X1 X2 DMS CLOCK

CNB TAXI RX #1 IGM CNB TAXI RX #2 IGM

VLTN VLTN
DSTRB DO0– DO7 CO0 – CO3 CSTRB DSTRB DO0 – DO8 CO0 – CO2 CSTRB

8 4 9 3

Data Command Data Command

Destination Destination Destination Destination

Data Path Control Logic Data Path Control Logic

07370F-12
Notes:
1. DMS = GND = 8 Bit Mode TLS = GND = Local Mode Pin 11 = Don’t Connect = Local Mode
2. DMS = VCC = 9 Bit Mode TLS = GND = Local Mode Pin 11 = Don’t Connect = Local Mode
3. Two 8-bit local mode systems in parallel will result in an effective data rate of 200 Mbps.
4. Use inverter for operation above 140 MHz only.
*Alternatively, the X1 inputs may be driven by external TTL frequency sources.

Figure 3. TAXIchip System in Local Mode

Am7968/Am7969 19
AMD

From Serial Media

SERIN– SERIN+ SERIN– SERIN+ SERIN– SERIN+

RX1 DMS RX2 DMS RX3 DMS

VCC
Am7969 Am7969 Am7969
Primary RX
CNB IGM CNB IGM CNB IGM N/C
CLK X2 X1 X2 X1 X2 X1

07370F-13

Crystal
OSC

Figure 4. Cascaded Receiver Clock Connections (Commercial –125 only)

20 Am7968/Am7969
AMD

Am7968/Am7969-125 OPERATING RANGES

ABSOLUTE MAXIMUM RATINGS Commercial (C) Devices
StorageTemperature . . . . . . . . . . . . –65°C to +150°C Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to +70°C
Ambient Temperature Supply Voltage (VCC) . . . . . . . . . . . . +4.5 V to +5.5 V
Under Bias . . . . . . . . . . . . . . . . . . . –55°C to +125°C Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Supply Voltage to Ground
Potential Continuous . . . . . . . . . . . . –0.5 V to +7.0 V
DC Voltage Applied to
Outputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Max
DC Input Voltage . . . . . . . . . . . . . . . –0.5 V to +5.5 V
DC Output Current . . . . . . . . . . . . . . . . . . . ±100 mA
DC Input Current . . . . . . . . . . . . . –30 mA to +5.0 mA
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maxi-
mum ratings for extended periods may affect device reliability.

Am7968/Am7969-125 21
AMD

DC CHARACTERISTICS over operating range unless otherwise specified

Am7968-125 TAXIchip Transmitter
Parameter
Symbol Parameter Description Test Conditions (Note 1) Min Max Unit
Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK
VOH1 Output HIGH Voltage VCC = Min, IOH = –1 mA 2.4 V
ACK VIN = 0 or 3 V
VOH2 Output HIGH Voltage VCC = Min, IOH = –3 mA 2.4 V
CLK VIN = 0 or 3 V
VOL Output LOW Voltage VCC = Min, IOL = 8 mA 0.45 V
ACK, CLK VIN = 0 or 3 V
VIH Input HIGH Voltage VCC = Max (Note 9) 2.0 V
VIL Input LOW Voltage VCC = Max (Note 9) 0.8 V
VI Input Clamp Voltage VCC = Min IIN = –18 mA –1.5 V
IIL Input LOW Current VCC = Max, VIN = 0.4 V –400 µA
IIH Input HIGH Current VCC = Max, VIN = 2.7 V 50 µA
II Input Leakage Current VCC = Max, All Inputs 50 µA
VIN = 5.5 V Except CLK
CLK Input 150 µA
ISC Output Short Circuit (Note 4) –15 –85 mA
Current ACK, CLK
Serial Interface Signals: SEROUT+, SEROUT–
VOH Output HIGH Voltage VCC = Min ECL Load VCC VCC V
–1.025 –0.88
VOL Output LOW Voltage VCC = Min ECL Load VCC VCC V
–1.81 –1.62
Miscellaneous Signals: X1, VCC1, VCC2, VCC3
VIHX Input HIGH Voltage X1 2.0 V
VILX Input LOW Voltage X1 0.8 V
IILX Input LOW Current X1 VIN = 0.45 V –900 µA
IIHX Input HIGH Current X1 VIN = 2.4 V +600 µA
ICC Supply Current SEROUT = ECL Pin VCC1 (TTL) 20 mA
Load, DMS = 0
Pin VCC2 (ECL) 45 mA
VCC1 = VCC2 =
VCC3 = Max Pin VCC3 (CML) 200 mA

*See notes following end of Switching Characteristics tables.

22 Am7968/Am7969-125
AMD

Am7969-125 TAXIchip Receiver

Parameter
Symbol Parameter Description Test Conditions (Note 1) Min Max Unit
Bus Interface Signals: DO0–DO7, DO8/CO3, DO9/CO2, CO0–CO1, DSTRB, CSTRB, IGM, CLK, CNB, VLTN
VOH Output HIGH Voltage VCC = Min, IOH = –1 mA 2.4 V
VIN = 0 or 3 V
VOL Output LOW Voltage VCC = Min, IOL = 8 mA 0.45 V
VIN = 0 or 3 V
VIH Input HIGH Voltage VCC = Max (Note 9) 2.0 V
VIL Input LOW Voltage VCC = Max (Note 9) 0.8 V
VI Input Clamp Voltage VCC = Min, IIN = –18 mA –1.5 V
IIL Input LOW Current VCC = Max, VIN = 0.4 V –400 µA
IIH Input HIGH Current VCC = Max, VIN = 2.7 V 50 µA
II Input Leakage Current VCC = Max, VIN = 5.5 V 50 µA
ISC Output Short Circuit –15 –85 mA
Current (Note 4)
Serial Interface Signals: SERIN+, SERIN–
VIHS Input HIGH Voltage (Notes 9, 21) VCC VCC V
SERIN+ –1.165 –0.88
VILS Input LOW Voltage (Notes 9, 21) VCC VCC V
SERIN+ –1.81 –1.475
VTHT Test Mode Threshold VCC = Max 0.25 V
SERIN–
VDIF Differential Input Voltage 0.3 1.1 V
VICM Input Common Mode (Note 6) 3.05 VCC V
Voltage –0.55
IIL Input LOW Current VCC = Max, VIN = VCC –1.81 V 0.5 µA
IIH Input HIGH Current VCC = Max, 220 µA
VIN = VCC –0.88 V
Miscellaneous Signals: X1, VCC1, VCC2
VIHX Input HIGH Threshold X1 2.0 V
VILX Input LOW Threshold X1 0.8 V
IILX Input LOW Current X1 VIN = 0.45 V –900 µA
IIHX Input HIGH Current X1 VIN = 2.4 V +600 µA
ICC Supply Current VCC1 = VCC2 = Max Pin VCC1 (TTL) 50 mA
DMS = 0 V Pin VCC2 (CML) 300 mA

Am7968/Am7969-125 23
AMD

SWITCHING CHARACTERISTICS (Note 20)

Am7968-125 TAXIchip Transmitter (Notes 10, 13, 22)
Parameter
No. Symbol Parameter Description Test Conditions Min Max Units
Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK
1 tP CLK Period 8n 25n ns
2 tPW CLK Pulse Width HIGH 30 ns
3 tPW CLK Pulse Width LOW 30 ns
4 tPW STRB Pulse Width HIGH (Note 7) 15 ns
5 tPW STRB Pulse Width LOW 15 ns
6 tBB Internal Byte Boundary to CLK↓ –9t1 20 ns
(Note 11) 8n +9
9 tS Data–STRB Setup Time 5 ns
10 tH Data–STRB Hold Time 15 ns
11 tH ACK↑ to STRB↓ Hold (Note 8) TTL Output Load 0 ns
12 tH ACK↓ to STRB↑ Hold TTL Output Load 0 ns
13 tPD STRB↑ to ACK↑ (Note 18) TTL Output Load 40 ns
14 tPD STRB↓ to ACK↓ TTL Output Load 23 ns
15 tPD CLK↓ to ACK↑ (Note 18) TTL Output Load 3t1 ns
n + 33
Serial Interface Signals: SEROUT+, SEROUT– (Note 2)
22 tSK✝ SEROUT± Skew ECL Output Load –200 +200 ps
23 tR ✝ SEROUT± Output Rise Time ECL Output Load .45 2 ns
24 tF✝ SEROUT± Output Fall Time ECL Output Load .45 2 ns
26 tPW✝ SEROUT ± Pulse Width LOW ECL Output Load t1 t1 ns
n – 5% n + 5%
27 tPW✝ SEROUT ± Pulse Width HIGH ECL Output Load t1 t1 ns
n – 5% n + 5%
Miscellaneous Signals: X1 (Note 15)
29 tPW X1 Pulse Width HIGH (Note 12) TTL Output Load on CLK 35 ns
30 tPW X1 Pulse Width LOW (Note 12) TTL Output Load on CLK 35 ns
32 tPD X1 ↑ to CLK↑ TTL Load 32 ns
33 tPD X1 ↓ to CLK↓ TTL Load 32 ns

24 Am7968/Am7969-125
AMD

Am7969-125 TAXIchip Receiver (Notes 13, 14, 22)

Parameter
No. Symbol Parameter Description Test Conditions Min Max Unit
Bus Interface Signals: DO0–DO7,DO8/CO3,DO9/CO2,CO0–CO1,DSTRB,CSTRB, IGM,CLK,CNB,VLTN
35 tP CLK Period (Note 24) 8n 25n ns
36 tPD Data Valid to STRB↑ Delay TTL Output Load 2t35 ns
n
37 tPD CLK↓ to STRB↑ TTL Output Load 2t35 ns
n +15
38 tPD CLK↑ to STRB↓ TTL Output Load t35 ns
n –7
3t35
38a tPD STRB↑ to CLK↑ (Note 23) TTL Output Load n –14 ns

39 tPD CLK↓ to Data Valid Delay TTL Output Load t35 ns

- n +23

40 tPW STRB Pulse Width HIGH TTL Output Load 5t35 5t35 ns
2n n

41 tPW CLK Pulse Width HIGH TTL Output Load 5t35 ns

n –15
42 tPW CLK Pulse Width LOW TTL Output Load 5t35 ns
n –15

43 tPD SERIN to CLK↓ Delay TTL Output Load t35 2t35 ns

2n +17 n +26
2t35
44 tPD CLK↑ to IGM↓ TTL Output Load ns
n +7

45 tPD CLK↑ to IGM↑ TTL Output Load 2t35 ns

n +10

46 tPD CNB↓ to IGM↓ TTL Output Load 20 ns

47 tS CNB↑ to CLK↑ Setup Time 2t35 ns
- n –32
(Note 5)
47A tS CNB↓ to CLK↑ Setup Time t35 ns
- n –31
(Note 19)
2t35
48 tH CNB↓ to CLK↑ Hold n +5 ns
2t35
49 tPW CNB Pulse Width LOW n ns

Serial Interface Signals: SERIN+, SERIN–

57 tJ✝ SERIN± Peak to Peak Input Jitter 5 ns
Tolerance (Note 16)
Miscellaneous Signals: X1 (Note 15)
60 tPW X1 Pulse Width HIGH 35 ns
61 tPW X1 Pulse Width LOW 35 ns

Am7968/Am7969-125 25
AMD

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26 Am7968/Am7969-175
AMD

Am7968/Am7969-175 OPERATING RANGES

ABSOLUTE MAXIMUM RATINGS Commercial (C) Devices
StorageTemperature . . . . . . . . . . . . –65°C to + 50°C Temperature (TC) . . . . . . . . . . . . . . 0°C to +70°C
Ambient Temperature Supply Voltage (VCC) . . . . . . . . . +4.5 V to +5.5 V
Under Bias . . . . . . . . . . . . . . . . . . . –55°C to +125°C Operating ranges define those limits between which the func-
Supply Voltage to Ground tionality of the device is guaranteed.
Potential Continuous . . . . . . . . . . . . –0.5 V to +7.0 V
DC Voltage Applied to
Outputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Max
DC Input Voltage . . . . . . . . . . . . . . . –0.5 V to +5.5 V
DC Output Current . . . . . . . . . . . . . . . . . . . +100 mA
DC Input Current . . . . . . . . . . . . . –30 mA to +5.0 mA
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maxi-
mum ratings for extended periods may affect device reliability.

Am7968/Am7969-175 27
AMD

DC CHARACTERISTICS over operating range unless otherwise specified

Am7968-175 TAXIchip Transmitter
Parameter
Symbol Parameter Description Test Conditions (Note 1) Min Max Unit
Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK
VOH1 Output HIGH Voltage VCC = Min, IOH = –1 mA 2.4 V
ACK VIN = 0 or 3 V
VOH2 Output HIGH Voltage VCC = Min, IOH = –3 mA 2.4 V
CLK VIN = 0 or 3 V
VOL Output LOW Voltage VCC = Min, IOL = 8 mA 0.45 V
ACK, CLK VIN = 0 or 3 V
VIH Input HIGH Voltage VCC = Max (Note 9) 2.0 V
VIL Input LOW Voltage VCC = Max (Note 9) 0.8 V
VI Input Clamp Voltage VCC = Min IIN = –18 mA –1.5 V
IIL Input LOW Current VCC = Max, VIN = 0.4 V –400 µA
IIH Input HIGH Current VCC = Max, VIN = 2.7 V 50 µA
II Input Leakage Current VCC = Max, All Inputs 50 µA
VIN = 5.5 V Except CLK
CLK Input 150 µA
ISC Output Short Circuit (Note 4) –15 –85 mA
Current ACK, CLK
Serial Interface Signals: SEROUT+, SEROUT–
VOH Output HIGH Voltage VCC = Min ECL Load VCC VCC V
–1.025 –0.88
VOL Output LOW Voltage VCC = Min ECL Load VCC VCC V
–1.81 –1.62
Miscellaneous Signals: X1, VCC1, VCC2, VCC3
VIHX Input HIGH Voltage X1 2.0 V
VILX Input LOW Voltage X1 0.8 V
IILX Input LOW Current X1 VIN = 0.45 V –900 µA
IIHX Input HIGH Current X1 VIN = 2.4 V +600 µA
ICC Supply Current SEROUT = ECL Pin VCC1 (TTL) 20 mA
Load, DMS = 0
Pin VCC2 (ECL) 45 mA
VCC1 = VCC2 =
VCC3 = Max Pin VCC3 (CML) 200 mA
*See notes following end of Switching Characteristics tables.

28 Am7968/Am7969-175
AMD

Am7969-175 TAXIchip Receiver

Am7968/Am7969-175 29
AMD

SWITCHING CHARACTERISTICS (Note 20)

Am7968-175 TAXIchip Transmitter (Notes 10, 13, 22)
Parameter
No. Symbol Parameter Description Test Conditions Min Max Units
Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK
1 tP CLK Period 5.7 n 8n ns
2 tPW CLK Pulse Width HIGH 20 ns
3 tPW CLK Pulse Width LOW 20 ns
4 tPW STRB Pulse Width HIGH (Note 7) 15 ns
5 tPW STRB Pulse Width LOW 15 ns
6 tBB Internal Byte Boundary to CLK↓ –9t1 20 ns
(Note 11) 8n +9
9 tS Data–STRB Setup Time 5 ns
10 tH Data–STRB Hold Time 15 ns
11 tH ACK↑ to STRB↓ Hold (Note 8) TTL Output Load 0 ns
12 tH ACK↓ to STRB↑ Hold TTL Output Load 0 ns
13 tPD STRB↑ to ACK↑ (Note 18) TTL Output Load 40 ns
14 tPD STRB↓ to ACK↓ TTL Output Load 23 ns
15 tPD CLK↓ to ACK↑ (Note 18) TTL Output Load 3t1 ns
n + 33
Serial Interface Signals: SEROUT+, SEROUT– (Note 2)
22 tSK✝ SEROUT± Skew ECL Output Load –200 +200 ps
23 tR ✝ SEROUT± Output Rise Time ECL Output Load .45 2 ns
24 tF✝ SEROUT± Output Fall Time ECL Output Load .45 2 ns
26 tPW✝ SEROUT ± Pulse Width LOW ECL Output Load t1 t1 ns
n – 5% n + 5%
27 tPW✝ SEROUT ± Pulse Width HIGH ECL Output Load t1 t1 ns
n – 5% n + 5%
Miscellaneous Signals: X1 (Note 15)
29 tPW X1 Pulse Width HIGH (Note 12) TTL Output Load on CLK 24 ns
30 tPW X1 Pulse Width LOW (Note 12) TTL Output Load on CLK 24 ns
32 tPD X1↑ to CLK↑ TTL Load 32 ns
33 tPD X1↓ to CLK↓ TTL Load 32 ns

30 Am7968/Am7969-175
AMD

Am7969-175 TAXIchip Receiver (Notes 13, 14, 22)

Parameter
No. Symbol Parameter Description Test Conditions Min Max Unit
Bus Interface Signals: DO0–DO7, DO8/CO3, DO9/CO2, CO0–CO1, DSTRB, CSTRB, IGM, CLK, CNB, VLTN
35 tP CLK Period (Note 24) 5.7 n 8 n ns
36 tPD Data Valid to STRB↑ Delay TTL Output Load 2t35 ns
–2
n
37 tPD CLK↓ to STRB↑ TTL Output Load 2t35 ns
n +15

38 tPD CLK↑ to STRB↓ TTL Output Load t35 ns

n –5

38a tPD STRB↑ to CLK↑ (Note 23) TTL Output Load 3t35 ns
n –10

39 tPD CLK↓ to Data Valid Delay TTL Output Load t35 ns

- n +23

40 tPW STRB Pulse Width HIGH TTL Output Load 5t35 5t35 ns
2n n
41 tPW CLK Pulse Width HIGH TTL Output Load 5t35 ns
n –7
42 tPW CLK Pulse Width LOW TTL Output Load 5t35 ns
n –4

43 tPD SERIN to CLK↓ Delay TTL Output Load t35 2t35 ns

2n +17 n +26

47A tS CNB↓ to CLK↑ Setup Time t35 ns

- n –31
(Note 19)

47B tS CNB↑ to CLK↓ Setup Time 29 ns

48 tH CNB↓ to CLK↑ Hold 2t35 ns
n –3

49 tPW CNB Pulse Width LOW 2t35 ns

n
Serial Interface Signals: SERIN+, SERIN–
57 tJ✝ SERIN± Peak to Peak Input Jitter 2 ns
Tolerance (Note 16)
Miscellaneous Signals: X1 (Note 15)
60 tPW X1 Pulse Width HIGH 21 ns
61 tPW X1 Pulse Width LOW 21 ns

Am7968/Am7969-175 31
AMD

(Page intentionally left blank)

32 Am7968/Am7969-125 Military
AMD

Am7968/Am7969-125 MILITARY OPERATING RANGES

ABSOLUTE MAXIMUM RATINGS Military (SMD) Devices
StorageTemperature . . . . . . . . . . . . –65°C to +150°C 5962-9052701M3A
5962-9052701MXA
Ambient Temperature
5962-9052801M3A
Under Bias . . . . . . . . . . . . . . . . . . . –55°C to +125°C
5962-9052801MXA
Supply Voltage to Ground
Temperature (TC) . . . . . . . . . . . . –55°C to +125° C
Potential Continuous . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC) . . . . . . . . . . . +4.75 V to +5.5 V
DC Voltage Applied to
Outputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Max Military (CPL) Devices
Am7968-125/LKC
DC Input Voltage . . . . . . . . . . . . . . . –0.5 V to +5.5 V
Am7968-125/DKC
DC Output Current . . . . . . . . . . . . . . . . . . . ±100 mA Am7969-125/LKC
DC Input Current . . . . . . . . . . . . . –30 mA to +5.0 mA Am7969-125/DKC
Stresses above those listed under Absolute Maximum Rat- Temperature (TC) . . . . . . . . . . . . . –30°C to +125° C
ings may cause permanent device failure. Functionality at or Supply Voltage (VCC) . . . . . . . . . . . . +4.5 V to +5.5 V
above these limits is not implied. Exposure to absolute maxi-
mum ratings for extended periods may affect device reliability. Operating ranges define those limits between which the func-
tionality of the device is guaranteed.

Am7968/Am7969-125 Military 33
AMD

DC CHARACTERISTICS over operating range unless otherwise specified (for CPL Prod-
ucts Group A, Subgroups 1, 2, 3 are tested unless otherwise noted)
Am7968-125 Military TAXIchip Transmitter
Parameter
Symbol Parameter Description Test Conditions (Note 1) Min Max Unit
Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK
VOH1 Output HIGH Voltage VCC = Min, IOH = –1 mA 2.4 V
ACK VIN = 0 or 3 V
VOH2 Output HIGH Voltage VCC = Min, IOH = –1 mA 2.4 V
CLK VIN = 0 or 3 V
VOL Output LOW Voltage VCC = Min, IOL = 8 mA 0.45 V
ACK, CLK VIN = 0 or 3 V
VIH Input HIGH Voltage VCC = Max (Note 9) TC = –30 to +125°C 2.0 V
TC = –55 to +125°C 2.1 V
VIL Input LOW Voltage VCC = Max (Note 9) 0.8 V
VI Input Clamp Voltage VCC = Min IIN = –18 mA –1.5 V
IIL Input LOW Current VCC = Max, VIN = 0.4 V –400 µA
IIH Input HIGH Current VCC = Max, VIN = 2.7 V 50 µA
II Input Leakage Current VCC = Max, All Inputs 50 µA
VIN = 5.5 V Except CLK
CLK Input 150 µA
ISC Output Short Circuit (Note 4) –15 –85 mA
Current ACK, CLK
Serial Interface Signals: SEROUT+, SEROUT–
VOH Output HIGH Voltage VCC = Min ECL Load VCC VCC V
–1.165 –0.88
VOL Output LOW Voltage VCC = Min ECL Load VCC VCC V
–1.81 –1.62
Miscellaneous Signals: X1, VCC1, VCC2, VCC3
VIHX Input HIGH Voltage X1 VCC = Max (Note 9) TC = –30 to +125°C 2.0 V
TC = –55 to +125°C 2.1 V
VILX Input LOW Voltage X1 0.8 V
IILX Input LOW Current X1 VIN = 0.45 V –900 µA
IIHX Input HIGH Current X1 VIN = 2.4 V +600 µA
ICC Supply Current SEROUT = ECL Pin VCC1 (TTL) 30 mA
Load, DMS = 0
VCC1 = VCC2 = Pin VCC2 (ECL) 45 mA
VCC3 = Max
Pin VCC3 (CML) 215 mA

*See notes following end of Switching Characteristics tables.

34 Am7968/Am7969-125 Military
AMD

Am7969-125 Military TAXIchip Receiver

Am7968/Am7969-125 Military 35
AMD

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

(Note 20) (for CPL Products Group A, Subgroups 9, 10, and 11 are tested unless other-
wise noted)
Am7968-125 Military TAXIchip Transmitter (Notes 10, 13, 22)
Parameter
No. Symbol Parameter Description Test Conditions Min Max Units
Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK
1 tP CLK Period 8n 25 n ns
2 tPW CLK Pulse Width HIGH 25 ns
3 tPW CLK Pulse Width LOW 25 ns
4 tPW STRB Pulse Width HIGH (Note 7) 20 ns
5 tPW STRB Pulse Width LOW 20 ns
6 tBB Internal Byte Boundary to CLK↓ –9t1 25 ns
(Note 11) 8n +3
9 tS Data–STRB Setup Time 10 ns
10 tH Data–STRB Hold Time 15 ns
11 tH ACK↑ to STRB↓ Hold (Note 8) TTL Output Load 0 ns
12 tH ACK↓ to STRB↑ Hold TTL Output Load 0 ns
13 tPD STRB↑ to ACK↑ (Note 18) TTL Output Load 45 ns
14 tPD STRB↓ to ACK↓ TTL Output Load 25 ns
15 tPD CLK↓ to ACK↑ (Note 18) TTL Output Load 3t1 ns
n + 43
Miscellaneous Signals: X1 (Note 15)
29 tPW X1 Pulse Width HIGH (Note 12) TTL Output Load on CLK 35 ns
30 tPW X1 Pulse Width LOW (Note 12) TTL Output Load on CLK 35 ns
32 tPD X1↑ to CLK↑ TTL Load 32 ns
33 tPD X1↓ to CLK↓ TTL Load 32 ns

36 Am7968/Am7969-125 Military
AMD

Am7969-125 Military TAXIchip Receiver (Notes 13, 14, 22)

Parameter
No. Symbol Parameter Description Test Conditions Min Max Unit
Bus Interface Signals: DO0–DO7, DO8/CO3, DO9/CO2, CO0–CO1, DSTRB, CSTRB, IGM, CLK, CNB, VLTN
35 tP CLK Period (Note 24) 8n 25 n ns
36 tPD Data Valid to STRB↑ Delay TTL Output Load 2t35 ns
n
37 tPD CLK↓ to STRB↑ TTL Output Load 2t35 ns
n +15
38 tPD CLK↑ to STRB↓ TTL Output Load t35 ns
n –7

38a tPD STRB↑ to CLK↑ (Note 23) TTL Output Load 3t35 ns
n –14

39 tPD CLK↓ to Data Valid Delay TTL Output Load t35 ns

- n +23

40 tPW STRB Pulse Width HIGH TTL Output Load 5t35 5t35 ns
2n n
41 tPW CLK Pulse Width HIGH TTL Output Load 5t35 ns
n –15

42 tPW CLK Pulse Width LOW TTL Output Load 5t35 ns

2n –15
t35 2t35
43 tPD SERIN to CLK↓ Delay TTL Output Load ns
2n +17 n +26
Serial Interface Signals: SERIN+, SERIN–
57 tJ✝ SERIN± Peak to Peak Input Jitter 5 ns
Tolerance (Note 16)
Miscellaneous Signals: X1 (Note 15)
60 tPW X1 Pulse Width HIGH 35 ns
61 tPW X1 Pulse Width LOW 35 ns

Note:
CLK (pin 19) must be connected to CNB (pin 24).

Am7968/Am7969-125 Military 37
AMD

Notes:*
1. For conditions shown as Min or Max use the appropriate value specified under operating range.
2. The clock fall to serial output delay is typically 3 bit times.
4. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
5. If the CNB↑ to CLK↑ setup time is violated, IGM will stay LOW.
6. Voltage applied to either SERIN± pins must not be above VCC nor below +2.5 V to assure proper operation.
7. t4 guarantees that data is latched. ACK (t11) timing may not be valid.
8. If t11 is not met, ACK response and timing are not guaranteed, but data will still be latched on STRB↑ (see t4).
9. Measured with device in Test mode while monitoring output logic states.
10. For the TAXI Transmitter, “n” is determined by the following table:

DMS TLS “n”

8 Bit
OPEN n = 1; Test Mode 2
GND
8 Bit
GND/VCC n = 10; Local/Test Mode 1
9 Bit
OPEN n = 1; Test Mode 2
VCC
9 Bit
GND/VCC n = 11; Local/Test Mode 1

Open OPEN 10 Bit

n = 1; Test Mode 2
or
1 10 Bit
2 VCC GND/VCC n = 12; Local/Test Mode 1

11. t6 (Internal Byte Boundary to CLK↓) is created by the variation of internal STRB propagation delays relative to internal byte
boundaries over temperatures and VCC. The internal byte boundary determines the byte in which data will come out
(SEROUT±). If STRB occurs before the byte boundary, then the data will be sent out two bytes later. If STRB occurs after the
byte boundary, then the output data will be delayed by one additional byte.
12. X1 Pulse Width is measured at a point where CLK output equals t2 or t3.
13. For the TAXI Transmitter, ‘Data’ is either DI0 – DI7, DI8/CI3, DI9/CI2, CI0 – CI1. For the TAXI Receiver, ‘STRB’ is either
CSTRB or DSTRB and ‘Data’ is either DO0 – DO7, DO8/CO3, DO9/CO2, CO0 – CO1.
14. For the TAXI Receiver, ‘n’ is determined by the state of the DMS and SERIN–
inputs. When SERIN– is held below VTHT max or left open, n=1. When SERIN– is held above 0.25 V and when:

DMS SERIN– “n”

< VTHTMAX or OPEN 8 Bit

n = 1; Test Mode
GND
8 Bit
> 2.5 V n = 10; Local Mode
9 Bit
< VTHTMAX or OPEN n = 1; Test Mode
VCC
> 2.5 V 9 Bit
n = 11; Local Mode

Open 10 Bit
< VTHTMAX or OPEN n = 1; Test Mode
or
1 10 Bit
2 VCC > 2.5 V n = 12; Local Mode

38 Am7968/Am7969
AMD

15. Jitter on X1 input must be less than ±0.2 ns to ensure that automatic test equipment can properly measure device
switching characteristics. The X1 input frequency will determine the byte rate reference for the receiver byte clock.
16. This specification is the sum of Data Dependent Jitter, Duty Cycle Distortion, and Random Jitter.
18. ACK delay is determined by t13 when the input latch is empty or by t15 when the latch is full (Busy mode). Also note that ACK
will not rise if STRB does not remain HIGH until ACK rises.
19. If t47A (CNBØ to CLK≠ setup) is violated, then output data will occur one byte time later.
20. All timing references are made with respect to +1.5 V for TTL–level signals or to the 50% point between VOH and VOL for
ECL signals. ECL input rise and fall times must be 2 ns ± 0.2 ns between 20% and 80% points. TTL input rise and fall times
must be 2 ns between 1 V and 2 V.
21. Device thresholds on the SERIN (+/–) pin(s) are verified during production test by ensuring that the input threshold is less
than VIHS (min) and greater than VILS (max). The figure below shows the acceptable range (shaded area) for the transition
voltage.
VCC
VCC = 0.88 V

VCC = 1.165 V

Input threshold
transition voltage

VCC = 1.475 V

VCC = 1.81 V

22. Switching Characteristics are tested during 8-bit local mode operation.
23. The limit for this parameter cannot be derived from t37 and t42.
24. This specification does not apply during reacquisition when CLK stretch can occur.
✝ This parameter is guaranteed but is not included in production tests.
* Notes listed correspond to the respective references made in the DC Characteristics and the Switching Characteristics
tables.

Am7968/Am7969 39
AMD

SWITCHING TEST CIRCUITS

VCC

VOUT VOUT

CL 50 Ω

2.4K 30 pF

VCC – 2 V

07370F-14 07370F-15

TTL Output Load ECL Output Load

Notes: Notes:
1. R1 = 500 Ω for the IOL = 8 mA 1. CL < 3 pF includes scope probe, wiring and stray
2. All diodes IN916 or IN3064, or equivalent capacitances without device in test fixture.
3. CL = 30 pF includes scope probe, wiring and stray 2. AMD uses Automatic test equipment load
capacitances without device in test fixture. configurations and forcing functions. This figure
is for reference only.
4. AMD uses constant current (A.T.E.) load
configurations and forcing functions. This figure is for
reference only.

40 Am7968/Am7969
AMD

SWITCHING TEST WAVEFORMS

3.0 V

2.0 V

1.5 V

1.0 V

2 ± 0.2 ns 2 ± 0.2 ns
07370F-16

TTL Input Waveform

VCC – 0.9 V

80%

50%

20%
VCC – 1.7 V
2 ± 0.2 ns 2 ± 0.2 ns
07370F-17

ECL Input Waveform

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Must Be Will Be
Steady Steady

May Will Be
Change Changing
from H to L from H to L

May Will Be
Change Changing
from L to H from L to H

Don’t Care Changing

Any Change State
Permitted Unknown

Does Not Center

Apply Line is High
Impedence
“Off” State
KS000010

Am7968/Am7969 41
42
AMD

30 29

32 33
1

3
CLK
2
SWITCHING WAVEFORMS

DATA IN

DATA OR
COMMAND

9
10

STRB 4 5

6 12
14
15

Am7968/Am7969
ACK 13

11
23 24
26
SEROUT+

22 27

SEROUT-
Note 2

Note: 27
2. The clock fall to serial output delay is typically 3 bit times. 23 26
24

07370F-18
Am7968 TAXIchip Transmitter AC
35
61

X1
60
DATA=02 DATA=34 DATA=SYNC (JK) DATA=02

SERIN+ 57

1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1
43

42
SWITCHING WAVEFORMS

CLK
41

DATA OUT DATA=XX DATA=02 DATA=34 COMMAND=0 DATA=02

DO M OR CO N

40
36 38

STRB 37
DSTRB OR CSTRB 38A

47B

47A
49

CNB
48

Am7968/Am7969
46 Note 1 Note 3
45

IGM
44
Note 1 Note 2

07370F-19
Notes:
1. IGM rises because CNB = 1 and SERIN = first half of non-sync byte.
2. IGM falls because CNB falls.
3. IGM falls because SERIN = first half of sync byte.

This diagram illustrates how timing relationships are measured. Functional operation is clarified on following pages.

Am7969 TAXIchip Receiver AC

AMD

43
44
AMD

TAXIchip Transmitter

INT CLK*

CLK OUTPUT
1 2 3 4 5 6
DATA/COMMAND
INPUT DATA 1 DATA 2 DATA 3 DATA 4
SWITCHING WAVEFORMS

STRB INPUT
(NOTE 1)

ACK OUT

INPUT LATCH* DATA 1 DATA 2 DATA 3 DATA 4

ENCODER LATCH* DATA 1 DATA 2 DATA 3 DATA 4

Am7968/Am7969
SHIFTER* SYNC SYNC DATA 1 DATA 2 SYNC DATA 3
11 000 100 0 1 11 000 100 0 1

NRZ DATA* SYNC SYNC DATA 1 DATA 2 SYNC DATA 3

11 000 100 0 1 11 0001 00 01

SEROUT
SERIAL OUTPUT DATA SYNC SYNC DATA 1 DATA 2 SYNC DATA 3

07370F-20
Note:
1. The input Latch is BUSY when the second STRB comes in; the internal STRB-ACK is delayed until the next CLK window.
Refer to Figure 3.

STRB to SEROUT Timing

(8-Bit Local Mode)
*Internal Signals
TAXIchip Receiver

INTERNAL CLOCK*

11 0 0 0 1 0 0 0 1
SERIN
SERIAL DATA DATA N SYNC DATA 1 CMD 1 DATA 3 DATA 4
11 0 00 10 0 0 1
SWITCHING WAVEFORMS

NRZ DATA* DATA N SYNC DATA 1 CMD 1 DATA 3 DATA 4

1 2 3 4 5 6
CLK OUT = CNB

DECODER LATCH* DATA N-1 DATA N SYNC DATA 1 CMD 1 DATA 3

DATA OUT DATA N-2 DATA N-1 DATA N NO CHANGE DATA 1 NO CHANGE

Am7968/Am7969
DSTRB OUT

COMMAND OUT NO CHANGE NO CHANGE NO CHANGE CMD 0 NO CHANGE CMD 1

CSTRB OUT

TAXIchip Receiver Timing

(8-Bit Local Mode)
07370F-21
AMD

45
46
* * * * * *
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 0 1 23 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 56 7 8 9 0 1 2 3 4 5 6 7 8 9
INTERNAL CLOCK*
AMD

11 0 0 0 1 0 0 0 1 (Notes 1 & 2)
SERIN
SERIAL DATA DATA N SYNC DATA 1 DATA 2 DATA 3

11 0 00 10 0 0 1

NRZ DATA* DATA N SYNC DATA 1 DATA 2 DATA 3

(Note 4)
SWITCHING WAVEFORMS

(Note 3)
CLK OUT = CNB
(Note 5)
IGM

DECODER LATCH* DATA N SYNC DATA 1 DATA 2 DATA 3

(Lost)

COMMAND OUT NO CHANGE NO CHANGE SYNC NO CHANGE NO CHANGE

CSTRB OUT

Am7968/Am7969
DATA OUT DATA N-1 DATA N NO CHANGE DATA 1 DATA 2

DSTRB OUT (Note 6)

(Note 7)
Notes:
07370F-22
*Internal Signals
1. Sync detected in Shifter, but not synchronized with internal state machine.
2. State machine re-cycled to new sync position.
3. Clock output delayed to new position.
4. The LOW time or HIGH time gets stretched depending on what state of the internal machine is reset.
5. IGM rises at the 6.5th state of the state machine.
6. Strobe falls at the rising edge of the clock out.
7. Strobe may be shifted one bit time if the state machine is reset at state 1.

TAXIchip Receiver Timing (8-Bit Mode/Local) Showing External Effect of SYNC Error
TAXIchip Receiver

INTERNAL CLOCK*

11 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 11 0 0 0 1 0 0 0 1
SERIN
SERIAL DATA DATA N SYNC SYNC DATA 1 DATA 2 SYNC

11 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 11 0 0 0 1 0 0 0 1

NRZ DATA DATA N SYNC DATA 1 DATA 2 SYNC

1 2 3 4 5 6
CLK OUT
SWITCHING WAVEFORMS

CNB TAXI #1 = 1

IGM TAXI #1 =
CNB TAXI #2

COMMAND OUT NO CHANGE NO CHANGE NO CHANGE NO CHANGE COMMAND 0 NO CHANGE

CSTRB OUT

Am7968/Am7969
TAXI #1
DATA OUT NO CHANGE NO CHANGE NO CHANGE DATA N-1 NO CHANGE NO CHANGE

DSTRB OUT

COMMAND OUT NO CHANGE NO CHANGE NO CHANGE NO CHANGE NO CHANGE NO CHANGE

CSTRB OUT

DATA OUT NO CHANGE NO CHANGE NO CHANGE DATA N NO CHANGE NO CHANGE

TAXI #2
DSTRB OUT
07370F-23
*Internal Signals
AMD

TAXIchip Receiver Timing

47
(8-Bit Cascade Mode)
AMD

PHYSICAL DIMENSIONS*
CD 028
28-Pin Ceramic DIP (measured in inches)
1.435
1.490 .098
MAX

.565
.605
1

.050 .100 .005

.065 BSC MIN
TOP VIEW .590
.615
.008
.160 .012
.220 .015
.060 .150
.125
0° MIN
.160
15°
06837D
.015 .700 BZ13 CD 028
.022 MAX 1/8/91 c dc

SIDE VIEW END VIEW

PL 028
28-Pin Plastic Leaded Chip Carrier
(measured in inches)

.020
.042 .050 MIN
.048 REF .042 .025
.056 R
.045

.026
.032 .013
.485 .450 .021
.300 .390
.495 .456 REF .430

.009
.450 .015 .090
.456 .120 06751F

.485 .165 BV 8 PL 028

12/31/91 c dc
.495 .180
TOP VIEW SIDE VIEW

*For reference only. All dimensions measured in inches. BSC is an ANSI standard for Basic Space Centering.

48 Am7968/Am7969
AMD

PHYSICAL DIMENSIONS
CLT028
28-Pin Ceramic Leadless Chip Carrier
(measured in inches)

.300
BSC

.150
BSC

.050
BSC .022
.028 .300
BSC

.150
.006 BSC
.022 SIDE VIEW
.015
MIN .054
.045 .065
.055 .064
TOP VIEW .075

.442
.458
.040 X 45° REF. (3x) .430
MAX
(OPTIONAL)

.442 .430
.458 MAX
PLANE 2
PLANE 1
07703D
CS47 CLT 028
04/28/94 ae

INDEX CORNER
.020 X 45° REF.
(OPTIONAL)
BOTTOM VIEW

Am7968/Am7969 49
TAXIchipTM Integrated Circuits
Technical Manual

1.0 INTRODUCTION
Modern electronic systems move data from point-to-point across physical layer bounda-
ries using either serial or parallel data links. Parallel data links provide fast data
transfers and are compatible with most computer architectures. However, conventional
parallel data links are burdened with cost/performance issues such as costly multi-con-
ductor cables, crosstalk, RFI, bit-to-bit skew and other concerns associated with multiple
wire interfaces. Serial data links, although simpler and less costly, have not provided
sufficient bandwidth to compete with the high data transfer rates of parallel links.
Recent technological advances have altered the cost performance trade-off between
serial and parallel data transfer techniques. A new chip set from Advanced Micro
Devices offers a high performance integrated alternative to traditional serial/parallel data
transfer techniques. The TAXlchip set (Transparent Asynchronous Xmitter-Receiver
Interface) provides the means to establish a transparent high speed serial link between
two high performance parallel buses. The TAXlchip set consists of a Transmitter, which
takes parallel data and transmits it serially at up to 175 MHz, and a Receiver, which
converts the serial data stream back to parallel form. TAXlchips provide a simple parallel
interface through a high speed serial link, while maintaining the data bandwidth required
by the system.

1.1 The Am7968 TAXI Transmitter

The TAXITM Transmitter consists of an input latch, an encoder, a parallel to serial shift
register, a multiplying Phase Locked Loop (PLL), and some control logic (Figure 1-1).
Data are input to the latch, encoded, and shifted out at the serial data rate. The encod-
ing used is the efficient 4B/5B scheme specified for the ANSI X3T9.5 Fiber Distributed
Data Interface (FDDI specification). This encoding divides an 8-bit byte into two, 4-bit
nibbles. Each nibble is encoded into a 5-bit symbol. The 10-bit encoded byte is format-
ted into an NRZI data stream for output to the media. This 4B/5B encoding is 80%
efficient, using a 125 Mbaud transmission rate to send 100 Mbps of data.
The Am7968 Transmitter has differential pseudo-ECL (referenced to +5 V) outputs
which can drive 50 Ω lines. This capability makes it easy to directly interface with
shielded twisted pair or coaxial cables.
The pseudo-ECL outputs are also compatible with the ECL interface of optical compo-
nents used to drive fiber optic cable. In addition to providing high bandwidth and low
attenuation, fiber optic data transmission also offers noise immunity, eliminates RFI and
provides data security. Declining optical components costs are bringing the advantages
of fiber optic data transmission to an ever wider range of applications, from process
control to avionics. The TAXlchip set is the ideal complement for fiber optic interfaces.

Publication# 12330 Rev. E Amendment /0

50 Issue Date: April 1994
AMD

Figure 1-1 Am7968 TAXI Transmitter Block Diagram

Data Command
N M

Strobe (STRB) Strobe &

Input Latch
Acknowledge (ACK Acknowledge

X1
Oscillator Encoder Latch
and
X2 Clock Gen.
Clock (CLK)
Data Mode
Select (DMS) Data Encoder

(SEROUT+)
Serial Out +
Media
Test Serial In Shifter (SEROUT–)
Serial Interface Interface
(TSERIN) Serial Out –

Test/Local Select (TLS)

Note: N can be 8, 9, or 10 bits. Total of N + M = 12. 12330E-1

Figure 1-2 Am7969 TAXI Receiver Block Diagram

(X1)
Oscillator
and
(SERIN+) Serial In + Media Clock Gen.
Shifter
(SERIN–) Serial In – Interface (X2)

PLL Clock
Decoder Generator
Latch

(DMS) Data Mode Select

Data Decoder Byte Sync (CNB) Catch Next Byte

Logic (IGM) I-Got-Mine

Output Latch (CLK) Clock

N M
(DSTRB) Data Strobe
(VLTN)
Violation Data Command
(CSTRB) Command Strobe

Note: N can be 8, 9, or 10 bits. Total of N + M = 12. 12330E-2

TAXIchip Integrated Circuits Technical Manual 51

AMD

1.2 The Am7969 TAXI Receiver

The TAXI Receiver (Figure 1-2) accepts the encoded data stream into a serial-to-paral-
lel converter, decodes and outputs the received data with an accompanying strobe. An
on-chip data tracking PLL performs the necessary clock recovery from the input serial
data stream.

2.0 USING THE TAXIchip SET

The current TAXlchip set has a maximum effective data throughput of 140 Mbps, over
ten times faster than the data rate of conventional RS-422 drivers and receivers. The
TAXlchip set has a frequency range of 40 MHz to 175 MHz corresponding to a parallel
data transfer rate of 4 to 17.5 Mbyte/sec. Data rates of less than 4 Mbyte/sec are
accommodated by the automatic insertion of Sync symbols in the absence of new data
or commands.
The TAXI Transmitter accepts parallel input data with a simple Strobe/Acknowledge
handshake, while the Receiver asserts an output strobe when data is available at its
parallel outputs. The high speed serial-to-parallel conversions and data encoding/de-
coding are transparent to the user, who sees only an effective parallel transfer rate of up
to 17.5 Mbyte/sec (see Figure 2-1). Appendix C, TAXI TIP # 89-07 addresses the use of
synchronous and asynchronous strobes.
It is important to note here that the user is not forced to supply data at the maximum
byte rate equivalent of the serial data rate. Data or Commands are sent down the serial
link only when the user strobes the Transmitter. For those byte clock cycles when the
Transmitter is not strobed, it automatically sends a special Sync symbol down the link.
The Sync symbol is a unique bit pattern which cannot be confused with any other valid
pattern.
For this reason, Sync is used to establish byte framing at the Receiver. See Appendix C,
TAXI TIP # 89-03 proper use of TAXI Sync. It also keeps the link active when no other
symbols are being sent, maintaining Receiver PLL lock. Sync will not over-write data
already present in the receiver’s output data latch. The serial rate is, therefore, truly
transparent to the user; at input data rates less than the equivalent serial bit rate, the
TAXI Transmitter will fill the gaps with Syncs, which do not disturb Receiver output data.

2.1 Data and Command

The Am7968 TAXI Transmitter and the Am7969 TAXI Receiver interface directly to an 8,
9, or 10 bit data bus. Each TAXlchip has 12 parallel interface lines which are designated
as either Command or Data bits. Command bits implement user defined system
supervisory functions, such as Initialize Your System, Re-try, Halt, or Error which cannot
be embedded in the ordinary data path.

52 TAXIchip Integrated Circuits Technical Manual

AMD

Figure 2-1 Basic TAXIchip Operation

6. The Data
1. Parallel Data comes out the
is Entered by RX and Data
the User Strobe is
Raised
4. The Serial
Data is Sent
Data
Out
Strobe
Data In
Am7968 Am7969 Data Out
Transmitter Receiver
Strobe
Acknowledge

3. The Data is
Encoded and 5. The Re-
2. The Data is then Converted ceiver takes the
Strobed in by into a Serial Serial Data and
the User Stream Converts it
Back to Parallel
Data and then
Decodes it

12330E-3

Three different widths are possible: 8 Data and 4 Command bits, 9 Data and 3 Com-
mand bits, and 10 Data and 2 Command bits. This choice of data and control bus widths
allows flexibility to meet different system bus width requirements, while providing the
capability of merging control and data into a common data stream.

2.2 Operational Modes: Local, Cascade and Test

A TAXIchip set point-to-point link can be operated in one of three modes: Local,
Cascade, or Test. Local mode consists of a single Transmitter communicating with a
single Receiver over the serial medium. Cascade mode for Am7968/7969-125 consists
of a single Transmitter driving two or more daisy chained (cascaded) Receivers over a
single serial medium. Cascade Operation for Am7968/Am7969-175 consists of a single
Transmitter driving a single Receiver as shown in Appendix C, TAXI TIPs #13 and #14.
Cascade mode permits direct interface with 16-bit, 32-bit and wider busses. The link
may be operated in any of the above modes using the TAXl’s internal PLL for bit rate
generation and tracking, or the link may be run in Test Mode with external frequency
multiplying and data tracking PLLs.

3.0 DATA ENCODING, VIOLATION AND SYNCS

3.1 Data Encoding
Any form of serial data transmission requires some form of encoding before the data are
output to the transmission medium. Encoding is the process of converting a set of m
data bits to a set of n code bits.
The purpose of the encoding operation is to include clock information in the data stream.
Without this timing information, the Receiver would not be able to distinguish adjacent
bits of the same value. For example, if we transmit a thousand ONEs followed by a
ZERO, the Receiver might detect only 999 ONEs, or perhaps 1001 ONEs, followed by
one or two ZEROs. An accurate clock is needed to tell the Receiver when to sample the
incoming bit stream to determine if the bit is a ONE or a ZERO. Since the Transmitter
and Receiver have only one data path between them, the clock (timing) information
must be included in the serial data stream.

TAXIchip Integrated Circuits Technical Manual 53

AMD

The TAXIchip set uses 4B/5B or 5B/6B coding, so that m is either 4 or 5, and n is either
5 or 6. In 8-bit mode, each 4-bit nibble is presented to one of two 4B/5B encoders to
produce 10 code bits, 5 from each encoder. In 9-bit mode, the more significant 4B/5B
encoder is replaced with a 5B/6B encoder to yield a total of 11 code bits. In 10-bit mode,
both encoders are replaced with 5B/6B encoders, yielding a total of 12 code bits.
The TAXIchip set can encode two types of data: either 8, 9, or 10-bit Data, or Com-
mands. Commands are special symbols which are typically used as control functions at
the receiving end of the link. Commands may be four, three, or two bits wide, corre-
sponding to a Data width of eight, nine, or ten bits respectively. The presence of any
non-ZERO bits on the Command inputs when STRB is asserted will cause a Command
symbol to be sent, regardless of the state of the Data lines. The Command bits are
encoded into 10,11, or 12 bit groupings which are special cases of the 4B/5B or 5B/6B
code not used for Data.
In the absence of Data or Commands, a unique symbol (Sync) is automatically gener-
ated to maintain link synchronization. If the user has not supplied a STRB during a byte,
a Sync symbol is sent.
NRZI stands for Non-Return to Zero, Invert on one. Logic ONEs are indicated by a
transition, while logic ZEROs produce no transition. Further encoding the 4B/5B
encoded data in this way ensures that the Receiver PLL will get a transition at least
every three clock times (the maximum number of ZEROs in the 4B/5B code). Since a
PLL can make a phase comparison and initiate a correction only at a transition,
maximizing the number of transitions helps to keep the loop solidly in lock.

54 TAXIchip Integrated Circuits Technical Manual

AMD

Table 3-1 TAXlchip Encoder Patterns

4B/5B ENCODER SCHEME 5B/6B ENCODER SCHEME
4-Bit 5-Bit 5-Bit 6-Bit
HEX Binary Encoded HEX Binary Encoded
Data Data Symbol Data Data* Symbol
0 0000 11110 00 00000 110110
1 0001 01001 01 00001 010001
2 0010 10100 02 00010 100100
3 0011 10101 03 00011 100101
4 0100 01010 04 00100 010010
5 0101 01011 05 00101 010011
6 0110 01110 06 00110 010110
7 0111 01111 07 00111 010111
8 1000 10010 08 01000 100010
9 1001 10011 09 01001 110001
A 1010 10110 0A 01010 110111
B 1011 10111 0B 01011 100111
C 1100 11010 0C 01100 110010
D 1101 11011 0D 01101 110011
E 1110 11100 0E 01110 110100
F 1111 11101 0F 01111 110101

10 10000 111110
11 10001 011001
12 10010 101001
13 10011 101101
14 10100 011010
15 10101 011011
16 10110 011110
17 10111 011111
18 11000 101010
19 11001 101011
1A 11010 101110
1B 11011 101111
1C 11100 111010
1D 11101 111011
1E 11110 111100
1F 11111 111101
* Notes:
HEX data is parallel input data which is represented by the 4- or 5-bit binary data listed in the column to
the immediate right of HEX data. Binary bits are listed from left to right in the following order.
8-Bit Mode: D7, D6, D5, D4, (4-Bit Binary), and D3, D2, D1, D0, (4-Bit Binary)
9-Bit Mode: D8, D7, D6, D5, D4, (5-Bit Binary), and D3, D2, D1, D0, (4-Bit Binary)
10-Bit Mode: D8, D7, D6, D5, D4, (5-Bit Binary), and D9,D3, D2, D1, D0, (5-Bit Binary)
Serial bits are shifted out with the most significant bit of the most significant nibble coming out first.

Table 3-2 TAXIchip Command Symbols

TAXIchip Integrated Circuits Technical Manual 55

AMD

Am7968 Transmitter Am7969 Receiver

Command Input Command Output
Encoded
HEX Binary Symbol Mnemonic HEX Binary
8-Bit Mode
0 0000 XXXXX XXXXX Data No Change No Change
(Note 2) (Note 2)
No STRB No STRB 11000 10001 JK (8-bit Sync) 0 0000
(Note 1) (Note 1)
1 0001 11111 11111 I I 1 0001
2 0010 01101 01101 TT 2 0010
3 0011 01101 11001 TS 3 0011
4 0100 11111 00100 IH 4 0100
5 0101 01101 00111 TR 5 0101
6 0110 11001 00111 SR 6 0110
7 0111 11001 11001 SS 7 0111
8 (Note 3) 1000 00100 00100 HH 8 1000
9 1001 00100 11111 HI 9 1001
A (Note 3) 1010 00100 00000 HQ A 1010
B 1011 00111 00111 RR B 1011
C 1100 00111 11001 RS C 1100
D (Note 3) 1101 00000 00100 QH D 1101
E (Note 3) 1110 00000 11111 QI E 1110
F (Note 3) 1111 00000 00000 QQ F 1111

9-Bit Mode
0 000 XXXXXX XXXXX Data No Change No Change
(Note 2) (Note 2)
No STRB No STRB 011000 10001 LK (9-bit Sync) 0 000
(Note 1) (Note 1)
1 001 111111 11111 I’I 1 001
2 010 011101 01101 T’T 2 010
3 011 011101 11001 T’S 3 011
4 100 111111 00100 I’H 4 100
5 101 011101 00111 T’R 5 101
6 110 111001 00111 S’R 6 110
7 111 111001 11001 S’S 7 111
10-Bit Mode
0 00 XXXXXX XXXXXX Data No Change No Change
(Note 2) (Note 2)
No STRB No STRB 011000 100011 LM (10-bit Sync) 0 00
(Note 1) (Note 1)
1 01 111111 111111 I’I ’ 1 01
2 10 011101 011101 T’T’ 2 10
3 11 011101 111001 T’S’ 3 11
Notes:
1. Command pattern Sync cannot be explicitly sent by Am7968 Transmitter with any combination of inputs
and STRB, but is used to pad between user data.
2. A strobe with all Os on the Command input lines will cause Data to be sent. See Table 3-1.
3. While these Commands are legal data and will not disrupt normal operation if used occasionally, they
may cause data errors if grouped into recurrent fields. Normal PLL operation cannot be guaranteed if
one or more of these Commands is continuously repeated.

56 TAXIchip Integrated Circuits Technical Manual

AMD

3.2 Violation Logic

The TAXI Receiver logic has been designed to detect the most common types of
transmission errors. It detects these errors by completely decoding the incoming data
patterns, and recognizes the following types of VIOLATIONS:
1. Illegal, reserved or unused data patterns (pure Violations).
2. Unused COMMAND combinations.
3. COMMAND in Upper half and DATA in Lower half pattern.
4. DATA in Upper half and COMMAND in Lower half pattern.
Type 1 and 2 VIOLATIONS are decoded and interpreted as either DATA or COMMAND
outputs with the appropriate STRB output. Type 3 & 4 VIOLATIONS are decoded as
COMMAND outputs with a CSTROBE output (even though one half would have been
transformed DATA/COMMAND or COMMAND/DATA by an error), since there is no
information available to the TAXI Receiver to indicate where the error lies. The user
needs to be aware of this possible transposition (possible with all four types of VIOLA-
TION), since the system must account for it. VIOLATION will always be the flag for
these detectable errors.
This method of detection is not 100% effective. As Appendix B shows, it will detect
approximately 50% of the possible double bit errors in Data. Double bit errors in
Command will be detected 99.8% of the time or more, depending upon the pattern
width. Appendix B contains a more detailed treatment of the efficiency of the violation
logic for the various data bit modes.
The method of detecting violations, is effective enough to be used to give an early
warning of transmission problems before the host’s error detection system would detect
the errors. It should not be used alone in fault sensitive systems, since it misses a
significant number of transmission errors which cause one valid DATA pattern to alias to
another VALID DATA PATTERN.

3.3 TAXI PLL Characteristics

The Phase Locked Loop in the TAXI Receiver is used to recover the data encoded in
the serial bit stream sent by the TAXI Transmitter. In order to ensure accurate data
recovery, the Receiver PLL must lock on to the underlying code rate of the Transmitter,
and must track minor changes in frequency and phase while rejecting noise superim-
posed on the bit stream. This noise includes both amplitude and phase/frequency
disturbances. Amplitude variations are dealt with in the Receiver’s input amplifier
(SERIN+/-), and are not passed through to the PLL, except for phase effects.
Phase/frequency noise, or jitter, can come from many sources, and can have many
different characteristics. Jitter can be introduced by the Transmitter, the Receiver, the
media interface or by the media itself. Examples of media induced jitter include reflec-
tions and edge perturbations caused by improper line termination, pulse width spreading
due to frequency dependent cable attenuation, and pulse dispersion caused by fiber
optic cable effects. Examples of media interface jitter include low light effects in optical
receivers and pulse width distortion caused by baseline shift (changing DC offset) in AC
coupled amplifiers.
The TAXI PLL has been optimized to allow correct data recovery in the presence of the
largest jitter possible. To this end, the PLL parameters, most notably loop bandwidth,
have been chosen to enhance the jitter tolerance of the TAXI Receiver.

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This optimization is at the expense of lock-up time. In TAXI systems, lock-up time is
relatively unimportant, since the system must achieve lock only during system power-up.
If the PLL achieves proper lock within a few tens, or even hundreds of microseconds, its
startup will be similar to the start-up characteristics of the system power supply.
The actual time to lock begins during power-up, when both Transmitter and Receiver
are marginally powered and the entire link is marginally functional. Transient effects
other than PLL characteristics, which typically occur during power-up, can either
lengthen or shorten the apparent lock time. These effects are a function of actual
implementation and are not discussed here. The discussion which follows assumes that
both Transmitter and Receiver are fully powered, and that the link is fully operational.
The only effects included are PLL transient effects.
If there is no data on the link (if the Transmitter is off, or if there is a quiet line) the data
recovery PLL will drift to its natural oscillation frequency. This frequency is determined
by component values and tolerances inside the Am7969 receive PLL, and will vary
slightly from both the Receiver reference frequency (at X1 of the Receiver) and the
Transmitter data frequency (X1 of the Transmitter).
When data appears on the line, the receive PLL must achieve phase lock from its
resting frequency. The structure of the PLL used in the TAXIchip set ensures that this
resting frequency will be no more than a few percent (typically less than 3%) from the
reference frequency applied at X1. This is in addition to the specified Transmitter/Re-
ceiver frequency mismatch allowed by the crystal tolerance specification of +0.1%.

Figure 3-1 Calculated Receiver Lock-Up Time

80
70
60
HQ
Lock-Up Time 50 JK
(µs) II
40
30
20
10

0
0.1 1 2
12330E-4
Percent Offset Frequency at 125 MHz

Neglecting frequency variations in the Transmitter and jitter in the data stream, the time
to lock is related to the PLL loop bandwidth and damping factor, and to the transition
density. The loop parameters are set by the internal component values and tolerance of
the TAXIchip set. A plot of calculated lock-up time vs Transmitter to Receiver frequency
offset and transition density is given in the Figure 3-1. Note that low transition density
causes longer lock times. In fact, at very low transition densities (1 transition per 10 bit
times of the HQ symbol), and large offset frequencies, the PLL may not be able to
acquire lock at all, even though the lock equation used to produce the graph seems to
indicate a solution. As the limits are approached, lock time may grow to several times
the value predicted by the lock equation.

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4.0 CLOCK GENERATION AND DISTRIBUTION

The serial baud rate for the Am7968 Transmitter is derived from a byte rate frequency
source. The TAXI Receiver must run at the same frequency as the TAXI Transmitter.
The relationship between serial baud rate and data byte rate depends on the width of
the transmitted data. For 8-bit data, the byte rate is multiplied by 10 to obtain the serial
clock rate. Since the maximum operating frequency is 125 MHz and the minimum
frequency is 40 MHz, the byte rate frequency range for 8-bit data is between 4.0 and
12.5 MHz. The multipliers for 9 and 10 bit data widths are 11 and 12 respectively. The
following table summarizes the byte rate frequency ranges for each data width selected.

Am7968/Am7969-125
Data Width PLL Multiplier Byte Rate
8 10 4.00 – 12.50 MHz
9 11 3.64 – 11.36 MHz
10 2 3.33 – 10.42 MHz

Am7968/Am7969-175
Data Width PLL Multiplier Byte Rate
8 10 12.5 –17.5 MHz
9 11 11.37 – 15.90 MHz
10 12 10.42 – 14.58 MHz

The source of byte rate frequency can be either from the built-in crystal oscillator or from
a TTL clock signal. The maximum allowable mismatch between Transmitter and
Receiver frequency sources is ±0.1%. This tolerance is derived from the PLL architec-
ture in the TAXI Receiver, and from considerations of crystal accuracy. More information
on crystal specifications and available distributors can be found in Appendix C, TAXI TIP
#89-05, TAXIchip set crystal specification.
When there is no incoming data, the Receiver PLL has no serial data stream to track.
This situation can arise if the Transmitter has not been powered up, or if the transmis-
sion medium is disconnected. In this case the VCO will drift to a frequency determined
by internal component tolerances. When data appears at the Receiver serial input, the
loop must acquire lock from this resting frequency. The worst case frequency offset and
the capture range of the PLL are designed to allow frequency mis-matching between
Transmitter and Receiver of ±0.1%, since this accuracy is achievable with inexpensive
available crystals.

4.1 TAXI Transmitter Clock Connections

The byte rate frequency source drives a multiplying PLL to create an internal bit rate
clock which is used for timing all internal logic. The X1 and X2 pins are used to input the
byte rate frequency source to the Transmitter. Their exact usage will vary, depending on
type of frequency source (crystal or external TTL) and mode of TAXI Transmitter
operation (Local or Test).

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4.1.1 Local Mode Transmitters

In Local mode, X1 and X2 are the crystal oscillator inputs. The external component
connections are shown in Figure 4-1. Zero temperature coefficient capacitors (type
NPO) should be used for good temperature stability.
Typical Crystal Specification
Fundamental Frequency 4.0 MHz –17.5 MHz +0.1%
Resonant Mode Parallel
Load Capacitor (Correlation) 30 pF
Operating Temperature Range 0°C to 70°C
Temperature Stability ±1.00 ppm
Drive Level (Correlation) 2 mW
Effective Series Resistance 25 Ω (max)
Holder Type Low Profile
Aging for 10 Years ±10 ppm

Figure 4-1 TAXlchip Crystal Connection

RESET
Am7968 or, Am7969

X1 X2

C C

12330E-5

C = 150 pF for a 12.5 – 17.5 MHz Crystal, 220 pF for a 4 MHz–12.5 MHz Crystal

The Transmitter may also be run in local mode by applying a TTL frequency source to
X1 and grounding X2. The TTL source may be either from a crystal oscillator module, or
from a neighboring TAXI Transmitter CLK output. In local mode, CLK is the buffered
output of the internal crystal oscillator. Connecting the CLK output of a TAXI Receiver
directly to the X1 input of a TAXI Transmitter is not recommended, because the
Transmitter’s clock stability and jitter requirements are not satisfied by the Receiver CLK
output.

4.2 TAXI Receiver Clock Connections

The considerations and connections for the TAXI Receiver are similar to those for the
TAXI Transmitter. The Receiver X1 and X2 inputs connect to an on-chip oscillator,
whose frequency is determined by a parallel resonant crystal, or is driven by an external
TTL frequency source. The oscillator provides the reference, which sets the expected
center frequency for the data synchronizing PLL. The synchronizing PLL tracks the
incoming data and generates a bit clock from the serial data stream. All of the internal
TAXI Receiver logic, including the logic that generates the CLK output, runs on this bit
rate clock. This recovered clock is as stable as possible in both frequency and phase, as
it tracks the incoming data stream. In addition to the bit synchronization accomplished
by the PLL, the logic will maintain byte synchronization (framing) with the incoming data

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using the Sync symbol to define byte boundaries. If the byte boundaries must be
re-aligned (on power-up or re-acquisition of signal), the logic will ensure that the CLK is
stretched (never shortened) upon re-sync to the new byte alignment. Due to this
behavior, the CLK output from the Receiver is not suitable as a direct frequency
reference for another TAXI Transmitter or Receiver. CLK is intended to be used by the
host system as a clock synchronous with the received data.

Figure 4-2 Cascaded Receiver Clock Connections

From Serial Media

SERIN– SERIN+ SERIN– SERIN+ SERIN– SERIN+

RX1 DMS RX2 DMS RX3 DMS

VCC
Am7969 Am7969 Am7969
(Primary Receiver)
CNB IGM CNB IGM CNB IGM N/C
CLK X2 X1 X2 X1 X2 X1

12.5 MHz
Crystal
OSC
12330E-6

4.2.1 Cascade Mode Receivers (Am7969-125 Only)

When using an on-board TTL clock source, Receivers which are in Cascade mode
should have their X1 pin tied to the Crystal Oscillator and their X2 pin grounded.
Figure 4-2 shows a typical cascaded Receiver clock connection. The frequency source
for the Local mode Receiver should be either a crystal oscillator (as shown) or another
external TTL source. It should not be the CLK output of another Receiver. As discussed
above, the CLK output from the Receiver is not suitable as a frequency source for other
TAXI Receivers.

5.0 INTERFACING WITH THE SERIAL MEDIA

The Am7968/Am7969 TAXlchip set is capable of providing a high speed point-to-point
serial link over fiber-optic, coaxial, or twisted pair media. The choice of the appropriate
medium depends primarily on line length and data rate. This chapter discusses the
issues involved in media choice and the requirements for driving different types of
media.
Any TAXIchip set to media interface design must first take into account the electrical
properties of the TAXI Transmitter and TAXI Receiver. The Transmitter serial output
drivers are open emitter, emitter followers which generate pseudo-ECL (PECL) levels
when terminated by pull-down resistors to a voltage more negative than V OL. PECL is
ECL referenced to the +5 V supply, so that VOH = (5–0.8) and VOL = (5–1.8) volts. A safe
termination voltage which guarantees meeting VOL is 3 V or less. The Receiver input is a
long-tailed pair which will switch on 50 mV differential input voltage, with a large

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common mode range. The average DC value of the input signal is therefore relatively
unimportant.
There are three broad classes of TAXl-to-media interface:
1. Very short (<3″ link length), usually DC coupled.
2. Terminated, DC coupled.
3. Terminated, AC coupled.
The short link is typical of a TAXIchip set to optical components connection. The
terminated cases are used for driving cables, also optical or other components with
incompatible power supply and/or logic level requirements may sometimes need circuits
and layout that exceed 3″.

5.1 Very Short Link, DC Coupled

For DC coupled inter-connections in which the distance between the serial pins and the
next device is less than 3″, transmission line terminations are not necessary. All that is
required is an appropriate PECL pull-down resistor, RE. Elimination of reflections is not
required for these short line lengths because the round-trip propagation is significantly
less than the 2 ns TAXIchip set rise and fall time. The effect of media mismatch in this
case is distortion and slowing of the transition due to the addition of the reflection to the
still changing edge.

Figure 5-1a Standard Load Circuit

IOH
VOH = 4.1 V

50 Ω

VCC –2 V = 3 V 12330E-7

Figure 5-1b Pull-Down with IOH Matched to Standard Load

C
VOH = 4.1 V

IOH RE

12330E-8

The lower limit for RE is that value which produces the maximum value of l OH. In a
standard PECL load circuit (Figure 5-1a) lOH max is given by:
(VOH – (VCC –2))/50 = (4.1–3)/50 = 22 mA
If we return RE to ground instead of 3 V (Figure 5-1b), the minimum value of RE
becomes 4.1 V/22 mA, or 186 Ω.
Reflections due to mismatch can be minimized by locating the pull-down resistor at the
end of the line, rather than the source. A mismatched line termination will give a
reflection coefficient less than one while leaving the end of the line open will give a
reflection coefficient of one (maximum reflection). Note that the supply voltage and logic

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level of the optical components must match those of the TAXIchip set in order for the DC
connection to work. If the supply voltage or the logic levels are incompatible, an AC
connection must be used.

5.2 Terminated, DC Coupled

The parallel termination shown in Figure 5-2 may be used for a DC connection of a TAXI
Transmitter to a TAXI Receiver. The parallel termination provides both the line termina-
′
tion (R1llR2 = Z0 = line characteristic impedance) and a pull-down voltage. The Thevenin
equivalent of this termination is Z0 pulled down to VCC–2 V, assuring both matched
termination and adequate VOL. Using VCC and a voltage divider provides pull-down
voltage without the need for a separate power supply.

Figure 5-2 Parallel Termination

VCC
TAXI TX TAXI RX
Pseudo-ECL R1
Driver
Copper Media

SEROUT Z0 SERIN
R2

VCC

R1
12330E-9
′
Thevenin R1 | / R2 = Z0
Equivalent

R2 (R1 + R2) VCC = VCC – 2 V

5.3 Terminated, AC Coupled

AC coupling is the connection of choice for many TAXIchip set applications. The typical
arrangement for an AC coupled link is shown in Figure 5-3. RE is returned to ground to
provide the PECL (pseudo-ECL) pull-down for the driver. The capacitor C blocks the DC
voltage, and R1 and R2 terminate the transmission line and provide a DC bias level for
the Receiver. Since only AC variations are passed through the coupling capacitor, the
bias level at the termination should be set to the midpoint of the signal swing expected
by the Receiver input stage. Note that this bias level is not the same as that which is
recommended for the DC coupled case.
The minimum value of RE was previously established as 186 Ω, to avoid exceeding
IOH max. The maximum value of RE must be small enough to supply the transmission
line with enough current to avoid cutting off the output driver. When switching from a
HIGH to the LOW state, the transmission line may cause the emitter voltage of the driver
to fall more slowly than the base voltage, causing the output transistor to turn off. When
the output transistor turns off, its output impedance becomes very high, causing the
falling edge rate to be controlled by the external load (RE and the transmission line).
This variation in edge rate cannot be tolerated until the falling edge crosses the

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threshold level of the receiver’s differential amplifier. Once the Receiver recognizes the
state change, variations in the falling edge are not significant.
To avoid edge rate variations due to driver turn-off, we must equate the voltage to which
the driver is taken at turn-off with a point in the logic swing which will guarantee that the
Receiver changes state. Since PECL logic swings are 800 mV, we may safely choose a
500 mV change at the driver (100 mV past the midpoint) as a guaranteed state change
at the Receiver. If the driver turns off instantly, we require the voltage divider formed by
RE and Z0 to produce a 500 mV change from VOH. We can write:
VOH RE/(RE + Z0) = VOH – 0.5
4.1 x RE/(RE + Z0) = 3.6
RE = 7.33 Z0
As a general rule, we may then say that:
186 < RE < 7.33 Z0

Figure 5-3 Pull-Down and Termination for AC Coupled Link

TAXI TX TAXI RX
VCC
Pseudo-ECL
Driver
R1
C Copper Media

SEROUT SERIN
RE R2

12330E-10

Figure 5-4 Serial Link with Output Driver Model

TAXI TX VCC TAXI RX

Pseudo-ECL
Driver (Model)
R1
R0 C B Copper Media

SWI
VOH SERIN
RE R2

12330E-11

5.4 Baseline Wander and the AC Coupling Capacitor

The 4B/5B and 5B/6B data encoding schemes which are used by the TAXIchip set are
run-length limited to a maximum of 3 consecutive LOW states (non-transitions in NRZI).
This type of encoding ensures that on average there will be less than ±10% variation in
the DC component of the encoded data.
When the encoded data is passed through an AC coupled link, the high-pass filtering of
the AC coupling will introduce jitter because of the fluctuating threshold caused by the
variation in DC component. This undesired side-effect of AC coupling is often described

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as baseline wander effect and is illustrated in Figure 5-5. In Figure 5-5a, the average DC
fluctuates between 40% and 60% of the maximum level (+10% of midpoint). After the
signal is capacitively coupled (Figure 5-5b), the average DC component is lost due to
high-pass filtering, causing an undesired shift in the signal levels. This shift in the signal
levels, coupled with non-zero rise and fall times of the serial stream cause pulse width
distortion and thus apparent jitter and possible increased error rates.
This DC shifting effect can be minimized if the values of the AC coupling components
are chosen appropriately. The DC level of the data will fluctuate at a data-dependent
frequency, fb, called the baseline wander frequency. The 3 dB corner frequency of the
AC coupling, f3dB=1/(2πRC), should be chosen below the minimum baseline wander
frequency of the data. This allows most DC variations to pass through the AC coupling
high-pass filtering, minimizing the DC shift in the signal.
To minimize f3dB we must maximize R and C. The resistance R is generally determined
either by the termination required by the transmission line or by biasing requirements on
both sides of the link. Hence, only the coupling capacitor C can be maximized to keep
f3dB as low as possible. The largest value capacitor that can be used is limited by the fact
that it must be an RF capacitor. RF capacitors are generally of the ceramic type (NPO
and X7R dielectrics) and are limited to a maximum value of approximately 1.0 µF.
0.1 µF capacitors have proven to be sufficient in laboratory tests of TAXIchip set
systems.
For a 0.1 µF capacitor, we must verify that the capacitive reactance at the lowest
fundamental frequency possible is less than 1Ω. The lowest fundamental frequency
possible is the frequency that results when the TAXIchip set is running at it’s lowest
BAUD rate (40 Mbaud) and the command or data pattern with the least number of
transitions is being sent. This pattern turns out to be the HQ command (FDDI terminol-
ogy) which has only 1 transition per command, or 1 transition per 10 bits when the
command is encoded. If a continuous stream of HQ commands are sent at 40 Mbaud,
the resultant fundamental frequency of the signal is 2 MHz. At 2 MHz, the capacitive
reactance of a 0.1 µF capacitor is calculated as follows:
1 1
XC = = = 0.8 Ω
2πfC 2π (2*106) (0.1*10-6)

Hence, in the worst case a 0.1 µF capacitor will give a reactance of less than 1 Ω, as
desired.
In summary, the largest value RF capacitor available should be used to optimize the
performance of the TAXlchip link.

Figure 5-5 Baseline Wander

Average DC Level Varies
with Data Pattern

a) Data Before AC Coupling

Varying DC is Filtered Out

Causing an Undesired DC
Shift in the Data
b) Data After AC Coupling 12330E-12

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5.5 Interfacing to Fiber Optic Transmitters/Receivers

The TAXlchip set can be used in conjunction with optical components and optical fiber
to form a simple fiber optic communication link. Optical transmission has many advan-
tages over conventional electrical transmission. These include: immunity to EMI/RFI,
low attenuation, electrical isolation, data security, and wide bandwidth. Because of these
features, use of optical fiber as the serial media will result in optimum performance of
the TAXIchip set link. Depending on the type of fiber and the optical components used,
TAXI links using optical fiber can cover distances of up to several kilometers.
Figure 5-6 shows a block diagram of a complete TAXI fiber optic link. The optical
components transmitters and receivers can be obtained from one of the sources listed in
Appendix A of this manual. The interface between the TAXlchips and the optical
components will be the subject of this section.

Optical TAXI /Optical Transceiver

Connectors Interface
Fiber
Optic
Cable
Fiber Optic Receiver
Am7969
Optical
Receiver
Detector:
PIN or Receiver
Avalanche Electronics
Photodiode 8, 4,
9, 3,
10 2

Data Command
12330E-13

5.5.1 DC-Coupled TAXl-Fiber Optic Transceiver Interface

When passing data between the TAXIchip set and an optical module, care must be
taken to assure that the logic levels of the TAXIchip set and the optical components are
matched. If the supply voltages of the optical components do not match those of the
TAXIchip set, then the logic levels will probably differ and the interface will require AC
coupling to isolate these different levels. However, if the power supply requirements
match those of the TAXIchip set (i.e. VCC = +5 V, VEE = GND) and if the two components
are connected to the same power and ground planes, a DC coupled interconnection
may be sufficient.

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For DC-coupled interconnections in which the distance between the TAXIchip set and
the optical module is less than 3″, transmission line terminations are not necessary. All
that is required is the appropriate ECL pull-down as shown in Figure 5-7(1) . On these
short line lengths, elimination of line reflections is not critical. However, without any
increase in complexity or power consumption, line reflections can be reduced simply by
locating the pull-down resistor, RE, at the end of the line instead of at the beginning. This
reduces the reflection coefficient at the end of the line, and therefore, reducing the
magnitude of the reflections.

Figure 5-7 DC-Coupled TAXl-Fiber Optic Interface (Unterminated)

+5 V +5 V

Optical Fiber
TAXI ODL ODL TAXI
L < 3″, Z0 L < 3″, Z0
TX TX RX RX
+ + + +
– 186 ≤ RE ≤ 7.2 (Z0) –
– –

RE RE RE RE

Note: 12330E-14
If the DC-coupled interconnection is longer than 3″, transmission line terminations are necessary. For this
case, the suggested configuration is shown in Figure 5-8. Note that the line termination network also provides
the desired pull-down to VCC – 2 V, sufficiently below the output LOW level of VCC – 1.8 V

Figure 5-8 DC-Coupled TAXl-Fiber Optic Interface

+5 V +5 V

R1 R1 Optical Fiber R1 R1
TAXI L>3″, Z0 ODL ODL L>3″, Z0
TAXI
TX TX RX RX
+ + + +
– – – –
R1R2
R2 R2 = Z0 R2 R2
R1+ R2
5R2
=3V
R1+ R2

Note: 12330E-15
If the optical and TAXI power and ground planes are decoupled as shown in Chapter 6, AC coupling is always
recommended to allow for variations in power and ground plane voltages. AC coupling is discussed in
Section 5.5.2.

(1) Adequate bypass capacitors have been omitted from this and the following figures to simplify the drawings.

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5.5.2 AC-Coupled TAXl-Fiber Optic Transceiver Interface

Some applications will require the TAXIchip set to optical transceiver interconnection to
be AC-coupled. AC coupling should be used in the following situations: a) when the
TAXIchip set and optical components are driven by a common power supply but the
supply pins are decoupled using the scheme recommended in Chapter 6, and b) when
the TAXIchip set and optical components operate on different power supplies.
AC coupling via capacitors along with the necessary design equations is shown in
Figure 5-9. In this configuration, RE is the ECL output pull-down resistor, C provides the
AC coupling, the connection is made with a transmission line (coax, twisted pair,
microstrip) of length L and characteristic impedance, Z0, and R1 and R2 provide a
matched line termination and voltage bias to the midpoint of the optical component’s
logic swing (Vbb).
The configuration shown in Figure 5-9 is recommended for any line length, L, which
separates the TAXIchip set and the optical module. Although the matched line termina-
tion is not necessary for L<3″, the Vbb bias voltage is always needed for AC-coupled
links. Therefore, even for line lengths where matched line terminations are not neces-
sary (less than 3″), the resistors R1 and R2 can be chosen to give a matched load
without any added complexity.

Figure 5-9 AC-Coupled TAXl-Fiber Optical Interface

VCC

+5 V R1
R1
TAXI ODL
L, Z0
TX C TX
+ +
– Vbb
– R1R2 R3R4
C = Z0
R2 R2 R1+ R2 = R3+ R4
RE RE
VIH + VIL (VCC – VEE) R2
Vbb = Midpoint of ODL = = VEE +
VEE Signal Swing 2 R1 + R2
Optical Fiber 5R4 Midpoint of Pseudo-
+5 V R3+ R4 = ECL Signal Swing = 3.7 V
R3 R3
VCC 186 < RE < 7.2 (Z0)

TAXI ODL C = Largest RF Capacitor Available

L, Z0
RX C RX
+ +
– –
C
RE RE
R4 R4
12330E-16
VEE

5.6 Interfacing to Coaxial Cable

In many applications, system cost can be reduced by using coaxial cable as the serial
media. Unlike optical fiber, which requires optical components between the fiber and the
TAXIchip set, coaxial cable can be connected directly to the TAXI SEROUT pins, giving
lower system costs.

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Because of the resultant lower system costs, coaxial cable is the recommended serial
medium for short-to-moderate length links. At longer lengths, the advantages of fiber
optic transmission (low attenuation, immunity to EMI and ground loops, etc.) make it the
media of choice.
The maximum length possible for a coaxial cable TAXI link depends on the type of
coaxial cable used and the data rate. Higher data rates will tend to limit link lengths
because attenuation and pulse dispersion on coaxial cable increases with frequency.
Many different types of coaxial cables are available. Some have far less attenuation
than others however, with low loss generally comes increased size and rigidity.
RG-58 is a commonly used, readily available type of coaxial cable. In lab tests using this
type of cable, it was found that the TAXlchip link could operate with a byte error rate of
better than 10–10 with a confidence limit of 95%, at byte rates of up to 12.5 MHz, at
distances of up to 200 feet. The confidence limit accounts for the statistical nature in
which errors occur in a digital system and it implies that we can be 95% sure that, under
the given circumstances, the byte error rate will be 10–10 or better. Note that a byte error
could have been due to a single bit error or more hence, the bit error rate may not be
equal to the byte error rate divided by ten.
Using the TAXlchip set in conjunction with coaxial cable as the serial media is quite
simple. Appropriate line terminations are required and AC coupling is strongly recom-
mended to eliminate ground loops. The recommended configuration, including the
necessary design equations, is shown in Figure 5-10. Each of the components that
make up the interface serve the same purpose as in the AC-coupled TAXl-fiber optic
interface shown in Figure 5-9.
Note that two coaxial cables comprise the link, one for each of the differential pseudo
ECL signals. These two lines should be calibrated for a propagation delay difference of
less than 0.2 ns.

Figure 5-10 Coaxial Cable Interface

+5 V
+5 V

TAXI R1 R1 TAXI
L, Z0
TX C RX
+ +
C
– –

RE R2 R2
RE

R1R2
= Z0
R1+ R2
5R2
= Midpoint of Pseudo-ECL Signal Swing = 3.7
R1+ R2
12330E-17
186 ≤ RE ≤ 7.2 (Z0)
C = Largest RF Capacitor Available

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Sample Values
Using RG-58A/U, 50 Ω coaxial cable, a successful TAXI link was established using the
following component values:
R1 = 68 Ω
R2 = 200 Ω
RE = 300 Ω
C = 0.1 µF

5.7 Interfacing to Twisted-Pair Cable

Another low cost alternative twisted pair cable. Twisted pair cable is generally more
lossy than coaxial cable making it suitable only for short distances. To reduce the
possibility of noise being induced along the line, the shielded twisted-pair cable is
recommended.
Using the TAXlchip set with shielded-twisted-pair as the serial medium is very similar to
using it with coaxial cable. The recommended configuration is shown in Figure 5-11,
where each of the components that make up the interface serve the same purpose as in
the AC-coupled TAXl-fiber optic interface shown in Figure 5-9.
Note that with shielded-twisted-pair, only one cable is required to form the link. The
twisted-pair conductors carry the differential pseudo-ECL signals and the shield is
grounded at the Receiver.

Figure 5-11 Shielded-Twisted Pair Cable Interface

+5 V
+5 V

TAXI R1 R1 TAXI
L, Z0
TX C RX
+ +
C
– –

RE R2 R2
RE

R1R2
= Z0/2
R1+ R2
12330E-18
5R2 Midpoint of Pseudo
= = 3.7 V
R1+ R2 ECL Signal Swing

186 ≤ RE ≤ 7.2 (Z0)

C = Largest RF Capacitor Available

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Sample Values
Using IBM Type 1 STP 150 Ω shielded twisted pair cable, a successful TAXI link was
established using the following component values:
R1 = 101 Ω
R2 = 291 Ω
R3 = 300 Ω
C = 0.1 µF

6.0 BOARD LAYOUT CONSIDERATIONS

While the TAXIchip devices are digital in application, they are essentially analog parts,
containing high frequency analog Phase Locked Loops. Reliable operation in a high
frequency analog and digital environment requires that some simple board layout rules
be followed.
For example, most TAXI applications which are laid out on a wire wrap board will not
work reliably. Because they have at most one power and ground plane, most wirewrap
cards have insufficient separation between small signal current and digital switching
current. Digital switching noise can couple into the analog PLL, causing phase errors
and loss of synchronization. The preferred realization of a TAXI application is on a
printed circuit board, where the user can control the layout of power and ground planes.

6.1 Printed Circuit Board Layout

6.1.1 Rules for Layout
The following rules should be followed to ensure minimal noise coupling:
1. Use a PC board with separate GND and VCC planes.
2. Use two capacitors which differ by at least a factor of ten in value to decouple the
devices. The reactance of large capacitors has a significant inductive component at
high frequencies. Because of this inductive component, a single large capacitor is not
very effective against high frequency noise. Two capacitors, one typically of 1 µF and
one of 0.1 µF are more efficient at decoupling than a single large capacitor of 1.1 µF.
The recommended layout is as shown in Figure 6-1.

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Figure 6-1 Transmitter and Receiver Decoupling Layouts

VCC Plane VCC Plane

A B C2 D C2
Transmitter Receiver
Am7968 Am7969

VCC1 6 C1 C3 7
(TTL) VCC1
Leads must (TTL)
C1 C3
VCC2 be very short
5 GND1
(ECL) C3 (less than 1/4″) 20
GND1 22 C1

VCC3 7 VCC2 8
(CML) (CML) C3
21 C1 C3 21 C1
GND2 GND2
(CML)
C1 = 0.1 µF (ceramic)
C2 = 1 µF Tantalum
C3 = 0.01 µF (ceramic) 12330E-19
To further decouple the TAXIchip set, it is highly recommended that ferrite beads be inserted
at locations A, B and D.

Figure 6-3 Jogs and Glitches in the Clock Line

Normal Overshoot < 0.5 V

CLK or X1
Jog or Glitch

12330E-20
Normal Undershoot < 0.5 V

3. Keep all bypass capacitors as close to the power pins of the device as possible. Lead
lengths should be minimized.
4. Use high quality RF grade capacitors such as type COG or X7R. Use of Z5U capaci-
tors is not recommended.
5. Ensure that the power supply does not have more that 100 mV of peak-to-peak noise
at any of the TAXI Vcc pins. Make this check while the TAXls are sending random
data.
6. While CLK can drive four X1 inputs or several TTL loads, the highest performance
can be achieved by reducing the load on the CLK pin. Care should be taken to en-
sure that no jogs or glitches occur in the CLK signal as shown in Figure 6-3. If pre-
sent, these glitches will be passed onto the PLL and cause an occasional error.

Serial Lines
7. Run serial outputs parallel to each other, or one on top of the other at all times and
route them away from the Transmitter. Do the same for serial inputs on the Receiver.
Running these serial traces adjacently will minimize noise caused by these extremely
fast signals on other traces. Use of strip lines for serial signals is recommended.

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8. When terminating serial lines to or from the TAXls ensure that the Vcc rail or ground
tap is not at a noisy location. Resistors can couple noise from a power supply rail into
the Serial lines. Vcc to Ground decoupling adjacent to the resistors is recommended
when using pullup/pulldown terminating resistor setups as shown in Figure 6-4.
When using only a pulldown, do not use decoupling as this could add more Vcc noise
into the serial signals.

Figure 6-4 Decoupling Terminations

Decoupling
+5 V Capacitor
+5 V
No Decoupling
Capacitor Required
TAXI R1 R1 TAXI
TX RX
+ +

– –

GND
RE R2 R2
RE

12330E-21

6.2 Layout using Fiber Optic Data Links

Because of their small signals levels, fiber optic data links require some care in layout.
Fiber optic data Link receivers consist of a photo sensitive diode and an amplifier. The
photo-diode converts light pulses into currents of around a few hundred nano-amps.
This signal current is then amplified and translated into an ECL signal.
TAXI Receivers and most digital chips switch hundreds of milliamps. If switching noise
from the digital section of the board gets coupled into the optical data link, the signal
from the light pulse data can be corrupted. To prevent the coupling of the optical data
link output with other digital signals, the user must ensure that small signal and digital
switching currents do not flow in the same path. This is done by separating both the
optical VCC plane and the optical ground plane from the V CC and Ground planes used by
other digital circuitry. See Figure 6-5.

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Figure 6-5 Fiber Optic Data Link Decoupling

As Appropriate
0.1 µF 4.7 µF Ferrite Bead (Part# 2743002111 by Fair-Rite)

TAXI VCC Plane

As Appropriate
FODL
VCC FODL GND Plane TAXI GND Plane
.1 µF TAXI GND Plane
Plane
4.7 µF

Logic VCC Plane

Power Supply
Ground

4.7 µF Logic GND Plane

As Appropriate
0.1 µF

12330E-22
Note: This connection includes a ferrite bead in the V CC circuit of the fiber optic components.

7.0 CASCADE MODE OPERATION

The TAXIchip set can be cascaded to send multiple byte words over a single serial
channel. Cascade operation is the loading of n bytes of data into a TAXI Transmitter,
and the serial transmission of that data through the Transmitter to the media. Data and
Command bytes are multiplexed into the Local Mode transmitter. Detailed block diagram
and explanation of the data multiplexing method are described in section 7.1. Also see
Appendix C, TAXI TIP #14.
For Am7969-125 TAXI Receivers, the connection is parallel for data and daisy-chained
for control. That is, the SERIN pins of all TAXI receivers are connected together and to
the media. The daisy chain of IGM to CNB control signals determines which Receiver
latches which incoming byte. The Receiver whose CNB input is connected to +5 V is the
primary Receiver, supplying the initial IGM, as well as a reference frequency for the X1
inputs of the down stream TAXI receivers.
Cascade mode does not increase data rate or throughput. The maximum data rate is
100 Mbits per second, cascaded(2) or not. The advantage of cascading lies in the fact
that the width of the data word is transparently maintained. If the application requires the
transfer of 32 bits of data, Cascade mode allows TAXI transmitters to latch all the data,
and send it over a single serial channel, and receive the data in proper order in four
TAXI receivers at the other end of the link.
Another advantage of cascade mode is that if a byte gets corrupted, the system can be
reset by just sending a Sync, ensuring that the first TAXI Receiver gets the first byte, the
second Receiver gets the second byte, and so on. Performing this reset operation with
latches would require additional logic to decode a Sync command which in turn would
reset all the latches.
For Am7969-175 TAXI Receivers, see Appendix C TAXI TIP #13 for single receiver
cascade operation.

(1)
Actually, in Non Auto-Repeat Cascade Mode, the throughput is less than 100 Mbits/s due to the need to
send Syncs.

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Figure 7-1 Cascaded TAXI System

Mixed Data
Sources

8 4

(Note 2) DI0–DI7 CI0–CI7 STRB ACK

ACK
SEROUT+
SEROUT– TAXI RX #1
TAXI TX #1
TLS DMS X1 X2 CLK

*
12.5 MHz

From an External
TTL Frequency Source

12.5 MHz

VCC
To Next
SERIN+ SERIN– X1 X2 DMS CLOCK SERIN+ SERIN– X1 X2 DMS CLOCK
Stage
CNB TAXI RX #1 IGM CNB TAXI RX #2 IGM
(Note 1) VLTN VLTN
DSTRB DO0–DO7 CO0–CO3 CSTRB DSTRB DO0–DO7 CO0–CO3 CSTRB
8 4 8 4

Data Command Data Command

Destination Destination Destination Destination

Data Path Control Logic Data Path Control Logic

12330E-1

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7.1 Transmit Cascaded Data with a Single TAXI Transmitter

For systems that require data transfer wider than a single byte, a single TAXI Transmit-
ter can be used to cascade the multiple bytes. This operation allows the data to be
multiplexed onto a single serial link, and then automatically demultiplexed and restored
to the original word width. The TAXI Receiver performs this demux operation automati-
cally when connected in the cascade configuration illustrated in the TAXlchip data sheet
and section 7.2.
The circuit shown in Figure 7-2 illustrates the basic technique that may be used to
control multiplexing of word-wide data into a single TAXI Transmitter.
This circuit assumes that the data to be transmitted is stored in appropriate registers
that are all loaded simultaneously. While many systems will already include these
storage elements, in the diagram these registers are shown as 74ALS374 octal D
flipflops. They could be any register with the appropriate number of bits for the data, and
a three-state controllable output. The registers are connected in a TRISTATE MUX
configuration wherein each output can be selected individually.
To clarify the illustration of the technique, the Command lines are not used, and have
been tied low. In systems that send Commands as part of the data stream, these lines
would be buffered in the same way as the data, except that the unused bits (or bytes)
need to be held low when Data is to be sent.
The controller for the automatic multiplexer consists of a shift register that can be loaded
with a 0 that shifts through and selects each data register in sequence, and strobes the
TAXI Transmitter. In the attached figure, this shift register is a 74LS174, but any
collection of flip-flops would serve as well. The shifter is loaded with a 0 when STROBE,
the signal that loads data into the registers, is a 1. The NAND gate (U1) at the input of
the first flip-flop assures that only a single 0 is possible while the registers are being
selected.
STRB for the Transmitter is derived from the CLK output of Transmitter, and is gated by
the same signals that select the data. It is important that no glitches appear on the TAXI
STRB input, since that will cause false data to be sent, and will disrupt the information
transfer. To assure that any race-caused glitches appearing at the output of the four
input NAND gate (U2) are suppressed, the counter must be clocked on the falling edge
of the CLK. This assures that, during the time the outputs are changing, the low on the
CLK input of the two input NAND gate (U3) will suppress anything happening on the
other input. When CLK rises, it will be the only signal active, and there should be no
false strobes. This configuration also assures the longest possible setup time for the
output of the data registers, since the STRB happens immediately before the outputs
change, and a full byte time before they change again. The other gates (U4, U5, U6) are
only buffer and inverters used to assure proper signal sense, and fanout. They may not
be needed in all systems.
Only four stages of shift register are required to select the four data registers, and the
fifth stage shown in the figure is used to provide the SYNC character required for some
cascade systems. The output of the fifth stage (ACK1 stands for one SYNC) is used to
ACK systems that require a SYNC between data words. The output of the fourth stage
(ACK0 stands for no SYNC) can be used for ACK in systems that expect to send
contiguous data, and no SYNCs between words (auto-repeat cascade). Either of these
outputs can be connected back to the DATA STRB input if the system is to run automati-
cally, as in data sampling systems.

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Figure 7-2 Cascade with One TAXI Transmitter

74LS174
ACK0
U1 LOAD1- LOAD2- LOAD3- LOAD4-
STROBE
D Q D Q D Q D Q D Q ACK1
DFF DFF DFF DFF DFF
CK CK CK CK CK
CLK2
CLK1
U6

U5
CLK Buffer;
U2 U3 May Not Be
Required for
Low Fanout
U4 System
LOADEN
32
DATA
8 8 8 8 CLK
CLK
OE- OE- OE- OE-
D Q D Q D Q D Q STRBIN
BUFFERS BUFFERS BUFFERS BUFFERS
STRB
CK CK CK CK SEROUT
2
74ALS374 74ALS374 74ALS374 74ALS374 ACK SEROUT
8 8 8 8
TAXI
BYTE1 BYTE2 BYTE3 BYTE4 8 DATA
4
COMMAND

Four-Byte Cascade Mode Logic 12330E-24

7.2 Receivers In Cascade Mode: Connections (Am7969-125 Only)

Unlike transmitters, all cascaded receivers are directly connected to the media, via the
two serial input data lines. All Receivers see the same serial data at the same time. The
Primary Receiver always receives the first byte of serial data after a Sync. The signals
used by the upstream Receiver to tell the downstream Receiver that it has captured a
byte are IGM (I Got Mine) and CNB (Catch Next Byte). After receiving its byte, the
upstream receiver raises its IGM signal, telling the next Receiver in line that it is to catch
the next byte on the serial line. In this way each succeeding Receiver down the line
catches each succeeding byte.
The second receiver waits for the Primary Receiver to capture data before capturing its
data (the second byte). Similarly, if there were a third Receiver it would wait until the
second Receiver had captured the second byte before capturing the third byte.
The connections of the cascaded (downstream) TAXI Receivers are as follows (see
Figure 7-3):
The CNB input of the cascaded Receiver is tied to the IGM of it’s upstream neighbor.
The CNB input of the first upstream or primary Receiver is tied high.
The IGM output of the last downstream Receiver is left unconnected normally. (This pin
is used differently in Auto-repeat Configuration, discussed in section 7.3).

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X1 is connected to a common Crystal Oscillator or a TTL Clock Source. It is not

recommended that X1 be connected to another Receiver’s CLK output.
X2 is grounded.
The DMS pins of all TAXls must be tied in the same state as the DMS pins on the
Transmitters.
The CSTRB/DSTRB pins on each of the Receivers are all active simultaneously. A
timing description for CSTRB and DSTRB is included in Appendix C, TAXI TIP #89-10
TAXI receiver CSTRB and DSTRB pulse width.
The VLTN pin has timing that is identical to the timing of the Data Out and the Com-
mand Out lines. Its connections are specific to each user’s applications.
If CNB is HIGH, the Receiver will catch the next valid byte of data and hold it. It will not
attempt to catch any more data until it sees a Sync command from the Transmitter or
until its CNB goes LOW and then HIGH again.

Figure 7-3 Receivers in Cascade Mode

12.5 MHz
Crystal
OSC
SERIN–
SERIN+
SERIN– SERIN–
SERIN+ SERIN+

CLK X2 X1 X2 X1 X2 X1

DMS DMS DMS

RX1 RX2 RX3
VCC Am7969 Am7969 Am7969
PRIMARY RX
CNB IGM CNB IGM CNB IGM
N/C
CSTRB CMD DATA DSTRB VLTN CSTRB CMD DATA DSTRB VLTN CSTRB CMD DATA DSTRB VLTN

D23-D16 D15-D8 D7-D0 12330E-25

*Transmission line terminations not shown.

The following section describes the functionality of individual pins:

The DSTRB Pin

Any one of the DSTRBs may be used as the user’s DSTRB to his system. When an
entire word has been received (signified internally by a Sync from the Transmitter) the
data in the Receivers are latched out to the output ports and all the DSTRBs are raised
(simultaneously) one cycle later. Likewise, if Commands are sent as part of the cascade
word, the CSTRB/DSTRB connections must be made appropriately.
Timing description for receivers in cascade mode is included in Figure 7-4.

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Figure 7-4 Receiver Timing—8-Bit Cascade Mode

Internal
Clock*
1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1
SERIN SYNC SYNC DATA 1 DATA 2 SYNC
DATA N
Serial Data
1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1

NRZ Data* DATA N SYNC SYNC DATA 1 DATA 2 SYNC

CLK OUT
1 2 3 4 5 6
CNB TAXI #1 = 1

IGM TAXI #1 =
CNB TAXI #2

Command
NO CHANGE NO CHANGE NO CHANGE NO CHANGE COMMAND 0 NO CHANGE
OUT
CSTRB OUT
TAXI
#1
DATA OUT NO CHANGE NO CHANGE NO CHANGE DATA N–1 NO CHANGE NO CHANGE

DSTRB OUT

Command NO CHANGE NO CHANGE NO CHANGE NO CHANGE NO CHANGE NO CHANGE

OUT
CSTRB OUT
TAXI
#2
DATA OUT NO CHANGE NO CHANGE NO CHANGE DATA N NO CHANGE NO CHANGE

DSTRB OUT

12330E-26
* Internal Signals

If CNB is HIGH, the Receiver will catch the next valid byte of data and hold it. It will not
attempt to catch any more data until it sees a Sync command from the Transmitter or
until its CNB goes LOW and then HIGH again.
If CNB is held LOW, the Receiver will not attempt to capture any data.
When the Primary Receiver RX1 catches a valid data byte it will raise its IGM (I Got
Mine) so the next Receiver RX2 can catch the next byte and so on down the line. After
all the receivers in the system have received their bytes a Sync must be sent or the next
byte of data will be lost(3) .
Referring to Figure 7-5 for a system of Cascaded Receivers.

(3)
In the Auto-Repeat Configuration, a Sync is not required.

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Figure 7-5 CNB and IGM Propagating Down Cascaded Receivers

Time

Serial
Sync Data 1 Data 2 Data 3 Sync
Data

CNB1 =
VCC a b c d

t46

IGM1
CNB2

IGM2
CNB3

IGM3 =
N/C

12330E-27
Note: Half of the byte is sufficient for the Receiver to decide whether the byte is a Sync or Data.

When CNB on the first Receiver is raised (Figure 7-3 it is tied to Vcc), its IGM does not
follow until the first half of a non-Sync byte is detected in its SERIN. Note that if a Sync
is detected, IGM does not go HIGH, since it is a Sync that makes IGM fall.
The IGM on RX1 rises when it sees a non-Sync byte, then since it is tied to the CNB of
RX2. RX2 will now be ready to accept the next byte of data.
RX2 will now wait for the next non-Sync byte to come down the SERIN lines. During this
time all the other downstream receivers will ignore the data on the SERIN lines because
their CNBs are still LOW. In the same way the upstream (Primary) Receiver will ignore
the SERIN lines because it has already caught one byte and thus it will continue to
ignore the data until it sees another Sync.
The IGM on RX2 rises when it sees the second non-Sync byte.
In this fashion, each Receiver will sequentially get ready to receive data as the CNBs
propagate down the IGMs.
When the first Receiver sees a Sync, it will lower its IGM which is connected to RX2’s
CNB which will lower its IGM and RX3’s CNB and so on. In this way the LOW IGM will
also propagate down all the Cascaded Downstream Receivers. CNB falling to IGM
falling is t46 ns.
In normal Cascade mode, the CNB on RXl is tied HIGH and thus, a Sync has to be sent
after all the receivers are full to ensure that RX1 is reset to accept the next byte of data.

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The Data Out Lines

When a Receiver sees the Sync symbol it sends the data byte it just received from its
Input Latch to its Decoder Latch, and then the receiver lowers its IGM. One more clock
cycle is required for the data to go to the Output Latch. At this point DSTRB is raised. In
this way all data bytes are output simultaneously from all receivers, two clock cycles
after the first Sync (or two clock cycles after a LOW CNB). The DSTRBs of all the
receivers rise simultaneously as well.

The VLTN (Violation) Pin

In Cascade mode the VLTN pin acts exactly like a Data Out line. The timings are exactly
the same. Violations do not change the output of the IGM pin. i.e., a Receiver that gets a
VLTN will still raise it’s IGM signal as if it received a valid data byte.

7.3 Auto-Repeat Configuration

7.3.1 Receiver Connections in Auto-Repeat Configuration
In Auto-repeat Configuration the IGM of the last Receiver on the line is inverted and tied
to the CNB of the Primary Receiver. This connection eliminates the need to send a Sync
between each Data Word.
In a 3-Receiver cascade system, IGM3 is inverted and tied to CNB1. When the IGM of
the last Receiver goes high, CNB1 goes LOW.
CNB1 going LOW ripples through the chain pulling each IGM LOW (t46 ns) until finally
the last IGM goes LOW again, pulling CNB1 HIGH resetting RX1 to receive new data.
In Figures 7-6 and 7-7, as each Receiver decodes its data byte, it raises its IGM and
thus the next Receiver’s CNB.

Figure 7-6 TAXI Receiver—Cascaded in Auto-Repeat

SERIN+
SERIN–

CNB IGM CNB IGM CNB IGM CNB IGM

CSTRB DSTRB CSTRB DSTRB CSTRB DSTRB CSTRB DSTRB

12330E-28

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Figure 7-7 Receiver Timing in Auto-Repeat Configuration

Serial
Sync Data 1 Data 2 Data 3
Data

CNB1

IGM1
CNB2

IGM2
CNB3

IGM3 =
12330E-29
CNB1
Note:
Only when a Receiver has a CNB = 1, can it accept new data. It then raises its IGM when it sees a non-Sync
byte. It won’t accept another data byte until it’s CNB has gone LOW and HIGH again.

When IGM1 goes high, CNB2 goes high. This allows RX2 to decode the next byte and
raise it’s IGM. IGM2 is connected to CNB3 and RX3 is now allowed to decode the next
byte and raise its IGM.
In Figure 7-8 since IGM3 = CNB1, CNB1 goes LOW.
When CNB1 goes LOW, RX1 is reset and it pulls it’s IGM LOW (t46 ns).
Since IGM1 is connected to CNB2, RX2 is reset and pulls its IGM LOW t 46 ns later.
CNB3 = IGM2 goes LOW, which causes IGM3 to follow it LOW t 46 ns later. IGM3 going
LOW makes CNB1 go HIGH again and RX1 is now set to receive the next byte of data
on the SERIN.
See Figure 7-9. Thus, the cycle starts over again.

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Figure 7-8 Receiver Timing in Auto-Repeat Configuration

Serial
Sync Data 1 Data 2 Data 3
Data

CNB1

t46

IGM1
CNB2

IGM2
CNB3

IGM3 =
CNB1
12330E-30

Note:
When IGM3 goes HIGH CNB1 goes LOW. Thus, IGM1 = CNB2 goes LOW t46 ns later, and IGM t46 ns after
that. This will ripple down to IGM3.

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Figure 7-9 Receiver Timing in Auto-Repeat Configuration

Serial
Sync Data 1 Data 2 Data 3 Data 4 Data 5 Data 6
Data

CNB1

IGM1
CNB2

IGM2
CNB3

IGM3 =
CNB1

12330E-31
Note: IGM3 = CNB1 so RX1 is now ready to receive new data. The cycle can now be repeated.

7.3.2 Timing Limitations of the Auto-Repeat Configuration

Note, however, that the t46 delay adds up as it ripples through the daisy chain. If the total
delay from the first to the last Receiver in the cascade is greater than 1 byte time,
parallel data will output 1 byte time later on some Receivers than on others.
The following example is for t46 = 20 ns and a 12.5 MHz byte rate, the time between the
start of one byte to the start of the next is 80 nanoseconds. When IGM on the last
Receiver goes HIGH forcing the CNB1 on the first one to go LOW, it will take 20 x R ns
(where R is the number of Receivers in cascade) before the last IGM goes LOW again,
(allowing CNB on the first Receiver to go HIGH).
In order for the first Receiver to capture the next byte its CNB cannot remain LOW for
more than X ns (where X must be less than 1 byte period).
X = (20 x R1) + (inverter delay) + (CNB to CLK set-up)
(R1 is the number of receivers that can be connected in cascade in this format)
The CNB to CLK set-up time is specified as t47 = [(byte time/n) –32 ns]
In 8 Bit mode at 12.5 Mbyte/s, CNB to clock setup = - [(80/10) –32] = 24 ns
Figure 7-10 demonstrates an alternative scheme which will allow a virtually unlimited
number of receivers to be cascaded. The fan-out of the inverter dictates the number of
AND gates that can be driven. Multiple inverters can be connected to the last IGM
output if needed. Using this scheme guarantees that all of the receivers in cascade will

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output data at the same time This also guarantees that the CNB on the first Receiver
goes active (HIGH) within 2 gate delays + 20 ns after it goes LOW. This leaves enough
time for the first Receiver to capture the (R+1)th byte of data.

Figure 7-10 TAXI Receiver—Cascaded In Auto-Repeat Configuration.

Configuration 2
SERIN +
SERIN -

CNB IGM CNB IGM CNB IGM CNB IGM

CSTRB

DSTRB
CSTRB

DSTRB

CSTRB

DSTRB

CSTRB

DSTRB
12330E-32

Figure 7-11 TAXI Receiver—Cascaded in Auto-Repeat Configuration.

Configuration 3

SERIN+
SERIN–

CNB IGM CNB IGM CNB IGM CNB IGM

CSTRB DSTRB CSTRB DSTRB CSTRB DSTRB CSTRB DSTRB

12330E-33

In practice, all the AND gates are not required. Using the above equation for X we can
calculate a value of R1 for which X is less than 1 byte period at the appropriate fre-
quency of operation. Then if the number of receivers to be cascaded is greater than R1,
an AND gate is needed for every (R1+1)th Receiver in cascade. The other receivers can
be directly connected as shown in Figure 7-11.

Syncs in Auto-Repeat Configuration and Recovering from Errors

A Sync in Auto-Repeat Configuration acts much like a Sync in Normal Cascade mode. It
resets all the Receivers and their IGMs so the upstream (Primary) Receiver receives the
next non Sync byte of data. This remains as the method of recovering from byte framing
errors.

7.4 Unbalanced Configuration (Am7968/Am7969-125 Only)

In reality there is no difference in connection between balanced and Unbalanced
Configurations. The name only indicates that the number of Transmit bytes and the
number of Receive bytes are unequal.
The TAXI Receivers do not care how many data bytes the Transmitter is sending to
them. One data byte can be transmitted to several Receivers. The only limitation here is

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the drive capability of the Transmitter and the termination circuit for multidrop transmis-
sion lines. Similarly, several Transmit bytes can be multiplexed to one Receiver. There
are no drive considerations in this case.
Figure 7-12 shows an example of an unbalanced mode of operation in which one
Transmitter is connected to three Receivers.

Figure 7-12 Unbalanced Configuration Example: One Transmitter to Three Receivers

TTL Data IN
8,
9,
10

+
SEROUT Am7968
–
X1 X2

OSC
Clock

X1 X1 X1
SERIN SERIN SERIN
VCC CNB IGM CNB IGM CNB
8, 8, 8,
9, Am7969 9, Am7969 9, Am7969
10 10 10

TTL Data OUT 12330E-34

Note that in the Unbalanced Configuration, attention has to be given to where a Sync
will be needed. Either the Auto-Repeat Receiver Configuration should be used or a
Sync must be provided every (R + 1) bytes, where R is the number of Receivers
cascaded together. More information on proper use and requirement of SYNC, refer to
Appendix C, TAXI TIP #8903.

8.0 TEST MODE

The Phase Locked Loops (PLLs) in the TAXlchips are designed to run within a fre-
quency range that has been set for maximum efficiency and accuracy. The lower limit of
this frequency range is 40 MHz.
In Test Mode, the PLLs of the Transmitter and the Receiver are disconnected and the
internal clock is applied from an external source. This allows the TAXls to function at a
much slower speed. This mode was designed to simplify the testing of TAXls in an
automatic testing production environment. A by-product of Test Mode is that it allows the
user to run the TAXls in systems that are slower than 4 MHz (the minimum byte rate). In
this mode there is no minimum frequency.
A system that needs to transfer data at LOW byte data rates can normally be imple-
mented without modifying the standard setup, and Test Mode need not be used. When
there is no data to be sent, the TAXlchips will keep the line active by sending Syncs.

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The serial link will operate in the 40 to 175 MHz range as determined by the byte rate
clock, but the byte data rate will be determined by how often the user strobes the TAXI
Transmitter. The transmission speed is transparent to the user.
Some applications may have a serial link bandwidth limitation. Typically, this means that
the media connecting the Transmitter to the Receiver can only handle serial data rates
that are lower than 40 MHz. The user can run the TAXlchips in Test Mode in order to
overcome the 40 MHz lower frequency limitation.
For convenience in the following discussions, encoded data width n has been set to 10,
corresponding to an 8-bit input byte, (i.e. DMS = LOW).
Since the multiplying PLL is turned off in Test Mode, an external clock source must be
supplied to the TAXls. In normal (non-test) mode, the Transmitter PLL multiplies the
byte clock by 10. The new 10X clock is called the bit clock or bitclk, and is used to
transmit the serial data. The Receiver PLL generates the same type of bitclk to decode
the incoming data and to track and follow any fluctuations in the transmission frequency
of the incoming data.
In test mode the Transmitter PLL is disconnected and the internal clock multiplier is
switched out. The internal logic is now clocked directly by the signal applied to the CLK
pin. The input to the CLK pin now becomes the bitclk and must be supplied by the user.
On the Receiver side, the internal data tracking PLL is disconnected in Test Mode. An
external clock recovery circuit must be used to allow the Receiver to track the incoming
serial data stream. This recovered bitclk is supplied to X1. Either a digital PLL or an
analog PLL (for faster rates) can be used for clock recovery as shown in Figure 8-2.
The Transmitter and Receiver Test Mode connections and functionality are given in the
following section.

8.1 Transmitter Connections

Refer to Figure 8-1.
The TLS pin is left floating. This is the pin that puts the Transmitter in Test Mode.
The RESET pin is left floating. RESET pin function is described in Appendix C, TAXI TIP
#89-02. The X2 pin is grounded.
SERIN is left floating (D/C = Do Not Connect).
The DMS pin is set in the appropriate state for 8-, 9- or 10-bit mode as desired by the
user.
The CLK is now an input for bitclk (the bit rate clock). This means that if the serial
transmission rate is to be 1.5 Kbits/s, CLK must be 1.5 kHz.
The ACK pin is raised only when a Sync byte is detected in the Transmitter’s shifter
latch (note that if STRB is lowered before ACK is seen, ACK will be suppressed. See the
STRB/ACK description in Section 7.1).
The X1 input is the reset pin for the internal state machines and can be left unconnected
in operational systems. For testing purposes, the following steps are to be taken upon
power up or initialization.
1. X1 should be kept HIGH and the Transmitter bitclked about 15 times
2. X1 should be lowered and the Transmitter bitclked about 200 times.

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This serves to flush all extraneous data from the buffers and reset all internal state
machines. Once this is completed the Transmitter may be Strobed. X1 should be left in
the LOW state upon completion of the initialization.
The STRB input must now be strobed only once every n = 10 bitclk pulses or more. This
will allow time for an 8 bit wide byte to be encoded to 10 bits and shifted out one bit
every clock pulse.
The parallel data input pins are provided with new data every 10 bitclk pulses. Setup
and hold times remain the same as in non-Test Mode with respect to STRB. (In the
non-Test modes, the clock rate is the byte rate and a new data word and a strobe is
provided every clock pulse. In test mode, the clock rate is the bit rate so the new data
word and strobe are provided every n clock pulses).
In Test Mode the Receiver expects only single ended data. Thus only one of the
SEROUT lines from the Transmitter is used. However, both lines must have pulldown
resistors to electrically balance the outputs.

Figure 8-1 Transmitter Test Mode Connections

Divide By n
or Byte Rate
Clock N/C

ACK TLS X1

STROBE

Data IN X2
8, 9, 10 RESET
Am7968
Bit Rate
CLK Clock
Generator
Command IN
4, 3, 2 CLS N/C = Test Mode

DMS
SEROUT+ SEROUT–
Can Be Set
for 8, 9, or
10-Bit Mode
300 Ω

300 Ω
To Receiver
Media Interface

12330E-35

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8.2 Receiver Connections

Refer to Figure 8-2.
Grounding SERIN– puts the Receiver in Test Mode. SERIN+ is a single ended 100K
ECL NRZ input.
The X1 pin now becomes the bit rate clock input (bitclk), just like the CLK pin on the
Transmitter.
The CLK pin remains a byte rate CLK out.

8.3 Timing Relationships in Test Mode

The timing parameters in Test Mode are similar to the parameters in standard mode.
Propagation delay values remain the same, however bit time relationships are now
calculated with respect to the new bit times. For example, using a bitclk = 1.0 kHz, which
is a 1 ms period, the byte time t35 = 10 bits x 1 ms = 10 ms. In the same way t 37, which is
the CLK falling to STRB rising delay is now [2 (t35/n) + 15 ns] = 2.015 ms. Note that
Setup and Hold times for SERIN to X1 are not specified and must be determined for
each application.

Figure 8-2 Receiver Test Mode Connections

Normal
Function

Single Ended
DSTRB CNB SERIN+ Input From
DATA STROBE Transmitter

SERIN–

DATA OUT X1
8, 9, 10 Am7969 X2
CMD STROBE RESET
CSTRB Clock Recovery
Circuit
Digital or Analog
COMMAND OUT PLL
4, 3, 2 CLK

DMS Byte Rate CLK Out

VLTN IGM

DMS Can Be
Set For 8, 9, or
Normal 10-Bit Mode
Function
12330E-36

TAXIchip Integrated Circuits Technical Manual 89

APPENDIX A

Fiber Optic Data Link Manufacturer List

Presented below is a partial listing of fiber optic data link suppliers that manufacture or
market optical components in a data rate range compatible with the TAXIchip set.
Several of these components have been demonstrated in a bench level evaluation in
conjunction with the TAXlchip set.

AMP
1 (800) 552-6752
(416) 475-6222 (Canada)

AT&T Microelectronics
(800) 372-2447

BT&D Technologies
Delaware Corporate Center 11
Suite 200
2 Righter Parkway
Wilmington, DE 19803
(800) 545-4306

Hewlett Packard
Customer Information Center
(800) 752-0900

Sumitomo Electric
777 Old Saw Mill River Rd.
Suite 230
Tarrytown, NY 10591-6725

90 TAXIchip Integrated Circuit Technical Manual

APPENDIX B

Error Detection Efficiency

When a received data pattern does not represent a valid coding symbol, the TAXI
Receiver asserts the VLTN pin to indicate that the current data contains an error.
The Receiver cannot detect the occurrence of a bit error that transforms one valid
symbol into another valid but incorrect symbol. This means that the transition error can
change a valid data symbol into a different valid data symbol, or in certain cases a valid
Command symbol and not be flagged by the Violation pin.
A single noise event on the serial link can cause at a minimum a double bit error. Single
bit errors are assumed to be impossible (or at least rare) because NRZI encoding would
require that the voltage level on the link be inverted after the event. There is no known
error mechanism external to the TAXIchip set which could cause this condition. Having
confirmed that all errors are at least 2 bits wide, let us examine the location at which
these errors can exist.
Consider the 4B/5B encoded data pattern for the TAXIchip set in the 8-bit mode. The
output corresponds to two five bit nibbles for each eight bit data byte. Shown below are
four nibbles, or two bytes of encoded data output, with six possible locations for double
bit errors within nibble 1 of Byte 2.

Figure B-1
Byte 2 Byte 1

Nibble 2 Nibble 1 Nibble 2 Nibble 1

MSB LSB MSB LSB MSB LSB MSB LSB

b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

A
B
C
D
E
12330E-37
F

Notes:
Error location A corresponds to a double bit error occurring in the Least Significant Bit of nibble 2 and the
Most Significant Bit of nibble 1.
Error locations B, C, D and E occur within the nibble between adjacent bits, and,
Error location F occurs between the LSB of nibble 1 (Byte 2) and the MSB of nibble 2 (Byte 1).

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For example, consider transmitting Hex B [1011], encoded as 10111. Error E occurs
changes bits b0 & b1, resulting in encoded pattern 10100, which is Hex 2 [0010]
2 bits changed, and the run length the error = 4 bits,
1011 becomes
0010
2 bits changed, and the run length
the error = 4 bits,
A double bit error can change valid data into a Violation, a valid Command byte, a 1-bit,
2-bit, 3-bit,or 4-bit data error. A summary of the occurrence of these errors for the six
error locations for 4B/5B encoding is summarized below in Table B1.

Table B-1 Error Type

A B C D E F
V=5 V=5 V=5 V=3 V=3 V=1
C=5 C=3 C=5 C=3 C=5 C=1
1B=4 1B=0 1B=2 1B=4 1B=0 1B=14
2B=2 2B=8 2B=4 2B=6 2B=6 2B=0
3B=0 3B=0 3B=0 3B=0 3B=0 3B=0
4B=0 4B=0 4B=0 4B=0 4B=2 4B=0

Table B-2 Similar reasoning for the 5B/6B encoding scheme results in seven possible error
locations, and the summary of the occurrence of these errors is listed below:
A B C D E F G
V=13 V=16 V=12 V=6 V=9 V=10 V=5
C=3 C=2 C=2 C=4 C=3 C=4 C=3
1B=10 1B=0 1B=0 1B=0 1B=8 1B=2 1B=22
2B=6 2B=14 2B=12 2B=14 2B=12 2B=12 2B=2
3B=0 3B=0 3B=4 3B=6 3B=0 3B=0 3B=0
4B=0 4B=0 4B=2 4B=2 4B=0 4B=4 4B=0

Utilizing this information one can determine the efficiency of the violation logic in the
TAXI Receiver. Figure B2 summarizes the violation effectiveness, as well as depicting
the number of bits in error in the undetected corrupted data. This information can be
extremely useful in determining what, if any, additional error detection schemes should
be implemented. Figure B3 graphically represents the run length of the corrupted data
for the undetected errors. As shown in this figure, there are a small percentage of
unlimited run length errors. This is due to the few data patterns, which, when corrupted
will cause a false Sync pattern to be generated. This pattern will cause a running error
which will continue until the next valid Sync realigns the byte edge to its proper position.
While these false Syncs occur very rarely, these are the most dangerous errors in a
TAXI system, this very well may dictate the maximum user packet size.

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Figure B-2
60
50
40
Percent of
Error 30
Events
20
10
0

Violation 1-Bit Error 2-Bit Error 3-Bit Error 4-Bit Error

8 Bit

9 Bit 12330E-38

10 Bit

Figure B-3

50
40
Percent of
30
Undetected
Error Events 20

0.027%
0.104

0.57
10
0

1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit Unlimited

Run Length of Error in Corrupted Data
8 Bit

9 Bit

10 Bit 12330E-39

TAXIchip Integrated Circuit Technical Manual 93

APPENDIX C

TAXI Technical Information Publications

The TAXI applications team has documented questions and answers that are general
purpose in nature and applicable to a wide range of applications. This documentation
has taken the form of TAXI Technical Information Publications (TlPs), and have been
incorporated in this revision of the technical manual. The contents of this appendix are
as follows:
TAXI TIP # 1: Subject: Receiver Response to Loss of Input Signal
TAXI TIP # 2: Subject: TAXlchip RESET Pin Function
TAXI TIP # 3: Subject: Proper Use for TAXI Sync
TAXI TIP # 4: Subject: TAXI PLL Lock-Up During Power-On!
TAXI TIP # 5: Subject: TAXIchip set Crystal Specification
TAXI TIP # 6: Subject: TAXI for FDDI Applications
TAXI TIP # 7: Subject: Synchronous vs. Asynchronous Strobe
TAXI TIP # 8: Subject: TAXI Receiver Lock Time
TAXI TIP # 9: Subject: TAXI Bridge: Bidirectional TAXI Communication
TAXI TIP # 10: Subject: TAXI Receiver CSTRB and DSTRB Pulse Width
TAXI TIP # 11: Subject: Using Receiver CLK Output to Run a TAXlchip Transmitter
TAXI TIP # 12: Subject: TAXlchip Pins Internal Circuit
TAXI TIP # 13 Subject: Demuxing a TAXIchip Receiver to Output Multi-Byte Words
TAXI TIP # 14 Subject: 32-Bit Multiplexed Cascade with the TAXIchip Transmitter
TAXI TIP # 15 Subject: General Device Information for 125/175 MHz TAXIchips
TAXI E.B. Nov ‘89: Subject: TAXlchip Error Rate Example

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TAXI TIPs

TAXI Technical Information Publication #89-01

Subject: Receiver Response to Loss of Input Signal

Question:
It is desired that the TAXI Receiver outputs be predictable and stable during conditions
when the TAXI Transmitter may cease transmitting (power-off) or is disconnected. How
can a system designer predict the TAXI Receiver outputs or use the TAXI Receiver in a
system where the TAXI Receiver must appear Inactive under these conditions? This
applies to both Coaxial and Fiber-Optic Systems.
Answer:
The key to this problem is interpreting the loss of incoming Tx data as a Quiet-Line-
State and either flagging the system accordingly or gating the TAXI Receiver outputs
with an inactive flag.
In a Coaxial coupled system the loss of incoming signal drive will cause the TAXI
Receiver inputs to rest at the input termination bias voltages. The differential serial
inputs will normally be at equal potential. To properly interpret a loss of signal as a
constant quiet state the input termination bias voltages must be altered slightly from
each other. To allow reliable interpretation of the offset as a constant logic state, the
offset voltage should typically be set to about 50 mV.
The TAXI Receiver will interpret the Quiet-Line-State differently depending upon the
operation mode (8-bit, 9-bit, or 10-bit). In 8-bit mode the Receiver will generate continu-
ous CSTRB’s with the Command outputs at F Hex, or all HIGH. In the 9-bit and 10-bit
modes there is no defined interpretation of an incoming quiet data stream. This will
cause the TAXI Receiver to generate continuous CSTRB’s and the Violation output will
be continuously HIGH. A one-shot may be used to determine Violation=HIGH duration
and then generate an inactive flag, or the system may interpret the Violation output
directly as an inactive or invalid condition flag and halt data-dependent system opera-
tions during any byte with Violation=HIGH.
In a Fiber-Optic coupled system two methods may be used, depending on the Optical
Receiver construction. If the Optical Receiver has a Carrier-Detect output this signal
may be used to flag an inactive state. If there is no Carrier-Detect, one may be gener-
ated using an ECL one shot arrangement which will detect loss of edges after a
predetermined period of say, for example, 80 bit times. The actual time may vary
depending on the desired response to loss of data.
In either condition, if the Receiver recovered Byte Clock (CLK) is used as a system
clock, then the system must be able to tolerate a shift in the CLK frequency of typically
about +/-3% to allow for Rx-PLL offset and drift during this period. (If the Optical
Receiver begins oscillation when the fiber is dark, the TAXI Receiver PLL may attempt
to track the oscillation resulting in an indeterminate Rx recovered clock frequency.
Optical Receiver dark response thus becomes a possible system concern.)

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TAXI Technical Information Publication #89-02

Subject: TAXlchip RESET Pin Function

Question:
How long must the RESET pin be held low in order to insure that the TAXIchip has
reset?
Answer:
The RESET pin is level sensitive and after a LOW input level is asserted it instantane-
ously forces the Phase Lock Loop (PLL) to its lowest possible frequency (approximately
5 to 10 MHz). A 1 ms LOW pulse should allow sufficient time for the PLL to reach a
stable state. Preliminary tests conducted in the lab reported that for the full TAXI
frequency and temperature range, the time required to recover from a reset was less
than 100 µs.
Resetting is intended to allow graceful recovery from the rare occurrence of a PLL
lock-up due to noise bursts on the serial data lines, as may occur when light is removed
from certain optical links. In a fiber-optic coupled system, loss of optical signal may
cause the optical receiver to oscillate, causing the TAXI Receiver to track the oscillation
to an indeterminate frequency. Care must be taken to avoid the oscillation, or a reset
can be used to recover from it. After reset, the PLL begins tracking incoming data, and
the byte boundary remains undefined until the transmitted data includes a Sync (JK).
The Sync is a unique bit pattern which forces the TAXI Receiver to align itself to the
correct byte boundary.
In a coaxial system when a loss of incoming signal drive occurs, there will be no data for
the TAXI Receiver to track. This quiet state will be interpreted as a continuous data
pattern. The Receiver decodes this Quiet-Line-State differently depending upon the
operational mode selected: 8-bit, 9-bit, or 10-bit. In 8-bit mode the TAXI Receiver will
generate continuous CSTRBs with command outputs all high ( F Hex). In 9-bit or 10-bit
modes there is no defined interpretation of an incoming quiet data stream thus generat-
ing continuous CSTRBs and forcing the violation output (VLIN) to be continuously high.
Further information on the effects of incoming signal drive loss is available in TAXI TIP
#89-01, Receiver Response to Loss of Input Signal.

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TAXI Technical Information Publication #89-03

Subject: Proper Use for TAXI Sync

Question:
What is the proper use for Sync? How often is a Sync needed?
Answer:
When a Transmitter has no data to send, it sends Sync. This symbol allows the
Receiver PLL to maintain phase and frequency lock with the transmitter, exactly as
would a normal DATA stream. It has the additional special property of being a unique bit
pattern that can be used to discover the byte boundaries in an otherwise continuous
bit stream.
The Receiver PLL takes some time to achieve phase and frequency lock (as described
in section 3.3). After lock is achieved the TAXI Receiver must align the incoming data to
the proper byte boundaries. The Receiver logic compares the incoming bit stream (bit by
bit and without regard for byte boundaries) with the pattern for Sync, and when it is
found, forces an internal bit counter to 0. The internal counter then continues to count
bits and run the byte rate logic without further reference until another Sync is found.
From this description of the Sync function, it is obvious that only ONE Sync symbol is
ever really required to define the byte boundary for the TAXI Receiver if the internal
counter continues to count correctly. It is unlikely that the internal logic function will
make a mistake, and therefore the counter will continue to count off the proper number
of bits per byte forever. However, there is some chance that noise can corrupt DATA
into a pattern that looks exactly like the Sync symbol. (The chance is about 0.13% of all
possible error types.) When this happens, the byte boundary is forced to an incorrect
position, and all data following is decoded incorrectly. TAXI Receiver violation detection
logic may or may not flag the errors, but the Receiver cannot distinguish properly framed
data from incorrectly framed data. The only thing that can correct this running error is
another Sync.
The minimum number of Syncs required in a user data stream is dictated by the system
sensitivity to running errors, and the system’s built in error detection mechanism.
However, it is a good practice to send a Sync every 1000 bytes.
Systems that send packetized data, should allow a Sync between each packet. This will
assure that if an error occurs, it will be terminated at the end of the packet and will not
corrupt the succeeding packets. Systems that send data at a rate slower than the TAXI
byte rate will have Sync automatically inserted as pad characters, so the user may not
need to specifically insert them.
Systems that send byte or short phrase data (commands or control words, for example)
might send a Sync before each byte or phrase to assure that the message is not missed
because of an earlier framing error.
From this discussion it should be clear that there is no RIGHT NUMBER of Syncs to
send with TAXI data. The correct number is dependent on the type of data the user is
sending, and the system sensitivity to running errors.

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TAXI Technical Information Publication #89-04

Subject: TAXI PLL Lock-Up During Power-On!

Question:
Is there a recommended power-on sequence for the TAXIchips to prevent PLL lock-up?
Answer:
Early versions of the -70 TAXIchips did have some sensitivities associated with hot-
plug-in lock-up, fast VCC rise time, and/or power supply sequencing during power-on
causing occasional PLL lock-up. These potential problems were addressed in the -125
TAXIchips with an improved circuit design. The -125 TAXIchips do not exhibit any
known power-on problems, but a PLL Reset function is available on a package pin and
may be used to restart the PLL if problems occur.
Use of the external PLL Reset pin should not be necessary with the -125 TAXIchips, but
there may be specific situations where its use may be helpful with the TAXI Receiver.
There are possible situations where large amounts of noise may occur on the Receiver
serial data inputs. Under these conditions the Rx-PLL may attempt to track the noise to
an indeterminate frequency. This deviation in frequency may adversely affect data
recovery when a good data stream reappears. System requirements may also place a
restriction on the allowed clock frequency deviation. Use of the PLL Reset function on
the Receiver may assist in the containment of some of these effects.
All VCCs may be powered-on simultaneously with a common supply. It is only recom-
mended that the TAXI GND pins be connected to a common Ground and the V CC pins
be separately filtered and decoupled to that Ground. Variations in power-on times due to
separate VCC filtering and decoupling are not a problem. Use of a common VCC supply is
sufficient as long as noise filtering of the supply at the TAXI V CC pins is adequate,
therefore use of separate power supplies for the VCCs is usually not necessary.

Refer to Section 6.1, for more information concerning power supply layout and decoupling. Further
information is also available in TAXI TIP #89-02, TAXI Receiver RESET Pin Function.

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TAXI Technical Information Publication #89-05

Subject: TAXIchip Set Crystal Specification

Question:
What are the design considerations for crystals used with TAXIchip set?
Answer:
The TAXIchip’s parallel mode oscillator uses a 4.0 MHz – 17.5 MHz crystal with a
frequency tolerance of 0.1%.
Any crystal will oscillate in either series or parallel mode depending upon the type of
oscillator used. By specifying parallel mode and the load, the manufacturer will calibrate
the crystal in parallel mode at the desired frequency. This could be important in
applications where frequency tolerance is critical due to the fact that the resonant
frequency in parallel mode is typically 0.02% above the series mode frequency.
As discussed in section 3.3, the time required to synchronize the data recovery circuit in
the Receiver is proportional to the delta between the Transmitter frequency and the
Receiver PLL resting frequency. The Receiver resting frequency is typically less than
±1% away from its own crystal frequency, due to mismatch between internal circuits.
The crystal specification of 0.1% is meant to be small enough to cause a negligible
effect on lock time while not increasing the crystal cost (0.025% crystals are quite
common). Sometimes tighter frequency and tolerance specifications may be necessary
to meet the user’s system requirements (i.e. FIFO depth, etc.).
More information on crystal specifications for the TAXIchip set may be found in
Section 4.1.1.
A partial list of vendors follows:

Typical 12.5 MHz

Distributor Part Number Phone Number
I.E.A. HC18U 12.500 (408) 435-1000
Calmax Corp. UM-12.5 (714) 957-1299
Monitor Products MM 49XlE12A-12.5 (619) 433-4510
Anderson Electronics 011-668-03260 (814) 695-4428
Target Electronics CC025A-12.5 (408) 733-0384

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TAXI Technical Information Publication #89-06

Subject: TAXl for FDDI Applications?

Question:
Can the TAXIchip set be used for FDDI physical layer applications?
Answer:
The TAXIchip set is code compatible with the FDDI physical layer but there are restric-
tions in the design which would cause difficulty in using the TAXIchip set for the physical
layer of an FDDI node. The TAXIchip set by itself cannot be used to build a fully
compliant FDDI node, although it provides several of the functions required.
The TAXI Transmitter is compatible with FDDI at the physical layer electrical interface
and can send all codes specified by FDDI. An exception to the encoding is that Quiet-
Line-State (QLS) is defined as fiber-dark for FDDI, requiring a static SEROUT=LOW,
and the Transmitter defines the equivalent of QLS, as Command F, as no-transitions,
with no control of the static logical state.
The TAXI Receiver is also compatible with FDDI at the physical layer electrical interface
and can recognize the codes specified by FDDI, with restrictions. The restrictions
concern Master-Line-State (MLS), Halt-Line-State (HLS), and the carrier detect function.
MLS and HLS are terms describing a data stream composed of a consecutive string of
HQ and HH symbols respectively, representing a line-state condition. The Receiver will
decode these symbols, but it does not count them to signal line-states as required
by FDDI.
MLS and HLS are relatively long run-length signals with 10 and 5 bit-times between
transitions respectively, as compared to a maximum limit of 3 bit-times for data. The
Receiver PLL was designed for wide operating frequency range, with tradeoffs in the
ability and time required to capture long run-length data sequences. The FDDI specifica-
tion allows 100 µs for the Receiver to lock upon and detect MLS following a long period
of QLS. A typical TAXI Receiver will meet these criteria but the production parts are
neither tested nor guaranteed for this condition. There are no problems associated with
tracking the MLS signal once the PLL has acquired lock.
HQ and HH, within the TAXI Receiver, require proper byte framing for detection. MLS and
HLS as specified by FDDI are not framed, therefore the transition may be located at any of
the ten bit locations. The result, as decoded within the TAXI Receiver, will be as follows:
MLS: 00100 00000 = HQ CMD-A 10% probability
00000 00100 = QH CMD-D 10% probability
all other = Violation 80% probability
HLS: 00100 00100 = HH CMD-8 20% probability
all other = Violation 80% probability
The FDDI line state definition does not preclude the insertion of an occasional sync
into the MLS or HLS data stream for proper framing, solving the recognition problem.
If full FDDI compliance is required, MLS and HLS must be detected external to the
TAXIchip set.
The carrier detect function, as specified by FDDI, requires the flagging of a QLS to the
MAC layer as long as the fiber is dark. The TAXI SERIN inputs must be static for this
condition to be met by the TAXI Receiver. This problem must be addressed directly by
the Optical receiver or gating of its outputs.
Functions of the FDDI MAC layer interface are not directly addressed in the TAXI
designs.

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TAXI Technical Information Publication #89-07

Subject: Synchronous vs. Asynchronous Strobe

Question:
When should synchronous vs. asynchronous strobing be employed?
Answer:
Inputs to the TAXI Transmitter can be strobed asynchronously, but with some limita-
tions. In local mode, the STROBE edge can rise at any time, without regard for place-
ment within any particular byte. The data associated with the STROBE (STRB) will be
latched into the Transmitter, and will be transmitted at the earliest opportunity. If some
system limitation insures that a second STRB cannot ever be within the same byte time
(80.0 ns at 125 MHz), then there is no need to observe the ACK output of the TAXI
Transmitter.
If no such guarantee exists, then ACK must be used to insure that no more than two
STRBS lie within a single byte. Again there is no restriction on STROBE placement
within a byte, since ACK will always insure that the capacity of the TAXI input buffer is
not exceeded. The TAXI input buffering can handle two STRBS within a single byte, but
this additional buffer must be flushed by the absence of a STRB in a given byte before
another two-strobe byte is encountered.
In an early revision of the 70 MHz Transmitter, there was a particular placement of
STROBE with respect to the falling edge of CLK, that could cause loss of data. This lead
to several revisions of technical literature mentioning the Prohibited Zone, and Uncer-
tainty Zone. This restriction in STROBE placement has been removed in the 125 MHz
version of the Transmitter. T6 in the data sheet, now refers only to the exact placement
of the internal byte boundary. Knowledge of this time is only important for synchronous
systems to predict in which byte the data will appear.
The only restriction on Local mode asynchronous STRB input would be in systems
which require contiguous data output from the TAXI Receiver. It is possible that when
strobing asynchronously, there will be an occasional byte with no strobe, and another
nearby byte with two strobes. The Transmitter has sufficient buffering to handle this
condition, but will pad the missing byte with a Sync character. For systems that have this
restriction, STRB should be made synchronous with the CLK of Transmitter.

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TAXI Technical Information Publication #89-08

Subject: TAXI Receiver Lock Time

Question:
In a fully operational system in which both the Transmitter and Receiver are powered
on, how long will it take for the Receiver to lock to new data after a quiet line?
Answer:
When data transmission stops and the link becomes quiet, the TAXI Receiver PLL will
drift to its natural resting frequency which by design, is less than 3% away from the
reference frequency applied at the X1 pin.
When data appears on the line, the Receiver PLL will achieve phase lock in a time
which is proportional to the incoming data edge density and PLL loop bandwidth.
Because this lock time is dependent on the data being transmitted, the time it takes for
the receiver to lock will depend on the specific system application. In Section 3.3, three
types of data are represented and their calculated lock times are shown. By dividing the
lock time for a specific data pattern by the X1 clock period, the number of bytes to lock
the PLL can be calculated.
Because time to lock is dependent on many variables, it is represented as a typical time.
If time to lock is critical to the specific application, we suggest you allow at least the
times shown.
Although there is no guaranteed specification for time to lock, a test is run (using a JK
pattern) as part of AMD outgoing tests to ensure that all devices can achieve lock within
a reasonable time. The test is performed by sending JKs for 640 µs, and then without
interruption, a full rate functional test is run. For the test to pass, the PLL must lock to
the JK pattern and then track the incoming data perfectly.

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TAXI Technical Information Publication #89-10

Subject: TAXI Receiver CSTRB and DSTRB Pulse Width

Question:
What is the maximum CSTRB and DSTRB pulse width?
Answer:
The internal logic of the TAXI Receiver determines the pulse width of CSTRB and
DSTRB based on the timing of an internal clock (Bit Clock). Under normal conditions,
the pulse width will be 4-bit times wide in the 8-bit mode, and 5-bit times wide in the
9- and 10-bit modes. An exception to this typical width is upon re-sync which can cause
the pulse to be expanded by up to 5 bit times as the byte boundaries are re-aligned to
the incoming data stream.
The number of bit times used to represent data differs based on the operational mode;
in 8-bit mode, data is encoded into 10 bits, in 9-bit mode 11-bits, and in 10-bit mode
2 bits. For example, a Receiver operating with a 12.5 MHz crystal and utilizing 8-bit
mode will have a clock period of 80 ns (1/12.5 MHz = 80 ns). Internally the Receiver
divides this period by 10, forming the internal bit boundaries used to represent the
encoded data. This example yields a 8 ns (80 ns/10 = 8 ns) bit period, which translates
to a internal clock rate of 125 MHz (1/8 ns = 125 MHz). Figure 11. shows a timing
diagram of a TAXI Receiver internal clock and its relationship to CLK, Data, and Strobe
outputs. The Receiver utilizes this divided clock to define its internal logic states.
The CSTRB and DSTRB signals are generated by using these logic states and have a
fixed relationship to the incoming encoded data. The figure shows that from the
beginning of the byte (state 0), the CSTRB or DSTRB delay is two internal clock periods
before going high, and the signal remains high for four internal clock periods then
returns to a low logic level. Actual pulse width will vary from this ideal width due to signal
rise and fall delay, propagation delay and effects of loads external to the Receiver. The
data sheet parameters reflect these delays and normal manufacturing guard bands.

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Figure 11 (8-Bit Mode Example) TAXI Receiver Internal Clock Distribution

9 0 1 2 3 4 5 6 7 8 9 0 1 2
Internal
Bit
Clock

Internal
Clock
(Byte Rate)

External
Clock
(CLK)
Internal
CSTRB &
DSTRB

External
CSTRB &
DSTRB

Internal
Data

External
Data
12330E-40

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TAXI Technical Information Publication #89-11

Subject: Using Receiver CLK Output to Run a TAXI Transmitter

Question:
Is it possible to use the Receiver CLK output to drive the X1 input of a TAXI Transmitter?
Answer:
To assure accurate transmission of data, the Transmitter must have a stable, jitter free,
byte rate reference to its multiplying PLL. This is typically derived from a crystal and can
be connected to any crystal controlled and noise free TTL source.
The Receiver synchronizes its internal clock with the incoming signal and recovers data
and clock for use by the receiving host system.
In the process of sending high speed data over typical serial links, the data may be
affected by noise from various sources. The PLL in the Receiver removes this noise and
delivers a synchronized clock to the Receiver logic and to the host system. However,
some of the noise may feed through the PLL and appear on the CLK output. The CLK
output can jitter as much as 2 ns when recovering data from a noisy link. This will not
typically affect normal logic functions, and can be ignored. If the Receiver must realign
its byte boundary, it will stretch CLK to the new alignment position and thus protect the
host logic from shortened CLK cycles.
These noise and phase jumps make the Receiver CLK output undesirable for use as a
Transmitter frequency source.
For systems that MUST use synchronized clocks (for example to avoid FIFO re-timing
logic) it is possible to filter the Receiver CLK output and make an adequate reference for
the Transmitter.
There are two basic approaches to provide this filter. The first is to use a crystal filter
(Figure 12). When placed between the Receiver CLK and Transmitter Xl, the crystal
filter can be effective in attenuating system jitter to levels nearly comparable to crystal
controlled reference clock levels. By the nature of a crystal filter, as the frequency of the
crystal used in the filter and the data rate frequency vary, the phase of the output varies.
This will make the filter seem to have a variable delay (+ or -) which must be accommo-
dated by the users logic.
The second method is to use a PLL tracking filter (Figure 13). The jitter attenuation
through the PLL is less than that through the crystal filter because the PLL has a
bandwidth several orders of magnitude larger. The PLL provides a solution whose
merits lie between the simplicity of the crystal filter and the need for tight crystal tracking
and matching. The PLL filter is relatively straight forward. Attention to proper grounding
and board layout should be followed. The PLL filter is more tolerant of component and
environmental variations than the crystal filter.

TAXIchip Integrated Circuits Technical Manual 105

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Figure 12 Crystal Filter

+5 V

SEROUT + SERIN + SEROUT + SERIN +

SEROUT - SERIN - 300 300 SEROUT - SERIN -
Am7968 Am7969 Am7968 Am7969
1 µF 2
+ 1
Transmitter Receiver Transmitter Receiver
300 7
X1 CLK X1 CLK 4 pF LT1016 X1 CLK X1 CLK
X2 X2 3 X2 X2
-

300 4 5 6

GND

Crystal Filter 12330E-41

Note: All crystals used are of same type.

Figure 13 PLL Filter

+5 V

1 µF
50

GND SEROUT +
SERIN +
VCC 15K 15K
SERIN – GND VCC VCM2 SEROUT –
V U1 -
V+ GND MC4024
Am7969 Am7968
TAXI MC4044 LMC660C VCX2 TAXI
Receiver 15K 15K V- Transmitter
4.7K +
D1
X1 CLK R 50 pF OUT 2 X1
GND
GND 4.7K CX2 CLK
X2 50 GND X2
1 µF

GND

Notes: 12330E-42
1. Filter components were chosen for the following loop parameters:
Noise Bandwidth = 10 kHz
Damping Factor = 0.5
Natural Frequency = 3.18 kHz
2. Refer to Motorola MC4024, MC4044 and National LMC660C data sheets for specifications.

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TAXI Technical Information Publication #89-12

Subject: TAXlchip Pins Internal Circuit

Question:
What do the TAXIchip I/O circuits look like?
Answer:
There are five different input circuits and two different output circuits in the TAXIchip set.
Each I/O circuit has Electro Static Discharge (ESD) protection circuit attached to it.
The five input types are: TTL Input, ECL Input, Three State Input (TSI), High Threshold
Input (HTI), and Oscillator (OSC).
The two output types are: TTL Output and ECL Output.
Each I/O circuit and the ESD circuit are shown on the following page. The following
table lists all Transmitter and Receiver pins and their I/O type.
Transmitter Receiver
Pin Pin Name I/O Type Pin Pin Name I/O Type
1 ACK TTL OUT 1 DO3 TTL OUT
2 STRB TTL IN 2 DO2 TTL OUT
3 SEROUT+ ECL OUT 3 DO1 TTL OUT
4 SEROUT– ECL OUT 4 DO0 TTL OUT
5 VCC2 5V 5 IGM TTL OUT
6 VCC1 5V 6 RESET HTI
7 VCC3 5V 7 VCC1 5V
8 RESET HTI 8 VCC2 5V
9 DMS TSI 9 SERIN+ ECL IN
10 CLS TSI 10 SERIN– ECL IN
11 SERIN ECL IN 11 DMS TSI
12 CI0 TTL IN 12 DSTRB TTL OUT
13 CI1 TTL IN 13 CSTRB TTL OUT
14 DI9/CI2 TTL IN 14 VLTN TTL OUT
15 DI8/CI3 TTL IN 15 CO0 TTL OUT
16 DI7 TTL IN 16 CO1 TTL OUT
17 DI6 TTL IN 17 DO9/CO2 TTL OUT
18 CLK TTL OUT 18 DO8/CO3 TTL OUT
19 X2 OSC 19 CLK TTL OUT
20 X1 OSC 20 GND1 GND
21 GND2 GND 21 GND2 GND
22 GND1 GND 22 X1 OSC
23 DI0 TTL IN 23 X2 OSC
24 DI1 TTL IN 24 CNB TTL IN
25 DI2 TTL IN 25 DO7 TTL OUT
26 DI3 TTL IN 26 DO6 TTL OUT
27 DI4 TTL IN 27 DO5 TTL OUT
28 DI5 TTL IN 28 DO4 TTL OUT

TAXIchip Integrated Circuits Technical Manual 107

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VCC

22K 11K

TTL IN

ESD

GND 12330E-43
GND 12330E-44

ESD TTL IN

VCC

C C

300

ECL IN 300
17K

ESD DMS/CLS IN 9K
50K

ESD

GND
GND
12330E-45
12330E-46
ECL IN Three-State IN

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VCC

3K 3K X1

ESD
125
5.3K
48K

RESET
REF. GND
X2 125
ESD 125
ESD

GND

GND 12330E-47
12330E-48

HIGH Threshold IN Oscillator

VCC VCC

50 300 300

ECL OUT

ESD

ECL OUT
TTL OUT
ESD

ESD

12330E-49 GND
12330E-50
GND

TTL OUT ECL OUT

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TAXI Technical Information Publication #89-13

Subject: Demuxing A TAXIchip Receiver Output to Multi-Byte Words

Question:
How can a single TAXI Receiver be used to receive multi-byte words?
Answer:
INTRODUCTION
For systems that require data reception wider than a single byte, a single TAXI Receiver
can be used to cascade the multiple bytes. This operation allows the data to be
demultiplexed from a single serial link and used by an external system.
In the following example, data is captured sequentially and output in the form of four
8-bit words. Commands, which can also be transmitted are not used in this example in
order to clarify the basics of the technique. Some simple modifications to include
commands will be presented at the end of this technical note.
The circuit shown in Figure 14 illustrates the logic configuration that has been built and
tested in the laboratory using nominal commercial parts. The circuit handles blocks of
data typically ranging from four bytes to 64K bytes.
The TAXI Receiver converts the serial information that is received by the SERIN+/–
inputs to the data information that is output by the D0–D7 Data pins, C0–C3 Command
pins, and the DSTRB, CSTRB, and VLTN pins. This data information output by the
single receiver is used by the controller to capture the incoming data and output it four
bytes at a time.

FUNCTIONAL DESCRIPTION
Controller Circuit:
The controller consists of a shift register constructed of four D flip-flops and a 3-input
NOR gate. The shifter is loaded with a 1 that progresses through the flip-flops sequen-
tially clocking the first column of four registers which capture the incoming data. When
the 1 is shifted through the fourth flip-flop, it raises the PCO signal for the CLKOUT D
flip-flop. On the following rising edge of the /CLK signal the bytes of cascaded data are
simultaneously clocked out through the second column of four registers that buffer the
cascaded data to the outside system.
Controller Clock:
The clock for the controller circuit is generated by OR-ing DSTRB and CSTRB. This
ensures that the DSTRB signal is captured for output to the external system. These signals
also prepare the way for a simple upgrade to allow the use of commands (explained later).
Sync Commands:
When not receiving blocks of data, Sync Commands (bytes) are received which keeps
the TAXI Receiver locked onto the correct byte rate and byte boundaries. This ensures
proper capture of the data at the beginning of the next block. In addition, before a block
of data is to be sent, a Sync Command must be received to reset the counter to the
proper byte alignment and initialize the system. The Sync Commands are sent by
default in the system because they are automatically inserted whenever a byte time
passes without a STRB (no data to send) pulse at the transmitter. It is important to note
that the Receiver generates a CSTRB and outputs zeros on the Command lines when a
Sync Command is received.

110 TAXIchip Integrated Circuits Technical Manual

OE VCC OE VCC VLTN
d0 Y0 d0 Y0 DSTRB
d1 Y1 d1 Y1
d2 Y2 d2 Y2 D0
d3 Y3 d3 Y3 -
d4 Y4 d4 Y4 -
d5 Y5 d5 Y5 - BYTE 8
Figure 14

d6 Y6 d6 Y6 -
d7 Y7 d7 Y7 -
d8 Y8 d8 Y8 -
d9 Y9 d9 Y9 D7
4-Byte Demux Cascade Receiver
GND CP GND CP

OE VCC OE VCC VLTN

d0 Y0 d0 Y0 DSTRB
d1 Y1 d1 Y1
d2 Y2 d2 Y2 D0
d3 Y3 d3 Y3 -
d4 Y4 d4 Y4 -
TAXI RX d5 Y5 d5 Y5 - BYTE 1
d6 Y6 d6 Y6 -
AM7969 d7 Y7 d7 Y7 -
008 d8 Y8 d8 Y8 -
001 d9 Y9 d9 Y9 D7

CNB
DMS
002 GND CP GND CP

/RESET
003
004
005
006
SERIN+ 007
SERIN- CO0 CHMNDO
CO1 OE VCC OE VCC
CO2 VLTN
CO3 Buffers d0 Y0 d0 Y0 DSTRB
d1 Y1 d1 Y1
DSTRB d2 Y2 d2 Y2 D0
CSTRB d3 Y3 d3 Y3 -
IGM d4 Y4 d4 Y4 -
CLM d5 Y5 d5 Y5 - BYTE 2
VLTM d6 Y6 d6 Y6 -
d7 Y7 d7 Y7 -
d8 Y8 d8 Y8 -

VCC1
VCC2
X1
X2
d9 Y9 d9 Y9 D7
VCC
GND CP GND CP

OE VCC OE VCC VLTN

d0 Y0 d0 Y0 DSTRB
VCC d1 Y1 d1 Y1
d2 Y2 d2 Y2 D0
d3 Y3 d3 Y3 -
D Q

PRB
NC VCC d4 Y4 d4 Y4 -
d5 Y5 d5 Y5 - BYTE 3
CLR d6 Y6 d6 Y6 -
QB d7 Y7 d7 Y7 -
d8 Y8 d8 Y8 -

CLK
d9 Y9 d9 Y9 D7
OSC

TAXIchip Integrated Circuits Technical Manual

CLK1 GND CP GND CP
CLK2
CLK3
SYNC CLK4
Logic Diagram of Cascaded Data with One TAXI Receiver

Data Capture Data Output

Registers Registers
GND CLR
PCD D Q
PRB

CLR CLKOUT
TAXI_CLK
/CLK QB
CLK

D Q D Q D Q D Q

PRB
PRB
PRB
PRB

CLR CLR CLR CLR Controller Block

QB QB QB QB
CLK_CNTR
CLK
CLK
CLK
AMD

12330D-61

CLR_CNTR

111
12330E-51
AMD

The circuitry that handles the Sync Commands or Sync Bytes generates several signals.
The CMND0, CLR_CNTR, Sync and PCO are the signals that are generated by Sync
Command logic. The CLR_CNTR signal is generated from the CMND0 and the CSTRB
signal which signify a Sync Command has been received. CLR_CNTR clears the
controller and then is latched by the rising edge of the Receiver CLK to form the Sync
signal. The Sync signal then generates an active PCO signal. The CLKOUT is then
driven High on the following rising edge of CLK if CLK4 has not already driven the
CLKOUT signal High. The Sync Command only clocks out the data when it is received
before the fourth byte of data has been received. In all other cases, the data is clocked
out by the logic involved with the fourth state of the controller. The Sync Commands that
follow this Sync Command hold the CLKOUT signal High to effectively hold the control-
ler circuitry in a constant state of reset with no change to the output data.
Buffering:
The buffering of signals should also be considered for this design. In this example, the
data outputs from the TAXI Receiver drive the first column of four low power registers.
This design does not exceed the driving capacity of the Receiver, but if different parts
are used, load calculations should be redone.
This system should work with any standard logic, although logic families should not be
mixed unless timing considerations have been made. This particular example uses low
power Schottky devices with relatively fast low power output registers.

TIMING CONSIDERATIONS
Some critical timing considerations must be met to ensure the proper operation of this
design. In order to capture the DSTRB signal, the timing of DSTRB going active and the
rising edge of the CLKx signals from the controller must agree with the setup and hold
times of the first column of registers. To ensure capture of Sync Commands, the
CLR_CNTR signal becoming active and the rising edge of the Receiver CLK must agree
with the setup and hold times of the Sync flip flop. To prevent glitches on the CLKx
signals and the potential capture of incorrect data, the timing between CLK_CNTR rising
and CLR_CNTR becoming active must be considered, CLR_CNTR needs to become
active at a time before CLK_CNTR can effect the output of CLKx. The timing diagram is
shown in Figure 16.
Figure 16 shows the timing of the system where one Sync Command is received
between data blocks being received. The premature Sync Command is not shown, but
can be derived by following the given timing diagram and known responses of the logic
given in Figure 15.

UPGRADE NOTES
Command Line Handling:
To add the capability to receive Commands in this design, only a few additions are
necessary. Since this design uses 8-bit data mode, 4-bit commands can be used. It will
be necessary to add command storage registers four bits wide as well as command
output registers four bits wide to output these Command lines correctly. The CLKx
signals as well as the CLKOUT signals for the existing registers need to be connected to
these new registers. The CLKx signals may need to be buffered to meet fanout limita-
tions of the controller circuitry.
Control Signals:
The signals that need to be output by the new features do not add to the logic. The
circuitry to capture the CSTRB signal is already designed into the system. The DSTRB
signal can be used as a CSTRB indicator, active Low, as well as a DSTRB indicator,

112 TAXIchip Integrated Circuits Technical Manual

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active High, without any additional logic. The VLTN signal is used for both Command
and Data violations. Buffering of the DSTRB and VLTN signals may be necessary as
illustrated in Figure 15 to meet the drive requirements of the first column of registers.
Data/Command Output Note:
In this system, when a nonSync Command byte is received the data line values
corresponding to that byte will change to the values last output from the TAXI Receiver
data lines. Conversely, when a data byte is received the command line values for that
byte will change to the values last output from the TAXI Receiver command lines. This is
a characteristic of the example given and depends on how the command and data
information is latched.
Altering the Number of Output Bytes:
The above described design is an example of a four byte cascaded serial data receiving
system. The same design techniques can be used to expand or reduce the number of
bytes output at a time by the system. The considerations that should be taken into
account for an altered system deal with board space and part cost in accordance with
the requirements of the situation at hand. For board space note see the PAL Usage
section below.
PAL Usage:
In this system, the use of a PAL could greatly reduce the amount of board space used.
The PAL could incorporate all of the flip-flops and buffering logic as well as the first
column of registers that capture the system information. The reason a PAL was not
used in the system described above was to help ensure the understanding of the design
concept. For this application it is recommended that the timing considerations men-
tioned before should be investigated to ensure proper operation of the system.

TAXIchip Integrated Circuits Technical Manual 113

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Figure 15 Timing Diagram of 4-Demux Cascaded Receiver

TAXI CLK

/CLK
4 1 2 3 4 Sync 1 2 3

DSTRB

CSTRB

RCVR DATA Byte 4 Byte 1 Byte 2 Byte 3 Byte 4 Byte 1 Byte 2 Byte 3

CLKCNTR

CLK1

CLK2

CLK3

CLK4

CLKCNTR

PCO

Sync

CLKOUT

DATA OUT Valid Data (for all four bytes)

12330E-52

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TAXI Technical Information Publication #89-14

Subject: 32-Bit Multiplexed Cascade with the TAXIchip Transmitter

Question:
How can a single TAXIchip Transmitter be used to send n-byte data words?
Answer:
I. INTRODUCTION
Many systems have DATA/CMD paths wider than the twelve lines available per TAXI
Transmitter. AMD TAXI applications has designed a circuit which economically multi-
plexes data words longer than eight bits using one TAXI Transmitter. The following
discussion is specifically for an Am7968 Transmitter with a 32-bit data word, but is also
applicable to systems with shorter or longer data words (with or without commands).

II. ADVANTAGES
There are several advantages to using the multiplexed data scheme utilizing one TAXI
Transmitter as opposed to a system using several Transmitters:
1) To implement the mux circuit for 32 bits requires one Am7968 TAXI Transmitter and
three relatively small integrated circuits. A 32-bit wide data path without multiplexing
requires four Am7968 TAXI Transmitters.
2) Four Am7968 TAXI Transmitters require more board real estate than three SSI parts
and one TAXI Transmitter.
3) Four Am7968 TAXI Transmitters will dissipate about 3.5 W, while one Am7968 and
three SSI chips dissipate only 1.25 W. The power saving is even more dramatic if op-
tical data links are being used. A design using four TAXI Transmitters and four
Am79h1000T optical data links would dissipate over 5 W of power. The same 32-bit
wide system using the multiplexing circuit would dissipate only 2.6 W!

III. IMPLEMENTATION
Implementation of the 32-bit multiplexed transmitter circuit is straightforward. (See
Figure 11). In addition to the Am7968 TAXI Transmitter, the following parts are required:
(1) 74LS00
(1) 74LS20
(1) 74LS174
A group of buffers with tri-state outputs (four Am29C821s in this example), would likely
be required in any type of point to point communication application and might already be
available in the host system. Additionally, a number of termination resistors are required.
The number and values are dependent upon the type of coupling and the media used.

IV. OPERATION
Referring to Figure 15, the data to be transmitted is assumed to be simultaneously
loaded into the buffers when a strobe pulse is input to the system. The controller for the
mux is the 74LS174, which is wired as a shift register. As a 0 (which occurs on strobe) is
shifted through the register, each buffer is enabled in turn. The NAND gate (U1) at the
input of D1, ensures that only a single 0 is possible while the registers are being
selected. The TAXI CLK signal, which is used to clock the 74LS174, is inverted to
provide set-up time to ensure that no false strobes reach the TAXI Transmitter. The
other four-input NAND gate (U2) enables the two-input NAND gate (U3), so that the
Transmitter will be strobed while there is data available in the buffers.

TAXIchip Integrated Circuits Technical Manual 115

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Jumpers are provided on the outputs of Q4 and Q5 to be inverted (U7) and fed back to
the first NAND gate (U1). If Q4 is shorted back to the strobe input, the system will run in
auto-repeat ACK 0 mode. This means that there will be a strobe on every clock cycle. In
this mode a sync will never be sent. If the output of Q5 is shorted back to the strobe
input, the system will run in auto-repeat ACK 1 mode. This means that a sync will be
automatically inserted in between each group of four data bytes.
On the receiver end of the link, the option is left up to the designer to either use four
Am7969 TAXI Receivers or to demultiplex the data and use only one Receiver.
Figure 16 has been included to give a detailed schematic of the circuit with an Am7969
TAXI Receiver on-board to complete the data path. Figures 17, 18, and 19 show typical
outputs for auto-run ACK0, auto-run ACK1 and Normal run modes.

V. CONCLUSION
To increase the length of a data word beyond eight bits, multiplex the data into an
Am7968 TAXI Transmitter. This method uses less power, less board space, and lowers
the parts cost of the system.

116 TAXIchip Integrated Circuits Technical Manual

STRB
U6
1 24
2 OC/VCC 23
D0 D0 Y0 22
D1 3
4 D1 Y1 21
D2 D2 Y2 20
D3 5
6 D3 Y3 19
D4 D4
Figure 16

7 Y4 18
D5 D5
D6 8 Y5 17
9 D6 Y6 16
D7 D7 U9
10 Y7 15
11 D8 Y8 14 1 14
D9 Y9 1A VCC
12 13 2 13
GND CP 1B 2D
2C 12 U1
AM29C821 4 3 2
D1 D1
GND 5 1C 10 4 5
2B D2 D2
6 1D 9 5 D3 D3
1Y 2A
7 8 11 D4 10 ACK0
GND 2Y D4
U5 13 D5 D5 12 ACK1
1 24 74LS2O 14 15
2 OC/VCC 23 GND D6 D6
D8 D0 Y0 22
D9 3
4 D1 Y1 21 9 CLK U12
D10 D2 Y2 20
D11 5 1 CLR
6 D3 Y3 19
D12 D4
7 Y4 18 74LS174
D13 D5
D14 8 Y5 17
JMP3
9 D6 Y6 16
D15 D7
10 Y7 15
11 D8 Y8 14
D9 Y9 U10
12 13
GND CP
1 14
1A VCC
AM29C821 2 13
3 1B 4B 12
GND
4 1Y 4A 11
5 2Y 4Y 10
U4 U11 6 2A 9
1 24 3B
7 8
D16 2 OC/VCC 23 2B 3A
3 D0 Y0 22
D17 D1 Y1 21 GND 3Y
D18 4 GND
5 D2 Y2 20 JMP2
D19 74LS0O
6 D3 Y3 19
D20 D4 Y4 18
D21 7
32-Bit Multiplexed Transmitter Circuit

8 D5 Y5 17
D22 D6 Y6 16 U2 AM7966
D23 9 PWR
10 D7 Y7 15 4 28 1
D8 D15 ACK To Coax or Fiber Media
11 Y8 14 4 27 2
D9 Y9 4 D14 STRB S2 S2
12 13 26 3 SERIN+
GND CP 4 D13 SEROUT+
25 4 SERIN-
4 D12 SEROUT-
AM29C821 24 5 138
4 D11 VCC2
23 6
GND VCC1 138
22 D10 7
GND1 VCC3
21 8 GND
U3 GND2 RESET/
1 24 20 9
X1 DMS
2 OC/VCC 23 19 10
D24 D0 X2 CLS
3 Y0 22 18 11
D25 D1 4 CLK SERIN
4 Y1 21 17 12
D26 D2 D18 C10

TAXIchip Integrated Circuits Technical Manual

5 Y2 20 4 16 13
D27 D3 C11
6 Y3 19 15 D17 14
D28 D4 Y4 18 D18/C13 D19/C12
D29 7
8 D5 Y5 17 PWR
D30 D6 Y6 16 GND
D31 9
10 D7 Y7 15
11 D8 Y8 14
D9 Y9
12 13
GND CP 4 3

AM29C821
GND
V C UB
C L DSC
G K
C
N
D

2
AMD

12330D-63
GND

117
12330E-53
AMD

Figure 17 AUTORUN ACK 0 (No Sync Between Data Bytes)

STRB

TXCLK

CSTRB
DSTRB
12330E-54

Figure 18 AUTORUN ACK 1 (One Sync Between Every Four Data Bytes)
D7

STRB

TXCLK

CSTRB
DSTRB
12330E-55

118 TAXIchip Integrated Circuits Technical Manual

AMD

Figure 19 Normal Run Mode (Transmission of Syncs Depends on Host)

STRB

TXCLK

CSTRB
DSTRB
12330E-56

TAXIchip Integrated Circuits Technical Manual 119

AMD

TAXI Technical Information Publication #89-15

Subject: General Device Information for 125/175 MHz TAXIchips

This T.I.P. provides general information about the design and manufacturing of the
125 MHz and 175 MHz TAXIchips. The information is separated into three categories:
Design, Wafer Fab, and Assembly/Packaging.
Design:
Transmitter (TX) Receiver (RX)

Product P/N: Am7968-125 Am7969-125

Am7968-175 Am7969-175
Die Number: 4768 4769
Chip Dimensions: 170 x 167 mils2 196 x 187 mils2
# NPN Transistors: 3386 4384
# PNP Transistors: 14 24
# Resistors: 2504 3556
# Diodes: 87 76
Equiv. Gate Count: 595 720
I/O Schematics: See TAXI TIP #89-12
Supply Currents: Typical Values (mA), VCC = 5.5 V Process=Nominal, CD 028 package,
Temp. forced with moving air flow (approx. thetaJMA= 20°C/W)
–55°C 0°C 25°C 70°C 125°C
Transmitter: 230 215 203 187 178
Receiver: 272 250 237 212 182

Wafer Fab:
Location: Fab 2A, San Antonio, TX (formerly Fab 11) Process ID:
Bipolar IMOX–S2: 402L–1156
Metal One: TiW (barrier metal): 1800 A nom. thickness AlCu: 1.0% Cu,
8000 A nom. thickness Pitch = 4 µ
Metal Two: AlCu: 1.0% Cu, 15500 A nom. thickness Pitch = 8 µ
Passivation: Silox/Nitride dual layer.
7500 A nominal thickness Nitride: 6800 A nominal thickness

120 TAXIchip Integrated Circuits Technical Manual

AMD

Assembly/Packaging:
CerDIP (CD 028)
LCC (CLT028) PLCC (PL 028)

Assembly Location: Manila Bangkok

Ld. Frame Material: CD: Alloy 42 Copper

Bond Wire: 1.25 mil 1.25 mil Au
Al/Si (1% Si)
Bonding Method: Ultrasonic Ball Bonding
Die Attach: Ag Glass Ag Filled Epoxy
Molding Compound: N/A Sumitomo 6300H

Lead Finish
CD 028 Comm.: Tin Plate

CD 028 Mil.: Solder Dip

CLT028 Mil.: Solder Dip

PL 028: Solder Plate

Thermal Impedance:

CD 0281 CLT0282 PL 0282

θJA TX : 41°C/W n/a 53°C/W

RX: 43°C/W n/a 52°C/W

θJC TX, RX: 4°C/W 10°C/W 12°C/W

1
socketed
2
surface mounted

TAXIchip Integrated Circuits Technical Manual 121

AMD

TAXI Technical Information Publication #89-Nov ’89

Subject: TAXIchip Error Rate Example

INTRODUCTION
A method was devised to establish a baseline TAXIchip set error rate. A series of tests
were conducted at a transmission rate of 125 MHz at room temperature, and various
power supply voltages. The data collected will be used to determine fiber optic and wire
interconnect BER (Bit Error Rate) tests to be completed at a later date.

METHOD
The test method used the TAXI Transmitters and Receivers to transfer data continu-
ously for at least one thousand hours per pair with different VCC conditions. To imple-
ment this test, five TAXI K2 boards were used. Each board includes a TAXI Transmitter
with a ROM data source, and a Receiver with a ROM data checker to test data integrity
on every byte. They were set up according to the diagrams in Figure 20, and intercon-
nected with AC coupled short coax lines.
In Setup 1, a single power supply with 5 V VCC was attached to TAXI K2 board #1.
Board #1 ran independently with the SEROUT+/– connected to its SERIN+/– with 50 Ω
coaxial cables.
Setup 2 had oscillating voltages (4 V to 6 V) connected to the V CC of TAXI K2 boards #2
and #3. The SEROUT+/– of board #2 were connected to the SERIN+/– of board #3, and
the SEROUT+/– of board #3 connected to the SERIN+/– of board #2, with 50 Ω coaxial
cables, forming two test setups with continually varying power supply voltages.
Setup 3 also uses two power supplies with one set at 4 V and the other at 6 V. These
two power supplies were connected to TAXI K2 boards #4 and #5. The SEROUT+/- and
SERIN+/- were connected in the same configuration as boards #2 and #3 in setup 2 with
50 Ω coaxial cables.
The power supply voltages used (4 and 6 V) are outside the data sheet specification for
the TAXIchip set. This test was intended to stress the parts and to simulate extreme
temperature and operating conditions.
These five boards were checked regularly, and the error counts were recorded. To verify
that these boards were still running correctly, they were made to fail intentionally and
then reset.

RESULT
The tests were completed after each board ran more than 1,000 hours. The table below
summarizes the results.
Board# Hours Errors Notes
1 1,606 0
2 1,623 8* Errors occurred between 438–558 hours
3 1,082 0
4 1,607 2* Errors occurred between 438–558 hours
5 1,082 0
.
* One error can cause multiple error counts. These were assumed to be one error event.

122 TAXIchip Integrated Circuits Technical Manual

AMD

Board #4 failed on another occasion after the errors indicated above, but this failure was
due to a power supply failure. Failure time was subtracted from the total run time, and
errors were not indicated in the total. Also, boards #2 and #4 ran over 1,000 hours each
without any error after the only noted error occurrence.

CONCLUSION
The fives sets of TAXI Transmitters and Receivers have run a sum total of 7,000 hours
(3.15 x 1014 bytes) with two error events.

Figure 20 TAXI K2 Board Transmit/Receive Section

VCC VCC

A B

TAXI TAXI ROM and

ROM TX TX Comparator

12330E-57

Note:
TAXI K2 board includes both TAXI TX and TAXI RX. Each half may be used independently or with other
boards with matching ROM data patterns. For the test described above, FDDI DDJ ROM patterns were used.

VCC Conditions
TAXI TX TAXI RX
SETUP 1 5 5
SETUP 2 4–6 Variable 4–6 Variable
4–6 Variable 4–6 Variable
SETUP 3 4 6
6 4

TAXIchip Integrated Circuits Technical Manual 123

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