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32 views151 pages

V93XX Datasheet: Specifications Are Subject To Change Without Notice

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khaled_emam

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You are on page 1/ 151

V93XX

Datasheet

Specifications are subject to change without notice.

© 2022 Hangzhou Vango Technologies, Inc.

This document contains information that is proprietary to Vango Technologies, Inc.

Unauthorized reproduction of this information in whole or in part is strictly prohibited.

V93XX Datasheet

Revision

Date Version Description

2019.07.19 2.0 Initial release

2020.11.25 2.1 Modify the description of SYS_STS register.

Modify ANA_CTRL0 BIT13 and BIT14 function

Modify ANA_CTRL1 BIT7 and BIT23 function

Add pull-up resistance to TX, RX and RSTN pin

When the RSTN pin remains low for a certain period of time, the chip will

2020.02.18 3.1 be reset. The time was changed from 1 ms to 2 ms

Open the input short circuit function of voltage channel and current channel

On-chip reference voltage changed to 1.21 V

The power supply voltage range is changed to 2.6 ~ 3.6 V

The power down threshold voltage is changed to 2.6 ~ 3.1 V

2022.01.20 3.2 Delete relevant contents of Roche coil

Modify SYS_INTSTS and SYS_INTEN registers ， increase the overflow

interrupt of high-speed energy accumulator

Modify the description of DMA_MODE bit in DSP_CTRL5 register (added

description: at least one channel of waveform buffer and upload must be

2022.03.01 3.3 opened before enabling DMA transmission).

Modify the description of bit3 and bit4 in DSP_CTRL5 registers, description

of DMA channel manual switch for waveform upload.

Delete the frequency function in DSP_CTRL0 register.

Modify the function description of UPERIOD and IPERIOD from half cycle

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V93XX Datasheet
unit to cycle unit

Modify SHORT_I of ANA_CTRL0, Change to current IA channel ADC input

short circuit

Modify the description of RCL clock intervals as determined time, and the

algorithm is the longest time interval x 1.5

Modify the description of forced shutdown energy accumulator and CF

output function in SYS_MISC register

The power down threshold voltage is changed to 2.6 ~ 3.05 V

2022.03.25 3.4 Modify the description of CLK1 in Chapter 5

Add Energy accumulator counter description

2022.05.19 3.5 Delete temperature measurement function

ADD V9340/V9343 type

Modify the table of parameter

2022.08.13 3.6 Modify UART baud rate range

Table 5-1 in the field register, ANA_CTRL1 instead of DSP_CTRL1.

2022.10.11 3.7 Modify the description of voltage dip in Section 11.2

2023.03.01 3.8 Change V9343 to V9340T

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V93XX Datasheet
Content

Revision ................................................................................................................................... 2

Figure List ................................................................................................................................ 8

Table List................................................................................................................................ 10

1. General Description ...................................................................................................... 13

1.1. Functional Block Diagram .......................................................................................... 15

1.2. Pin Description ......................................................................................................... 16

1.2.1. V9381 Pin Description ...................................................................................... 16

1.2.2. V9360 Pin Description ...................................................................................... 17

1.2.3. V9340 Pin Description ...................................................................................... 17

1.2.4. V9340T Pin Description ..................................................................................... 18

1.2.5. Pin Description ................................................................................................ 18

1.3. Parameters .............................................................................................................. 20

1.4. Absolute Maximum Ratings ........................................................................................ 22

2. Registers..................................................................................................................... 24

2.1. Registers List ........................................................................................................... 24

2.2. Analog Control Registers............................................................................................ 30

2.2.1. ANA_CTRL0 Register ........................................................................................ 30

2.2.2. ANA_CTRL1 Register ........................................................................................ 31

2.3. System Control & Status Register ............................................................................... 34

2.3.1. SYS_BAUDCNT1 Register .................................................................................. 34

2.3.2. SYS_BAUDCNT8 Register .................................................................................. 35

2.3.3. SYS_INTSTS Register ....................................................................................... 35

2.3.4. SYS_INTEN Register ......................................................................................... 41

2.3.5. SYS_STS Register ............................................................................................ 45

2.3.6. SYS_MISC Register .......................................................................................... 50

2.3.7. SYS_BLKX Register .......................................................................................... 53

2.3.8. SYS_IOCFGXX Register ..................................................................................... 54

2.3.9. SYS_VERSION Register ..................................................................................... 58

2.4. Metering Control Registers ......................................................................................... 58

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V93XX Datasheet
2.4.1. DSP_CTRL0 Register ........................................................................................ 58

2.4.2. DSP_CTRL1 Register ........................................................................................ 63

2.4.3. DSP_CTRL2 Register ........................................................................................ 67

2.4.4. DSP_CTRL3 Register ........................................................................................ 72

2.4.5. DSP_CTRL4 Register ........................................................................................ 76

2.4.6. DSP_CTRL5 Register ........................................................................................ 78

2.5. Metering Data Register .............................................................................................. 82

2.5.1. DC Component Register .................................................................................... 82

2.5.2. RMS Register ................................................................................................... 83

2.5.3. Active/ Reactive Power Register ......................................................................... 84

2.5.4. Fundamental Wave Channel Register .................................................................. 85

2.5.5. Line Frequency Register .................................................................................... 86

2.6. Energy Accumulator Register ..................................................................................... 86

2.7. Phase Measurement Register ..................................................................................... 88

2.8. Power-creep Threshold Register.................................................................................. 88

2.9. Voltage Swell or Dip Threshold Register ....................................................................... 89

2.10. Fast Detection Threshold Register ............................................................................ 90

2.11. Waveform Data Register ......................................................................................... 90

2.12. Calibration Register................................................................................................ 91

2.12.1. DC Bias Setting Register .................................................................................. 91

2.12.2. RMS Calibration Register ................................................................................. 91

2.12.3. Power Calibration Register ............................................................................... 92

2.12.4. Threshold Register .......................................................................................... 93

2.12.5. Phase Calibration Register ............................................................................... 95

2.12.6. Bandpass Filter Register .................................................................................. 95

2.13. Checksum Register ................................................................................................ 96

3. Main Power Supply ..................................................................................................... 100

3.1. Power Supply Monitoring Circuit ............................................................................... 100

3.2. Digital Power Supply ............................................................................................... 101

3.3. Power on Reset Circuit ............................................................................................ 101

4. Bandgap circuit .......................................................................................................... 102

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V93XX Datasheet
5. Clock ........................................................................................................................ 104

5.1. External input high-frequency clock .......................................................................... 106

5.2. High-Frequency RC Oscillator ................................................................................... 106

5.3. Low-Frequency RC Oscillator .................................................................................... 107

5.4. External Input Clock ............................................................................................... 107

6. RESET ...................................................................................................................... 108

6.1. Reset Related Registers ........................................................................................... 108

6.2. Power-On Reset (POR) ............................................................................................ 108

6.3. External Reset ........................................................................................................ 109

6.4. RX Reset ............................................................................................................... 110

6.5. Global Software Reset ............................................................................................. 112

7. UART ........................................................................................................................ 113

7.1. Overview ............................................................................................................... 113

7.2. Broadcast Communication ....................................................................................... 114

7.3. Read Operation ...................................................................................................... 116

7.4. Write Operation ...................................................................................................... 118

7.5. Block Reading Operation .......................................................................................... 120

8. SPI ........................................................................................................................... 125

8.1. Overview ............................................................................................................... 125

8.2. Write Operation ...................................................................................................... 126

8.3. Read Operation ...................................................................................................... 127

8.4. Initialize interface ................................................................................................... 128

8.5. 4-wire SPI Mode ..................................................................................................... 129

8.6. 3-wire SPI Mode ..................................................................................................... 129

9. DSP .......................................................................................................................... 130

9.1. Overview ............................................................................................................... 130

9.2. Features ................................................................................................................ 130

9.3. Functional Diagram ................................................................................................. 131

9.4. Application Description ............................................................................................ 133

9.4.1. Phase Calibration ........................................................................................... 133

9.4.2. Frequency Calculation .................................................................................... 133

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V93XX Datasheet
9.4.3. Phase Test .................................................................................................... 134

9.4.4. Power-creep Detection.................................................................................... 134

10. Active Waveform upload and buffer .............................................................................. 136

10.1. Active Waveform upload ....................................................................................... 136

10.1.1. Overview ..................................................................................................... 136

10.1.2. Timing and Format ....................................................................................... 137

10.2. Waveform Buffer ................................................................................................. 138

11. Electrical Signal monitoring ......................................................................................... 139

11.1. Zero-crossing Detection ........................................................................................ 139

11.2. Voltage Swell/Dip ................................................................................................ 140

11.3. Over-voltage and under-voltage/Over-current and under-current ............................... 141

12. Energy Accumulator ................................................................................................... 143

12.1. High-speed Energy Accumulator ............................................................................ 144

12.2. Low-speed Energy Accumulator ............................................................................. 145

12.3. CF Output ........................................................................................................... 145

12.4. Energy Accumulator Power-creep Detection ............................................................ 146

12.5. Active Accumulation uploading Interface ................................................................. 146

13. Signal IO Ports .......................................................................................................... 148

13.1. Overview ............................................................................................................ 148

13.2. Functional Description .......................................................................................... 148

14. Outline Dimensions .................................................................................................... 150

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V93XX Datasheet
Figure List

Figure 1-1 Functional block diagram .......................................................................................... 15

Figure 1-2 V9381 Pin Description .............................................................................................. 16

Figure 1-3 V9360 Pin Description .............................................................................................. 17

Figure 1-4 V9340 Pin Description .............................................................................................. 17

Figure 1-5 V9340T Pin Description............................................................................................. 18

Figure 3-1 Main Power System ................................................................................................ 100

Figure 3-2 Power-down monitoring .......................................................................................... 101

Figure 4-1 Register for Bandgap Circuit .................................................................................... 102

Figure 5-1 Clock generation .................................................................................................... 104

Figure 6-1 Timing for POR ...................................................................................................... 109

Figure 6-2 Timing for RSTN .................................................................................................... 110

Figure 6-3 Timing for RX Reset of UART ................................................................................... 111

Figure 6-4 Timing for RX Reset of SPI ...................................................................................... 111

Figure 6-5 Timing of Global Software Reset .............................................................................. 112

Figure 7-1 Structure of an 11-Bit data byte (from LSB to MSB) ................................................... 113

Figure 7-2 command frame for broadcast writing operation ........................................................ 114

Figure 7-3 Communication protocol for read operation ............................................................... 116

Figure 7-4 Communication protocol for write operation .............................................................. 118

Figure 7-5 address mapping for block reading ........................................................................... 121

Figure 7-6 Communication protocol for block reading operation .................................................. 121

Figure 8-1 Communication protocol for SPI write operation......................................................... 126

Figure 8-2 Communication protocol for SPI read operation ......................................................... 127

Figure 8-3 Communication protocol for 4 wire SPI mode ............................................................ 129

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V93XX Datasheet
Figure 8-4 Communication protocol for 3 wire SPI mode ............................................................ 129

Figure 9-1 Functional Diagram 1 of Metering DSP ...................................................................... 131

Figure 9-2 Functional Diagram 2 of Metering DSP ...................................................................... 132

Figure 10-1 Communication timing of DMA SPI ......................................................................... 137

Figure 11-1 output waveform for voltage/current zero-crossing................................................... 140

Figure 11-2 Over-voltage and under-voltage/Over-current and under-current detect ..................... 141

Figure 12-1 Functional block diagram of energy bucket .............................................................. 143

Figure 13-1 Functional Block Diagram of signal IO ports ............................................................. 148

Figure 14-1 Outline dimension for V9381 ................................................................................. 150

Figure 14-2 Outline dimension for V9360 ................................................................................. 150

Figure 14-3 Outline dimension for V9340/V9340T ..................................................................... 151

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V93XX Datasheet
Table List

Table 1-1 Pin description .......................................................................................................... 18

Table 1-2 Parameters ............................................................................................................... 20

Table 1-3 Absolute maximum ratings ......................................................................................... 22

Table 2-1 Register list .............................................................................................................. 24

Table 2-2 Analog Control Register 0 (0x00, ANA_CTRL0) .............................................................. 30

Table 2-3 Analog Control Register 1 (0x01, ANA_CTRL1) .............................................................. 31

Table 2-4 UART transmitting data 1bit count value (0x70, SYS_BAUDCNT1) ................................... 34

Table 2-5 UART receiving data 8bit count value (0x71, SYS_BAUDCNT8) ........................................ 35

Table 2-6 System Interrupt Register (0x72, SYS_INTSTS) ............................................................ 35

Table 2-7 System Interrupt Enable Register (0x73, SYS_INTEN) ................................................... 41

Table 2-8 System Status Register (0x74, SYS_STS) ..................................................................... 45

Table 2-9 System Control Register (0x75, SYS_MISC) .................................................................. 50

Table 2-10 Block-reading Address Register 0 (0x79, SYS_BLK0_ADDR) .......................................... 53

Table 2-11 Block-reading Address Register 1 (0x7A, SYS_BLK1_ADDR) .......................................... 53

Table 2-12 Block-reading Address Register 2 (0x7B, SYS_BLK2_ADDR) .......................................... 53

Table 2-13 Block-reading Address Register 3 (0x7C, SYS_BLK3_ADDR) .......................................... 53

Table 2-14 IO Configuration Register 0 (0x7D, SYS_IOCFGX0) ...................................................... 54

Table 2-15 P0CFG Bit[5:0] Description ....................................................................................... 54

Table 2-16 IO Configuration Register 1 (0x7E, SYS_IOCFGX1) ...................................................... 57

Table 2-17 Version Information Register (0x7F, SYS_VERSION) ..................................................... 58

Table 2-18 Metering Control Register 0 (0x02, DSP_CTRL0) .......................................................... 58

Table 2-19 Metering Control Register 2 (0x03, DSP_CTRL1) .......................................................... 63

Table 2-20 Metering Control Register 2 (0x04, DSP_CTRL2) .......................................................... 67

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V93XX Datasheet
Table 2-21 Metering Control Register 3 (0x05, DSP_CTRL3) .......................................................... 72

Table 2-22 Metering Control Register 4 (0x06, DSP_CTRL4) .......................................................... 76

Table 2-23 Metering Control Register 5 (0x07, DSP_CTRL5) .......................................................... 78

Table 2-24 DC Component Register ........................................................................................... 82

Table 2-25 Voltage/ Current/ Measurement Signal (M) RMS Register .............................................. 83

Table 2-26 Active/ Reactive Power Register................................................................................. 84

Table 2-27 Fundamental Wave Channel Instantaneous Register..................................................... 85

Table 2-28 Fundamental Wave Channel Average Register ............................................................. 85

Table 2-29 Line Frequency Register (0x21, DSP_DAT_FRQ) .......................................................... 86

Table 2-30 Energy Accumulator Register .................................................................................... 86

Table 2-31 Phase Measurement Register .................................................................................... 88

Table 2-32 Power-creep Threshold Register ................................................................................ 88

Table 2-33 Voltage Swell or Dip Threshold Register ...................................................................... 89

Table 2-34 Fast detection Threshold Register .............................................................................. 90

Table 2-35 Waveform Data Register ........................................................................................... 90

Table 2-36 DC Bias Setting Register........................................................................................... 91

Table 2-37 Voltage/ Current/ Measurement RMS Calibration Register ............................................. 91

Table 2-38 Total-wave Active/ Reactive Power Calibration Register ................................................. 92

Table 2-39 Threshold Register ................................................................................................... 93

Table 2-40 Phase Calibration Register (0x33, DSP_CFG_PHC) ....................................................... 95

Table 2-41 Bandpass Filter Register (0x37, DSP_CFG_BPF)........................................................... 95

Table 2-42 Checksum Register (0x38, DSP_CFG_CKSUM) ............................................................. 96

Table 2-43 Self-checking Register .............................................................................................. 96

Table 5-1 Clock Generation Related Registers............................................................................ 105

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V93XX Datasheet
Table 6-1 Reset Related Registers ............................................................................................ 108

Table 7-1 UART communication errors...................................................................................... 113

Table 7-2 Structure of Data Byte (B7:B0) From Master MCU to V93XX on Broadcast Operation ....... 114

Table 7-3 Structure of Data Byte (B7:B0) From Master MCU to V93XX on Read Operation .............. 116

Table 7-4 Structure of Data Byte (B7:B0) From V93XX to Master MCU on read Operation ............... 117

Table 7-5 Structure of Data Byte (B7:B0) From Master MCU to V93XX on Write Operation .............. 118

Table 7-6 Structure of Data Byte (B7:B0) From V93XX to Master MCU on Write Operation .............. 120

Table 7-7 Structure of Data Byte (B7:B0) From Master MCU to V93XX on block reading Operation .. 121

Table 7-8 Structure of Data Byte (B7:B0) From V93XX to Master MCU on block reading Operation .. 123

Table 8-1 SPI communication errors ........................................................................................ 125

Table 8-2 Structure of Data Byte (B7:B0) From Master MCU to V93XX on write Operation .............. 126

Table 8-3 Structure of Data Byte (B7:B0) From Master MCU to V93XX on read Operation ............... 127

Table 8-4 Structure of Data Byte (B7:B0) From V93XX to Master MCU on read Operation ............... 127

Table 8-5 SPI interface initialization data (hexadecimal) ............................................................. 128

Table 9-1 Phase Calibration Description .................................................................................... 133

Table 9-2 Frequency register source FRQ_SEL description .......................................................... 133

Table 9-3 Frequency Constant Description ................................................................................ 134

Table 10-1 Active waveform data upload configuration ............................................................... 136

Table 10-2 Active waveform data upload format ........................................................................ 137

Table 10-3 waveform buffer data format .................................................................................. 138

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V93XX Datasheet
1. General Description

The V93XX is a single-phase metering chip which supports the total-wave and fundamental-wave of

various modes and supports various power grids to monitor events. Furthermore, the waveform data

can be transmitted via DMA by SPI protocol, or storage locally through the waveform buffer.

 Main Power: 3.3 V power supply, voltage input range 2.6 V to 3.6 V.

 Reference voltage: 1.21 (typical T.C. 10 ppm/°C)

 Low-power design: the typical consumption in normal operation is about 2.6 mA.

 Metering Features:

➢ 3 independent oversampling ∑/∆ ADCs: one of the ADC (channel A) can measure voltage, the

other ADC with multifunction measure current.

➢ Highly Metering Accurate:

 Supports the requirements of IEC 62053-21:2020/ IEC 62053-22:2020 and IEC 62053-

23:2020.

 Less than 0.1% error in active energy metering over a dynamic range of 5000:1

 Less than 0.2% error in reactive energy metering over a dynamic range of 5000:1

 Less than 0.5% error in current/voltage RMS over a dynamic range of 5000:1.

➢ Supports various measurements:

 DC components of voltage and current signal

 Total /fundamental instantaneous/average current/voltage RMS

 Total instantaneous/average active /reactive/apparent power

 10 or 12 cycles of total RMS

 Fundamental instantaneous/average active /reactive/apparent power

 active/reactive energy, active/reactive/apparent power, Irms, constant value, and

fundamental wave are selectable

 Line frequency and phase

➢ DC signals measurement

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V93XX Datasheet
➢ Software calibration

➢ Accelerating calibration when weak current is applied.

 Supports detection for over-current, over-voltage, under-current, under-voltage, voltage dip, and

voltage swell

 Supports waveform buffer and waveform transmitted by DMA

 Supports active upload for energy accumulation

 Current input: current shunt resistor, CT, Hall cell, and TMR supportive

 CTI input clock frequency: 6.5536 MHz

 Supports UART communication interface

 Supports SPI communication interface

 Operating Temperature:

-40~+85 °C (V9381/ V9360/ V9340)

-40~+105 °C (V9340T)

 Storage Temperature: -55~+150 °C

 Package: SSOP(M)24, SOP(M)16, SOP8

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V93XX Datasheet
1.1. Functional Block Diagram

Px Px CTI 32KIN

Signal Wave
upload RCH
monitor
by SPI Clock Controller

RCL

ROM
RAM SPI
IA
Metrology Host
System
IB AFE DSP MCU
Controller
3-ch ADC
U
UART

Energy
Energy
upload
CF
by UART

V93XX

Px CF1/CF2 Px

Figure 1-1 Functional block diagram

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V93XX Datasheet
1.2. Pin Description

1.2.1. V9381 Pin Description

A1/SPCSN

RX/MOSI
A0/SPCK

TX/MISO

32KIN
RSTN
P2

P6
P0

P1
24

13
V9381

12
1

9
IBP

IAN
IBN

VSS
IAP
CTI

DVCC

VREF
NC

VDD

Figure 1-2 V9381 Pin Description

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V93XX Datasheet
1.2.2. V9360 Pin Description

DVCC

VDD
CTI

RX
NC

P3
16

9
V9360
1

8
IBN
UN

IBP
UP

IAN

IAP

VSS

Figure 1-3 V9360 Pin Description VREF

1.2.3. V9340 Pin Description

TX/RX
DVCC
VSS

REF
8

V9340
1

4
VDD

IAP
IAN

Figure 1-4 V9340 Pin Description

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V93XX Datasheet
1.2.4. V9340T Pin Description

TX/RX
DVCC
VSS

REF
8

5
V9340T
1

4
VDD

IAP
IAN

Figure 1-5 V9340T Pin Description

1.2.5. Pin Description

Table 1-1 Pin description

Pin No.
Mnemonic Type Description
V9381 V9360 V9340/V9340T

1 15 CTI Input Input pin for 6.5536 MHz clock.

2 16 NC Floating

Positive input pin for Voltage Channel

3 1 2 UP Input
Sampling.

Negative input pin for Voltage Channel

4 2 UN Input
Sampling.

Negative input pin for current channel B

5 3 IBN Input
sampling.

6 4 IBP Input Positive input pin for current channel B

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V93XX Datasheet
sampling.

Negative input pin for current channel A

7 5 3 IAN Input
sampling.

Positive input pin for current channel A

8 6 4 IAP Input
sampling.

3.3 V power supply.

9 9 1 VDD Power This pin must be decoupled to a ≥0.1 μF

capacitor.

10 7 8 VSS Ground Ground

Digital power output.

This pin must be connected to a parallel circuit

11 10 7 DVCC Power
combined by a ≥4.7 μF capacitor and 0.1 μF

capacitor, and then grounded.

On-chip reference voltage.

Input/
12 8 5 VREF This pin must be connected to a 1 μF
Output capacitor, and then grounded.

13 - X32KIN Input 32 KHz CLK input pin (Digital IO interface).

Reset input, active low.

After power on, the “RSTN” could be driven

low for at least 2 ms by MCU to force the chip

14 - RSTN Input
into the reset state.

There is a pull-up resistor inside the chip,

which is about 50K ohm.

CF1/ CF2/ single interruption/ all

15 - P6 Output
interruption/ automatic data uploads

CF1/ CF2/ single interruption/ all

16 - P5 Output
interruption/ automatic data uploads

CF1/ CF2/ single interruption/ all

17 11 P3 Output
interruption/ automatic data uploads

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V93XX Datasheet
CF1/ CF2/ single interruption/ all
18 12 P2 Output
interruption/ automatic data uploads

UART communicates with RX pin. / SPI

interface in slave mode. It’s used for data

19 13 6 RX/MOSI Input input.

There is a pull-up resistor inside the chip,

which is about 50 Kohm.

UART communicates with TX pin. / SPI

interface in slave mode. It’s used for data

20 14 6 TX/MISO Output output.

There is a pull-up resistor inside the chip,

which is about 50 Kohm.

Address select pin 1 for UART. / Chip select

21 - A1/SPCSN Input
pin for SPI

Address select pin 0 for UART. / SPI interface

22 - A0/SPCK Input
in slave mode. It’s used for clock input.

CF1/ CF2/ single interruption/ all

23 - P1 Output
interruption/ automatic data uploads

CF1/ CF2/ single interruption/ all

24 - P0 Output
interruption/ automatic data uploads

1.3. Parameters

Table 1-2 Parameters

Unless otherwise specified, the data are based on the test results of TA = 25 ℃, VDD = 3.3 V.

Parameter Min. Typ. Max. Unit Remark

Phase Error Between Channels

PF=0.8 Capacitive ±0.05 Degree

PF=0.5 Inductive ±0.05 Degree

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V93XX Datasheet
Parameter Min. Typ. Max. Unit Remark

Dynamic Range 5000:1 @ 25°C

Active Energy Metering
0.1 % Fundamental frequency deviation
Error
within ± 25%

Active Energy Metering

1.6 kHz
Bandwidth

Dynamic Range 5000:1 @ 25°C

Reactive Energy Metering
0.1 % Fundamental frequency deviation
Error
within ± 25%

Reactive Energy Metering

1.6 kHz
Bandwidth

Dynamic Range 2000:1 @ 25°C

VRMS Metering Error 1 % Fundamental frequency deviation
within ± 25%

VRMS Metering Bandwidth 1.6 kHz

Dynamic Range 5000:1 @ 25°C

IRMS Metering Error 1 % Fundamental frequency deviation
within ± 25%

IRMS Metering Bandwidth 1.6 kHz

Frequency Measurement

Range 40 70 Hz

Error 0.01 Hz

Analog Input

Maximum Signal Level ±200 mV Peak value

ADC

DC Offset 10 mV

Resolution 23 Bit Sign bit is included.

Bandwidth (-3dB) 0.4 3.2 6.4 kHz

On-chip Reference

Reference Error -18 18 mV @ 25˚C

Power Supply Rejection

92 dB
Ratio

ppm/°
Temperature Coefficient 10 30
C

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V93XX Datasheet
Parameter Min. Typ. Max. Unit Remark

Output Voltage 1.210 V

Power Supply

VDD33 2.6 3.3 3.6 V

POR Detection Threshold 1.22 1.3 1.34 V Error: ±10%

Power-Down Detection
2.6 2.8 3.05 V
Threshold

Digital Power Supply (DVCC)

Voltage 1.5 V Programmable. Error: ±10%

Current 35 mA

CTI

RCL frequency -50% 32.768 +50% KHz

RCH frequency -20% 6.5536 +20% MHz

Logic Input RX

Input High Voltage, VINH 2.4 V

Input Low Voltage, VINL 0 0.4 V

Input Current, IIN 1 μA

Input Capacitance, CIN 10 pF

Baud Rate 1200 19200 bps Automatic baud rate adaption

Related to system CLK, the highest

SPI Data Rate 800 KHz speed is one sixteenth of system

CLK.

1.4. Absolute Maximum Ratings

Unless otherwise specified, the data are based on the test results of TA = 25 ℃, VDD = 3.3 V. Operating

circumstance exceeding Absolute Maximum Ratings may cause permanent damage to the device.

Table 1-3 Absolute maximum ratings

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V93XX Datasheet
Parameter Mnemonic Min. Max. Unit Description

Analog Power Supply VDD -0.3 +3.63 V To ground.

Digital Power Supply DVCC -0.3 +1.98 V To ground.

Analog Input Voltage IAP/IAN/IBP/IBN -0.3 3.3 V To ground.

Analog Input Voltage UP/UN -0.3 3.3 V To ground.

-40 +85 ˚C V9381/V9360/V9340

Operating Temperature
-40 +105 ˚C V9340T

Storage Temperature -55 +150 ˚C

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2. Registers

All register will be reset to default value which are hexadecimal when V93XX is in the reset state.

There are four kinds of reset conditions, including power on reset (POR) external pin reset, global

software reset, and RX reset.

2.1. Registers List

Table 2-1 Register list

Register Type Address Description Default

DSP_CTRL0 R/W 0x00 Analog Control Register 0. 0x00000000

DSP_CTRL1 R/W 0X01 Analog Control Register 1. 0x00000000

DSP_CTRL0 R/W 0x02 Metering Control Register 0. 0x00000000

DSP_CTRL1 R/W 0x03 Metering Control Register 1. 0x00000000

DSP_CTRL2 R/W 0x04 Metering Control Register 2. 0x00000000

DSP_CTRL3 R/W 0x05 Metering Control Register 3. 0x00000000

DSP_CTRL4 R/W 0x06 Metering Control Register 4. 0x00000000

DSP_CTRL5 R/W 0x07 Metering Control Register 5. 0x00000000

DSP_DAT_PA R 0x08 Instantaneous Active Power of channel A. --

DSP_DAT_QA R 0x09 Instantaneous Reactive Power of channel A. --

DSP_DAT_SA R 0x0A Instantaneous Apparent Power of channel A. --

DSP_DAT_PB R 0x0B Instantaneous Active Power of channel B. --

DSP_DAT_QB R 0x0C Instantaneous Reactive Power of channel B. --

DSP_DAT_SB R 0x0D Instantaneous Apparent Power of channel B. --

DSP_DAT_RMS0UA R 0x0E Instantaneous RMS of Voltage. --

DSP_DAT_RMS0IA R 0x0F Instantaneous RMS of current A. --

DSP_DAT_RMS0IB R 0x10 Instantaneous RMS of Current B. --

Instantaneous Value of Fundamental wave of

DSP_DAT_CH1 R 0x11 --
Channel 1.

DSP_DAT_CH2 R 0x12 Instantaneous Value of Fundamental wave of --

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Channel 2.

DSP_DAT_PA1 R 0x13 Average Active Power of Channel A. --

DSP_DAT_QA1 R 0x14 Average Reactive Power of Channel A. --

DSP_DAT_SA1 R 0x15 Average Apparent Power of Channel A. --

DSP_DAT_PB1 R 0x16 Average Active power of Channel B. --

DSP_DAT_QB1 R 0x17 Average Reactive power of Channel B. --

DSP_DAT_SB1 R 0x18 Average Apparent Power of Channel B. --

DSP_DAT_RMS1U R 0x19 Average RMS of Voltage. --

DSP_DAT_RMS1IA R 0x1A Average RMS of Current A. --

DSP_DAT_RMS1IB R 0x1B Average RMS of Current B. --

Average value of Fundamental wave of Channel

DSP_DAT_CH1_AVG R 0x1C --
1.

Average value of Fundamental wave of Channel

DSP_DAT_CH2_AVG R 0x1D --
2.

DSP_DAT_RMSU_AV Average RMS of Voltage for 10 or 12 cycles

R 0x1E --
G (chose by line frequency).

DSP_DAT_RMSIA_AV Average RMS of Current IA for 10 or 12 cycles

R 0x1F --
G (chose by line frequency).

DSP_DAT_RMSIB_AV Average RMS of Current IB for 10 or 12 cycles

R 0x20 --
G (chose by line frequency).

DSP_DAT_FRQ R 0x21 Line Frequency. --

DSP_DAT_DCU R 0x22 DC value of voltage channel. --

DSP_DAT_DCIA R 0x23 DC value of current channel A. --

DSP_DAT_DCIB R 0x24 DC value of Current channel B. --

DSP_CFG_CALI_PA R/W 0x25 To set gain calibration for the active power A. 0x00000000

DSP_CFG_DC_PA R/W 0x26 To set offset calibration for the active power A. 0x00000000

DSP_CFG_CALI_QA R/W 0x27 To set gain calibration for Reactive power A. 0x00000000

DSP_CFG_DC_QA R/W 0x28 To set offset calibration for Reactive power A. 0x00000000

DSP_CFG_CALI_PB R/W 0x29 To set gain calibration for Active power B. 0x00000000

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DSP_CFG_DC_PB R/W 0x2A To set offset calibration for Active power B. 0x00000000

DSP_CFG_CALI_QB R/W 0x2B To set gain calibration for Reactive power B. 0x00000000

DSP_CFG_DC_QB R/W 0x2C To set offset calibration for Reactive power B. 0x00000000

DSP_CFG_CALI_RMS
R/W 0x2D To set gain calibration for Voltage RMS. 0x00000000
U

DSP_CFG_RMS_DCU R/W 0x2E To set offset calibration for Voltage RMS. 0x00000000

DSP_CFG_CALI_RMSI
R/W 0x2F To set gain calibration for Current RMS A. 0x00000000
A

DSP_CFG_RMS_DCIA R/W 0x30 To set offset calibration for Current RMS A. 0x00000000

DSP_CFG_CALI_RMSI
R/W 0x31 To set gain calibration for Current RMS B. 0x00000000
B

DSP_CFG_RMS_DCIB R/W 0x32 To set offset calibration for Current RMS B. 0x00000000

Phase Error Calibration Register.

[10:0]= phase error calibration value for channel

A
DSP_CFG_PHC R/W 0x33 0x00000000
[26:16]= phase error calibration value for

channel B, where the range is from

-766~767.

DSP_CFG_DCU R/W 0x34 To set the DC calibration for the voltage channel. 0x00000000

To set the DC calibration for the current channel

DSP_CFG_DCIA R/W 0x35 0x00000000
A.

To set the DC calibration for the current channel

DSP_CFG_DCIB R/W 0x36 0x00000000
B.

Band-pass filter coefficient. Related to setting the

DSP_MODE by Bit[7:4] of metering control

DSP_CFG_BPF R/W 0x37 Setting 0x806764B6 at DSP_MODE=0, 1, 2; 0x00000000

Setting 0x80DD7A8C at DSP_MODE=6, 7;

Setting 0x82B465F0 at DSP_MODE=8.

The frequency of other modes would be not

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V93XX Datasheet
supported to measure, so setting to 0x0.

DSP_CFG_CKSUM R/W 0x38 Configuration register for checksum. 0x00000000

Anti-creep threshold for energy accumulator.

When the accumulated value of the anti-creep

energy accumulator over this threshold and the

EGY_PROCTH R/W 0x39 accumulated value of the high-speed energy 0x00000000

accumulator under this threshold, the

accumulated value of the high-speed energy

accumulator will be cleared.

Accumulation threshold for energy accumulator.

Because the energy accumulator was 46Bit, the

accumulated value of the high-speed energy

EGY_PWRTH R/W 0x3A 0x00000000
accumulator equals to this threshold*16384; the

accumulated value of the low-speed energy

accumulator equals to this value*4.

EGY_CONST1 R/W 0x3B Energy accumulator 1 accumulating constant. 0x00000000

EGY_OUT1L R/W 0x3C Energy accumulator 1 accumulating lower bit. 0x00000000

Energy accumulator 1 accumulating higher bit.

EGY_OUT1H R/W 0x3D 0x00000000
Effective for lower 14 bit.

EGY_CFCNT1 R 0x3E Energy accumulator 1 pulse counter. 0x00000000

EGY_CONST2 R/W 0x3F Energy accumulator 2 accumulating constant. 0x00000000

EGY_OUT2L R/W 0x40 Energy accumulator 2 accumulating lower bit. 0x00000000

Energy accumulator 2 accumulating higher bit.

EGY_OUT2H R/W 0x41 0x00000000
Effective for lower 14 bit.

EGY_CFCNT2 R 0x42 Energy accumulator 2 pulse counter. 0x00000000

EGY_CONST3 R/W 0x43 Energy accumulator 3 accumulating constant. 0x00000000

EGY_OUT3 R/W 0x44 Energy accumulator 3 accumulating value. 0x00000000

EGY_CFCNT3 R 0x45 Energy accumulator 3 pulse counter. 0x00000000

EGY_CONST4 R/W 0x46 Energy accumulator 4 accumulating constant. 0x00000000

EGY_OUT4 R/W 0x47 Energy accumulator 4 accumulating value. 0x00000000

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EGY_CFCNT4 R 0x48 Energy accumulator 4 pulse counter. 0x00000000

EGY_CONST5 R/W 0x49 Energy accumulator 5 accumulating constant. 0x00000000

EGY_OUT5 R/W 0x4A Energy accumulator 5 accumulating value. 0x00000000

EGY_CFCNT5 R 0x4B Energy accumulator 5 pulse counter. 0x00000000

EGY_CONST6 R/W 0x4C Energy accumulator 6 accumulating constant. 0x00000000

EGY_OUT6 R/W 0x4D Energy accumulator 6 accumulating value. 0x00000000

EGY_CFCNT6 R 0x4E Energy accumulator 6 pulse counter. 0x00000000

EGY_CONST7 R/W 0x4F Energy accumulator 7 accumulating constant. 0x00000000

EGY_OUT7 R/W 0x50 Energy accumulator 7 accumulating value. 0x00000000

EGY_CFCNT7 R 0x51 Energy accumulator 7 pulse counter. 0x00000000

EGY_CONST8 R/W 0x52 Energy accumulator 8 accumulating constant. 0x00000000

EGY_OUT8 R/W 0x53 Energy accumulator 8 accumulating value. 0x00000000

EGY_CFCNT8 R 0x54 Energy accumulator 8 pulse counter. 0x00000000

To set the lower threshold for the power-creep

DSP_OV_THL R/W 0x55 0x00000000
detection.

To set the upper threshold for the power-creep

DSP_OV_THH R/W 0x56 0x00000000
detection.

DSP_SWELL_THL R/W 0x57 To set the lower threshold for the voltage swell. 0x00000000

DSP_SWELL_THH R/W 0x58 To set the upper threshold for the voltage dip. 0x00000000

DSP_DIP_THL R/W 0x59 To set the lower threshold for the voltage dip. 0x00000000

DSP_DIP_THH R/W 0x5A To set the upper threshold for the voltage dip. 0x00000000

To set over-voltage threshold for fast detection.

FD_OVTH R/W 0x5B 0x00000000
Bit width is 30bit.

To set under-voltage threshold for fast detection.

FD_LVTH R/W 0x5C 0x00000000
Bit width is 30bit.

To set over-current threshold in current channel

FD_IA_OCTH R/W 0x5D 0x00000000
A for fast detection. Bit width is 30bit.

To set under-current threshold in current channel

FD_IA_LCTH R/W 0x5E 0x00000000
A for fast detection. Bit width is 30bit.

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To set over-current threshold in current channel
FD_IB_OCTH R/W 0x5F 0x00000000
B for fast detection. Bit width is 30bit.

To set under-current threshold in current channel

FD_IB_LCTH R/W 0x60 0x00000000
B for fast detection. Bit width is 30bit.

To control the phase measurement. Enable phase

DSP_PHS_STT R/W 0x61 --
measurement once for writing operation.

DSP_PHS_U R 0x62 Voltage phase. 1

Voltage waveform data which before zero-

DSP_PHS_UN R 0x63 0
crossing.

DSP_PHS_UP R 0x64 Voltage waveform data which after zero-crossing. 0x80000000

DSP_PHS_I R 0x65 Current phase. 1

Current waveform data which before zero-

DSP_PHS_IN R 0x66 0
crossing.

DSP_PHS_IP R 0x67 Current waveform data which after zero-crossing. 0x80000000

Waveform data reading. It can repeatable

reading the address and obtain the overall

DAT_WAVE R 0x69 waveform data. If there is no need to read all 0

data, it would be reset the bit 31 of DSP_CTRL5

to read address.

Voltage swell time records, half-wave as unit.

DAT_SWELL_CNT R/C 0x6A Effective as 24bit. Writing any value into this 0

address would be clear this counter to zero.

Voltage dip time records, half wave as unit.

DAT_DIP_CNT R/C 0x6B Effective as 24bit. Writing any value into this 0

address would be clear this counter to zero.

Software reset register.

SYS_SFTRST W 0x6C Writing 0x4572beaf into this address would be --

happen software reset once.

This register stores the system clock count value

SYS_BAUDCNT1 R 0x70 --
of the first bit of the UART frame header sent by

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V93XX Datasheet
V93XX.

This register stores the system clock count value

SYS_BAUDCNT8 R 0x71 of the 8 bits of the UART frame header received --

by V93XX.

SYS_INTSTS R/C 0x72 Interrupt status register. --

SYS_INTEN R/W 0x73 Interrupt enable register. 0x00000000

SYS_STS R 0x74 System status register. --

SYS_MISC R/W 0x75 System control register. --

SYS_BLK0_ADDR R/W 0x79 Register for block reading address 0. 0

SYS_BLK1_ADDR R/W 0x7A Register for block reading address 1. 0

SYS_BLK2_ADDR R/W 0x7B Register for block reading address 2. 0

SYS_BLK3_ADDR R/W 0x7C Register for block reading address 3. 0

Output configuration register for P0, P1, P2 and

SYS_IOCFGX0 R/W 0x7D 0
P3.

SYS_IOCFGX1 R/W 0x7E Output configuration register for P4, P5 and P6. 0

SYS_VERSION R 0x7F Present hardware version. --

2.2. Analog Control Registers

When power-on reset (POR), RSTN pin reset, RX reset, or global software reset occurs, all analog control

registers will be reset to the default value. The default value in the following tables of this section are in

format of hexadecimal.

The address range of Analog Control Register is 0x00~0x01 which all is readable and writable. Also, all

the metering control registers need to be configuration verification and self-checking.

2.2.1. ANA_CTRL0 Register

Table 2-2 Analog Control Register 0 (0x00, ANA_CTRL0)

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0x00, R/W, Analog Control Register 0, ANA_CTRL0

Bit Default Value Description

These bits must hold its default value for proper

31:18 Reserved 0
operation.

These bits must hold its default value for proper

17:14 Reserved 0
operation.

To select the analog input for Channel IB.

13 MEA 0 0: differential IB input

1: Reserved

12 Reserved 0 The bit must hold its default value for proper operation.

Current IA channel ADC input short circuit.

11 SHORT_I 0 0: short circuit

1: Normal

Voltage U channel ADC input short circuit.

10 SHORT_V 0 0: short circuit

1: Normal

These bits must hold its default value for proper

9:0 Reserved 0
operation.

2.2.2. ANA_CTRL1 Register

Table 2-3 Analog Control Register 1 (0x01, ANA_CTRL1)

0x01, R/W, Analog Control Register 1, ANA_CTRL1

Default
Bit Description
Value

31:30 ADCKSEL[1:0] 0 The options of clock frequency divider rate for the ADC

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0x01, R/W, Analog Control Register 1, ANA_CTRL1

Default
Bit Description
Value

00 corresponds to 819.2 KHz.

00: ×1

01: ×2

10: ×1/4

11: ×1/2

To adjust the 6.5M RC frequency.

29:24 RCHTRIM[5:0] 0 000000~011111: step-up the frequency by 1.25%

100000~111111: step-down the frequency by 1.25%

23 Reserved 0 The bit must hold its default value for proper operation.

To enable the 6.5M RC oscillator.

0: enable
22 RCCLK_PD 0
1: disable

This bit must be set to 0 for proper operation.

21:15 Reserved 0 These bits must hold its default value for proper operation.

To adjust the gain of current ADC in the channel B.

000: 4

001: 1

14:12 GIB[2:0] 0 010: 32

011: 16

100/101/110/111: prohibited

GIB[2:0] is recommended set to 000 for proper operation.

11 GU 0 To adjust the gain of voltage ADC.

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0x01, R/W, Analog Control Register 1, ANA_CTRL1

Default
Bit Description
Value

0: 8

1: 4

This bit must be set to 0 for proper operation.

To adjust the gain of current ADC in the channel A.

000: 32

001: 16

10:8 GIA[2:0] 0 010: 4

011: 1

100~111: prohibited

GIA[2:0] is recommended set to 000 for proper operation.

The external input CTI clock enable.

7 XRST_PD 0 0: enable

1: disable

6:5 Reserved 0 These bits must hold its default value for proper operation.

To roughly adjust the temperature coefficient of the

Bandgap circuit.

00: 0 ppm

4:3 RESTL[1:0] 0
01: -58 ppm

10: +111 ppm

11: +56 ppm

To finely adjust the temperature coefficient of the Bandgap

2:0 REST[2:0] 0
circuit.

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V93XX Datasheet
0x01, R/W, Analog Control Register 1, ANA_CTRL1

Default
Bit Description
Value

000: 0 ppm

001: +7 ppm

010: +14 ppm

011: +28 ppm

100: -32 ppm

101: -21 ppm

110: -14 ppm

111: -7 ppm

2.3. System Control & Status Register

When power-on reset (POR), RSTN pin reset, RX reset, or global software reset occurs, all system control

registers will be reset to the default value. The default value in the following tables of this section are in

format of hexadecimal.

In the V93XX, the mainly functions of System Control Register is controlling interface, interrupt, RAM,

and IO output. SYS_INTEN (0x73) controls enable interruption, SYS_INTSYS (0x72) is interrupted status

output whether reverse, whether turn off the energy accumulator when power down and whether turn

off the energy accumulator when in wrong calibration. SYS_RAMADDR (0x77) is controlling internal RAM

address. SYS_RAMDATA is internal RAM data registers. SYS_BLK0_ADDR~SYS_BLK3_ADDR are blocked

reading address. SYS_IOCFGX0~SYS_IOCFGX1 are the control register of IO output

2.3.1. SYS_BAUDCNT1 Register

Table 2-4 UART transmitting data 1bit count value (0x70, SYS_BAUDCNT1)

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0x70, UART transmitting data 1bit count value, SYS_BAUDCNT1

bit R/W Default Value Description

31:14 - - - Reserved.

13:0 BAUDCNT1 R This register stores the system clock count value of

the first bit of the UART frame header sent by V93XX.

2.3.2. SYS_BAUDCNT8 Register

Table 2-5 UART receiving data 8bit count value (0x71, SYS_BAUDCNT8)

0x71, UART receiving data 8bit count value, SYS_BAUDCNT8

Bit R/W Default Value Description

31:17 - - - Reserved.

16:0 BAUDCNT8 R This register stores the system clock count value of the

8 bits of the UART frame header received by V93XX.

2.3.3. SYS_INTSTS Register

Table 2-6 System Interrupt Register (0x72, SYS_INTSTS)

0x72, System Interrupt Register, SYS_INTSTS

Bit R/W Default value Description

31:30 - - - Reserved.

Flag bit for high-speed energy accumulator 2

overflow interrupt

Read 0: high-speed energy accumulator overflow

29 EGY2OV R/C 0
did not happen

Read 1: high-speed energy accumulator overflow

happened

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0x72, System Interrupt Register, SYS_INTSTS

Bit R/W Default value Description

Write 0: no effects

Write 1: clear the bit

Flag bit for high-speed energy accumulator 1

overflow interrupt

Read 0: high-speed energy accumulator overflow

did not happen

28 EGY1OV R/C 0
Read 1: high-speed energy accumulator overflow

Write 1: clear the bit

Flag bit for the SPI communication error.

When any one of condition below happens, the bit

will set to “1”.

19 SPI_ERR R/C 0 A, SPI overtime (rising edge of each 2 SPCK needs

to shorter than 20 ms)

B, SPI CLK counter error (the number of clocks

not equals to 48 at 4-wire SPI)

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0x72, System Interrupt Register, SYS_INTSTS

Bit R/W Default value Description

Read 0: SPI error did not happen

Read 1: SPI error happened

write 0: no effects

write 1: clear the bit

18:17 Reserved - - -

Flag bit for the UART communication error.

When any one of condition as below happens, the

bit will set to “1”.

A: UART overtime (each 2 Bytes needs to shorter

than 20 ms)

16 UART_ERR R/C 0 B: UART checksum bit error

C: UART checksum byte error

Read 0: UART error did not happen

Read 1: UART happened

write 0: no effects

write 1: clear the bit

Flag bit for active waveform uploading finished.

Read 0: active waveform uploading did not finish

15 DMA_FINISH R/C 0 Read 1: active waveform uploading finished

Write 0: no effects

Write 1: clear the bit

Flag bit for checksum error. Checksum from

correct to error, it would be interrupted.

Read 0: checksum error did not happen

14 CKERR R/C
Read 1: checksum error happened

Write 0: no effects

Write 1: clear the bit

Flat bit for CTI external input clock status.

13 HSE_FAIL R/C
Read 0: CTI external input clock error has

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0x72, System Interrupt Register, SYS_INTSTS

Bit R/W Default value Description

occurred l did not happen

Read 1: CTI external input clock error has

happened

Write 0: no effects

Write 1: clear the bit

Flag bit for reference error

Read 0: reference error did not happen

12 REF_ERR R/C Read 1: reference error happened

Write 0: no effects

Write 1: clear the bit

Flag bit for BIST error

Read 0: BIST error did not happen

11 BIST_ERR R/C Read 1: BIST error happened

Write 0: no effects

Write 1: clear the bit

Flag bit for current zero-crossing, it could to select

the channel IA or IB by bit20 of metering control

register (Table 2-19 Metering Control Register 2

(0x03, DSP_CTRL1)), and to select the direction of

zero-crossing by bit19~bit18 of metering control

10 ISIGN R/C
register (0x03,DSP_CTRL1).

Read 0: current zero-crossing did not happen

Read 1: current zero-crossing happened

Write 0: no effects

Write 1: clear the bit

Flag bit for voltage zero-crossing, it could to select

the direction of zero-crossing by bit19~bit18 of

9 USIGN R/C
DSP_CTRL1

Read 0: voltage zero-crossing did not happen

Write 1: clear the bit

3 CURPOWER_UPD R/C 0 Flag bit for instantaneous power data updating.

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0x72, System Interrupt Register, SYS_INTSTS

Bit R/W Default value Description

Read 0: instantaneous power data did not update

Read 1: instantaneous power data updated

Write 0: no effects

Write 1: clear the bit

Flag bit for average power data updating.

V93XX Datasheet
0x73, System Interrupt Enable Register, SYS_INTEN

Bit R/W Default Value Description

These bits must hold its default value for proper

31:30 Reserved 0
operation.

Interrupt for high-speed energy accumulator 2

overflow
29 EGY2OV R/W 0
0: disable interrupt

1: enable interrupt

Interrupt for SPI transmission error.

19 SPI_ERR R/W 0 0: disable interrupt

1: enable interrupt

These bits must hold its default value for proper

18:17 Reserved
operation.

Interrupt for UART transmission error.

16 UART_ERR R/W 0 0: disable interrupt

1: enable interrupt

Waveform uploading finished.

15 DMA_FINISH R/W 0 0: disable interrupt

1: enable interrupt

Interrupt for checksum error.

14 CKERR R/W 0 0: disable interrupt

1: enable interrupt

Interrupt for CTI external input clock error.

13 HSE_FAIL R/W 0
0: disable interrupt

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Interrupt for the Instantaneous RMS data

5 CURRMS_UPD R/W 0 updating.

0: disable interrupt

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V93XX Datasheet
0x73, System Interrupt Enable Register, SYS_INTEN

Table 2-8 System Status Register (0x74, SYS_STS)

0x74, System Status Register, SYS_STS

Bit R/W Default Value Description

31 - - - Reserved

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0x74, System Status Register, SYS_STS

Bit R/W Default Value Description

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V93XX Datasheet
0x74, System Status Register, SYS_STS

Bit R/W Default Value Description

Status bit for reset.

1: power on reset

2: external reset
22:20 RST_SOURCE R -
3: RX low-level voltage reset

4: software reset

Others are reserved.

1: negative

Sign bit for active power Channel B. Under the power-

creep detection, no refresh the flag bit.

10 PBSIGN R 0
0: positive

1: negative

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0x74, System Status Register, SYS_STS

Bit R/W Default Value Description

Sign bit for reactive power Channel A. Under the

power-creep detection, no refresh the flag bit.

9 QASIGN R 0
0: positive

1: negative

Sign bit for active power Channel A. Under the power-

creep detection, no refresh the flag bit.

8 PASIGN R 0
0: positive

1: negative

7 - - - Reserved

Status bit for CTI external input clock status.

6 HSEFAIL R 0 0: normal

1: abnormal

Status bit for SRAM BIST.

5 BISTERR R 0 0: SRAM BIST normal

1: SRAM BIST error

Status bit for RAM initialization finished

4 RAMINITIAL 0 0: failed

1: finished

Status bit for Phase measurement finished

3 PHSDONE 0 0: failed

1: finished

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0x74, System Status Register, SYS_STS

Bit R/W Default Value Description

Status bit for power down. When the power input

(VDD) is lower than 2.8V (±7%), power down event

2 PD R 0 happens.

0: VDD >= 2.8V (±7%)

1: VDD < 2.8V (±7%)

Status bit for the reference of ADC whether electric

leaking.

1 REFLK R 0 0: ADC reference circuit normal

1: ADC reference circuit decrease is greater than

2.5%.

Status bit for Checksum. Checksum calculation

address range: 0x0 ~ 0x7, 0x25 ~ 0x3A, 0x55 ~ 0x60

0 CHECKSUM R 1
0: checksum correct

1: checksum incorrect

2.3.6. SYS_MISC Register

Table 2-9 System Control Register (0x75, SYS_MISC)

0x75, system Control Register, SYS_MISC

Bit R/W Default Value Description

These bits must hold its default value for proper

31:25 Reserved R 0
operation.

24:16 WAVE_STORE_CNT R 0 Count value for Waveform storage.

These bits must hold its default value for proper

15:6 Reserved 0
operation.

5 BIST_EGY_EN R/W 0 When RAM self-test has error, force the energy

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0x75, system Control Register, SYS_MISC

Bit R/W Default Value Description

accumulator and CF output to disable.

0: enable

1: disable

The control bits for the energy accumulator and

CF counter (Bit[15] and Bit[7:6]) in DSP_CTRL1

register will not change.

Although the DSP_CTRL1 register value has not

changed, the energy accumulator and CF output

functions will not be restored automatically and

need to be opened manually by the user after

the state returns to normal.

When checksum has error, force the energy

accumulator and CF output to disable.

0: enable

1: disable

The control bits for the energy accumulator and

4 CK_EGY_EN R/W 0 CF counter (Bit[15] and Bit[7:6]) in DSP_CTRL1

register will not change.

Although the DSP_CTRL1 register value has not

changed, the energy accumulator and CF output

functions will not be restored automatically and

need to be opened manually by the user after

the state returns to normal.

When power-down, force the energy

3 PD_EGY_EN R/W 0 accumulator and CF output to disable.

0: enable

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0x75, system Control Register, SYS_MISC

Bit R/W Default Value Description

1: disable

The control bits for the energy accumulator and

CF counter (Bit[15] and Bit[7:6]) in DSP_CTRL1

register will not change.

Although the DSP_CTRL1 register value has not

changed, the energy accumulator and CF

output functions will not be restored

automatically and need to be opened manually

by the user after the state returns to normal.

Reverse output on Interrupted pin.

0: interrupt pin triggered by high-level voltage,

2 INTPOL R/W 0 and default is low-level voltage.

1: interrupt pin triggered by low-level voltage,

and default is high-level voltage.

To enable the UART continue writing mode.

1 UARTBURSTEN R/W 0 0: enable

1: disable

To enable baud rate self-adapting for UART. It

suggests enabling before changing system CLK.

0: disable Baud rate self-adapting function.

Baud rate self-adapting only for first time

0 UARTAUTOEN R/W 0
communication.

1: enable Baud rate self-adapting function.

Baud rate self-adapting for every time

communication.

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2.3.7. SYS_BLKX Register

Table 2-10 Block-reading Address Register 0 (0x79, SYS_BLK0_ADDR)

0x79, Block-reading Address Register 0, SYS_BLK0_ADDR

Bit R/W Default Value Description

31:24 ADDR3 R/W 0 Block-reading address 3.

23:16 ADDR2 R/W 0 Block-reading address 2.

15:8 ADDR1 R/W 0 Block-reading address 1.

7:0 ADDR0 R/W 0 Block-reading address 0.

Table 2-11 Block-reading Address Register 1 (0x7A, SYS_BLK1_ADDR)

0x7A, Block-reading Address Register 1, SYS_BLK1_ADDR

Bit R/W Default Value Description

31:24 ADDR7 R/W 0 Block-reading address 7.

23:16 ADDR6 R/W 0 Block-reading address 6.

15:8 ADDR5 R/W 0 Block-reading address 5.

7:0 ADDR4 R/W 0 Block-reading address 4.

Table 2-12 Block-reading Address Register 2 (0x7B, SYS_BLK2_ADDR)

0x7B, Block-reading Address Register 2, SYS_BLK2_ADDR

Bit R/W Default Value Description

31:24 ADDR11 R/W 0 Block-reading address 11.

23:16 ADDR10 R/W 0 Block-reading address 10.

15:8 ADDR9 R/W 0 Block-reading address 9.

7:0 ADDR8 R/W 0 Block-reading address 8.

Table 2-13 Block-reading Address Register 3 (0x7C, SYS_BLK3_ADDR)

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0x7C, Block-reading Address Register 3, SYS_BLK3_ADDR

Bit R/W Default Value Description

31:24 ADDR15 R/W 0 Block-reading address 15.

23:16 ADDR14 R/W 0 Block-reading address 14.

15:8 ADDR13 R/W 0 Block-reading address 13.

7:0 ADDR12 R/W 0 Block-reading address 12.

2.3.8. SYS_IOCFGXX Register

Table 2-14 IO Configuration Register 0 (0x7D, SYS_IOCFGX0)

0x7D, IO Configuration Register 0, SYS_IOCFGX0

Bit R/W Default Value Description

31:24 P3CFG R/W 0 Configuration as the same as P0CFG.

23:16 P2CFG R/W 0 Configuration as the same as P0CFG.

15:8 P1CFG R/W 0 Configuration as the same as P0CFG.

7:0 P0CFG R/W 0 Bit[7:6]:

00: as shown in the Table 2-15, it can be configured the

different combination interruption.

10: CF1 output. Bit[5:0] can be configured arbitrary value.

01: CF2 output. Bit[5:0] can be configured arbitrary value.

11: Actively energy accumulation data uploads. Bit[5:0] can

be configured arbitrary value.

Table 2-15 P0CFG Bit[5:0] Description

Bit[5:3] Bit[2:0]

0 0 High impedance.

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0 1 Current zero-crossing interruption.

0 2 Voltage zero-crossing interruption.

0 3 Current zero-crossing interruption.

0 4 Voltage zero-crossing interruption.

0 5 High speed energy accumulator 1 overflow interrupt

0 6 High speed energy accumulator 2 overflow interrupt

0 7 1st type interruption.

1 0 Waveform refresh interruption.

1 1 Instantaneous RMS refresh interruption.

1 2 Average RMS refresh interruption.

1 3 Instantaneous power refresh interruption.

1 4 Average power refresh interruption.

1 5 Waveform storage finish interruption.

1 6 Waveform storage address overflow interruption.

1 7 Waveform data upload finish interruption.

2 0 IB channel under-current interruption.

2 1 IB channel over-current interruption.

2 2 IA channel under-current interruption.

2 3 IA channel over-current interruption.

2 4 Voltage Channel under-voltage interruption.

2 5 Voltage Channel over-voltage interruption.

2 6 Voltage dip interruption.

2 7 Voltage swell interruption.

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3 0 Reference error.

3 1 CTI external input clock error.

3 2 SPI communication error interruption.

3 3 UART communication error interruption.

3 4 Power-down interruption.

3 5 Parameter self-checking error interruption.

3 6 Phase test finish interruption.

3 7 RAM self-checking error.

4 0 1st type interruption.

4 1 2nd type interruption.

4 2 3rd type interruption.

4 others 4th type interruption.

5 0 3rd type interruption.

5 1 1st and 2nd type interruption.

5 2 1st and 3rd type interruption.

5 3 1st and 4th type interruption.

5 4 2nd and 3rd type interruption.

5 5 2nd and 4th type interruption.

5 6 3rd and 4th type interruption.

5 7 All interruption.

6 0 1st, 2nd and 3rd type interruption.

6 1 1st, 2nd and 4th type interruption.

6 2 1st, 3rd and 4th type interruption.

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6 3 2nd, 3rd and 4th type interruption.

6 others All interruption.

7 1 Active waveform updating for chip select of SPI, SPIMAS_SPCSN.

7 2 Active waveform updating for SPI clock, SPIMAS_SPCK.

7 4 Active waveform updating for SPI data, SPIMAS_SPDO.

7 others Prohibited output.

While the IO interface is not configured (i.e. all zero), output is high impedance.

⬧ 1st type interruption: current zero-crossing interruption, voltage zero-crossing interruption, high-

speed energy accumulator 1/2 overflow interruption.

⬧ 2nd type interruption: waveform refreshes interruption, instantaneous RMS refresh interruption,

average RMS refreshes interruption, instantaneous power value refresh interruption, average power

value refreshes interruption, waveform storage finish interruption, waveform storage overflow

interruption and waveform data upload finished interruption.

⬧ 3rd type interruption: IB channel under-current interruption, IB channel over-current interruption,

IA channel under-current interruption, IA channel over-current interruption, voltage channel under-

voltage interruption, voltage channel over-voltage interruption, voltage dip interruption and voltage

swell interruption.

⬧ 4th type interruption: SPI communicating error interruption, UART communicating error interruption,

parameters self-checking error interruption, phase measurement finished interruption, power-down

interruption, reference error interruption, CTI external input clock error interruption and RAM self-

checking error interruption.

Table 2-16 IO Configuration Register 1 (0x7E, SYS_IOCFGX1)

0x7E, IO Configuration Register 1, SYS_IOCFGX1

Bit R/W Default Value Description

31:24 Reserved 0 These bits must hold its default value for proper operation.

23:16 P6CFG R/W 0 Configuration as the same as P0CFG.

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0x7E, IO Configuration Register 1, SYS_IOCFGX1

Bit R/W Default Value Description

15:8 P5CFG R/W 0 Configuration as the same as P0CFG.

7:0 P4CFG R/W 0 Configuration as the same as P0CFG.

2.3.9. SYS_VERSION Register

Table 2-17 Version Information Register (0x7F, SYS_VERSION)

0x7F, Version Information Register, SYS_VERSION

Bit R/W Default Value Description

31:0 VERSION R - Present hardware version.

2.4. Metering Control Registers

When power-on reset (POR), RSTN pin reset, RX reset, or global software reset occurs, all metering

control registers will be reset to the default value. The default value in the following tables of this section

are in format of hexadecimal.

All the metering control registers need to be configuration verification and self-checking.

2.4.1. DSP_CTRL0 Register

Table 2-18 Metering Control Register 0 (0x02, DSP_CTRL0)

0x02, R/W, Metering Control Register 0, DSP_CTRL0

Bit R/W Default Value Description

Double refresh time for Instantaneous power value

and RMS value.

31 CURDAT_RATE R/W 0 0: refresh time for instantaneous power value is 20

ms and instantaneous RMS value is 10 ms.

1: refresh time for instantaneous power value is 40

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0x02, R/W, Metering Control Register 0, DSP_CTRL0

Bit R/W Default Value Description

ms and instantaneous RMS value is 20 ms.

The bit must hold its default value for proper

30 Reserved 0
operation.

Source comes from the register value of

DSP_DAT_FRQ.

00: accumulation value for line frequency test value

of 16 cycles (the default update time is 320 ms)

29:28 FRQ_SEL R/W 0 01: line frequency test value of 1 cycle (the default

update time is 20 ms)

10: line frequency test value of 64 cycles (the

default update time is 1280 ms)

11: Reserved

To enable the DC metering mode.

27 DC_METER_MODE R/W 0 0: disable

1: enable

The bit must hold its default value for proper

26：25 - - 0
operation.

Source select for Apparent power calculation.

24 S_MODE R/W 0 0: by RMS value

1: by power value

Fundamental Channel selectable.

0: channel 1, fundamental active power A; channel

23:20 CFG_CHANNEL R/W 0
2, fundamental active power B

1: channel 1, fundamental active power A; channel

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0x02, R/W, Metering Control Register 0, DSP_CTRL0

Bit R/W Default Value Description

2, fundamental voltage RMS

2: channel 1, fundamental active power A; channel

2, fundamental current RMS A

3: channel 1, fundamental active power A; channel

2, fundamental current RMS B

4: channel 1, fundamental active power B, channel

2, fundamental voltage RMS

5: channel 1, fundamental active power B; channel

2, fundamental current RMS A

6: channel 1, fundamental active power B; channel

2, fundamental current RMS B

7: channel 1, fundamental voltage RMS; channel 2,

fundamental current RMS A

8: channel 1, fundamental voltage RMS, channel 2,

fundamental current RMS B

9: channel 1, fundamental current RMS A; channel

2, fundamental current RMS B

10~15: the same as configured 0

To select mode for Reactive power B.

19 QB_MODE R/W 0 0: total wave, reactive power

1: fundamental wave, reactive power

To select mode for Reactive power A.

18 QA_MODE R/W 0 0: total wave, reactive power

1: fundamental wave, reactive power

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0x02, R/W, Metering Control Register 0, DSP_CTRL0

Bit R/W Default Value Description

Calculate the total power whether pass high-pass

filter.
17 PQ_HPFSEL R/W 0
0: pass

1: not pass

Calculate the fundamental data whether pass high-

pass filter:
16 FUND_HPFSEL R/W 0
0: pass

1: not pass

Calculate the total voltage RMS data whether pass

high-pass filter:
15 RMSU_HPFSEL R/W 0
0: pass

1: not pass

Calculate the total current IA RMS data whether

pass high-pass filter:

14 RMSIA_HPFSEL R/W 0
0: pass

1: not pass

Calculate current IB RMS data whether pass high-

pass filter:
13 RMSIB_HPFSEL R/W 0
0: pass

1: not pass

Metering data response time.

12 RESPONSE_TIME R/W 0 0: normal

1: 2 times

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0x02, R/W, Metering Control Register 0, DSP_CTRL0

Bit R/W Default Value Description

Average RMS refresh time.

00: 40 ms

11:10 AVGRMS_RATE R/W 0 01: 80 ms

10: 320 ms

11: 640 ms

Average power refresh time.

00: 40 ms

9:8 AVGPQ_RATE R/W 0 01: 80 ms

10: 320 ms

11: 640 ms

DSP Operating Mode.

0: 128 sampling points per cycle by DSP at 6.5536

MHz system clock

1: 64 sampling points per cycle by DSP at 6.5536

MHz system clock

2: 32 sampling points per cycle by DSP at 6.5536

MHz system clock.

3, 4, and 5: Reserved.
7:4 DSP_MODE R/W 0
6: 64 sampling points per cycle by DSP at 3.2768

MHz system clock

7: 32 sampling points per cycle by DSP at 3.2768

MHz system clock

8: 32 sampling points per cycle by DSP at 819.2

KHz system clock (supported only up to 2 channels

instantaneous current RMS calculation.)

9: 16 sampling points per cycle by DSP at 409.6

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0x02, R/W, Metering Control Register 0, DSP_CTRL0

Bit R/W Default Value Description

KHz system clock (supported only up to 2 channels

instantaneous current RMS calculation.)

Others: the same as mode 0

3 - - 0 Reserved

To enable the voltage channel (including ADC and

2 ADCUEN R/W 0
DSP).

To enable the current channel B (including ADC and

1 ADCIBEN R/W 0
DSP).

To enable the current channel A (including ADC and

0 ADCIAEN R/W 0
DSP).

2.4.2. DSP_CTRL1 Register

Table 2-19 Metering Control Register 2 (0x03, DSP_CTRL1)

0x03, R/W, Metering Control Register 2, DSP_CTRL1

Bit R/W Default Value Description

Automatic gain compensation for filter.

By default, this function was enabled. This bit does not

influence DC metering. It will automatic turn off during

31 BW_COMP R/W 0
the DC metering.

0: enable

1: disable

The bit must hold its default value for proper

30:22 Reserved 0
operation.

To select the energy accumulator CLK. It needs the

23 EGY_CLK_SEL R/W 0 stable time around 107 μs when CLK switch over.

Please disable CF before it is stable.

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0x03, R/W, Metering Control Register 2, DSP_CTRL1

Bit R/W Default Value Description

0: 204.8 KHz

1: 32.768 KHz

0: disable

To write “0” into the bit31 of the DSP_CTRL0 the

accumulating cycle of energy accumulator 3, 4, 5, 6,

7, and 8 is 20ms.

To write “1” into the bit31 of the DSP_CTRL0, the

accumulating cycle of energy accumulator 3, 4, 5, 6,

7, and 8 is 40 ms.

1: enable
22 LCF_ACC R/W 0
To write “0” into the bit31 of the DSP_CTRL0, the

accumulating cycle of energy accumulator 3, 4, and 5

is 10 ms. Energy accumulator 6, 7, and 8 not

accumulate.

To write “1” into the bit31 of the DSP_CTRL0, the

accumulating cycle of energy accumulator 3, 4, and 5

is 20 ms. Energy accumulator 6, 7, and 8 not

accumulate.

Voltage channel digital PGA:

21 PGA_U R/W 0 0: X1

1: X4

To select the input source for current zero-crossing.

20 PHSI_SEL R/W 0 0: current channel IA

1: current channel IB

To select the detect method of zero-crossing:

0: negative direction (it indicates the signal changing

19:18 SIGN_SEL R/W 0 from positive to negative is occurring a zero-crossing

event)

1: positive direction (it indicates the signal changing

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0x03, R/W, Metering Control Register 2, DSP_CTRL1

Bit R/W Default Value Description

from negative to positive is occurring a zero-crossing

event)

2: positive and negative direction

3: disable the zero-crossing detection function

Actively power accumulating data uploads, the upload

interface can pass SYS_IOCFGX P0/ P1/ P2/ P3/ P4/

P5/ P6 pin configuration as the actively data uploads.

Can use communicating methods to configure UART

baud rate.

17 AUTO_BAUD R/W 0 0: When UART communicates, baud rate is the same

as last time serial communication. The baud rate when

SPI communication is 4800.

1: When UART communicates, baud rate is as much

again of last time serial communication. The baud rate

when SPI communication is 9600.

To enable the active power accumulating data uploads.

16 AUTO_TX_EN R/W 0 0: disable

1: enable

To enable the low-speed energy accumulator and CF

counter. The accumulating speed of low-speed energy

15 EGY_LC_EN R/W 0 accumulator is 50 Hz.

0: disable

1: enable.

To control the CF2 polarity.

14 CF2_INV R/W 0 0: original polarity

1: reverse polarity

To Enable the CF2 output.

13 CF2_EN R/W 0 0: disable

1: enable.

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0x03, R/W, Metering Control Register 2, DSP_CTRL1

Bit R/W Default Value Description

To select the input source of CF2.

12 CF2_SEL R/W 0 0: from the energy accumulator 1

1: from the energy accumulator 2

The bit must hold its default value for proper

11 Reserved 0
operation.

To control CF1 polarity.

10 CF1_INV R/W 0 0: original polarity

1: reverse polarity

To enable CF1 output.

9 CF1_EN R/W 0 0: disable CF1 output

1: enable CF1 output

To select the input source of CF1.

8 CF1_SEL R/W 0 0: from the energy accumulator 1

1: from the energy accumulator 2

To enable the energy accumulator 2 and CF2 counter.

The accumulating speed of energy accumulator 2 is

7 CALCEN2 R/W 0 204.8 KHz.

0: disable

1: enable.

To enable the energy accumulator 1 and CF1 counter.

The accumulating speed of energy accumulator 1 is

6 CALCEN1 R/W 0 204.8 KHz.

0: disable

1: enable

To select the CF pulse width

0: 80 ms

5:4 CF_PULSE R/W 0 1: 40 ms

2: 20 ms

3: 10 ms

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0x03, R/W, Metering Control Register 2, DSP_CTRL1

Bit R/W Default Value Description

CF pulse speed up output.

0: Normal mode

3:2 CF_FAST_EN R/W 0 1: 4x faster

2: 8x faster

3: 16x faster

To determine the power of power-creep. The power-

creep determination uses continuous 3 average and

threshold compare. If lower the threshold, then here

1 PWR_CRP_EN R/W 0
will be the power-creep status.

0: disable the power-creep detection

1: enable the power-creep detection

To enable the High-speed energy accumulator.

0 CRP_EN R/W 0 0: disable the power-creep detection

1: enable the power-creep detection

2.4.3. DSP_CTRL2 Register

Table 2-20 Metering Control Register 2 (0x04, DSP_CTRL2)

0x04, R/W, Metering Control Register 2, DSP_CTRL2

Bit R/W Default Value Description

The energy accumulator 4 accumulating mode.

0: power accumulation

1: current RMS accumulation

31:30 INMODE4 R/W 0
2: constant accumulation

3: configurable fundamental-wave channel

accumulation

29 A_SEL4 R/W 0 To enable the energy accumulator 4, channel A

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0x04, R/W, Metering Control Register 2, DSP_CTRL2

Bit R/W Default Value Description

accumulating.

0: disable

1: enable

To enable the energy accumulator 4, channel B

accumulating.
28 B_SEL4 R/W 0
0: disable

1: enable

The energy accumulator 4, multiple channel

accumulating mode choice.

When power accumulating,

0, 3: active power accumulation

27:26 TYPE_SEL4 R/W 0 1: reactive power accumulation

2: apparent power accumulation

When RMS accumulating, high bit zero represents

accumulating sum;

High bit one represents accumulating difference.

For each signal type choices which feed into the energy

accumulator 4.

0: the positive value of the energy accumulator adding

1: the negative value of the energy accumulator adding

25:24 PROCMODE4 R/W 0
(Here the actual accumulating value is the positive

which exchanged from the original value.)

2: the original value of the energy accumulator adding

3: the absolute value of the energy accumulator adding

The energy accumulator 3 accumulation mode

0: power accumulation

23:22 INMODE3 R/W 0 1: current RMS accumulation

2: constant accumulation

3: configurable the fundamental wave channel

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0x04, R/W, Metering Control Register 2, DSP_CTRL2

Bit R/W Default Value Description

accumulation

To enable the energy accumulator 3, channel A

accumulating.
21 A_SEL3 R/W 0
0: disable;

1: enable

To enable the energy accumulator 3, channel B

accumulating.
20 B_SEL3 R/W 0
0: disable

1: enable

The energy accumulator 3, multiple channel

accumulating mode choice.

When power accumulating,

0, 3: active power accumulation

19:18 TYPE_SEL3 R/W 0 1: reactive power accumulation

2: apparent power accumulation

When RMS accumulating,

High bit zero represents accumulating sum; high bit

one represents accumulating difference.

For each signal type choices which feed into the energy

accumulator 3.

0: the positive value of the energy accumulator adding

1: the negative value of the energy accumulator adding

17:16 PROCMODE3 R/W 0
(Here the actual accumulating value is the positive

which exchanged from the original value.)

2: the original value of the energy accumulator adding

3: the absolute value of the energy accumulator adding

The energy accumulator 2 accumulating mode.

15:14 INMODE2 R/W 0 0: power accumulation

1: current RMS accumulation

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0x04, R/W, Metering Control Register 2, DSP_CTRL2

Bit R/W Default Value Description

2: constant accumulation

3: configurable the fundamental wave channel

accumulation

To enable the energy accumulator 2, channel A

accumulating.
13 A_SEL2 R/W 0
0: disable

1: enable

To enable the energy accumulator 2, channel B

accumulating.
12 B_SEL2 R/W 0
0: disable

1: enable

The energy accumulator 2, multiple channel

accumulating mode choice.

When power accumulating,

0, 3: active power accumulation

11:10 TYPE_SEL2 R/W 1: reactive power accumulation

2: apparent power accumulation

When RMS accumulating,

High bit zero represents accumulating sum; high bit

one represents accumulating difference.

For each signal type choices which feed into the energy

accumulator 2.

0: the positive value of the energy accumulator adding

1: the negative value of the energy accumulator adding

9:8 PROCMODE2 R/W 0
(Here the actual accumulating value is the positive

which exchanged from the original value.)

2: the original value of the energy accumulator adding

3: the absolute value of the energy accumulator adding

7:6 INMODE1 R/W 0 The energy accumulator 1 accumulating mode.

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0x04, R/W, Metering Control Register 2, DSP_CTRL2

Bit R/W Default Value Description

0: power accumulation

1: current RMS accumulation

2: constant accumulation

3: configurable the fundamental wave channel

accumulation

To enable the energy accumulator 1, channel A

accumulating.
5 A_SEL1 R/W 0
0: disable

1: enable

To enable the energy accumulator 1, channel B

accumulating.
4 B_SEL1 R/W 0
0: disable

1: enable

Multiple channel accumulating mode choice.

When power accumulating,

0, 3: active power accumulation

1: reactive power accumulation

3:2 TYPE_SEL1 R/W 0
2: apparent power accumulation

When RMS accumulating,

High bit zero represents accumulating sum; high bit one

represents accumulating difference.

For each signal type choices which feed into the energy

accumulator 1.

0: the positive value of the energy accumulator adding

1: the negative value of the energy accumulator adding

1:0 PROCMODE1 R/W 0
(Here the actual accumulating value is the positive

which exchanged from the original value.)

2: the original value of the energy accumulator adding

3: the absolute value of the energy accumulator adding

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2.4.4. DSP_CTRL3 Register

Table 2-21 Metering Control Register 3 (0x05, DSP_CTRL3)

0x05, R/W, Metering Control Register 3, DSP_CTRL3

Bit R/W Default Value Description

The energy accumulator 8 accumulating mode.

0: power accumulation

1: current RMS accumulation

31:30 INMODE8 R/W 0
2: constant accumulation

3: configurable the fundamental wave channel

accumulation

To enable the energy accumulator 8, channel A

accumulating.
29 A_SEL8 R/W 0
0: disable

1: enable

To enable the energy accumulator 8, channel B

accumulating.
28 B_SEL8 R/W 0
0: disable

1: enable

The energy accumulator 8, multiple channel

accumulating mode choice.

When power accumulating,

0, 3: active power accumulation

27:26 TYPE_SEL8 R/W 0 1: reactive power accumulation

2: apparent power accumulation

When RMS accumulating,

High bit zero represents accumulating sum; high bit one

represents accumulating difference.

For each signal type choices which feed into the energy

25:24 PROCMODE8 R/W 0 accumulator 8.

0: the positive value of the energy accumulator adding

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0x05, R/W, Metering Control Register 3, DSP_CTRL3

Bit R/W Default Value Description

1: the negative value of the energy accumulator adding

(Here the actual accumulating value is the positive

which exchanged from the original value.)

2: the original value of the energy accumulator adding

3: the absolute value of the energy accumulator adding

The energy accumulator 7 accumulating mode

0: power accumulation

1: current RMS accumulation

23:22 INMODE7 R/W 0
2: constant accumulation

3: configurable the fundamental wave channel

accumulation

To enable the energy accumulator 7, channel A

accumulating
21 A_SEL7 R/W 0
0: disable

1: enable

To enable the energy accumulator 7, channel B

accumulating
20 B_SEL7 R/W 0
0: disable

1: enable

The energy accumulator 7, multiple channel

accumulating mode choice.

When power accumulating,

0, 3: active power accumulation

19:18 TYPE_SEL7 R/W 0 1: reactive power accumulation

2: apparent power accumulation

When RMS accumulating,

High bit zero represents accumulating sum; high bit

one represents accumulating difference.

17:16 PROCMODE7 R/W 0 For each signal type choices which feed into the energy

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0x05, R/W, Metering Control Register 3, DSP_CTRL3

Bit R/W Default Value Description

accumulator 7.

0: the positive value of the energy accumulator adding

1: the negative value of the energy accumulator adding

(Here the actual accumulating value is the positive

which exchanged from the original value.)

2: the original value of the energy accumulator adding

3: the absolute value of the energy accumulator adding

The energy accumulator 6 accumulating mode.

0: power accumulation

1: current RMS accumulation

15:14 INMODE6 R/W 0
2: constant accumulation

3: configurable the fundamental wave channel

accumulation

To enable the energy accumulator 6, channel A

accumulating.
13 A_SEL6 R/W 0
0: disable

1: enable

To enable the energy accumulator 6, channel B

accumulating.
12 B_SEL6 R/W 0
0: disable

1: enable

The energy accumulator 6, multiple channel

accumulating mode choice.

When power accumulating,

0, 3: active power accumulation

11:10 TYPE_SEL6 R/W
1: reactive power accumulation

2: apparent power accumulation

When RMS accumulating,

High bit zero represents accumulating sum; high bit one

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0x05, R/W, Metering Control Register 3, DSP_CTRL3

Bit R/W Default Value Description

represents accumulating difference.

For each signal type choices which feed into the energy

accumulator 6.

0: the positive value of the energy accumulator adding

1: the negative value of the energy accumulator adding

9:8 PROCMODE6 R/W 0
(Here the actual accumulating value is the positive

which exchanged from the original value.)

2: the original value of the energy accumulator adding

3: the absolute value of the energy accumulator adding

The energy accumulator 5 accumulating mode.

0: power accumulation

1: current RMS accumulation

7:6 INMODE5 R/W 0
2: constant accumulation

3: configurable the fundamental wave channel

accumulation

To enable the energy accumulator 5, channel A

accumulating.
5 A_SEL5 R/W 0
0: disable

1: enable

To enable the energy accumulator 5, channel B

accumulating.
4 B_SEL5 R/W 0
0: disable

1: enable

The energy accumulator 5, multiple channel

accumulating mode choice.

When power accumulating,

3:2 TYPE_SEL5 R/W 0
0, 3: active power accumulation

1: reactive power accumulation

2: apparent power accumulation

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0x05, R/W, Metering Control Register 3, DSP_CTRL3

Bit R/W Default Value Description

When RMS accumulating,

High bit zero represents accumulating sum; high bit

one represents accumulating difference.

For each signal type choices which feed into the energy

accumulator 5.

0: the positive value of the energy accumulator adding

1: the negative value of the energy accumulator adding

1:0 PROCMODE5 R/W 0
(Here the actual accumulating value is the positive

which exchanged from the original value.)

2: the original value of the energy accumulator adding

3: the absolute value of the energy accumulator adding

2.4.5. DSP_CTRL4 Register

Table 2-22 Metering Control Register 4 (0x06, DSP_CTRL4)

0x06, R/W, Metering Control Register 4, DSP_CTRL4

Bit R/W Default Value Description

31:30 IPERIOD R/W 0 To select the detection time of over-current or under-

current. When the number of sampling points of over-

current or under-current in the sampling points during the

half-cycle is greater than or equal to the ITH value, it will

be considered as the effective half-cycle. If the number of

consecutive effective half-cycle reaches the value set by

IPERIOD, it will be considered as this event happened.

0: half cycle

1: 1 cycle

2: 2 cycles

3: 4 cycles

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0x06, R/W, Metering Control Register 4, DSP_CTRL4

Bit R/W Default Value Description

29:24 ITH R/W 0 To determine the threshold of half-cycle is effective half-

cycle.

0: 1 time

1: 2 times

63: 64 times

23:22 UPERIOD R/W 0 The same as IPERIOD configurable conditions.

0: half cycle

1: 1 cycle

2: 2 cycles

3: 4 cycles

21:16 UTH R/W 0 The same as ITH configurable conditions.

0: 1 time

1: 2 times

63: 64 times

15:10 Reserved These bits must hold its default value for proper operation.

9 IBLCSEL R/W 0 IB under- current test source.

0: no pass IB wave data of high pass filter

1: pass IB wave data of high pass filter

8 IBOCSEL R/W 0 IB: over-current test source.

0: no pass IB wave data of high pass filter

1: pass IB wave data of high pass filter

7 IALCSEL R/W 0 IA under-current test source.

0: no pass IA wave data of high pass filter

1: pass IA wave data of high pass filter

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0x06, R/W, Metering Control Register 4, DSP_CTRL4

Bit R/W Default Value Description

6 IAOCSEL R/W 0 IA over-current test source.

0: no pass IA wave data of high pass filter

1: pass IA wave data of high pass filter

5 ULVSEL R/W 0 Channel U under-voltage test source.

0: no pass channel U wave data of high pass filter

1: pass channel U wave data of high pass filter

4 UOVSEL R/W 0 Channel U over-voltage test source.

0: no pass channel U wave data of high pass filter

1: pass channel U wave data of high pass filter

3 Reserved 0 The bit must hold its default value for proper operation.

2 FDIBEN R/W 0 To enable the fast detection for IB.

0: disable IB over or under current test

1: enable IB over or under current test

1 FDIAEN R/W 0 To enable the fast detection for IA.

0: disable IA over or under current test

1: enable IA over or under current test

0 FDUEN R/W 0 To enable the fast detection.

0: disable channel U over or under voltage test

1: enable channel U over or under voltage test

2.4.6. DSP_CTRL5 Register

Table 2-23 Metering Control Register 5 (0x07, DSP_CTRL5)

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0x07, R/W, Metering Control Register 5, DSP_CTRL5

Bit R/W Default Value Description

Reset reading the address of waveform storage,

31 WAVE_ADDR_CLR R/W 0
write 1 to reset.

The operating mode of waveform storage:

30:29 WAVE_MEM_MODE R/W 0
0: storage by manual, full then stop. This time is

the single storage.

1: storage by manual, trigger or manual stop.

This time is the cyclic storage.

2: storage by trigger, full then stop. This time is

the single storage.

3: disable

Waveform storage to trigger manual switch:

28 WAVE_MEM_EN R/W 0
write 1 = enable, write 0 = disable

19:16 WAVE_LENGTH R/W 0
channel.

0: 1 cycle

1: 2 cycles

2: 3 cycles

……

15: 16 cycles

The bit must hold its default value for proper

15 Reserved - -
operation.

Voltage waveform whether pass high-pass filter

14 WAVE_U_HPF_SEL R/W 0
choice:

0: no pass high-pass filter

1: pass high-pass filter

Current IA waveform whether pass high-pass

13 WAVE_IA_HPF_SEL R/W 0
filter choice:

0: no pass high-pass filter

1: pass high-pass filter

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0x07, R/W, Metering Control Register 5, DSP_CTRL5

Bit R/W Default Value Description

Current IB waveform whether pass high-pass

12 WAVE_IB_HPF_SEL R/W 0
filter choice:

0: no pass high-pass filter

1: pass high-pass filter

The bit must hold its default value for proper

11 Reserved - -
operation.

To enable the waveform storage and DMA of

10 WAVE_U_SEL R/W 0
channel U. The bit decides whether storage or

transmit data of channel U:

0: no

1: yes

To Enable the waveform storage and DMA of

9 WAVE_IA_SEL R/W 0
channel IA. The bit decides whether storage or

transmit data of channel IA:

0: no

1: yes

To enable the waveform storage and DMA of

8 WAVE_IB_SEL R/W 0
channel IB. The bit decides whether storage or

transmit data of channel IB (If waveform storage

and configure bit 8, bit 9, and bit 10 enable at

the same time, the bit becomes invalid):

0: no

1: yes

DMA mode parity check choice:

7 SP_CHECK R/W 0
0: odd parity

1: even parity

DMA mode polarity choice:

6 SPI_POL R/W 0
0: negative

1: positive

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0x07, R/W, Metering Control Register 5, DSP_CTRL5

Bit R/W Default Value Description

DMA mode phase choice:

5 SPI_PHA R/W 0
0: negative

1: positive

DMA channel choice:

4:3 DMA_MANUALCTRL R/W 0
0: disable

1: enable by manual

2: stop by manual

3: reserved

DMA channel operating mode:

2:0 DMA_MODE R/W 0
0: transmit starting by manual, until maximum

cycle then stops.

1: transmit starting by manual, trigger or by

manual stop.

2: trigger starting, stop by manual.

3: trigger starting, until maximum cycle then

stops.

4~7: transmit by manual, stop by manual.

Before enabling DMA transmission, at least one

channel of waveform storage and upload must

be opened.

2.5. Metering Data Register

When power-on reset (POR), RSTN pin reset, RX reset, or global software reset occurs, all metering

control registers will be reset to the default value.

2.5.1. DC Component Register

Table 2-24 DC Component Register

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Address Register R/W Data Format Description

32-bit DC value of voltage

0x22 DSP_DAT_DCU R
Complement Code channel. By default, the

32-bit DC value of current updating time is 40

0x23 DSP_DAT_DCI R
Complement Code channel A. ms; stable time is

120 ms.
32-bit DC value of Current
0x24 DSP_DAT_DCIB R
Complement Code channel B.

2.5.2. RMS Register

Table 2-25 Voltage/ Current/ Measurement Signal (M) RMS Register

Address Register R/W Data Format Description

32-bit Instantaneous
0x0E DSP_DAT_RMS0U R
Complement Code RMS of voltage.
By default, the
32-bit Instantaneous
0x0F DSP_DAT_RMS0IA R updating time is 10
Complement Code RMS of current A.
ms; stable time is
Instantaneous 30 ms.
32-bit
0x10 DSP_DAT_RMS0IB R RMS of current
Complement Code
B.

32-bit Average RMS of

0x19 DSP_DAT_RMS1U R
voltage. Under the default
Complement Code
state, the updating
32-bit Average RMS of
0x1A DSP_DAT_RMS1IA R time is 40 ms;
Complement Code Current A.
stable time is 120

32-bit Average RMS of ms.

0x1B DSP_DAT_RMS1IB R
Complement Code Current B.

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Address Register R/W Data Format Description

Average RMS of

Voltage for 10 or
32-bit
0x1E DSP_DAT_RMSU_AVG R 12 cycles (chose
Complement Code
by line

frequency.)

Average RMS of

Current IA for 10
32-bit
0x1F DSP_DAT_RMSIA_AVG R or 12 cycles
Complement Code
(chose by line

frequency.)

Average RMS of

Current IB for 10
32-bit
0x20 DSP_DAT_RMSIB_AVG R or 12 cycles
Complement Code
(chose by line

frequency.)

2.5.3. Active/ Reactive Power Register

Table 2-26 Active/ Reactive Power Register

Address Register R/W Data Format Description

32-bit Instantaneous Active

0x08 DSP_DAT_PA R
Complement Code Power of channel A.

32-bit Instantaneous Reactive By default, the

0x09 DSP_DAT_QA R
Complement Code Power of channel A. updating time is

Instantaneous Apparent 20 ms; stable

32-bit
0x0A DSP_DAT_SA R
Power of channel A. time is 60 ms.
Complement Code

32-bit Instantaneous Active

0x0B DSP_DAT_PB R
Complement Code Power of channel B.

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Address Register R/W Data Format Description

32-bit Instantaneous Reactive

0x0C DSP_DAT_QB R
Complement Code Power of channel B.

32-bit Instantaneous Apparent

0x0D DSP_DAT_SB R
Complement Code Power of channel B.

32-bit Average Active power of

0x13 DSP_DAT_PA1 R
Complement Code Channel A.

32-bit Average Reactive power

0x14 DSP_DAT_QA1 R
Complement Code of Channel A.

32-bit Average Apparent Power By default, the

0x15 DSP_DAT_SA1 R
Complement Code of Channel A. updating time is

Average Active power of 80 ms; stable

32-bit
0x16 DSP_DAT_PB1 R
Channel B. time is 240 ms.
Complement Code

32-bit Average Reactive power

0x17 DSP_DAT_QB1 R
Complement Code of Channel B.

32-bit Average Apparent Power

0x18 DSP_DAT_SB1 R
Complement Code of Channel B.

2.5.4. Fundamental Wave Channel Register

Table 2-27 Fundamental Wave Channel Instantaneous Register

Address Register R/W Data Format Description

32-bit Instantaneous value of Fundamental wave

0x11 DSP_DAT_CH1 R
Complement Code of Channel 1.

32-bit Instantaneous value of Fundamental wave

0x12 DSP_DAT_CH2 R
Complement Code of Channel 2.

Table 2-28 Fundamental Wave Channel Average Register

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Address Register R/W Data Format Description

32-bit Complement Average value of Fundamental wave of

0x1C DSP_DAT_CH1_AVG R
Code Channel 1.

32-bit Complement Average value of Fundamental wave of

0x1D DSP_DAT_CH2_AVG R
Code Channel 2.

2.5.5. Line Frequency Register

Table 2-29 Line Frequency Register (0x21, DSP_DAT_FRQ)

Address Register R/W Data Format Description

Line frequency is related to FRQ_SEL.

32-bit
0x21 DSP_DAT_FRQ R By default, the updating time is 320 ms;
Complement Code
stable time is 640 ms.

2.6. Energy Accumulator Register

Table 2-30 Energy Accumulator Register

Address Register R/W Data Format Description

Anti-creep threshold for energy accumulator.

When the accumulated value of the anti-creep

energy accumulator over this threshold and

0x39 EGY_PROCTH R 32-bit Unsigned the accumulated value of the high-speed

energy accumulator under this threshold, the

accumulated value of the high-speed energy

accumulator will be cleared.

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Address Register R/W Data Format Description

0x3A EGY_PWRTH R/W 32-bit Unsigned Accumulation threshold for energy

accumulator. Due to the energy accumulator

was 46bit, the accumulated value of the high-

speed energy accumulator equals to this

value*16384; the accumulated value of the

low-speed energy accumulator equals to this

value*4.

0x3B EGY_CONST1 R/W 32-bit Unsigned Energy accumulator 1 accumulating constant.

0x3C EGY_OUT1L R/W 32-bit Unsigned Energy accumulator 1 accumulating low bit.

0x3D EGY_OUT1H R/W 32-bit Unsigned Energy accumulator 1 accumulating high bit

Low 14bit effective.

0x3E EGY_CFCNT1 R/W 32-bit Unsigned Energy accumulator 1 pulse counter.

0x3F EGY_CONST2 R 32-bit Unsigned Energy accumulator 2 accumulating constant.

0x40 EGY_OUT2L R/W 32-bit Unsigned Energy accumulator 2 accumulating low bit.

0x41 EGY_OUT2H R/W 32-bit Unsigned Energy accumulator 2 accumulating high bit

Low 14bit effective.

0x42 EGY_CFCNT2 R/W 32-bit Unsigned Energy accumulator 2 pulse counter.

0x43 EGY_CONST3 R 32-bit Unsigned Energy accumulator 3 accumulating constant.

0x44 EGY_OUT3 R/W 32-bit Unsigned Energy accumulator 3 accumulating value.

0x45 EGY_CFCNT3 R/W 32-bit Unsigned Energy accumulator 3 pulse counter.

0x46 EGY_CONST4 R 32-bit Unsigned Energy accumulator 4 accumulating constant.

0x47 EGY_OUT4 R/W 32-bit Unsigned Energy accumulator 4 accumulating value.

0x48 EGY_CFCNT4 R/W 32-bit Unsigned Energy accumulator 4 pulse counter.

0x49 EGY_CONST5 R 32-bit Unsigned Energy accumulator 5 accumulating constant.

0x4A EGY_OUT5 R/W 32-bit Unsigned Energy accumulator 5 accumulating value.

0x4B EGY_CFCNT5 R/W 32-bit Unsigned Energy accumulator 5 pulse counter.

0x4C EGY_CONST6 R 32-bit Unsigned Energy accumulator 6 accumulating constant.

0x4D EGY_OUT6 R/W 32-bit Unsigned Energy accumulator 6 accumulating value.

0x4E EGY_CFCNT6 R/W 32-bit Unsigned Energy accumulator 6 pulse counter.

0x4F EGY_CONST7 R 32-bit Unsigned Energy accumulator 7 accumulating constant.

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Address Register R/W Data Format Description

0x50 EGY_OUT7 R/W 32-bit Unsigned Energy accumulator 7 accumulating value.

0x51 EGY_CFCNT7 R/W 32-bit Unsigned Energy accumulator 7 pulse counter.

0x52 EGY_CONST8 R 32-bit Unsigned Energy accumulator 8 accumulating constant.

0x53 EGY_OUT8 R/W 32-bit Unsigned Energy accumulator 8 accumulating value.

0x54 EGY_CFCNT8 R/W 32-bit Unsigned Energy accumulator 8 pulse counter.

2.7. Phase Measurement Register

Table 2-31 Phase Measurement Register

Address Register R/W Data Format Description

To control the phase measurement.

0x61 DSP_PHS_STT R/W 32-bit Unsigned Enable phase measurement once for

writing operation.

0x62 DSP_PHS_U R 32-bit Unsigned Voltage Phase Value.

The waveform data before voltage zero-

0x63 DSP_PHS_UN R 32-bit Unsigned
crossing.

The waveform data after voltage zero-

0x64 DSP_PHS_UP R 32-bit Unsigned
crossing.

0x65 DSP_PHS_I R 32-bit Unsigned Current Phase Value.

The waveform data before current zero-

0x66 DSP_PHS_IN R 32-bit Unsigned
crossing.

The waveform data after current zero-

0x67 DSP_PHS_IP R 32-bit Unsigned
crossing.

2.8. Power-creep Threshold Register

Table 2-32 Power-creep Threshold Register

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Address Register R/W Data Format Description

To set the lower threshold for the power creep

32-bit detection for instantaneous active power/

0x55 DSP_OV_THL R/W
Complement Code reactive power/ apparent power of channel A

and B.

To set the upper threshold for the power creep

32-bit detection for instantaneous active power/

0x56 DSP_OV_THH R/W
Complement Code reactive power/ apparent power of channel A

and B.

2.9. Voltage Swell or Dip Threshold Register

Table 2-33 Voltage Swell or Dip Threshold Register

Address Register R/W Data Format Description

32-bit Complement To set the lower threshold for the voltage

0x57 DSP_SWELL_THL R/W
Code swell.

32-bit Complement To set the upper threshold for the voltage

0x58 DSP_SWELL_THH R/W
Code swell.

32-bit Complement To set the lower threshold for the voltage

0x59 DSP_DIP_THL R/W
Code dip.

32-bit Complement To set the upper threshold for the voltage

0x5A DSP_DIP_THH R/W
Code dip.

Times records of voltage swell, half wave as

32-bit Complement
0x6A DAT_SWELL_CNT R/C a unit. 24bit effective. When write in any
Code
value, can clear zero the counter value.

Times records of voltage dip, half wave as a

32-bit Complement
0x6B DAT_DIP_CNT R/C unit. 24bit effective. When write in any
Code
value, can clear zero the counter value.

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2.10. Fast Detection Threshold Register

Table 2-34 Fast detection Threshold Register

Address Register R/W Data Format Description

30-bit Complement To set over-voltage threshold for fast

0x5B FD_OVTH R/W
Code detection. Bit width is 30bit.

30-bit Complement To set under-voltage threshold for fast

0x5C FD_LVTH R/W
Code detection. Bit width is 30bit.

30-bit Complement To set over-current threshold in channel A for

0x5D FD_IA_OCTH R/W
Code fast detection. Bit width is 30bit.

30-bit Complement To set under-current threshold in channel A for

0x5E FD_IA_LCTH R/W
Code fast detection. Bit width is 30bit.

30-bit Complement To set over-current threshold in channel B for

0x5F FD_IB_OCTH R/W
Code fast detection. Bit width is 30bit.

30-bit Complement To set under-current threshold in channel B for

0x60 FD_IB_LCTH R/W
Code fast detection. Bit width is 30bit.

2.11. Waveform Data Register

Table 2-35 Waveform Data Register

Address Register R/W Data Format Description

Waveform reading. It can repeatable reading the

address and obtain the overall wave data. If there

32-bit Complement
0x69 DAT_WAVE R is no need to read all data, it would be reset the
Code
bit 31 of metering control register (0x07,

DSP_CTRL5) to read address.

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2.12. Calibration Register

When power-on reset (POR), RSTN pin reset, RX reset, or global software reset occurs, all calibration

registers will be reset to the default value. The default value in the following tables of this section are in

format of hexadecimal.

All the calibration registers need to be configuration verification and self-checking.

2.12.1. DC Bias Setting Register

Table 2-36 DC Bias Setting Register

Default
Address Register R/W Format Value Description
Value

32-bit Complement To set the DC compensation for the

0x34 DSP_CFG_DCU 0 R/W
Code voltage channel.

32-bit Complement To set the DC compensation for the

0x35 DSP_CFG_DCIA 0 R/W
Code current channel A.

32-bit Complement To set the DC compensation for the

0x36 DSP_CFG_DCIB 0 R/W
Code current channel B.

All registers for calibration need to be configuration verification and self-checking.

2.12.2. RMS Calibration Register

Table 2-37 Voltage/ Current/ Measurement RMS Calibration Register

Default
Address Register R/W Data Format Description
Value

32-bit Complement To set gain calibration for

0x2D DSP_CFG_CALI_RMSU 0 R/W
Code Voltage RMS.

32-bit Complement To set offset calibration for

0x2E DSP_CFG_RMS_DCU 0 R/W
Code Voltage RMS.

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Default
Address Register R/W Data Format Description
Value

32-bit Complement To set gain calibration for

0x2F DSP_CFG_CALI_RMSIA 0 R/W
Code Current RMS A.

32-bit Complement To set offset calibration for

0x30 DSP_CFG_RMS_DCIA 0 R/W
Code Current RMS A.

32-bit Complement To set gain calibration for

0x31 DSP_CFG_CALI_RMSIB 0 R/W
Code Current RMS B.

32-bit Complement To set offset calibration for

0x32 DSP_CFG_RMS_DCIB 0 R/W
Code Current RMS.

2.12.3. Power Calibration Register

Table 2-38 Total-wave Active/ Reactive Power Calibration Register

Default
Address Register R/W Data Format Description
Value

32-bit Complement To set gain calibration for the

0x25 DSP_CFG_CALI_PA 0 R/W
Code active power A.

32-bit Complement To set offset calibration for the

0x26 DSP_CFG_DC_PA 0 R/W
Code active power A.

32-bit Complement To set gain calibration for

0x27 DSP_CFG_CALI_QA 0 R/W
Code Reactive power A.

32-bit Complement To set offset calibration for

0x28 DSP_CFG_DC_QA 0 R/W
Code Reactive power A.

32-bit Complement To set gain calibration for Active

0x29 DSP_CFG_CALI_PB 0 R/W
Code power B.

32-bit Complement To set offset calibration for Active

0x2A DSP_CFG_DC_PB 0 R/W
Code power B.

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Default
Address Register R/W Data Format Description
Value

32-bit Complement To set gain calibration for

0x2B DSP_CFG_CALI_QB 0 R/W
Code Reactive power B.

32-bit Complement To set offset calibration for

0x2C DSP_CFG_DC_QB 0 R/W
Code Reactive power B.

2.12.4. Threshold Register

Table 2-39 Threshold Register

Default
Address Register R/W Data Format Description
Value

Energy accumulator anti-creep

threshold. When anti-creep energy

accumulator exceeds the EGY_CRPTH

and high-speed energy accumulator

not exceeds the EGY_PWRTH, the

accumulating value of high-speed

accumulator will be cleared.

Metering chip has a power-creep

32-bit Complement energy accumulating register for

0x39 EGY_PROCTH 0 R/W
Code energy accumulator 1 and 2

respectively, and they have the same

accumulation speed. After enabling

the power-creep detection in the

energy accumulator, the input would

be fixed to 1 in this power-creep

energy accumulator.

User should configure threshold for

the power-creep detection register

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Default
Address Register R/W Data Format Description
Value

(EGY_CRPTH) and energy

accumulating threshold register

(EGY_PWRTH). If the accumulating

value of power-creep energy

accumulator register reaches the

value of EGY_CRPTH first, the energy

accumulating register will be cleared,

and system enter the power-creep

status. When the accumulating value

of energy accumulating register

reaches the value of EGY_PWRTH

first, the power-creep energy register

will be cleared, system starts to work

and operates normally.

The actual bit width of register

EGY_CRPTH is 32bit. The register

contents will be padded with 0s

automatically in the 4 least significant

bits when the power-creep calculated.

It would be calculated after extended

to 36 digits.

Accumulation threshold for energy

accumulator. Due to the energy

accumulator was 46bit, the

32-bit Complement accumulated value of the high-speed

0x3A EGY_PWRTH 0 R/W
Code energy accumulator equals to this

value*16384; the accumulated value

of the low-speed energy accumulator

equals to this value*4.

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Default
Address Register R/W Data Format Description
Value

32-bit Complement To set the lower threshold for the

0x55 DSP_OV_THL 0 R/W
Code power-creep determination.

32-bit Complement To set the upper threshold for the

0x56 DSP_OV_THH 0 R/W
Code power-creep determination.

2.12.5. Phase Calibration Register

Table 2-40 Phase Calibration Register (0x33, DSP_CFG_PHC)

Default
Address Register R/W Data Format Description
Value

Phase Error Calibration Register. The

register needs to be configuration

verification and self-checking.

32-bit [10:0]= phase error calibration value

0x33 DSP_CFG_PHC 0 R/W
Complement Code for channel A;

[26:16]= phase error calibration

value for channel B;

Where the range is from -766 to 767.

2.12.6. Bandpass Filter Register

Table 2-41 Bandpass Filter Register (0x37, DSP_CFG_BPF)

Default Data
Address Register R/W Description
Value Format

32-bit Band-pass filter coefficient. Related to

0x37 DSP_CFG_BPF 0 R/W Complement setting the DSP_MODE by Bit[7:4] of

Code metering control register 0

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Default Data
Address Register R/W Description
Value Format

(0x02,DSP_CTRL0)

Setting 0x806764B6 at DSP_MODE=0, 1,

Setting 0x80DD7A8C at DSP_MODE=6, 7;

Setting 0x82B465F0 at DSP_MODE=8.

The frequency of other modes would be not

supported to measure, so setting to 0x0.

2.13. Checksum Register

Table 2-42 Checksum Register (0x38, DSP_CFG_CKSUM)

Default
Address Register R/W Data Format Description
Value

This register needs to participate in

parameter configuration self-check. This

register participates in parameter

configuration self-check along with the

addresses 0x0 ~ 0x7, 0x25 ~ 0x3A,

0x55 ~ 0x60. If all the above register

32-bit
values add up to 0xFFFFFFFF, the
0x28 DSP_CFG_CKSUM 0 R/W Complement
parameter configuration self-check
Code
passes.

To ensure parameter configuration self-

check successful, the register should

write correct value (0xFFFFFFFF - the

sum of the configuration values of other

registers participating in the check).

Table 2-43 Self-checking Register

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V93XX Datasheet
Name Type Address Description Default

ANA_CTRL0 R/W 0x00 Analog Control Register 0. 0x00000000

ANA_CTRL1 R/W 0X01 Analog Control Register 1. 0x00000000

DSP_CTRL0 R/W 0x02 Metering Control Register 0. 0x00000000

DSP_CTRL1 R/W 0x03 Metering Control Register 1. 0x00000000

DSP_CTRL2 R/W 0x04 Metering Control Register 2. 0x00000000

DSP_CTRL3 R/W 0x05 Metering Control Register 3. 0x00000000

DSP_CTRL4 R/W 0x06 Metering Control Register 4. 0x00000000

DSP_CTRL5 R/W 0x07 Metering Control Register 5. 0x00000000

To set gain calibration for the active power

DSP_CFG_CALI_PA R/W 0x25 0x00000000
A.

To set offset calibration for the active

DSP_CFG_DC_PA R/W 0x26 0x00000000
power A.

To set gain calibration for Reactive power

DSP_CFG_CALI_QA R/W 0x27 0x00000000
A.

To set offset calibration for Reactive power

DSP_CFG_DC_QA R/W 0x28 0x00000000
A.

DSP_CFG_CALI_PB R/W 0x29 To set gain calibration for Active power B. 0x00000000

DSP_CFG_DC_PB R/W 0x2A To set offset calibration for Active power B. 0x00000000

DSP_CFG_CALI_QB R/W 0x2B To set gain calibration for Reactive power B. 0x00000000

To set offset calibration for Reactive power

DSP_CFG_DC_QB R/W 0x2C 0x00000000
B.

DSP_CFG_CALI_RMSU R/W 0x2D To set gain calibration for Voltage RMS. 0x00000000

DSP_CFG_RMS_DCU R/W 0x2E To set offset calibration for Voltage RMS. 0x00000000

DSP_CFG_CALI_RMSIA R/W 0x2F To set gain calibration for Current RMS A. 0x00000000

DSP_CFG_RMS_DCIA R/W 0x30 To set offset calibration for Current RMS A. 0x00000000

DSP_CFG_CALI_RMSIB R/W 0x31 To set gain calibration for Current RMS B. 0x00000000

DSP_CFG_RMS_DCIB R/W 0x32 To set offset calibration for Current RMS. 0x00000000

Phase Error Calibration Registers.

DSP_CFG_PHC R/W 0x33 [10:0]= phase error calibration value for 0x0000000

channel A

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V93XX Datasheet
[26:16]= phase error calibration value for

channel B.

Where the range is from -766 to 767.

To set the DC compensation for the voltage

DSP_CFG_DCU R/W 0x34 0x00000000
channel.

To set the DC compensation for the current

DSP_CFG_DCIA R/W 0x35 0x00000000
channel A.

To set the DC compensation for the current

DSP_CFG_DCIB R/W 0x36 0x00000000
channel B.

Band-pass filter coefficient. Related to

setting the DSP_MODE by Bit[7:4] of

metering control register 0

(0x02,DSP_CTRL0).

DSP_CFG_BPF R/W 0x37 Setting 0x806764B6 at DSP_MODE=0,1,2; 0x00000000

setting 0x80DD7A8C at DSP_MODE=6,7;

setting 0x82B465F0 at DSP_MODE=8.

The frequency of other modes would be not

supported to measure, so setting to 0x0.

DSP_CFG_CKSUM R/W 0x38 Configuration register for checksum. 0x00000000

Anti-creep threshold for energy

accumulator. When the accumulated value

of the anti-creep energy accumulator over

this threshold and the accumulated value of

EGY_PROCTH R/W 0x39 0x00000000
the high-speed energy accumulator under

this threshold, the accumulated value of

the high-speed energy accumulator will be

cleared.

Accumulation threshold for energy

accumulator. Due to the energy

EGY_PWRTH R/W 0x3A accumulator was 46bit, the accumulated 0x00000000

value of the high-speed energy

accumulator equals to this value*16384;

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V93XX Datasheet
the accumulated value of the low-speed

energy accumulator equals to this value*4.

To set the lower threshold for the no-load

DSP_OV_THL R/W 0x55 0x00000000
determination.

To set the upper threshold for the no-load

DSP_OV_THH R/W 0x56 0x00000000
determination.

To set the lower threshold for the voltage

DSP_SWELL_THL R/W 0x57 0x00000000
dip.

To set the upper threshold for the voltage

DSP_SWELL_THH R/W 0x58 0x00000000
swell.

To set the lower threshold for the voltage

DSP_DIP_THL R/W 0x59 0x00000000
dip.

To set the upper threshold for the voltage

DSP_DIP_THH R/W 0x5A 0x00000000
swell.

To set over-voltage threshold for fast

FD_OVTH R/W 0x5B 0x00000000
detection. Bit width is 30bit.

To set under-voltage threshold for fast

FD_LVTH R/W 0x5C 0x00000000
detection. Bit width is 30bit.

To set over-current threshold in channel A

FD_IA_OCTH R/W 0x5D 0x00000000
for fast detection. Bit width is 30bit.

To set under-current threshold in channel A

FD_IA_LCTH R/W 0x5E 0x00000000
for fast detection. Bit width is 30bit.

To set over-current threshold in channel B

FD_IB_OCTH R/W 0x5F 0x00000000
for fast detection. Bit width is 30bit.

To set under-current threshold in channel B

FD_IB_LCTH R/W 0x60 0x00000000
for fast detection. Bit width is 30bit.

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V93XX Datasheet
3. Main Power Supply

Features of V93XX main power system as below:

• 3.3V single main power supply, the voltage input range: 2.6~3.6V

• The power supply of the internal digital circuit comes from the Digital main power circuit

(DVCCLDO)

• The power supply of the oscillator circuit comes from 3.3V main power

• Supporting power down detection

• Controllable CF detection of power down alarm

Ana log
Oscil lat or
circu its

VDD
0.1 μF
Po wer sup ply
PO R
mon it or mon it or

mon it or

DVCCL DO DVCC

Dig ita l circu its

4.7 μF 0.1 μF

Figure 3-1 Main Power System

3.1. Power Supply Monitoring Circuit

V93XX integrates an internal power-down detection circuit to supervise the voltage on pin “VDD” all the

time. When the voltage on the pin “VDD” is lower than 2.8V (±7%), the power-down interrupt would be

generated. The power supply monitoring circuit is always on work.

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V93XX Datasheet

VDD

2.8V(±7%)

PDN flag

CLR operat ion

INTPDN flag

CF(Px)

INT(Py)

Figure 3-2 Power-down monitoring

3.2. Digital Power Supply

V93XX integrates an on-chip LDO (DVCCLDO) and supplies voltage for digital circuit. This circuit could

output stable voltage with the power supply (VDD) has ripple noise. It is recommended to decouple the

pin DVCC externally with a ≥4.7μF capacitor in parallel with a 0.1μF capacitor. LDO is always on work.

The DVCCLDO has a driving capability of 35 mA. When the load current on the digital circuits is less than

35 mA, the DVCCLDO outputs stable voltage. When the load current is higher than 35mA, the output

voltage reduces as the current increases.

3.3. Power on Reset Circuit

The internal power-on reset circuit supervises the output voltage on “DVCCLDO” all the time. When the

output voltage is lower than 1.3V, POR reset signal will be generated and force the chip into the reset

state. When the output voltage is higher than 1.3V, the reset signal will be released, and the chip will

get to the Default State.

POR is always on work.

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V93XX Datasheet
4. Bandgap circuit

In the V93XX, the Bandgap circuit outputs a reference voltage and bias current, about 1.21V with a

typical temperature coefficient of 10 ppm/˚C, for ADCs and the 6.5 MHz RC oscillator. By default, the

Bandgap circuit was enabled. This circuit consumes about 0.09 mA (typical).

Users can configure RESTL<1:0> (Bit[4:3]) and REST<2:0> (Bit[2:0]) of analog control register (0x01,

ANA_CTRL1) to adjust the temperature coefficient of Bandgap circuit to cancel the temperature

coefficient introduced by the external components, with the following steps:

1) Assume the current settings of relative bits are REST<2:0>=’010’ and RESTL<1:0>=’00’, which

corresponds to the temperature coefficient of Bandgap is +14 ppm.

2) Measure meter errors in high and low temperature conditions. For example, this meter has 0

error at 20℃, and the measuring errors are 0.6% at 80℃ and -0.4% at -40℃ respectively. Then

a -(0.6%-(-0.4%))/2=-0.5% measuring error needs to be compensated relative to high

temperature working condition, equivalent to -0.5%/(80-20)=-5000/60=-83 ppm.

3) As measured error is minus two times of Reference temperature coefficient error, to compensate

a -83 ppm error, an additional +41.5 ppm of Bandgap REF temperature coefficient adjustment is

needed. Taking the initial +14 ppm setting into consideration, the actual adjustment should be

+55.5 ppm. According to the lookup table of RESTL<1:0> and REST<2:0>, user should set

temperature coefficient adjustment.

Attention: For the adjustment of Reference temperature parameters would influence the basic error;

therefore, when customers designed each new product, please first confirm the temperature parameter

of Reference then calibrate the error of the meter.

A temperature coefficient drift of x in the Bandgap circuit results in a drift of -2x in the measurement

error.

Figure 4-1 Register for Bandgap Circuit

Default
Register Bit Description
Value

Bit[4:3] 0 To roughly adjust the temperature coefficient of the Bandgap

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V93XX Datasheet
Default
Register Bit Description
Value

circuit.
RESTL<1:0>

00: 0 ppm

01: -58 ppm

10: +111 ppm

11: +56 ppm

In order to obtain the best metering performance and

temperature performance during normal metering, it must

be iterated according to the calculated result.

To finely adjust the temperature coefficient of the Bandgap

circuit
ANA_CTRL1

000: 0 ppm

001: +7 ppm

010: +14 ppm

011: +28 ppm

Bit[2: 0]
0 100: -32 ppm
REST<2:0>
101: -21 ppm

110: -14 ppm

111: -7 ppm

In order to obtain the best metering performance and

temperature performance during normal metering, it must

be iterated according to the calculated result.

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V93XX Datasheet
5. Clock

The on-chip RC oscillator circuit and the external input clock provide clocks for the V93XX:

 An external 6.5536 MHz of the pins “CTI”, “CLK1”. After the frequency divider, SDIV, controlled by

DSP_MODE (Bit<7:4>, Table 2-18 Metering Control Register 0 (0x02, DSP_CTRL0)). This clock

source for all digital block uses. After the frequency divider, ADIV, controlled by ADCKSEL

(Bit25<31:30>, analog control register, 0x01, ANA_CTRL1). This clock source for ADC uses. After

POR, RSTN pin reset, RX reset, or global software reset, this oscillator circuit starts to run

automatically.

 On-chip 6.5 MHz (The deviation is within ±20% from chip to chip for mass production. The

temperature deviation from -40~85 degree for each specific chip is less than ±5%.) RC oscillator

generates the clock, “CLK2”. When the CTI external input clock was disabled, it would be an optional

clock source for digital block uses. This circuit can be disabled.

 On-chip 32 KHz (±50%) RC oscillator generates the clock,” CLK3”. This clock source for IO ports

filter use. This circuit keeps on working until the system is powered off.

 External CLK (32768 Hz), input from X32KIN pin. This clock source for low-speed energy

accumulator uses. The clock source of energy accumulator would be controlled by EGY_CLK_SEL

(bit23, metering control register 1 (Table 2-19 Metering Control Register 2 (0x03, DSP_CTRL1))).

As mentioned above, the relationship between the 4 clocks source as the shown below:

CTI Sytem clock

SDIV
(6.5536MHz) CLK1 SCLK
CLK

CLK2 ADC clock

ADIV
6.5MHz (±20%) RC ADCCLK
Supervising
circuit

Energy
CLK4
accumulator
X32KIN(32.768kHz)
clock

CLK3
IO ports filter
32kHz(±50%) RC

Figure 5-1 Clock generation

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V93XX Datasheet
Table 5-1 Clock Generation Related Registers

Default
Register Bit Description
Value

The external input CTI clock enable.

Bit7
0
XRST_PD 0: enable

1: disable

To enable the 6.5-MHz RC clock.

Bit[22] 0: enable
0
RCCLK_PD 1: disable

The bit must be set to 0 for proper operation.

Bit[23] To disable the CTI external input clock by set this

0
XTALPD bit to 1. By default, this circuit is enabled.
ANA_CTRL1
To adjust the 6.5M RC frequency.
Bit[29:24] 000000~011111: step-up the frequency by 1.25%
0
RCTRIM<5:0> 100000~111111: step-down the frequency by

1.25%

To select the clock frequency for the ADC.

00 corresponds to 819.2 KHz.

Bit[31:30] 00: ×1
0
ADCKSEL<1:0> 01: ×2

10: ×1/4

11: ×1/2

DSP Operating Mode.

0: 128 sampling points per cycle by DSP at

DSP_CTRL0 (Table
6.5536 MHz system clock
2-18 Metering
Bit[7:4] 1: 64 sampling points per cycle by DSP at 6.5536
Control Register 0 0
DSP_MODE<1:0> MHz system clock
(0x02,
2: 32 sampling points per cycle by DSP at 6.5536
DSP_CTRL0))
MHz system clock.

3, 4, and 5: Reserved.

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V93XX Datasheet
Default
Register Bit Description
Value

6: 64 sampling points per cycle by DSP at 3.2768

MHz system clock

7: 32 sampling points per cycle by DSP at 3.2768

MHz system clock

8: 32 sampling points per cycle by DSP at 819.2

KHz system clock (supported only up to 2

channels instantaneous current RMS calculation.)

9: 16 sampling points per cycle by DSP at 409.6

KHz system clock (supported only up to 2

channels instantaneous current RMS calculation.)

Others: the same as mode 0

DSP_CTRL1 (Table To selection the clock for Energy accumulator. It

2-19 Metering needs the stable time around 107 us when CLK
Bit23
Control Register 2 0 switch over. Please disable CF before it is stable.

(0x03, EGY_CLK_SEL
0: 204.8 KHz
DSP_CTRL1))
1: 32768 Hz

5.1. External input high-frequency clock

Users can input 6.5536 MHz clock in CTI pin. CLK1 clock is provided for V93XX for system, metering

VMA, ADC, UART/ SPI interface and energy module. If the CTI pin does not have external clock, the

system automatically uses the RCH clock (CLK2 clock) for V93XX for system, metering VMA, ADC, UART/

SPI interface and energy module.

5.2. High-Frequency RC Oscillator

The V93XX has an internal high-frequency 6.5 MHz RC oscillator (The deviation is within ±20% from chip

to chip for mass production. The temperature deviation from Celsius -40~85 degree for each specific

chip is less than ±5 %.)

Under the metering mode, when CTI external input clock error, the circuit will automatically turn on and

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V93XX Datasheet
produce clock (CLK2) to work as an optional clock source for digital circuits.

After POR, RSTN pin reset, RX reset, or global software reset, this circuit and Bandgap circuit will be

working automatically.

5.3. Low-Frequency RC Oscillator

V93XX the low-frequency RC oscillator can generate a 32 KHz (±50%) RC clock (CLK3) to drive the IO

ports filter (RSTN/ RX/ A0/ A1 pin) for using the signal input.

This oscillator is always on work until the system is powered off.

5.4. External Input Clock

The external can inject a 32768 Hz frequency clock into the X32KIN pin of V93XX to provide CLK4 clock

for low-speed accumulation of energy barrel of V93XX.

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V93XX Datasheet
6. RESET

6.1. Reset Related Registers

Table 6-1 Reset Related Registers

Register Bit Description

Flag bits to indicate the reset source

Bit22 Bit21 Bit20 Description

0x74 Bit[22:20] 0 0 1 A POR event occurred.

SYS_STS RST_SOURCE 0 1 0 A RSTN event occurred.

0 1 1 An RX reset event occurred.

1 0 0 A global software reset occurred.

0x6c, SFTRST Writable only, in the form of 32-bit 2’ complement.

Software Reset Control Write “0x4572BEAF” to the register to reset the system and all circuit is

Register back to initial state.

6.2. Power-On Reset (POR)

In V93XX, the internal power-on reset circuit supervises the output voltage on “DVCCLDO” all the time.

When the output voltage is lower than 1.3 V, the reset signal will be generated and force the chip into

the reset state. When the output voltage is higher than 1.3 V, the reset signal will be released, and the

chip will get to the Default State in 500 μs.

When a POR event occurs, the bit “RST_SOURCE” (Bit[22:20], 0x74, SYS_STS) will be reset to

“0b001”.

In the reset state, the master MCU and the VMA metering architecture cannot access RAM. When the

chip exits from the reset state, RAM will implement the self-checking in about 1.25 ms. If there is no

error occurring, RAM can be accessed.

In the reset state, the UART/SPI serial interface is idle. The UART/SPI serial interface starts to run

immediately once the chip exits from the reset state.

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V93XX Datasheet
DVCCLDO

1.3 V

VSS
When the output voltage on DVCCLDO is
higher th an 1.3 V, the reset signal will be
released an d th e chi p will exit from the reset
500 μs
state in 500 μs.

Internal reset
signal

Reset state

RAM
self-checking
RAM access 1.25 ms
When the output voltage on
DVCCLDO is higher t han 1.3 V,
RAM can be accessed in about 1.75
1.75 ms ms.

UART/SPI
communication

Figure 6-1 Timing for POR

6.3. External Reset

In V93XX, the external reset circuit supervises the status on pin “RSTN” all the time. When the input

on pin “RSTN” must be driven low for at least 2 ms to force the chip into the reset state. Pull to the

logic high, and 900μs later the chip will exit from the reset state and get back to the Default State.

When a RSTN event occurs, the bit “RST_SOURCE” (Bit[22:20], 0x74, SYS_STS) will be reset to

“0b010”.

In the reset state, the master MCU and the VMA metering architecture cannot access RAM. When the

chip exits from the reset state, RAM will implement the self-checking in about 1.25 ms. If there is no

error occurring, RAM can be accessed.

In the reset state, the UART/ SPI serial interface is idle. The UART/SPI serial interface starts to run

immediately once the chip exits from the reset state.

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V93XX Datasheet

The input on pin RSTN must be driven

2 ms low for 2 ms to force the chip into the
Reset State.
Input on
RSTN pin
//
900 μs
Internal reset
signal When the input on pin RSTN is pulled
high, the chip will exit from the reset
state in 900 µs and get back to the
Default State.
Reset state
500 μs

RAM
self-checking
RAM access 1.25 ms
//
When the input on pin RSTN is
2.15 ms pulled high, RAM can be accessed
in 2.15 ms.

UART/SPI
communication

Figure 6-2 Timing for RSTN

6.4. RX Reset

“RX” reset depends on the communication type.

In the UART mode, when the “RX/ MOSI” pin continuously inputs a low level of 92.5 ms to force the

chip into the reset state. Pull to the logic high, and 900 μs later the chip will exit from the reset state

and get back to the Default State.

In the SPI mode, when the “RX/ MOSI” pin and “A1/ SPCSN” pin continuously inputs a low level of

92.5 ms and fed a clock source on pin “A0/ SPCK” which the frequency above the 50 Hz, then force

the chip into the reset state. Pull to the logic high, and 900 μs later the chip will exit from the reset state

and get back to the Default State

When the “RX” reset occurs, the bit “RST_SOURCE” (Bit[22:20], 0x74, SYS_STS) will be reset to

“0b011”.

In the reset state, the master MCU and the VMA metering architecture cannot access RAM. When the

chip exits from the reset state, RAM will implement the self-checking in about 1.25 ms. If there is no

error occurring, RAM can be accessed.

In the reset state, the UART/SPI serial interface is idle. The UART/SPI serial interface starts to run

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V93XX Datasheet
immediately once the chip exits from the reset state.

when the RX/MOSI pin continuously inputs a low

92.5 ms level of 92.5 ms to force the chip into the reset
state
Input on
RX pin
//
900 μs
Internal reset
signal When the input on pin RX is pulled
high, the chip will exit from the reset
state in 900 µs and get back to the
Default State.
Reset state
500 μs

RAM
self-checking
RAM access 1.25 ms
//
When the input on pin RX is
2.15 ms pulled high, RAM can be accessed
in 2.15 ms.

UART
communication

Figure 6-3 Timing for RX Reset of UART

92.5 ms

Clock frequency above 50Hz

Input on A0/
//
SPCK pin
when the RX/MOSI pin continuously
92.5 ms inputs a low level of 2122 RCL clock
intervals to force the chip into the reset
Input on RX/ state
MOSI and A1/
SPCSN pin //
900 μs
Internal
reset signal When the input on pin RX is pulled
high, the chip will exit from the reset
state in 900 µs and get back to the
Default State.
Reset state
500 μs

RAM
self-checking
RAM access 1.25 ms
//
When the input on pin RX is
2.15 ms pulled high, RAM can be accessed
in 2.15 ms.

UART
communicatio
n

Figure 6-4 Timing for RX Reset of SPI

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V93XX Datasheet
6.5. Global Software Reset

In V93XX, writing of “0x4572BEAF” in the register “SYS_SFTRST” (0x6C) can force the chip into the

Reset State, and the chip will exit and get back to Default State in 650 μs.

When the global software reset occurs, the bit “RST_SOURCE” (Bit[22:20], 0x74, SYS_STS) will be

reset to “0b100”.

In the Reset State, the master MCU and the VMA metering architecture cannot access RAM. When the

chip exits from the Reset State, RAM will implement the self-checking in about 1.25ms. If there is no

error occurring, RAM can be accessed.

In the Reset State, the UART serial interface is idle. The UART serial interface starts to run immediately

once the chip exits from the Reset State.

Write of “0x4572BEAF” to register

“0x6C” to force the chip into the
Writing of Reset State, and the chip will exit
from the Reset State in 650 μs.
register 0x4572BEAF
“0x6C” 650 μs

Internal reset
signal

Reset state
500 μs RAM
RAM access self-checking
1.25 ms
//

Write of “0x4572BEAF” to 1.9 ms

UART
communication

Figure 6-5 Timing of Global Software Reset

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V93XX Datasheet
7. UART

7.1. Overview

V93XX supports two communication modes, UART and SPI, which can switch between SPI communication

and UART communication without using external hardware jumper. After POR reset, RSTN reset, RX reset

or soft reset, V93XX uses UART communication by default. If you want to communicate by SPI, you must

initialize the SPI interface once through the SPI protocol.

Support multi-machine mode, that is, when the output data port is idle, it is a high resistance state. Up

to 4 V93XX share a single data bus via physical addresses A0 and A1.

The data byte received and transmitted via the UART serial interface of the V93XX is composed of 11

bits, including 1-bit start bit (logic low), 8-bit data bits, 1-bit odd parity bit and 1-bit stop bit (logic high),

as shown in the following figure. When the V93XX sends command, the least significant bit and least

significant byte always are shifted out firstly.

START B0 B1 B2 B3 B4 B5 B6 B7 P STOP

Figure 7-1 Structure of an 11-Bit data byte (from LSB to MSB)

UART protocol is a half-duplex protocol. The end of the send command for 1ms later, then V93XX would

upload data.

UART supports 1200bps to 19200bps baud rate and it can self-adapting the baud rate which received

from the first frame header. The baud rate will also be fine-tuned through the following communication.

If the baud rate of communication has a large change, it needs rerunning the baud rate self-adapting.

Before this event, it needs to set the UARTAUTOEN Bit0 of SYS_MISC to 1.

V93XX also has the command for continually writing or broadcast writing. This mode can save the

parameter configurable time.

Under the following conditions, the UART transmission will be aborted and back to IDLE state.

Table 7-1 UART communication errors

No Conditions UARTERR set to 1

1 UART frame header error. NO

2 UART overtime, each 2 Bytes needs to shorter than 20 ms. YES

3 UART parity bit error. YES

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V93XX Datasheet
4 UART sends checksum byte from master MCU has error. YES

7.2. Broadcast Communication

--Supports writing to consecutive registers of 1~16 addresses

--Don’t care about device address{A1,A0}

--V93XX no response

Batch writes to register for multiple V93XX devices via broadcast writing by master MCU. This mode can

save the parameter configurable time. The figure below is the command frame for broadcast writing

operation.

From HEADER Data 0 Data 0 Data 0 Data 0 Data N Data N Data N Data N
Host 0x7D
CMD1 CMD2
Byte 0 Byte 1 Byte 2 Byte 3
CKSUM 0 ... Byte 0 Byte 1 Byte 2 Byte 3
CKSUM N

From
V93XX No response

Figure 7-2 command frame for broadcast writing operation

Table 7-2 Structure of Data Byte (B7:B0) From Master MCU to V93XX on Broadcast Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

1 HEADER 0 1 1 1 1 1 0 1

To select the data length on broadcast

writing (N)

0: write 1 data of 32 bits

2 CMD1 X* X* 0 0
1: write 2 data of 32 bits

15: write 16 data of 32 bits

3 CMD2 X* Start address for broadcast writing operation (D0)

Data 0
4 “Bit[7:0]” of the target data write into register (address D0)
Byte 0

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

Data 0
5 “Bit[15:8]” of the target data write into register (address D0)
Byte 1

Data 0
6 “Bit[23:16]” of the target data write into register (address D0)
Byte 2

Data 0
7 “Bit[31:24]” of the target data write into register (address D0)
Byte 3

Checksum 0. Add the above 4 target data bytes (Data 0 Byte 0~3), CMD1, and

CMD2, invert the sum, and then add it to “0x33” to obtain the checksum. The

8 CKSUM 0 equation is as below:

CKSUM 0 = 0x33 + ~(CMD1 + CMD2 + Data 0 Byte 0 + Data 0 Byte 1 + Data

0 Byte 2 + Data 0 Byte 3)

… … …

Data N
5xN+4 “Bit[7:0]” of the target data write into register (address DN=D0+N)
Byte 0

Data N
5xN+5 “Bit[15:8]” of the target data write into register (address DN=D0+N)
Byte 1

Data N
5xN+6 “Bit[23:16]” of the target data write into register (address DN=D0+N)
Byte 2

Data N
5xN+7 “Bit[31:24]” of the target data write into register (address DN=D0+N)
Byte 3

Checksum N. Add the above 4×(N+1) target data bytes (Data 0~N Byte 0~3),

CMD1, and CMD2, invert the sum, and then add it to “0x33” to obtain the

checksum. The equation is as below:

5xN+8 CKSUM N
CKSUM N = 0x33 + ~(CMD1 + CMD2 + Data 0 Byte 0 + Data 0 Byte 1 + Data

0 Byte 2 + Data 0 Byte 3 + ….. + Data N Byte 0 + Data N Byte 1 + Data N Byte

2 + Data N Byte 3)

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

*X could be 0 or 1.

If the length N equals to 0 on broadcast writing operation, master MCU only sends first 8 bytes of

command frame to V93XX.

7.3. Read Operation

--Supports writing to consecutive registers of 1~16 addresses

--device address {A1,A0} must be matched correctly

--V93XX would be responded

From HEADER
CMD1 CMD2 CKSUM
Host 0x7D

From
Data 0 Data 0 Data 0 Data 0
V93XX CKSUM
Byte 0 Byte 1 Byte 2 Byte 3

Figure 7-3 Communication protocol for read operation

Table 7-3 Structure of Data Byte (B7:B0) From Master MCU to V93XX on Read Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

1 HEADER 0 1 1 1 1 1 0 1

To select the data length on read

operation

0: write 1 data of 32 bits

2 CMD1 A1 A0 0 1
1: write 2 data of 32 bits

15: write 16 data of 32 bits

3 CMD2 X* Start address for read operation (D0)

Checksum. Add the above CMD1 and CMD2, invert the sum, and then add it to
4 CKSUM
“0x33” to obtain the checksum. The equation is as below:

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

CKSUM = 0x33 + ~(CMD1 + CMD2)

* X could be 0 or 1.

Table 7-4 Structure of Data Byte (B7:B0) From V93XX to Master MCU on read Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

Data 0
1 “Bit[7:0]” of the target data read from register (address D0)
Byte 0

Data 0
2 “Bit[15:8]” of the target data read from register (address D0)
Byte 1

Data 0
3 “Bit[23:16]” of the target data read from register (address D0)
Byte 2

Data 0
4 “Bit[31:24]” of the target data read from register (address D0)
Byte 3

… … …

Data N
4xN+1 “Bit[7:0]” of the target data read from register (address DN=D0+N)
Byte 0

Data N
4xN+2 “Bit[15:8]” of the target data read from register (address DN=D0+N)
Byte 1

Data N
4xN+3 “Bit[23:16]” of the target data read from register (address DN=D0+N)
Byte 2

Data N
4xN+4 “Bit[31:24]” of the target data read from register (address DN=D0+N)
Byte 3

Checksum. Add the above 4×(N+1) target data bytes (Data 0~N Byte 0~3,

comes from V93XX), CMD1, and CMD2(comes from MCU), invert the sum, and
4xN+5 CKSUM
then add it to “0x33” to obtain the checksum. The equation is as below:

CKSUM = 0x33 + ~(CMD1 + CMD2 + Data 0 Byte 0 + Data 0 Byte 1 + Data

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

0 Byte 2 + Data 0 Byte 3 + ….. + Data N Byte 0 + Data N Byte 1 + Data N

Byte 2 + Data N Byte 3)

*X could be 0 or 1.

If the length N equals to 0 on read operation, V93XX only sends 5 bytes of response frame to master

MCU.

7.4. Write Operation

--Supports writing to consecutive registers of 1~16 addresses

--device address {A1, A0} must be matched correctly

--V93XX would be responded

From HEADER Data 0 Data 0 Data 0 Data 0 Data N Data N Data N Data N
Host 0x7D
CMD1 CMD2
Byte 0 Byte 1 Byte 2 Byte 3
CKSUM 0 ... Byte 0 Byte 1 Byte 2 Byte 3
CKSUM N

From CKSUM
V93XX

Figure 7-4 Communication protocol for write operation

Table 7-5 Structure of Data Byte (B7:B0) From Master MCU to V93XX on Write Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

1 HEADER 0 1 1 1 1 1 0 1

To select the data length on write

operation

0: write 1 data of 32 bits

2 CMD1 A1 A0 1 0
1: write 2 data of 32 bits

15: write 16 data of 32 bits

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

3 CMD2 X* Start address for write operation (D0)

Data 0
4 “Bit[7:0]” of the target data write into register (address D0)
Byte 0

Data 0
5 “Bit[15:8]” of the target data write into register (address D0)
Byte 1

Data 0
6 “Bit[23:16]” of the target data write into register (address D0)
Byte 2

Data 0
7 “Bit[31:24]” of the target data write into register (address D0)
Byte 3

Checksum 0. Add the above 4 target data bytes (Data 0 Byte 0~3), CMD1, and

CMD2, invert the sum, and then add it to “0x33” to obtain the checksum. The

8 CKSUM 0 equation is as below:

CKSUM 0 = 0x33 + ~(CMD1 + CMD2 + Data 0 Byte 0 + Data 0 Byte 1 + Data

0 Byte 2 + Data 0 Byte 3)

… … …

Data N
5xN+4 “Bit[7:0]” of the target data write into register (address DN=D0+N)
Byte 0

Data N
5xN+5 “Bit[15:8]” of the target data write into register (address DN=D0+N)
Byte 1

Data N
5xN+6 “Bit[23:16]” of the target data write into register (address DN=D0+N)
Byte 2

Data N
5xN+7 “Bit[31:24]” of the target data write into register (address DN=D0+N)
Byte 3

Checksum N. Add the above 4×(N+1) target data bytes (Data 0~N Byte 0~3),

5xN+8 CKSUM N CMD1, and CMD2, invert the sum, and then add it to “0x33” to obtain the

checksum. The equation is as below:

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

CKSUM N = 0x33 + ~(CMD1 + CMD2 + Data 0 Byte 0 + Data 0 Byte 1 + Data

0 Byte 2 + Data 0 Byte 3 + ….. + Data N Byte 0 + Data N Byte 1 + Data N Byte

2 + Data N Byte 3)

*X could be 0 or 1.

If the length N equals to 0 on broadcast writing operation, master MCU only sends first 8 bytes of

command frame to V93XX.

Table 7-6 Structure of Data Byte (B7:B0) From V93XX to Master MCU on Write Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

Checksum (comes from V93XX). Used to verify that the write operation was

successful.

If CKSUM and CKSUM N (comes from master MCU) was equal, this time write
1 CKSUM
operation was succeeded.

If CKSUM and CKSUM N (comes from master MCU) was not equal, this time

write operation was failed.

7.5. Block Reading Operation

In order to facilitate the user to read the required data at one time and improve communication

efficiency, V93XX provides address mapping function: The user maps the address of the data item that

needs to be continuously operated to the address register, so that the user can perform the block read

operation on the data in different places by operating the address register.

Up to 16 data register addresses can be mapped.

The block reading operation can start from any position in the mapped address register. If the address

plus the number of reads exceeds the buffer size, the read is started from the beginning. For example,

10 data are read from the 13th mapping address, and after the 16th address, the data of 6 addresses

is continuously read from the first one.

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V93XX Datasheet
Metering data or
Address mapping control register
regiser
Register address 0
Register address 1
Address mapping
0 Register address 2
Start address of Address mapping Register address 3
block reading 1
Register address 4
Address mapping
number Register address 5
2
s Register address 6
Register address 7

Address mapping
15
Register address X-2
Register address X-1
Register address X

Figure 7-5 address mapping for block reading

Feature:

--Support block reading operation by address mapping from 1~16 addresses that are not

consecutive.

--Device address {A1,A0} must be matched correctly.

--V93XX would be responded.

From HEADER
CMD1 CMD2 CKSUM
Host 0x7D

From
Data 0 Data 0 Data 0 Data 0
V93XX CKSUM
Byte 0 Byte 1 Byte 2 Byte 3

Figure 7-6 Communication protocol for block reading operation

Table 7-7 Structure of Data Byte (B7:B0) From Master MCU to V93XX on block reading Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

1 HEADER 0 1 1 1 1 1 0 1

2 CMD1 To select the data length on block A1 A0 1 1

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

reading operation

0: write 1 data of 32 bits

1: write 2 data of 32 bits

15: write 16 data of 32 bits

To select the start address on block

reading operation

16 block reading addresses are set by 4

registers of SYS_BLKX_ADDR

For example: if N=4 (length is 5) and

M=4(setting start address), it would start

to read address from the bit7~0 of

SYS_BLK1_ADDR register in the ADDR4.

The 5 register addresses for block reading

operation as below:

3 CMD2 X* X* X* X*
1: stored address ADDR4 in the Bit7~0 of

the SYS_BLK1_ADD

2: stored address ADDR5 in the Bit15~8

of the SYS_BLK1_ADD

3: stored address ADDR6 in the Bit23~16

of the SYS_BLK1_ADD

4: stored address ADDR7 in the Bit31~24

of the SYS_BLK1_ADD

5: stored address ADDR8 in the Bit7~0 of

the SYS_BLK2_ADD

4 CKSUM Checksum. Add the above CMD1 and CMD2, invert the sum, and then add it to

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

“0x33” to obtain the checksum. The equation is as below:

CKSUM = 0x33 + ~ (CMD1 + CMD2)

*X could be 0 or 1.

Table 7-8 Structure of Data Byte (B7:B0) From V93XX to Master MCU on block reading Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

Data 0
1 “Bit[7:0]” of the target data read from register (address ADDRM)
Byte 0

Data 0
2 “Bit[15:8]” of the target data read from register (address ADDRM)
Byte 1

Data 0
3 “Bit[23:16]” of the target data read from register (address ADDRM)
Byte 2

Data 0
4 “Bit[31:24]” of the target data read from register (address ADDRM)
Byte 3

… … …

Data N
4xN+1 “Bit[7:0]” of the target data read from register (address ADDRM+N)
Byte 0

Data N
4xN+2 “Bit[15:8]” of the target data read from register (address ADDRM+N)
Byte 1

Data N
4xN+3 “Bit[23:16]” of the target data read from register (address ADDRM+N)
Byte 2

Data N
4xN+4 “Bit[31:24]” of the target data read from register (address ADDRM+N)
Byte 3

Checksum. Add the above 4×(N+1) target data bytes (Data 0~N Byte 0~3,

4xN+5 CKSUM comes from V93XX), CMD1, and CMD2(comes from MCU), invert the sum, and

then add it to “0x33” to obtain the checksum. The equation is as below:

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

CKSUM = 0x33 + ~ (CMD1 + CMD2 + Data 0 Byte 0 + Data 0 Byte 1 + Data 0

Byte 2 + Data 0 Byte 3 + ….. + Data N Byte 0 + Data N Byte 1 + Data N Byte

2 + Data N Byte 3)

*X could be 0 or 1.

If the length N equals to 0 on read operation, V93XX only sends 5 bytes of response frame to master

MCU.

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V93XX Datasheet
8. SPI

8.1. Overview

V93XX supports two communication modes, UART and SPI, which can switch between SPI communication

and UART communication without using external hardware jumper. After POR reset, RSTN reset, RX reset

or soft reset, V93XX uses UART communication by default. If you want to communicate by SPI, you must

initialize the SPI interface once through the SPI protocol.

Support multi-machine communication mode, that is, when the output data port is idle, it is a high-

resistance state. Through SPICSN chip selection signal support multiple V93XX to share a data bus.

The SPI interface of V93XX is a standard 4-wire or 3-wire SPI interface. 4-wire SPI mode must have a

50μs interval between every 2 read and write operations. 3-wire SPI mode has been low at chip select

pin. When the V93XX sends command, the least significant byte and most significant bit always are

shifted out firstly. The polarity and phase are 0.

When SPI reading register, the maximum speed can be 1/4 of system CLK; when reading RAM, the

maximum speed can be 1/16 of system CLK. When the MCU reads the RAM or register of V93XX, if

V93XX does not get the data in time, V93XX will send the wrong checksum byte to the MCU.

The RAM address range is 0x11~0x38, 0x43~0x54, 0x68, and 0x69. The remaining addresses are

registers.

Before performing SPI read and write, it needs to write 0x5A7896B4 to the 0x7F addresses. If it does

not do this, any SPI communication will be ignored.

SPI overtime mechanism: During communication, the time between the rising edges of every 2 SPCK

needs to be shorter than 20ms, otherwise an SPI timeout is considered to occur.

Under the following conditions, an exception occurs in the SPI communication.

Table 8-1 SPI communication errors

The condition for the

No Condition SPI_ERR set to 1 next successful

communication

1 SPI overtime (rising edge of every 2 SPCK needs Yes No

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V93XX Datasheet
to shorter than 20 ms).

2 4-wire SPI CLK error (not equals to 48 clocks). Yes No

Re-initialize SPI
3 V93XX reset happens. No
interface

8.2. Write Operation

After the write operation is completed, V93XX will not return a valid response to the MCU. It needs to

read back the value of the register to confirm the success of the write operation.

From Data Data Data Data

CMD CKSUM
Host Byte 0 Byte 1 Byte 2 Byte 3

From
V93XX

Figure 8-1 Communication protocol for SPI write operation

Table 8-2 Structure of Data Byte (B7:B0) From Master MCU to V93XX on write Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

1 CMD Register address for write operation 0

Data
2 “Bit[7:0]” of the target data write into register
Byte 0

Data
3 “Bit[15:8]” of the target data write into register
Byte 1

Data
4 “Bit[23:16]” of the target data write into register
Byte 2

Data
5 “Bit[31:24]” of the target data write into register
Byte 3

Checksum 0. Add the above 5 target data bytes (Data Byte 0~3) and CMD1,

6 CKSUM invert the sum, and then add it to “0x33” to obtain the checksum. The

equation is as below:

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

CKSUM = 0x33 + ~(CMD + Data Byte 0 + Data Byte 1 + Data Byte 2 + Data

Byte 3)

8.3. Read Operation

From
CMD
Host

From Data Data Data Data

V93XX CKSUM
Byte 0 Byte 1 Byte 2 Byte 3

Figure 8-2 Communication protocol for SPI read operation

Table 8-3 Structure of Data Byte (B7:B0) From Master MCU to V93XX on read Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

1 CMD Register address for read operation 1

2 -*

3 -* MCU generates 40 clocks is used for receiving 5 bytes of response frame sent

4 -* back by V93XX.

5 -* MCU sends any data has no effect on the operation.

6 -*

*- this byte could be any value

Table 8-4 Structure of Data Byte (B7:B0) From V93XX to Master MCU on read Operation

Order Byte B7 B6 B5 B4 B3 B2 B1 B0

When the MCU sends a CMD to the V93XX, the data received by the MCU doesn’t
1 -*
have to be concerned.

Data
2 “Bit[7:0]” of the target data read from register
Byte 0

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V93XX Datasheet
Order Byte B7 B6 B5 B4 B3 B2 B1 B0

Data
3 “Bit[15:8]” of the target data read from register
Byte 1

Data
4 “Bit[23:16]” of the target data read from register
Byte 2

Data
5 “Bit[31:24]” of the target data read from register
Byte 3

Checksum. Add the above 4 target data bytes (Data Byte 0~3, comes from

V93XX) and CMD1 (comes from MCU), invert the sum, and then add it to “0x33”

6 CKSUM to obtain the checksum. The equation is as below:

CKSUM = 0x33 + ~(CMD + Data Byte 0 + Data Byte 1 + Data Byte 2 + Data

Byte 3)

*- this byte could be any value

8.4. Initialize interface

The default communication interface of V93XX is UART. If it wants to initialize the SPI communication

interface, it needs to write 0x5A7896B4 to the 0x7F address, that is, the MCU must sends the following

6 bytes of data to V93XX via the SPI protocol.

Table 8-5 SPI interface initialization data (hexadecimal)

CMD Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 CKSUM

0xFE 0xB4 0x96 0x78 0x5A 0x18

Because of the SPI write operation, V93XX will not send a valid response to the MCU. After writing

0x5A7896B4 to the 0x7F address to complete the SPI interface initialization, it cannot directly confirm

whether the initialization is valid. It is recommended to read any readable register and check if the

checksum byte is correct to confirm that the SPI interface initialization process is completed correctly.

After POR, RSTN pin reset, RX reset, or global software reset occurs, the SPI interface is reset and the

V93XX is restored to the UART communication interface. After that, the initialization process of SPI

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V93XX Datasheet
interface needs to be performed again before SPI read-write operation.

8.5. 4-wire SPI Mode

-- SPI interface initialization must be performed after POR, RSTN pin reset, RX reset, or global

software reset occurs on V93XX

-- There must be a 50 μs interval between every 2 read or write operations

-- The number of clocks per read or write must be 48

-- Chip select pin must be pulled back high after each read or write operation

SPICSN

SPICLK

SPIMOSI {1'b0, ADDR[6:0]} Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Check Sum
} write mode
SPIMISO

SPIMOSI {1'b0, ADDR[6:0]}

} read mode
SPIMISO Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Check Sum

Figure 8-3 Communication protocol for 4 wire SPI mode

8.6. 3-wire SPI Mode

-- SPI interface initialization must be performed after POR, RSTN pin reset, RX reset, or global

software reset occurs on V93XX

-- Chip select pin is always low

-- The number of clocks per read or write must be 48

-- The clock pin must be pulled low for at least 400μs before each read or write operation

SPICSN
(Always low) >400μs
SPICLK
SPIMOSI {1'b0, ADDR[6:0]} Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Check Sum
} write mode
SPIMISO
SPIMOSI {1'b0, ADDR[6:0]}
} read mode
SPIMISO Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Check Sum

Figure 8-4 Communication protocol for 3 wire SPI mode

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V93XX Datasheet
9. DSP

9.1. Overview

Metering DSP are mainly used in calculating total-wave active power, fundamental-wave active power,

total/ fundamental-wave reactive power, total-wave apparent power, total-wave RMS and

fundamental-wave RMS; also provides power grid events to detect and waveform storage functions.

The energy accumulator can flexible configuration, providing 2 high-speed energy accumulators and 6

low-speed energy accumulators.

Waveform data can output to external by DMA or internal storage.

9.2. Features

--Support 1 voltage channel and 2 current channels metering at the same time

--Selectable the full-wave bandwidth

--Provide 2 configurable fundamental-wave channels which can calculate power and RMS of

fundamental-wave.

--Selectable refresh time for average power value or average RMS.

--Provide the average RMS of 10 or 12 cycles which used in voltage flicker detection.

--Support to determine the power-creep, voltage swell or dip, over or under- voltage and over or

under- current.

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V93XX Datasheet
9.3. Functional Diagram

BIAS DC
LPF

UP
UN
APGA ADC LPF - HPF
T ota l v ol ta ge
wav eform

Fund. volta ge
wav eform
LPF

DC
BIAS LPF

Phase compens ation

IAP
IAN
APGA ADC LPF - HPF
T ota l Current a
wav eform

Fund. Curre nta

wav eform
LPF
AC

DC
BIAS LPF

IB
ADC - T ota l Current b
MUX

APGA wav eform

LPF HPF
Ib Fund. Currentb
wav eform
LPF
AC

Temp. Sensor

Figure 9-1 Functional Diagram 1 of Metering DSP

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V93XX Datasheet

T ota l v ol ta ge Freq.
wav eform Measurement
BPF

T ota l v ol ta ge
wav eform

T ota l Current a
wav eform RMS Calculation
T ota l Currentb
wav eform

T ota l v ol ta ge Inst.
wav eform Total
T ota l Current a Watta
wav eform Avg.

T ota l v ol ta ge Inst.
wav eform Total
T ota l Current b Wattb
wav eform Avg.

T ota l v ol ta ge
wav eform

T ota l Current a Inst.

MUX

wav eform 90 degree VARa

Shift
Fund. volta ge Avg.
wav eform

Fund. Currenta
wav eform

T ota l v ol ta ge
wav eform

T ota l Currentb Inst.

MUX

wav eform 90 degree VARb

Shift
Fund. volta ge Avg.
wav eform

Fund. Curre ntb

wav eform

Fund. Inst.
Watta Avg.
Fund. volta ge
wav eform
MUX

Fund. Curre nta Fund. Inst.

wav eform
Wattb Avg.
Fund. Currentb
wav eform

Fund. Inst.
RMS Avg.

Figure 9-2 Functional Diagram 2 of Metering DSP

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V93XX Datasheet
9.4. Application Description

9.4.1. Phase Calibration

Table 9-1 Phase Calibration Description

DSP_MODE calibration accuracy(degree) Calibration range(degree)

0x00, 0x01, 0x02 0.005493164 ±4.21875

0x06, 0x07 0.010986328 ±8.4375

0x08 0.021972656 ±16.855

Phase correction of IA phc_ia = Angle to be corrected /calibration_acuracy

Phase correction of IB phc_ib = Angle to be corrected /calibration_acuracy

IA and IB error correction values are combined in complement form and written into the error correction

register (0x33, DSP_CFG_PHC).

9.4.2. Frequency Calculation

V93XX supports frequency measurement, which is stored in the grid frequency register (0x21,

DSP_DAT_FRQ). Users need to configure the bandpass filter coefficient according to different DSP_MODE

(Table 2-18 Metering Control Register 0 (0x02, DSP_CTRL0) ). For details, please refer to the bandpass

filter coefficient register (Table 2-41 Bandpass Filter Register (0x37, DSP_CFG_BPF)).

The user accumulates the number of cycles and the DSP_MODE configuration frequency constant through

the FRQ_SEL configuration frequency test of the metering control register 0 (0x02, DSP_CTRL0).

Grid frequency = wave_cnt*freq_const/DSP_DAT_FRQ

Table 9-2 Frequency register source FRQ_SEL description

RQ_SEL wave_cnt

0 16

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V93XX Datasheet
1 1

2 64

Table 9-3 Frequency Constant Description

DSP_MODE Frequency constant

0x08 1600

0x06, 0x07 3200

0x00, 0x01, 0x02 6400

9.4.3. Phase Test

Metering chip supports voltage phase and current phase measurement. The operation principle is,

master MCU sends command to register DSP_PHS_STT (0x5f) and sets to 1 via UART/SPI interface.

After the metering chip is decoded as a phase measurement command, it starts to use the 6.4 KHz for

sampling frequency (When DSP_MODE is 0, 1, 2, the sampling frequency of voltage signal used for

phase testing is 6.4 KHz. When DSP_MODE is 6 and 7, the sampling frequency of voltage signal used

for phase testing is 3.2 KHz) to counting. Until positive zero-crossing events happened, it stops

counting. This counting value will write into the voltage phase register DSP_PHS_U (0x62) and current

phase register DSP_PHS_I (0x65). It also records two voltage sampling values before and after the

positive zero-crossing DSP_PHS_UN (0x63), DSP_PHS_UP (0x64) and two current sampling values

before and after the zero-crossing DSP_PHS_IN (0x66), DSP_PHS_IP (0x67). User can obtain better

accurate phase value by interpolation method.

9.4.4. Power-creep Detection

Active power, reactive power, and apparent power support the power-creep function. See Table 2-32

Power-creep Threshold Register. When the instantaneous active power/reactive power/apparent power

of the channel A and the channel B are higher than the upper threshold, the startup state is entered.

When the instantaneous active power/reactive power/apparent power of the channel A and the channel

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V93XX Datasheet
B are lower than the upper threshold, the power-creep state is entered.

The user can check whether the instantaneous active power/reactive power/apparent power is in the

power-creep state by Bit17~Bit12 of the SYS_STS system status register description (0x74, SYS_STS).

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V93XX Datasheet
10. Active Waveform upload and buffer

V93XX waveform data can be transferred through DMA, or stored locally through waveform buffer.

Trigger mode supports command trigger and event trigger.

10.1. Active Waveform upload

10.1.1. Overview

The V93XX supports the DMA mode for data transmission and sends up to 3 original waveform data to

the external MCU through the SPI interface host mode. The user can set the active waveform upload

through the metering control register 5 (0x07, DSP_CTRL5), and configure the active waveform data

upload IO port P0~P6 through IO configuration register 0 (0x7D, SYS_IOCFG0) and IO configuration

register 1 (0x7E, SYS_IOCFG1).

The number of sampling points per cycle of the DMA transmission data is related to DSP_MODE (Bit[7:4])

of DSP_CTRL0 (Table 2-18 Metering Control Register 0 (0x02, DSP_CTRL0)); the number of channels is

related to Bit10~8 of DSP_CTRL5 (0x07, DSP_CTRL5). Its relationship is shown in the following table:

Table 10-1 Active waveform data upload configuration

The number of waveform transmission Sampling points (related to DSP_MODE) Baud Rate

1 256 819.2 KHz

3 128 819.2 KHz

2 128 819.2 KHz

1 128 409.6 KHz

3 64 409.6 KHz

2 64 409.6 KHz

1 64 204.8 KHz

1、2、3 32 204.8 KHz

Vango Technologies, Inc. 136 / 151

V93XX Datasheet
10.1.2. Timing and Format

The V93XX transmits the original waveform of the signal to the peripheral device via the DMA SPI

interface. The SPI polarity and phase are configurable. When the polarity is 0 and the phase is 0, the

transmission timing is as follows:

DSCS

DSCK

DSDO D21 D21 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 A2 A1 A0 0 0 0 C

22-bit DATA 3-bit AD C Address CRC

DATA bit21

Figure 10-1 Communication timing of DMA SPI

Transmission mode: The transmission of 32-bit data is completed at one time. The format of the data

frame for each transmission is as follows:

Table 10-2 Active waveform data upload format

Bit Contents

31:30 Same as Bit29.

29:8 The original waveform of 22-bit for each channel ADC signal source.

7 0

Indicates whether the present waveform data is from a voltage channel.

6 0: no

1: yes

Indicates whether the present waveform data is from a channel IA.

5 0: no

1: yes

Vango Technologies, Inc. 137 / 151

V93XX Datasheet
Indicates whether the present waveform data is from a channel IB

4 0: no

1: yes

3:1 000

0 Odd parity bit. The check range is the forward 31bit.

10.2. Waveform Buffer

After the waveform buffer function is enabled, the waveform data is stored in the RAM, supporting

single-channel waveform data storage and dual-channel waveform data simultaneous storage mode. If

the waveform buffer of three channels is enabled at the same time, the channel IB is invalid. The user

can configure the waveform buffer and start and end condition selection by metering control register 5

(0x07, DSP_CTRL5). After the waveform buffer configuration is completed, the user can check whether

the waveform buffer is completed by the WAVE_STORE of the system interrupt status register (0x72,

SYS_INTSTS). After completion, the user can obtain waveform buffer data by repeatedly reading the

waveform data register (0x69, DAT_WAVE), and it can read up to 309 data every time.

Table 10-3 waveform buffer data format

channel High 16Bit Low 16Bit

IA IADATA2n+1 IADATA2n

IB IBDATA2n+1 IBDATA2n

U UDATA2n+1 UDATA2n

IA+IB IBDATAn IADATAn

IA+U IADATAn UDATAn

IB+U IBDATAn UDATAn

IA+IB+U (the channel IB

IADATAn UDATAn
is invalid at this time)

Where the range of n is 0~308

Vango Technologies, Inc. 138 / 151

V93XX Datasheet
11. Electrical Signal monitoring

11.1. Zero-crossing Detection

The V93XX supports zero-crossing detection for voltage channel and current channel (the zero-crossing

channel can be selected as the channel IA or channel IB by Bit20 of Metering Control Register 1 (Table

2-19 Metering Control Register 2 (0x03, DSP_CTRL1)). The zero-crossing direction can be selected by

Bit19~Bit18 of the metering control register 1 (0x03, DSP_CTRL1). When the voltage/current channel

signal has a zero-crossing event, the voltage zero-crossing flag USIGN/current zero-crossing flag ISIGN

of the system interrupt status register (0x72, SYS_INTSTS) is set to 1. The user needs to write 1 to clear.

When the voltage/current zero-crossing interrupt output is enabled, USIGN/ISIGN of the system

interrupt enable register (0x73, SYS_INTEN) is set to 1. To configure the voltage/current zero-crossing

interrupt output by configuring IO Configuration Register 0 (0x7D, SYS_IOCFG0) or IO Configuration

voltage zero-crossing flag USIGN/current zero-crossing flag ISIGN.

To configure the voltage/current zero-crossing interrupt output square wave by configuring IO

Configuration Register 0 (0x7D, SYS_IOCFG0) or IO Configuration Register 1 (0x7E, SYS_IOCFG1).The

output level of pin Px is automatically inverted according to the voltage/current zero-crossing status in

real time. Each time a zero-crossing event occurs, the IO port is inverted once.

The following figure is configured to enable the zero-crossing interrupt output. When the zero-crossing

detection mode is selected as the negative zero-crossing point, the USIGN/ISIGN flag bit, the zero-

crossing interrupt output, and the zero-crossing output square wave waveform.

Vango Technologies, Inc. 139 / 151

V93XX Datasheet

Voltage/current signal

Clear flag bit

USIGN/ISIGN_Flag bit

Figure 11-1 output waveform for voltage/current zero-crossing

11.2. Voltage Swell/Dip

The V93XX can be programmed to indicate voltage swell/dip. See Table 2-33 Voltage Swell or Dip

Threshold Register.

When the voltage RMS value is above the upper limit of the voltage swell threshold, the voltage swell

status bit (USWELL of the SYS_STS system status register (0x74, SYS_STS)) is set to 1. At the same

time, the voltage swell flag (USWELL of the system interrupt status register (0x72, SYS_INTSTS)) is set

to 1, and the flag bit is written to 1 to clear.

When the voltage RMS value is lower than the lower limit of the voltage swell threshold, the voltage swell

status bit (USWELL of the SYS_STS system status register description (0x74, SYS_STS)) is restored to

When the voltage RMS value is lower than the lower limit of the voltage dip threshold, the voltage dip

status bit (UDIP of the SYS_STS system status register (0x74, SYS_STS)) is set to 1. At the same time,

the voltage dip flag (UDIP of the system interrupt status register (0x72, SYS_INTSTS)) is set to 1, and

the flag bit is written to 1 to clear.

When the voltage RMS value is higher than the high limit of the voltage dip threshold, the voltage dip

status bit (UDIP of the SYS_STS system status register description (0x74, SYS_STS)) is restored to 0.

Vango Technologies, Inc. 140 / 151

V93XX Datasheet
At the same time, the voltage swell/sag time record can be obtained by reading the register

DAT_SWELL_CNT/DAT_DIP_CNT, and the half wave is in units. 24Bit is valid. Write any value to this

register to clear the count value.

The voltage swell interrupt flag and voltage dip interrupt flag can be configured by configuring the IO

port output. See Table 2-14 IO Configuration Register 0 (0x7D, SYS_IOCFGX0) and Table 2-16 IO

Configuration Register 1 (0x7E, SYS_IOCFGX1).

11.3. Over-voltage and under-voltage/Over-current and

under-current

PEAK

Threshold of
over-voltage/current
Threshold of
under-voltage/current

Normal Over-voltage/current Under-voltage/current

Figure 11-2 Over-voltage and under-voltage/Over-current and under-current detect

The V93XX can be programmed to indicate over-voltage/under-voltage of channel U, over-voltage/under-

voltage of channel IA, and over-voltage/under-voltage of channel IB. See Table 2-34 Fast detection

Threshold Register. The user can enable the detection for over-voltage/under-voltage of channel U, over-

current/under-current of channel IA, and over-current/under-current of channel IB by FDUEN, FDIAEN,

and FFIBEN of metering control register 4 (Table 2-22 Metering Control Register 4 (0x06, DSP_CTRL4)).

The detection source supports high-pass filters and by-pass. The over-voltage or under-voltage/over-

current or under-current detection time length is selectable.

1) Support waveform monitoring of three ADCs.

2) Each ADC waveform monitor has two thresholds: upper threshold (over-voltage, over-current); lower

threshold (under-voltage, under-current)

3) Exceeding the upper limit threshold sample points: For example, if the set value is 4, it means that if

more than 4 of the half cycle sampling points exceed the upper limit threshold, the half cycle waveform

Vango Technologies, Inc. 141 / 151

V93XX Datasheet
is considered to exceed the upper limit.

4) Exceeding the upper threshold half-cycle number: For example, if the set value is 2, it means that if

two consecutive half-cycles are exceeding the upper limit, an over-voltage or over-current event is

considered to occur.

5) Below the lower limit threshold sample points: For example, if the set value is 4, it means that if low

than or equal to 4 of the half cycle sampling points exceed the low limit threshold, the half cycle waveform

is considered to below the lower limit.

6) below the lower threshold half-cycle number: For example, if the set value is 2, it means that if two

consecutive half-cycles are below the lower limit, an over-voltage or over-current event is considered to

occur.

7) When the event occurs, the flag bit is generated. The user can check the system status bit (SYS_STS

system status register (0x74, SYS_STS)) and the flag bit (system interrupt status register (0x72,

SYS_INTSTS)).

8) The corresponding event flag can be configured by interrupt enable and IO port output.

9) Response time: When the half-wave number is set to 1 and enabled or disabled the high-pass filter,

the response time is 10 ms, that is, when the input signal exceeds the threshold, the event interrupt can

be output after a half cycle.

Vango Technologies, Inc. 142 / 151

V93XX Datasheet
12. Energy Accumulator

PA A_SE TYPE_SEL1 INMODE1

B_SE
PB L1

M
A_SE
QA Power L1
No
Load B_SE
U CF
QB L1
X Counter
PWRTH1 1

SA A_SE
L1 M 0
<0 Energy CF
SB B_SE
L1
U X
Accumulator Generator CF1
1 1
X ABS CF
SEL
PROCMODE1 CF2
A_SE TYPE_SEL1
RMSIA L1 Energy
No Load
B_SE
RMSIB L1 1

Constant1

A_SE
CH1 L1 Energy
Module 1
B_SE
CH2 L1

Energy
Module 2

Energy
Module 3

Energy
Module 4

Energy
Module 5

Energy
Module 6

Energy
Module 7

Energy
Module 8

Figure 12-1 Functional block diagram of energy bucket

The V93XX has eight energy accumulators, including two high-speed energy accumulators and six low-

speed energy accumulators. Each energy accumulators have four accumulation modes: power

accumulation, current RMS accumulation, constant accumulation, and configurable fundamental channel

accumulation.

The power accumulation is enabled by the channel an accumulation (A_SEL) and the channel B

accumulation (B_SEL), which can realize only accumulating channel A power, only accumulating channel

B power, and accumulating A and B power. Power can be selected for active power, reactive power and

apparent power by TYPE_SEL.

The current accumulation is enabled by the channel An accumulation (A_SEL) and the channel B

accumulation (B_SEL), which can realize only accumulating channel IA RMS, only accumulating channel

Vango Technologies, Inc. 143 / 151

V93XX Datasheet
IB RMS, and accumulating IA and IB RMS. Accumulating two-channel IA and IB RMS value can be selected

by TYPE_SEL to accumulate the summation or accumulation difference of two channels (RMSIA+RMSIB

or RMSIA-RMSIB).

The constant accumulation is not affected by enabling the A/B channel accumulation.

The power accumulation is enabled by the channel an accumulation (A_SEL) and the channel B

accumulation (B_SEL), which can realize only accumulating channel A power, only accumulating channel

B power, and accumulating A and B power. Power can be selected for active power, reactive power and

apparent power by TYPE_SEL.

Configurable fundamental channel accumulation, enabled by A channel accumulation (A_SEL) and B

channel accumulation switch, which can realize only accumulating fundamental channel 1 data,

accumulating only fundamental channel 2 data, accumulating fundamental channel 1 plus accumulating

fundamental channel 2.

There are four types of data operation that are accumulated for each input energy accumulator. Taking

the active power of two channels as an example, the operation method is as follows.

0: The energy accumulator only accumulates positive numbers. Only accumulate data with PA+PB>0.

If PA+PB<0, do not accumulate.

1: The energy accumulator only accumulates negative numbers (in this case, the actual accumulated

value is a positive value of the original value conversion). Only data with PA+PB<0 (abs (PA+PB)) is

added. If PA+PB>0, do not accumulate.

2: The energy accumulator accumulates the original value. Accumulate PA+PB.

3: The energy accumulator accumulates the absolute value. Accumulate abs (PA+PB)

12.1. High-speed Energy Accumulator

To enable high-speed energy accumulator 1, it needs to configure CALCEN1 (Bit[6]) in DSP_CTRL1 (Table

2-19 Metering Control Register 2 (0x03, DSP_CTRL1)). To enable high-speed energy accumulator 2, it

needs to configure CALCEN2 (Bit[7]) in DSP_CTRL1. The default accumulative acceleration of the high-

speed energy accumulator is 204.8 KHz, and 32768 Hz can also be selected by the energy accumulator

clock (bit23 in DSP_CTRL1).

High-speed energy accumulator supports CF output.

Vango Technologies, Inc. 144 / 151

V93XX Datasheet
12.2. Low-speed Energy Accumulator

The six low-speed energy accumulators are enabled by DGY_LC_EN (Bit[15]) in DSP_CTRL1 (Table 2-19

Metering Control Register 2 (0x03, DSP_CTRL1)). The default accumulated acceleration is 50 Hz.

The accumulation speed of low-speed energy accumulator is controlled by CURDAT_RATE (Bit[31]) in

DSP_CTRL0 (Table 2-18 Metering Control Register 0 (0x02, DSP_CTRL0)) and LCF_ACC (Bit[22]) in

DSP_CTRL1.

When CURDAT_RATE=0:

LCF_ACC=0, the accumulation period of the energy buckets 3, 4, 5, 6, 7, 8 is 20 ms;

LCF_ACC=1, the accumulation period of the energy buckets 3, 4, and 5 is 10 ms, and the energy buckets

6, 7, and 8 are not accumulated.

⚫ When CURDAT_RATE=0:

LCF_ACC=0, the accumulation period of the energy accumulators 3, 4, 5, 6, 7, 8 is 20 ms;

LCF_ACC=1, the accumulation period of the energy accumulators 3, 4, and 5 is 10 ms, and the

energy accumulators 6, 7, and 8 are not accumulated.

⚫ When CURDAT_RATE=1:

LCF_ACC=0, the accumulation period of the energy accumulators 3, 4, 5, 6, 7, 8 is 40 ms;

LCF_ACC=1, the accumulation period of the energy accumulators 3, 4, and 5 is 20 ms, and the

energy accumulators 6, 7, and 8 are not accumulated.

12.3. CF Output

V93XX supports 2 channels of CF. The CF output is configured by the Meter Control Register 1 (Table

2-19 Metering Control Register 2 (0x03, DSP_CTRL1)) to select the IO port output.

CF supports source selection. It can be selected from the energy accumulator 1 or the energy

accumulator 2.

CF supports polarity selection, pulse width selection, and accelerated weak-signal calibration.

Refer to the description of CF in Metering Control Register 1 (0x03, DSP_CTRL1) for details.

Vango Technologies, Inc. 145 / 151

V93XX Datasheet
12.4. Energy Accumulator Power-creep Detection

Energy accumulator anti-creep threshold. When anti-creep energy accumulator exceeds the

EGY_CRPTH and high-speed energy accumulator not exceeds the EGY_PWRTH, the accumulating value

of high-speed accumulator will be cleared.

There is a power-creep energy accumulating register for energy accumulator 1 and 2, which they have

the same accumulation speed.

User should configure threshold for the power-creep threshold register (EGY_CRPTH) and energy

accumulating threshold register (EGY_PWRTH). If the accumulating value of power-creep energy

accumulator register reaches the value of EGY_CRPTH first, the energy accumulating register will be

cleared, and system enter the power-creep status. When the accumulating value of energy

accumulating register reaches the value of EGY_PWRTH, the power-creep energy register will be

cleared, system start to work and operating normally.

The actual bit width of register EGY_CRPTH is 32bit. The register contents will be padded with 0s

automatically in the 4 least significant bits when the power-creep calculated. It would be calculated

after extended to 36 digits.

User can judge whether in power-creep status through SYS_STS (BIT19, BIT18) .

12.5. Active Accumulation uploading Interface

Active data uploading interface can configure pins, P0/ P1/ P2/ P3/ P4/ P5/ P6, to be the active data

interface through SYS_IOCFGX.

1. Asynchronous transfer mode by 1 data wire.

2. Interface configuration: 11-bit transmission (start bit + 8 data bit + parity bit + stop bit)

Communication baud rate: SPI communication data rate is 4800, it also can operate at 9600. UART

communication data rate is same as present baud rate, also double the present baud rate.

To enable the function of double baud rate if BIT17 setting to 1 at the metering control register 1 (Table

2-19 Metering Control Register 2 (0x03, DSP_CTRL1)).

3. Communication time interval: 20 ms/ 40 ms (the same to instantaneous power refresh time)

4. Frame header: 0x7D

Vango Technologies, Inc. 146 / 151

V93XX Datasheet
5. Checksum: the energy accumulator 1 accumulating data plus the energy accumulator 2 accumulating

data. Total accumulate 8 bytes and reverse them, then plus 0x33 to obtain the checksum.

6. Frame length: 10 bytes

7. To enable this block by BIT 16 of metering control register 1 (DSP_CTRL1).

Protocol format as below:

frame the energy accumulator 1 the energy accumulator 2 checksum

header accumulating data accumulating data

0x7D 4 bytes 4 bytes 1 byte

Vango Technologies, Inc. 147 / 151

V93XX Datasheet
13. Signal IO Ports

13.1. Overview

The V93XX provides up to seven signal outputs, and seven output signals are used to map the internal

output sources.

13.2. Functional Description

The seven signal output ports can be configured as CF output, energy upload interface, waveform active

upload DMA channel interface, zero-crossing square wave and four types of interrupt output. The signal

output port can be set to output a single signal, or it can be set to output certain types of interrupt

signals. See Table 2-14 IO Configuration Register 0 (0x7D, SYS_IOCFGX0) and Table 2-16 IO

Configuration Register 1 (0x7E, SYS_IOCFGX1) for details.

1st type interruption: current zero-crossing interruption, voltage zero-crossing interruption, high-

speed energy accumulator 1/2 overflow interruption.

2nd type interruption: waveform refreshes interruption, instantaneous RMS refresh interruption,

average RMS refreshes interruption, instantaneous power value refresh interruption, average power

value refreshes interruption, waveform storage finish interruption, waveform storage overflow

interruption and waveform data upload finished interruption.

3rd type interruption: IB channel under-current interruption, IB channel over-current interruption,

IA channel under-current interruption, IA channel over-current interruption, voltage channel under-

voltage interruption, voltage channel over-voltage interruption, voltage dip interruption and voltage

swell interruption.

4th type interruption: SPI communicating error interruption, UART communicating error interruption,

parameters self-checking error interruption, phase measurement finished interruption, power-down

interruption, reference error interruption, CTI external input clock error interruption and RAM self-

checking error interruption.

Figure 13-1 Functional Block Diagram of signal IO ports

Description:

Vango Technologies, Inc. 148 / 151

V93XX Datasheet
1) When the output port is used as the CF output, it is supported to set the width of the output pulse

and select the output polarity. When the output period is less than twice the CF output pulse width, CF

is output at a duty cycle of 50%. For example, if the output width is 80 ms and the output period is less

than 160 ms, it will be output according to the duty cycle of 50%.

2) Using the UART protocol when the TX output for energy upload.

3) When used as the interrupt event output port, the output port defaults to low level output. If the

event occurs, it outputs a high level until the user clears the event flag bit, and the output state returns

to the default level.

4) When used as a zero-crossing square wave output, the output port defaults to a low-level output.

If configured as a positive zero-crossing, the IO port flips when the signal transitions from a negative

signal to a positive signal.

5) When used as a DMA output port, the SPI protocol is required, and the user is required to select

the SPLK, SPDO, and SOCS ports.

Vango Technologies, Inc. 149 / 151

V93XX Datasheet
14. Outline Dimensions

8.40
8.20
8.00
Unit：mm

1.05
0.75
0.20
0.15

1.25 BSC
24 13
5.50
8.00
7.80
7.60

5.30
5.10

1 12

0~8°
0.37
0.65BSC
0.29
1.75

0.80
1.85

1.65

0.85

0.75
2.00 MAX

0.25
0.05

Figure 14-1 Outline dimension for V9381

A
A

θ3
A X
A1

Dimensions (Unit: mm)

D
Symbol Min. Nom. Max.
16 9 θ1
A 1.40 1.73
A1 0.05 0.18
A2 1.35 1.55
h

h θ4 E 5.84 6.24
E1 3.84 4.04
D 9.90 10.10
L 0.40 0.70
e 1.27TYP
θ2 L
b 0.36 0.46
L1
E1

b1 0.36 0.46
E

b c 0.2TYP
c1 0.2TYP
“X” b1
θ1 8°TYP
θ2 8°TYP
θ3 4°TYP
c1
c

θ4 15°TYP

1 2 3 e
8 A-A
Index Area (0.25D+0.75E)

Figure 14-2 Outline dimension for V9360

Vango Technologies, Inc. 150 / 151

V93XX Datasheet
θ3 θ1
h Dimensions (Unit: mm)
h

A3
Symbol MIN NOM MAX
R1 A 1.35 1.55 1.75
A2 R
A

A1 0.05 0.15 0.25

B A2 1.25 1.40 1.65

L2
A3 0.50 0.60 0.70
B θ2 θ b 0.38 - 0.51
A1

θ4 b1 0.37 0.42 0.47

L
c 0.17 - 0.25
(L1) c1 0.17 0.20 0.23
D D 4.80 4.90 5.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27BSC
L 0.45 0.60 0.80
b L1 1.04REF
L2 0.25BSC
b1 R 0.07 - -
R1 0.07 - -
c1 c h 0.30 0.40 0.50
θ 0° - 8°
θ1 15° 17° 19°
E
E1

θ2 11° 13° 15°

Section B-B θ3
θ4
15°
11°
17°
13°
19°
15°

e b

Figure 14-3 Outline dimension for V9340/V9340T

Vango Technologies, Inc. 151 / 151

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