SCHEME OF EVALUATION SPRING END SEMESTER-2024

EMBEDDED SYSTEM DESIGN AND APPLICATIONS

EC- 3033

Q1a What are the three main components of the Embedded System?

The three main components of an embedded system are:

1. It Embeds Hardware similar to a Computer
2. It Embeds Main Application Software: Application software may Concurrently
Perform a Series of Tasks
3. It Embeds a Real Time Operating System(RTOs) that Suprevises the Application
Software running on Hardware.

Q1b Name the steps involved in Embedded system design.

1. Requirements
2. Specification
3. Architecture
4. Components
5. System Integration

Q1c List out features of 8051 microcontroller

1. 8-Bit Microcontroller
2. 128 Bytes of RAM
3. 4 Kb of On-Chip ROM
4. Two Timers
5. One Serial Port
6. 4 I/O Ports
7. 6 Interrupt Sources:

Q1d.

11.0592/12= 921.6kHz ; T= 1/921.6kHz = 1.085 µs

MOV R2, #200 1 Machine Cycle = 1 x 1.085 µs = 1.085 µs

Time to execute this instruction = 1.085 µs

Q1e. what is the purpose of watchdog timer in a PIC microcontroller and how is
it used?
The purpose of a watchdog timer in a PIC microcontroller is to monitor the operation
of the microcontroller and reset it if it becomes unresponsive or enters into an
unexpected state.The watchdog timer is typically used to enhance the reliability of the
system by ensuring that the microcontroller continues to operate correctly, even in the
presence of software bugs, glitches, or unexpected conditions.

How it's used:

The watchdog timer is initially enabled by the software.
The software periodically resets or reloads the watchdog timer before it times out.
This prevents the watchdog timer from resetting the microcontroller.
When the watchdog timer expires, it generates a reset signal, causing the
microcontroller to reset and restart its operation.

Q1f.

(¼)x10 MHZ= 2.5 MHz

(1/64)x 2.5 MHz = 39062.5Hz

T = 1/39062.5 = 25.6 µs

Q1g. Name the four signals in SPI bus and specify their roles

The four signals in the Serial Peripheral Interface (SPI) bus are:

SCK (Serial Clock)

MOSI (Master Output Slave Input):
MISO (Master Input Slave Output):
SS(Slave Select/Chip Select):

Q1h. How many instruction sets does arm have and state their names.
ARM supports Three instruction sets :

ARM (32-bit)
Thumb (16-bit)
Jazzle(8-bit)

Q1i.

MOV R2, R1, LSR#3

R1=0X9A

After execution R2= 0x13

Q1j. Define the preemptive and nonpremptive type of scheduling.

Preemptive Scheduling:

In preemptive scheduling, the operating system can interrupt a currently running task
to allocate the CPU to another task with higher priority.Tasks are assigned priorities,
and the scheduler selects the task with the highest priority that is ready to run.The
currently running task can be preempted (paused) if a higher-priority task becomes
ready to run.

Examples of preemptive scheduling algorithms include Round-Robin, Shortest

Remaining Time First (SRTF), and Priority Scheduling.
Non-preemptive Scheduling:
In non-preemptive scheduling, once a task starts executing, it continues to run until it
completes, voluntarily yields the CPU, or blocks for I/O.
The operating system cannot interrupt a task that is already running, even if a higher-
priority task becomes ready to run. Tasks are typically assigned priorities, but the
scheduler only selects the next task to run when the currently running task voluntarily
relinquishes the CPU. Non-preemptive scheduling relies on tasks cooperating by
yielding the CPU when they are done or waiting for an event.

Examples of non-preemptive scheduling algorithms include First Come, First Served

(FCFS) and Shortest Job Next (SJN).

Q2a. Explain memory organization of Princeton and Harvard architecture. Give

memory map a debit card with a neat sketch.
Q2b. Draw and explain program memory and data organization of 8051
microcontroller.
List out the addressing modes of 8051 and explain any 5 addressing modes with
suitable example.
Immediate Addressing: In immediate addressing mode, the operand is specified
directly in the instruction.
Example: MOV A, #25h

This instruction moves the immediate value 25h (hexadecimal) into register A.

Direct Addressing: In direct addressing mode, the operand is the address of a

memory location where the data is stored.
Example: MOV A, 30h

This instruction moves the contents of the memory location 30h into register A.

Register Addressing: In register addressing mode, the operand is the contents of a

register.

Example: MOV R2, A

This instruction moves the contents of register A into register R2.

Register Indirect Addressing: In register indirect addressing mode, the operand is

the contents of the memory location pointed to by a register.

Example: MOV A, @R0

If R0 contains 50h, this instruction moves the contents of the memory location 50h
into register A.

Indexed Addressing: In indexed addressing mode, the operand is obtained by adding

an offset to the contents of a register.

Example: MOV A, 30h + R2

If R2 contains 05h, this instruction moves the contents of the memory location 35h
(30h + 05h) into register A.

Q3a. Draw and explain PORT pin operation for two cases of PIC 18 series
microcontroller. Assume: First case when PIC microcontroller places Logic 0 on
data bus.

3 (b)Write a short note I2C and USB.

I2C (Inter-Integrated Circuit): I2C is a synchronous, multi-master, multi-slave serial

communication protocol developed by Philips Semiconductor (now NXP
Semiconductors). It is widely used for communication between integrated circuits and
peripherals in embedded systems, consumer electronics, and other applications. Key
features of I2C include:
Connecting a MASTER (PIC) to One or more number Slave IC’s using only two
wires for the Connection.(SCL (Serial Clock) SDA(Serial Data))
• Modes of Operation :
• STANDARD MODE
• FAST MODE
• HIGH SPEED MODE
Two-Wire Communication: I2C uses only two wires for communication: a serial data
line (SDA) and a serial clock line (SCL).

STANDARD MODE :
 Maximum Data Rate : 100 kbits/s
 7-bit Addressing
 The Maximum No of Slave 112
FAST MODE :
Maximum Data Rate : 400 kb/s
SCL & SDA Lines : High impedance
HIGH SPEED MODE:
Maximum Data rate : 1.7 Mb/s
3.4 Mb/s
36 times faster than Standard mode

USB (Universal Serial Bus):

USB is a popular serial communication standard used for connecting peripherals to

computers and other host devices. Developed in the mid-1990s, USB has evolved into
a versatile and widely adopted interface for a wide range of devices. Key features of
USB include:
USB Device communication is based on Pipes (Logical Channels)

A pipe is a connection from the host controller to a Logical Entity, found on a device
and named “an Endpoint”.

A USB device can have up to 32 Endpoints

Maximum of 30 endpoints for normal use

Two types of Pipes :

 STREAM
 MESSAGE
A STREAM Pipe is a Uni-directional pipe connected to unidirectional end point that
transfers data using an ISOCHRONOUS, INTERRUPT OR BULK TRANSFER

A Message Pipe is a Bidirectional pipe connected to a Bidirectional Endpoint that is

exclusively used for control data flow.

An endpoint is built into the USB device by the manufacturer.

Q4a. Explain the operation of timer1 with a neat diagram.

Q4b.

In CAN terminology,
A Logical 1 on the bus is called “recessive” and Logical 0 is “dominant” When all
nodes are transmitting 1’s, the bus is said to be in recessive state,
When a node transmits a “0”, the bus is in the dominant state. Data are sent on the
network in Packets known as Data Frames.

The two types of Frame Format

Standard CAN protocol or Base Frame Format

Extended CAN or ExtendedFrame Format

Error Detection and Correction :

The CAN Protocol defines five different ways of detecting errors

1. Bit Monitoring :
Ex : if a bit “1” is placed on the bu,s but signal Received at the Receiving end
bit “0” : Bit error
2. Bit Stuffing
Ex: If 5 consecutive bits of the same level 1 1 1 1 1 , then add sixth bit of
opposite level “0”
3. Stuff error : Receiver is not received the exact data

4. Frame Check
Ex : CAN messsage have a fixed format
if a CAN Controller detects an invalid value in one the fileds ( CRC Delimter,
ACK Delimeter) Frame Check error
5. Acknowledgment Check
Message with Dominant “ 0s” level : ACK field
Message with Recessive “1s” : if transmitter can’t detect a dominant level
in the ACK slot, an Acknowledgement error is signalled.
6.Cyclic Redundancy Check (CRC) :
Each Message features 15-bit Cyclic Redundancy Check Sum if any other
node that detects a different CRC message, CRC error

Q5a. Explain pipelining scheme of ARM7TDMI and ARM9TDMI. With a neat

diagram explain the different general purpose registers of ARM processors.

Pipelining Scheme of ARM7TDMI and ARM9TDMI:

Q5(a) General Purpose Registers of ARM Processors:
Q5b. Explain briefly three different instruction sets of ARM processors. Explain
the operation of the following ARM instructions.
i. BIC R2, R4, #0X25
ii. TST R4, 0X25

BIC R5, R2, #0x25 (Bit wise Clear)

R2 AND (NOT “0x25”)

Final Result Copied in to R5

TST R4,0X25 (Test Instruction)

R4 AND 0x25

After execution CPSR registers gets update the flags and Result won’t store in any
register.

ARM State : 32-bit Instruction set : When processor is started

Thumb State : 16-bit Instruction set ; By Altering bit T bit in CPSR
Jazzelle state : 8-Bit Instruction set : By Altering bit J-bit in CPSR
To get High code density, T & J states are provided
T=0 ; CPSR : ARM Processor : ARM State
T=1 ; CPSR : ARM Processor Thumb state
Thumb state operation can achieve only by using BX & BLX instructions is possible.

Q6a. List out different task state and explain with a state diagram.

Possible states in for a Task

• Dormant
• Ready
• Running
• Blocked

Dormant
• If a task remains Unexecuted for a long time or not scheduled for processing
for a long time it is termed as “Dormant”.
.
READY
If any other task with higher priority is getting executed by that time the other task
which is created will have to “WAIT” until the higher priority task execution is
complete.
This state of the task which can be executed but waiting for other one to complete is
called “READY State”.
Running :
When a task is getting executed i.e is being given the processor time, it is referred to
be as running state
Blocked :
When a Task is being executed but at the some point in time it requires some external
I/P, it goes blocked.

6(b) Write a short note on RMS and EDF of RTOS.

Rate-Monotonic Scheduling (RMS):

RMS is a static priority scheduling algorithm used in real-time systems. It assigns

priorities to tasks based on their periods, with shorter period tasks having higher
priorities. The task with the shortest period (highest priority) is scheduled first.
RMS assumes that tasks are periodic and have known execution times.

It is optimal for scheduling periodic tasks with deterministic execution times when the
system load is less than 100%. RMS guarantees schedulability if the sum of the CPU
utilization of all tasks is less than or equal to the number of processors (for
multiprocessor systems).

RMS does not consider deadlines explicitly, which can lead to task missing deadlines
if overloaded or if tasks have variable execution times.
Earliest Deadline First (EDF):

EDF is a dynamic priority scheduling algorithm used in real-time systems. It assigns

priorities to tasks based on their deadlines, with the task having the earliest deadline
having the highest priority.

EDF dynamically adjusts task priorities as deadlines approach, ensuring that tasks with
impending deadlines are scheduled first.

EDF is optimal for scheduling periodic and aperiodic tasks with arbitrary execution
times, as it minimizes the number of missed deadlines under certain conditions. Unlike
RMS, EDF explicitly considers task deadlines, ensuring that tasks meet their deadlines
as long as the system is schedulable.

EDF may suffer from priority inversion and may require additional mechanisms (e.g.,
priority inheritance) to mitigate these issues in practice.

EDF is more flexible than RMS but may incur higher scheduling overhead due to
frequent priority changes.

6(b)

p1= 50 , t 1=25 , p2=75, t2=30

P1=50 (Deadline) P2 Deadline

P1 P1 P2
0 10 20 25 30 40 50 55 60 70 75

P1 Deadline is 50 misses deadline for completion of Burst time, So these two

processes Cannot be schedule using Rate Monotonic Scheduling

p1=50 p2=75 p1 p1

P1 P2 P1 P2 P1 P2 P1
0 10 20 25 30 40 50 55 60 70 80 90 100 110 120 125130135 140 150

EDF Can be scheduled for these processes.

P1 has earliest deadline, so its initial priority is higher than that of process p2.
P2 begins running at the end of the cpu burst time for p1=25.
P2 Higher priority than p1 because its next deadline at time p2=75
At second deadline p1 at 100 p2 is preempted because p1 has an earlier deadline.
At 125 p2 resumes the execution and completes at 135

1= 25 p2=75 t2=30