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Sequential Logic Design

Introduction
 Sequential circuits are digital circuits that are used to store and use the
previous information to determine the output.
 Sequential circuits include memory elementsto store the binary information as
given in the figure 3.1.
 It’s constructed using flip flop, counter and shift registers.

Fig 3.1 – Sequential Circuit

3.1 Flip flop

 Flip-flop is a basic digital memory circuit.
 It can store binary information (1 and 0).
 A flip-flop is constructed using logic gates.
Types of Flip Flop
1. SR flip-flop 2. JK flip-flop 3. T flip-flop 4. D flip-flop

3.1.1 SR flip flop

 It is a two input (S- Set and R-Reset) and two output ((Q+1) and (Q+1)') flip flop
along with clock input.
 There are four different input combinations and four different modes of
operations.
 The fourth input combination (S = 1 and R =1) is called as invalid state.
 Output is changing at the rate of clock.
 Truth table and circuit diagram of SR FF is shown in the figure 3.2.
 SR FF - Block Diagram SR FF - Logic diagram

INPUT OUTPUT Mode

S (Set) R (Reset) (Q+1) (Q+1)’
0 0 Q Q’ No change
0 1 0 1 Set
1 0 1 0 Reset
1 1 X X Invalid

SR FF - Truth table
Fig 3.2 SR FF

3.1.2 JK flip flop

 It is a two input (J and K) and two output ((Q+1) and (Q+1)') flip flop along
with clock input.
 There are four different input combinations and four different operations.
 The fourth input combination (J = 1 and K =1) is toggles or invert the output (1
to 0 or 0 to 1).
 Output is changing at the rate of clock.
 Truth table and circuit diagram of JK FF is shown in the figure 3.3.

JK FF - Block Diagram JK FF - Logic diagram

INPUT OUTPUT Mode

J K (Q+1) (Q+1)’
 0 0 Q Q’ No change
0 1 0 1 Set
1 0 1 0 Reset
1 1 Q’ Q Toggle

JK FF - Truth table

Fig 3.3JK FF
3.1.3 D flip flop (Data flip flop)
 It is a one input (D) and two output ((Q+1) and (Q+1)') flip flop along with
clock input.
 There are two different input combinations and two different operations.
 Output is changing at the rate of clock.
 It is also called as data flip flop.
 Truth table and circuit diagram of JK FF is shown in the figure 3.4.

D FF - Block Diagram D FF - Logic diagram

INPUT OUTPUT Mode

D (Q+1) (Q+1)’
0 Q Q’ No change
1 1 0 Set

D FF - Truth table

Fig 3.4D Flip Flop

3.1.4 Concept of Triggering

Triggering is the process of changing the output by clock input . Digital circuit uses
edge triggering and level triggering as two different types of triggering methods to
change the output from one state to another state.
3.1.4.1 Edge Triggering
 Output transition occurs either at the positive (rising) edge or negative (falling) edge of
the clock.

Positive Edge triggering Negative Edge triggering

3.1.4.2 Level Triggering

 Output transition occurs either at the high level (1) or low level (0) of the clock.

High level triggering Low level triggering

3.1.5 Applications of Flip flop
 Flip Flops are used as the basic storage unit in digital electronics.
 Flip Flops are largely used as shift registers and for the transfer of data.
 Flip Flops also used in digital signal processing circuits.
 Flip Flops are used as counters.
 It is used in the frequency dividers circuits.

3.2 Registers
3.2.1. Shit Registers
 A Shift Register is a device that is used to store more than one bits of
information.
 In register, multiple flip-flops are connected together to store multiple bits of
data.
 Shift registers are sequential circuit.
  Shift registers can move or shift the stored data.
Types of shift registers
1. Serial In Serial Out shift register (SISO)
2. Serial In parallel Out shift register (SIPO)
3. Parallel In Serial Out shift register (PISO)
4. Parallel In parallel Out shift register (PIPO)
3.2.1.1 Serial In Serial Out shift register (SISO)
 The symbol and logic diagram of four bit SISOusing D FFis shown in figure 3.6
and 3.7.
 It has four D flip flops connected serially.
 Serial datais applied at the D input of the first FF.
 The Q output of the first FF is connected to the D input ofthe second FF, the Q
output of the second FF is connected to the D input of the third FF and the
Qoutput of the third FF is connected to the D input of the fourth FF.
 The data is outputted from theQ terminal of the last FF

Figure 3.6–SISO Symbol

Figure 3.7 - four bit SISO using D FF

3.2.1.2 Serial In parallel Out shift register (SIPO)
 The symbol and logic diagram of four bit SIPOusing D FF is shown in figure 3.8
and 3.9.
 In this type of register, the data bits are entered into the register serially.
 Data stored in the register is shifted out in parallel form.
  Once the data bits are stored, each bit appears on its respective output line and
allbitsareavailable at the same time.

Figure 3.8 – SIPO Symbol

Figure 3.9 - four bit SIPO using D FF

3.2.1.3 Parallel In Serial Out shift register (PISO)

 The symbollogic diagram of four bit PISOusing D FF is shown in figure 4 and
4.1.
 The data bits are entered at the same time into all the four D FF.
 The data bits are transferred out of the register serially, i.e. on a bit-by-bit.
 In PISO, Shift and Load input is used to provide the input data and get the
output from PISO.
 Figure 4 – PISO Symbol

Figure 4.1 - four bit PISO using D FF

3.2.1.4 Parallel In parallel Out shift register (PIPO)

 The symbol logic diagram of four bit PIPO using D FF is shown in figure 4.2 and
4.3.
 The data bits are entered at the same time into all the four D FF.
 The data bits are transferred out fromall the four D FF at the same time.

D - FF
D - FF D – FF D - FF

Figure 4.2 – PIPO Symbol

 Figure 4.3 - four bit PIPO using D FF

Application of shift registers

 Temporary data storage.
 Data transfer.
 Data manipulation (arithmetic right and left shit operation on binary data).
 The serial-in serial-out and parallel-in parallel-out shift registers are used to
produce time delay to digital circuits.

3.2.2. Serial to Parallel Converter

3.2.3. Parallel to Serial Converter

3.3 Counters
 Counter is a sequential circuit
 It is used as a counting device and it can count the specific event in the system.
 It is constructed by interconnecting the Flip flops.
Classification of counters
1. Asynchronous counters:
 In Asynchronouscounters, all the flip flops in the counters will not
change at the same time (flip flops are not in sync with clock).
 The clock signal of the all the flip flops arenot connected to the common
source.
 The Asynchronouscounters are also called as ripple counters.
 Up, down and decade counters are asynchronous counters.
 2. Synchronous counters:
 In Synchronous counters, all the flip flops in the counters will change at
the same time (flip flops are in sync with clock).
 The clock signal of the all the flip flops areconnected to the common
source.
 Ring and Johnson counters are synchronous counters.

3.3.1 Asynchronous (ripple) Up counters

 Asynchronousupcounter is used to count in the upwards direction (0, 1, 2, 3, 4,
5 and so on).
 It is constructed using three JK flip flops.
 The Logic diagram of 3 bit asynchronous up counter is shown in the figure 4.4.

Fig 4.4 – Logic circuit diagram of 3 bit Asynchronous up Counter

CLK Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Table 1.1 – Truth table of 3 bit Asynchronous up Counter

 Fig 4.5 – Timing diagram of 3 bit Asynchronousup Counter
Operation of 3 bit Asynchronous up Counter
 All the JK flip flops in the counter are negative edge triggered.
 All the flip flops are considered in toggle mode (J = 1 and K = 1).
 The truth table of the 3 bit Asynchronous up Counter is given in the table 1.1
 Timing diagram of 3 bit Asynchronous up Counter is shown in the figure 4.5
 Q0 will change its states at the every clock cycle.
 Q1 will change its states when Q0 change from 1 to 0.
 Q2 will change its states when Q1 change from 1 to 0.

3.3.2. Synchronous down counters

3.4 Decade Counter

 Decade Counter is an asynchronous up counter.
 It is counts in 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
 Total counting states are ten, hence it’s called as decade counter.
 It is constructed using four JK flip flops.
 The Logic diagram of decade counter is shown in the figure 4.6.
 Fig 4.6 - Logic diagram of decade counter

Operation of decade Counter

 All the JK flip flops in the counter are negative edge triggered.
 All the flip flops are considered in toggle mode (J = 1 and K = 1).
 The clock input of every flip flop is connected to the output of next flip flop,
except the last one.
 The output of the NAND gate is connected in parallel to the clear input ‘CLR’ to
all the flip flops
 When the Decade counter is at REST, the count is equal to 0000. This is first
stage of the counter cycle.
 When we connect a clock signal input to the counter circuit, then the circuit will
count the binary sequence.
 At the 10th (1010) counting state, the NAND gate output is connected to clear
input, so it resets all the flip flop stages in decade counter.
 This means the pulse after count 9 will again start the count from count 0 and it
is depicted into state diagram in the figure 4.7.

CLK X3 X2 X1 X0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
 9 1 0 0 1

Table 1.2 – Truth table of decade counter

Fig 4.7 – State diagram decade counter

3.4.1 Synchronous counter Ring counter

 Ring counter is a synchronous counter in which all the FFs aretriggered simultaneously
(in parallel) by the clock-input pulses.
 The Q output of each stage is connected to the D input of the next stage, but the
Q output of the last FF is connected back to the D input of the first FF.
 All the FFs are arranged in a ring and, therefore, the name ring counter.
 Four bit ring counter is shown on the figure 4.8.
 Initially, the ring counter is loaded with ‘1000’.
 After the every clock pulse, the counter moves to ‘0100’ -> ‘0010’ -> ‘0001’ and
again to the initial state ‘1010’as shown in the figure 4.9.

Fig 4.8 – Logic diagram of 4 bit ring counter

 Fig 4.9 - State diagram Table 1.3 - Truth table

3.4.2 Twisted ring counter (or) Johnson counter

 Johnson counters are synchronous counters in which all the FFs are triggered
simultaneously (in parallel) by the clock-input pulses.
 The Q output of each stage is connected to the D input of the next stage, but the
Q’(Inverted Q) output of the last FF is connected back to the D input of the first
FF.
 Four bit twisted ring counter is shown on the figure 5.
 Initially, the state of the counter is 0000. After each clock pulse, the
level of Q1 is shifted to Q2, the level of Q2 to Q3, Q3 to Q4 and the level of Q4 to
Q1.
 Four bit Johnson counter, has eight different sequence as shown in the state
diagram (fig 5.1) and truth table (table 1.4).

Fig 5 – Logic diagram of 4 bit johnson counter

 Fig 5.1 - State diagram Table 1.4 - Truth table
3.4.3 Application of Decade counters
 Digital watches
 To create time delays
 To generate pulse trains
 Frequency counters/dividers

Review Questions
MCQ QUESTIONS
1. Flip-Flop is used to ___________binarybits
a. Add b. Store c. Subtract d. None
2. T flip-flop is used to ________ output
a. Set b. No change c. Reset d. Toggle/Invert
3. Which is called as data flip-flop?
a. SR FF b. D FF c. T FF d. JK FF
4. There are ____ types of shift registers
a. 3 b. 2 c. 4 d. 6
5. Counter is a_______ circuit
a. Combinational b. Sequential c. Both d. None
6. Ripple counteris a________ counter
a. Asynchronous b. Synchronous c. Both d. None
7. Number of counting states in decade counter is__
a. 9 b. 8 c. 10 d. 11
8. Counter are constructed using_____
a. Adder b. flip-flops c. Mux d. None
9. In _____ counter all the flip-flops are connected with same clock source
a. Synchronous b. Asynchronous c. Ripple d. None
10. Delay is generated using______
a. Adder b. Counter c. Mux d. None

ANS: 1-b, 2-d, 3-b, 4-c, 5-b, 6-a, 7-c, 8-b, 9-a, 10-b.