2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)

Simulation Study of a Junctionless Double Gate

Tunnel Field Effect Transistor in 20nm Channel Length
Sadhana Subhadarshini Mohanty1,Pradipta Dutta2, Jitendra Kumar Das3
School of Electronics Engineering, KIIT Deemed to be University
Bhubaneswar,India
1mohanty.sadhana031@gmail.com, 2pduttafet@kiit.ac.in, 3jkdasfet@kiit.ac.in

Abstract—In this paper, a Junctionless Double Gate Tunnel FET (JL- also improved by taking work function difference and high
DGTFET) has been designed and the performance is analyzed using Sentaurus dielectric constant material and spacer [22].
2D simulation technique. In JLT, uniform and heavy doping concentration is
In this paper, the simulated structure and characteristics
taken all over the source, channel and drain regions. Like TFET, tunneling in
junctionless tunnel field effect transistor (JLTFET) also occurs due to BTBT of JL-DGTFET is explained. The operational principle of
mechanism. This paper comprehensively presents the novel architecture of the Junctionless TFET is analogous to TFET which is explained in
JL-DGFET which shows much promise in resolving the certain important issues Section II. In Section III, the electrical characteristics of the
related to the limitations of the conventional MOSFET and CMOS industry.
device is performed by introducing different dielectric constants
From dc analysis of JL-DGTFET, high ON-current about ~10-3Amp and very
low OFF-current about ~10-6 Amp are obtained which signify very low leakage set as gate dielectric, different gate and drain biases. The
currents and high ON-to-OFF current ratio. JLFET is usually popular due to conclusion of this work is finally summarized in Section IV.
lesser number of fabrication steps and less production cost comparing to other
contemporary logic devices. Here device is simulated with the variation of II. DEVICE STRUCTURE AND SIMULATION
different gate dielectric constant, gate and drain biases.
The schematic structure of a junctionless p-type channel
Keywords—Junctionless transistor (JLT), Band-to-Band Tunneling (BTBT),
Tunnel Field Effect Transistor (TFET), JL-DGTFET. double gate TFET (JL-DGTFET) is shown in Fig. 1.This JLT
having two gates; one front gate at the top and one back gate at
I. INTRODUCTION the bottom. The JLTFET is mainly a transistor with no
Continuous scaling of channel length to sub 20nm regime, junctions (i.e. junctionless) including uniform doping all over
Metal-Oxide-Semiconductor FETs yield objection in fabrication the source, channel and drain regions [21]. Considering source
as it needs addition of very high impurity carrier concentration as heavily doped p-type, the JLTFET is made to perform as
at the Source and Drain(S/D) junctions [1]. So further similar to TFET where ON and OFF states are maintained for
fabrication is rather impossible in sub 20nm regime and it gives different gate voltages at a constant drain bias, Vd. When a
rise to the problem of short-channel-effects (SCEs) and leakage voltage is applied to the gate, after reaching to the threshold
currents [1].To replace this conventional FETs and to fulfill the point, the band bending occurs so that electron starts tunneling
present requirement for ultra-low power applications, tunneling from the source valence band to the channel conduction band to
FETs (TFETs) [3][5] structure is introduced due to its unique make the device ON [23].
properties of low IOFF and low sub threshold slope (SS <60
mV/decade) [2]-[8]. The on-state drive current of TFET
depends upon the band-to-band tunneling (BTBT) mechanism
[8] and the limitation of the drive current at ON state [9] is
improved by the Junctionless transistor(JLT) [10][13].This new
transistor architecture has been governed by J. P. Colinge [11]
in the year 2011.The transistor enhances the device
performances as it has less fabrication complexity and low cost Fig. 1: Structure of Junctionless double gate transistor
[14][15].At zero gate bias, the junctionless transistor is fully
volume depleted so that in the off state, very less amount of TABLE 1: Parameters and its related value taken for the simulation
Parameter Value taken
OFF current is obtained. With the application of a gate bias
Channel length(Lch) 20nm
(positive for n-channel),the JLT satisfy flat band condition Thickness of gate dielectric material (Tox) nm
(VGS=VFB) and further increasing the gate bias, it enters into the Junction depth or body thickness(Tsi) 10nm
accumulation region with a high ON-current [17].As the Gate height 10nm
resistance of deeply doped semiconductor is controlled by the Doping concentration(NA) 1×1019 cm−3
gate electrode of the junctionless transistor, it is named as gated Gate bias (Vg) 0.5 V to 2 V
resistor [16].Becoming a promising device in future technology, Drain bias (Vd ) 0.5 V to 2 V
new JLT devices have been proposed such as SOI(Silicon-on- Dielectric material r EOT
Insulator) and BP(bulk planar) JLFET, silicon nanowire (Si- Dielectric SiO2 3.9 2nm
NW) junctionless transistors [11][18],GAA(Gate-all-around) constant(εr) Si3N4 7.5 1.04nm
And Al2O3 0.86nm
JLFET [19].Due to good dc characteristics and low sub- Effective Oxide HfO
2 25 0.31nm
threshold slope of TFET [8] and high ON current of Lilienfeld’s Thickness(EOT)
La2O3 30 0.26nm
JLFET [14], the Junctionless TFET(JLTFET) was proposed by
TiO2 80 0.09nm
B. Ghosh et al. [20] integrating the advantages of both the
transistors, TFET and JLFET .The performance of JLTFET is

978-1-5386-8333-0/18/$31.00 ©2018 IEEE

 III. RESULTS AND DISCUSSION for less value of gate bias. It happens due to the existence of
In this section, we have done all simulations using Sentaurus potential barrier at the drain channel boundary in ON state.
TCAD with nonlocal BTBT model for justifying the
accumulation of current due to the tunneling of electron from
source region to channel region of the regime [24]. Considering
high doping concentration (1019cm-3), a band gap narrowing
(BGN) model was enabled using Old Slotboom BGN model.
The effect of high dielectric constant and biases on device
characteristics is presented here based on simulation results.
Fig. 2 shows the transfer characteristics of the device of a
20nm gate length JLT at constant Vd=1V with different gate
dielectric constants. Since it is a p-channel device, from the
simulation result it is observed that by increasing dielectric
constant, OFF current reduces while change in the ON current
is almost negligible.

Fig. 4: ID~VDS graph for Junctionless double gate TFET with different gate
biases.Lch=20nm,Tsi=10nm,Tox=2nm(SiO2) and VG varies from 0.5V to 2V.

IV. CONCLUSION

We have designed and simulated a 2D 20nm JL-DGTFET

device in Sentaurus TCAD. The characteristics of the device are
presented in previous sections. It is observed that JL-DGTFET
shows better ON current without pn-junction as comparable to
conventional TFET. Also JL-DGTFET has simpler fabrication
steps and less prone to design variability. The proposed JL-
DGTFET with high gate dielectric constant material offers
better ON current about ~10-3Amp and OFF current of ∼10-
6
Fig. 2: ID~VGS plot for Junctionless double gate TFET with different Amp.
dielectric constants. Lch=20nm,Tsi=10nm,Tox=2nm and VD=1V.
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