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1158 CS F342 20240527010246 Mid Semester Question Paper

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72 views4 pages

1158 CS F342 20240527010246 Mid Semester Question Paper

Uploaded by

tejatejeswar6
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

II SEMESTER 2023-2024
CS F342 COMPUTER ARCHITECTURE
COMPREHENSIVE EXAM PART A (CLOSED BOOK)
TIME: 60 Min. 18/05/2024 MM: 30
IDNO: NAME:

Q1. Explain in brief the ‘From Target’ delayed branch technique. [2]

Q2. Explain in brief the working of Column Associative cache. [2]

Q3. What do you understand by ‘Strided prefetch? Where is it used? [2]

Q4. Explain the term ‘miss under miss’. [2]

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Q5. Consider the pipelined datapath shown in Figure below.
(a) Describe the difficulty in executing the following instructions in this datapath. How many stall cycles
(if any) must be inserted to correctly execute this code?
Sw+ rs,rt,imm
Beq rs, rt, Label

Sw+ rs,rt,imm is a post increment store function which is coded as I type instruction. It does the
following task: M[R[rs]]  R[rt]
R[rs]  R[rs] + imm
Also show the changes required in datapath to be able to execute sw+ instruction

(b) Show how the number of stalls (if any) could be minimized with forwarding in the figure below. Give
the governing equations for the forwarding/hazard detection unit. [10]

EQUATIONS:

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Q6. A single-issue, statically-scheduled, deeply pipelined processor is executing a program. During the
entire program run, the processor commits a total of 1,000,000 instructions. With a perfect BTB, there
would be no stalls in the pipeline and the program would complete in exactly one millisecond. However,
the BTB is not perfect. Of the 1,000,000 instructions, 200,000 are branches. Only 170,000 of those are BTB
hits. Of the 170,000 BTB hits, 150,000 are correctly predicted, while for the other 20,000 the BTB
incorrectly predicts the direction. Of the 30,000 BTB misses, 10,000 are not taken and 20,000 are taken.
There are no delay slots, and the processor makes no attempt to correct a mispredicted branch until the
branch goes through the last stage of the pipeline. At the end of that last pipeline stage the correct direction
and target are known and, if needed, in the next cycle the fetch restarts from the first instruction that should
execute after the branch. With this imperfect BTB, the overall execution time of the program is 1.8
milliseconds. How many stages are there in the processor’s pipeline? You can ignore the pipeline fill time.
Show your work. [6]

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Q7. It is possible to include tpl rd, rt instruction in a singlecycle processor by modifying the datapath and
control unit as discussed in class and shown below. The instruction does the following task:
tpl rd,rt # Memory[R[rd]]  3*R[rt]
# R[rt] 3*R[rt]
Mark on the diagram shown below the changes in connections and/or components of the datapath for
implementation of tpl. You can add only muxes and wires to the datapath. You may modify a component
of datapath, but ALU cannot be modified. Write the values against all control signals and show all the
modifications (if any) made to the existing components of the datapath. [6]

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