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MP - Unit 6

Microprocessor notes

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11 views5 pages

MP - Unit 6

Microprocessor notes

Uploaded by

Prathamesh Narale
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Unit No.

6: Pentium, Pentium Pro and Pentium 5 Microprocessor


 Introduction to Pentium Microprocessor
 The memory System
 Special Pentium Registers
 Pentium Memory Management
 Introduction to Pentium Pro Microprocessor
 Internal Structure of the Pentium Pro
 Memory System
 Pentium 4 and Core2
 Memory Interface
 Register Set
 Hyper Threading Technology
 Multiple Core technology
 CPUID (CPU Identification)
Introduction to Pentium Microprocessor
Made by Intel in 1993
Made a drastic change in microprocessor history.
This achieved the speed of more than 10x than previous processors.
Internet and multimedia accessable due to its speed
Features of Pentium Microprocessor
 Made by Intel in 1993
 Internet and multimedia accessable due to its speed.
 Has separate data and instruction memory
 Available with 66 Mhz – 99 MHz clock (Gives higher speed of execution)
 Has two 32 bit of MPU and ALU
 2 execution units (U & V) known as Integer UV Pipelining
 64 bit data bus (8 level memory banking)
 32 bit address bus (64TB Virtual Memory)
 5 stage pipelining (Execution speed increases)
 Has on chip floating point unit. Floating point unit supports 8 stage pipelining (Graphic
purpose).
 Has on chip L1 cache memory (no delay in bus interface)
Hyper Threading Technology
 Previously microprocessor were of single core (reads and executes instruction )
 After adding additional cores to CPU, CPU was able to able to read and execute more
instructions at a time. This increased the performance of CPU.
 That is it has 2 physical processing units on a single chip.
 To increase the performance and make it faster intel introduced hyper threading technology.
 Hyper threading was first introduced by Intel in 2002 on Pentium 4.
 This technology was added to CPU for each physical core that’s on the CPU.
 Basically hyper threading virtually doubles the number of cores that are on the CPU

 So when we observe dual core processor through lens of OS we will have quad core (4 cores).
 Hyper threading does not double the number of cores physically it only doubles virtually.
 OS will schedule the work load between these threads.
 Each virtual core can be individually interrupted or directed.
 This increases number of independent instructions in pipelining.
 This makes the processor faster.
 Advantage of hyper threading
1. Video Editing
2. Gaming
3. Heavy Software
Registers in Pentium
 Four 32-bit registers (EAX, EBX, ECX,
EDX) (Extended)
 Four 16-bit registers (AX, BX, CX, DX)
 Eight 8-bit registers (AH, AL, BH, BL,
CH, CL, DH, DL)
 ECX is used for count in loop instructions
Flag Register

 All the previous flags i.e. 0 to 17 are same as that of 8085, 8086, 80386
 AC – Alignment Check (1 if word or double word is addressed on non word or non double
word boundary)
 VIF – Virtual Interrupt (Copy of Interrupt Flag)
 VIP – Virtual Interrupt Pending. (Used in multitasking environments to provide virtual
interrupt flags)
 ID – Identification (Supports CPUID- provide system with information about Pentium
microprocessor)
CPUID
 CPUID stands for CPU Identification and is an instruction introduced by Intel starting with the
Pentium processor.
 CPUID instruction is executed by placing specific values in the EAX register and then
invoking the CPUID instruction.
 After executing the instruction, the information is returned in several registers: EAX, EBX,
ECX, and EDX.
 Basic Processor Information (EAX = 0)
 Processor Type and Features (EAX = 1)
 EBX Contains the information about the CPU’s brand ID cache size, and other such identifiers.
 ECX and EDX Feature flags, where each bit represents whether a specific feature is supported.
 Required for - System Optimization, Compatibility Checking, Debugging and Diagnostics
Special Registers in Pentium
 Control Registers: CR0, CR1, CR2, CR3, CR4 (Controls CPU operations like paging).
 Debug Registers: DR0–DR7 (Used for hardware breakpoints in debugging).
 Test Registers: TR6, TR7 (Obsolete, used in older Pentium processors).
 Segment Registers: CS, DS, ES, SS, GS, FS (Handles memory segmentation).
Control Registers
 CR0 to CR4 i.e. total 5 control
registers
 Each of 32 bits
 Pentium and further series gets
an additional control register
CR4
 CR1 is reserved by intel
 CR2 has page fault linear address

REGISTER NAME FUNCTION

CR0 NE Numerical Error (1 if Standard Numeric Coprocessor Error


Detected)

WP Write Protect (1 when supervisor can write to user level segments)

AM Alignment Mask (Checks alignment when 1)

NW Not Write (If 1 then data cache is inhibited from cache write)

CD Cache Disable (If 1 cache will not fill with new data)

CR3 PWT 1 = Enables write through cache in system

PCD 1 = External hardware can control level 2 cache memory

CR4 VME Virtual Mode Extension (support virtual interrupt flag in virtual
mode)

PVI Protected Mode Virtual Interrupt (Support virtual interrupt flag in


protected. mode)

TSD Time-date Stamp Disable (1= Read from time stamp counter)

DE Debugging Extension (1 = I/O breakpoints)

PSE Page Size Extension (1 = 4Mb page size)

MCE Machine Check Enable (1 = Machine Check)


Memory System in Pentium
 The memory system in Pentium processors plays a critical role in performance.
 It consists of cache memory, main memory (RAM), and virtual memory.
 Cache memory is the fastest and stores frequently used data.
 Pentium processors introduced Level 1 (L1) and Level 2 (L2) cache memory.
 L1 cache is closest to the CPU cores, providing quick access to critical data.
 L2 cache is larger but slightly slower, storing less frequently accessed data.
 The Pentium architecture utilizes advanced memory management techniques.
 Features like virtual memory allow for efficient use of physical RAM.
 Memory bandwidth and latency affect overall system performance.
Introduction to Pentium Pro
 Released in 1995 by Intel as part of the P6 microarchitecture family.
 Designed for high-performance computing and server applications.
 Dynamic execution and out-of-order execution.
 Used in workstations and servers; laid the foundation for modern processors.
 SuperScalar Architecture: Executes multiple instructions per clock cycle
 Dynamic Branch Prediction: Improves pipeline efficiency by predicting instruction paths..
Internal Structure of Pentium Pro
 Instruction Pool
 Retire Unit
 Level 1 Data Cache
 Dispatch and Execute Unit
 BIU
 Level 2 Cache
 Level 1 Instruction Cache
 Instruction Fetch & Decode

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