COMPACT 10-B SUCCESSIVE

APPROXIMATION (SAR) ADC WITH UNIT-

LENGTH CAPACITORS

4TH YEAR ANALOG IC PROJECT

SUBMITTED BY:
TOMER ELKABETZ 205437692
YUVAL AVERBUCH 311309587

SUPERVISED BY:
MR. DAVID ZAGURI
PROF. JOSEPH SHOR

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Contents
1. ABSTRACT .......................................................................................4

2. ADC PERFORMANCE METRICS ............................................................5

2.1 Static characteristics for ADC performance ............................................................... 5

2.1.1 Offset Error ................................................................................................................ 5

2.1.2 Gain Error .................................................................................................................. 6
2.1.3 DNL - Differential Non-Linearity............................................................................... 7
2.1.4 INL – Integral Non-Linearity ..................................................................................... 8

2.1.5 Missing code ............................................................................................................. 8

2.1.6 Systematic and Random Error................................................................................. 9

2.2 Dynamic characteristics for ADC performance ....................................................... 10
2.2.1 Signal to Noise Ratio (SNR) .................................................................................. 10
2.2.2 Signal to Quantization Noise Ratio )SQNR( ........................................................ 11
2.2.3 Signal to Noise and Distortion Ratio (SNDR) ....................................................... 12
2.2.4 EFFECTIVE NUMBER OF BITS (ENOB): ............................................................ 12
3. SAR ADC ........................................................................................ 13

3.1 Work plan: ................................................................................................................... 13

3.2 SAR OPERATION AND TIMING .............................................................................. 13

3.3 SAR’s Components Analog Scheme........................................................................ 15

3.3.1 Binary Weighted Capacitor Digital to Analog Converter ................................... 15

3.3.2 COUNTER ............................................................................................................... 16

3.3.3 Sample and Hold .................................................................................................... 17

3.3.4 Comparator.............................................................................................................. 18
3.3.5 Successive Approximation Logic ........................................................................... 19
4. UNIT-LENGTH DAC LAYOUT TECHNIQUE ............................................ 21

4.1 Theory from Article ..................................................................................................... 21

4.1.1 Unit Element Capacitor .......................................................................................... 21
4.1.2 Unit Length Capacitors ........................................................................................... 22
4.1.3 Segmented DAC ..................................................................................................... 23

4.2 Custom DAC Specification ........................................................................................ 24

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4.3 DAC Implementation .................................................................................................. 25
4.4 Documentation Setbacks Along the Way................................................................. 27

4.5 Capacitance Measuring ............................................................................................. 28

4.6 Accurate the manual layout capacitor size to reach binary scale .......................... 29

4.6.1 DNL problem ........................................................................................................... 29

4.6.2 Missing Code Problem ........................................................................................... 31
4.6.3 Additional Attempts to Improve DNL and Accurate DAC Step Output: .............. 32
4.7 Layout Metal Layer .................................................................................................... 33

4.8 DAC Performance and Characteristics Graphs ....................................................... 35

5. COMPARATOR TRANSISTOR LEVEL ....................................... 37
5.1 Strong Arm Latch Scheme ........................................................................................ 37

5.2 Strong Arm Latch Operation ..................................................................................... 38

5.3 Circuit Performance Reliability .................................................................................. 39
5.3.1 Gain Improvement: ................................................................................................. 39
5.3.2 Comparator decision improvement ....................................................................... 40

5.4 Comparator Integration in Circuit .............................................................................. 42

5.4.1 Initial condition ............................................................................................... 42
5.4.2 Timing Matching between Comparator to SAR Logic ................................ 43

5.4.3 SAL Parasitic Capacitance..................................................................................... 46

6. SAMPLE AND HOLD INTEGRATE ............................................. 49

7 APPENDIX: SETUP FOR CUSTOM LAYOUT AND EXPLANATION OF

RUNNING LAYOUT SIMULATION. ........................................................... 54

7.1High lights .................................................................................................................... 54

7.2 Extension .................................................................................................................... 54

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1. Abstract
According to Moore’s law, we observe that the number of transistors in
an integrated circuit (IC) doubles about every two years. Or in electrical
engineer perspective we tried to reduce the size and simultaneous
improve power consumption.

In our final project to graduated first degree in EE at Bar-Ilan University

we design and layout 10-bit DAC that based on unit-length capacitors
bank and integrate it at SAR ADC architecture.
We based our research on Pieter Harpe article:
“A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR
Filter”
that publish at IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 3,
MARCH 2019.

The project is implemented in cadence virtuoso 65 nm technology and

the power supply used is 1 volts.

Between ADC components the DAC is occupies the largest area, and that
doe to he is built from capacitor interconnect that are known them very
large then transistors.
In this document we are explored way to overcome the DAC size.
Our innovation and advantage is that the fundamental unit-length
capacitor placed above the ADC circuit. Its expressed by placing the ADC
circuits (substrate to metal 3) directly under the capacitors (metal 6 to
metal 7) separated by grounded shield (metal 4 to metal 5).
Hence we reduced the area on chip that the ADC.

In addition, we are implement the comparator analog scheme, we

design strong arm letch PMOS base.

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2. ADC PERFORMANCE METRICS
2.1 Static characteristics for ADC performance

2.1.1 Offset Error

The offset error as shown in the figure below is defined as the difference between the
nominal and actual offset points. For an ADC, the offset point is the midstep value when the
digital output is zero, and for a DAC it is the step value when the digital input is zero. This
error affects all codes by the same amount and can usually be compensated for by a
trimming process. If trimming is not possible, this error is referred to as the zero-scale error.
Due to non-ideal effects like a mismatch between internal components, the actual transfer
function of an ADC deviates from the ideal staircase response. The offset error shifts the
transfer function along the horizontal axis and hence causes a shift in the code transition
points.

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2.1.2 Gain Error

The gain error shown in the figure below is defined as the difference between the nominal
and actual gain points on the transfer function after the offset error has been corrected to
zero. For an ADC, the gain point is the midstep value when the digital output is full scale, and
for a DAC it is the step value when the digital input is full scale. This error represents a
difference in the slope of the actual and ideal transfer functions and as such corresponds to
the same percentage error in each step. This error can also usually be adjusted to zero by
trimming.

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2.1.3 DNL - Differential Non-Linearity

The differential nonlinearity error shown in the figure below is the difference between an
actual step width (for an ADC) or step height (for a DAC) and the ideal value of 1 LSB.
Therefore, if the step width or height is exactly 1 LSB, then the differential nonlinearity error
is zero. If the DNL exceeds 1 LSB, there is a possibility that the converter can become
nonmonotonic. This means that the magnitude of the output gets smaller for an increase in
the magnitude of the input. In an ADC there is also a possibility that there can be missing
codes i.e., one or more of the possible 2n binary codes are never output.

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2.1.4 INL – Integral Non-Linearity

The integral nonlinearity error shown in the figure below is the deviation of the values
on the actual transfer function from a straight line. This straight line can be either a best
straight line which is drawn so as to minimize these deviations or it can be a line drawn
between the end points of the transfer function once the gain and offset errors have been
nullified. The second method is called end-point linearity and is the usual definition adopted
since it can be verified more directly.
For an ADC the deviations are measured at the transitions from one step to the next, and for
the DAC they are measured at each step. The name integral nonlinearity derives from the
fact that the summation of the differential nonlinearities from the bottom up to a particular
step, determines the value of the integral nonlinearity at that step.

2.1.5 Missing code

This characteristic means that there is code which not represented by the ADC. In this case
the DNL of this code will be > |1| LSB.

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2.1.6 Systematic and Random Error

In the article they do 10 samples to characterize chip to chip variation. The results:

In the figures above we can learn about the difference between systematic to random
component.
systematic error cause by our design metrics.
random error is cause by inaccuracy or variation by manufacturer printing.

First, we see on (b) 'noise like' pattern and spike around codes 128 and 896. Which are
attributes to systematic error source. Second, (c) figure is more consistent with random
capacitor mismatch.

The article clam that the reason for the spikes in DNL systematic error is caused by dynamic
effects, such as DAC or reference settling, or an incomplete comparator reset. One offer to
solve it is to reduce the internal clock rate or by adding redundancy to the SAR algorithm.

To solve the random mismatch, the article suggests design differential DAC and that because
the most random mismatch occurred between the capacitor size and value.

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2.2 Dynamic characteristics for ADC performance

2.2.1 Signal to Noise Ratio (SNR)

Signal-to-noise ratio is defined as the ratio of the power of a signal (meaningful input) to the
power of background noise (meaningless or unwanted input):

𝑃𝑠𝑖𝑔𝑛𝑎𝑙
𝑆𝑁𝑅 =
𝑃𝑛𝑜𝑖𝑠𝑒

where P is average power. Both signal and noise power must be measured at the same or
equivalent points in a system, and within the same system bandwidth.
Usually the signal, which is referred here, is a sinusoidal signal. This dynamic property
accounts for the whole noise present in the entire Nyquist range. Its value depends on the
magnitude of the input signal and it proportionately decreases with the reduction in the
signal amplitude.
The value of SNR is given by SNR = ((6.02*Resolution) + 1.76).

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2.2.2 Signal to Quantization Noise Ratio )SQNR(

The SQNR reflects the relationship between the maximum nominal signal strength and
the quantization error (also known as quantization noise).

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2.2.3 Signal to Noise and Distortion Ratio (SNDR)

Signal-to-noise and distortion ratio is a measurement of the purity of a signal.

SNDR is defined as:

𝑃𝑠𝑖𝑔𝑛𝑎𝑙
𝑆𝑁𝐷𝑅 = 𝑃
quantization error + 𝑃𝑅𝑎𝑛𝑑𝑜𝑚 𝑛𝑜𝑖𝑠𝑒 +𝑃𝑑𝑖𝑠𝑡𝑜𝑟𝑡𝑖𝑜𝑛

where P is the average power of the signal, quantization error, random noise and distortion
components.
distortion is the alteration of the original shape (or other characteristic) of a signal.
SNDR is usually expressed in dB .

2.2.4 EFFECTIVE NUMBER OF BITS (ENOB):

The resolution of an ADC is specified by the number of bits used to represent the analog
value.
Ideally, a 12-bit ADC will have an effective number of bits of almost 12. However, real signals
have noise, and real circuits are imperfect and introduce additional noise and distortion.
Those imperfections reduce the number of bits of accuracy in the ADC. The ENOB describes
the effective resolution of the system in bits. An ADC may have a 12-bit resolution but the
effective number of bits, when used in a system, may be 9.5.

where

 ENOB is given in bits

 SNDR (signal, noise, and distortion) is a power ratio indicating the quality of the signal in
dB.
 the 6.02 term in the divisor converts decibels (a log10 representation) to bits (a
log2 representation)
 the 1.76 term comes from quantization error in an ideal ADC.

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3. SAR ADC
3.1 Work plan:
1. First simulation is designated for check the SAR logic functionality and therefore we
design the blocks from ideal component.
2. Secondly we design Unit length DAC and build his layout.
3. In the end we build strong arm latch compotator.

SAR logic design scheme:

3.2 SAR OPERATION AND TIMING

The conversion included 11 clock cycle:

1. there is a ‘reset’ input that use to initial the counter for the first conversion.
2. The first clock cycle dedicates to reset all the registers in the SAR Logic to ‘0’.
3. Whenever new conversion start, the registers sets the most significant bit to ‘1’ and
all other bits to ‘0’. That means the input to the DAC IS ‘1000000000’ and the
𝑉𝐷𝐷
corresponding analog output voltage is [𝑉].
2
4. This voltage will get compared with the sampled input voltage
5. Base on the comparator result, the output of the SAR Logic change:
- If 𝑉𝑆𝑎𝑝𝑚𝑙𝑒 > 𝑉𝐷𝐴𝐶 than the MSB will kept on ‘1’.
- If 𝑉𝑆𝑎𝑝𝑚𝑙𝑒 < 𝑉𝐷𝐴𝐶 than the MSB will be set to ‘0’.
6. The next bit will be set to ‘1’ for the new comparison: ‘X100000000’.
- If 𝑉𝑆𝑎𝑝𝑚𝑙𝑒 > 𝑉𝐷𝐴𝐶 than the following bit will kept on ‘1’.
- If 𝑉𝑆𝑎𝑝𝑚𝑙𝑒 < 𝑉𝐷𝐴𝐶 than the following will be set to ‘0’.
7. Repeat till all bits will be defined.
8. After 11 cycle we can sample the outputs by the following code:
sum the binary weights of the high logic bits.
9. We are design a negative counter. hence he is finish his count when all his flip-flop
on ‘0’ and therefore the next conversion will start at positive clock edge.

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 10. As we can notice, the comparator has mistaken when 𝑉𝐷𝐴𝐶 is very close to 𝑉𝑆𝑎𝑝𝑚𝑙𝑒 .
There for, at the layout's step ,we designed a strong arm latch comparator.
AAll the parameter and accuracy can be found on section 4.

SAR logic operation waveform

We can see all block integration:

First we can see that every 11 clock cycle the sample and hold output rise and reset the
system.
Secondly we can see that DAC output ,which express the digital SAR output and based on
comparator result and SAR logic operation, is observed by the decision that the DAC output
voltage take.
Finally and after 11 clock cycle we can see that the DAC output voltage is closed to Sample
and Hold output voltage.

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3.3 SAR’s Components Analog Scheme
3.3.1 Binary Weighted Capacitor Digital to Analog Converter

 The binary weighted capacitor:

𝐵0 → 20 ∙ 𝐶0 𝐵5 → 25 ∙ 𝐶0
1
𝐵1 → 2 ∙ 𝐶0 𝐵6 → 26 ∙ 𝐶0
𝐵2 → 22 ∙ 𝐶0 𝐵7 → 27 ∙ 𝐶0
3
𝐵3 → 2 ∙ 𝐶0 𝐵8 → 28 ∙ 𝐶0
𝐵4 → 24 ∙ 𝐶0 𝐵9 → 29 ∙ 𝐶0
 Last significant bit resolution:
Due to we have 10 bit the ideal capacitor DAC resolution is

𝑉𝑟𝑒𝑓 𝑉𝐷𝐷
𝐿𝑆𝐵 = 20 +21 + ...+29 = 1023 = 0.975 [𝑚𝑉]

 According to elementary capacitor-divider principle:

Cref
𝑉𝑜𝑢𝑡 = 𝑉𝑟𝑒𝑓
CTotal
𝑉𝑜𝑢𝑡 = 𝑉𝑟𝑒𝑓 ∙ (𝐵0 ∙ 20 + 𝐵1 ∙ 2−1 𝐵1 + . . . +𝐵9 ∙ 2−9 )
where 𝐶𝑟𝑒𝑓 represents the sum of all capacitances connected to 𝑉𝑟𝑒𝑓 That is all bits
that on state ‘1’ logic.
CTotal represents the total capacitance of the array.

 In our SAR ADC, the DAC voltage reference is set to 𝑉𝐷𝐷 = 1 [𝑉]

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Waveform:

3.3.2 COUNTER

The counter purpose is to count full ADC system cycle that composed from 11 clock cycle
and reset the SAR’s components in the end of every system cycle.
The counter feed the sample and hold input.
Meanwhile in this time the SAR logic operate his calculate and decide the system digital
outputs. This topology base on negative chaining logic: where all the registers low then the
output high.

We added the buffers because the timing of the FF and ideal pulse voltage source.

Waveform:

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3.3.3 Sample and Hold

The Sample and Hold component use to sample the SAR ADC system input signal and save
his value until the SAR logic finish his operation and present digital output.
waveform

As we can see from the graph, the input signal is sample when the counter output high and
hold the value until the next time that the counter output high.

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3.3.4 Comparator

The comparator use to compare the input signal with DAC's output which based on SAR logic
algorithm. The comparator output is feeding the sar logic.
We plan in the first step comperator with 𝑔𝑎𝑖𝑛 = 1000 and in the following we convert it
with strong arm latch Pmos amplifier that we design.

As we can see from the graph, when the input voltage above DAC voltage the comparator
output is high and when the input voltage below DAC voltage the comparator output is low.

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3.3.5 Successive Approximation Logic

Zoom-in:

At the SAR logic there are two arrays of FF:

1. Upper array, shift register of '1', accordance with the fact that one value will be in
the position according to the iteration number.
2. Downer array, the SAR logic.

Whenever new conversion start, we are design the SAR logic’s registers set up to
‘1000000000’ that means the most significant bit to ‘1’ and all other bits to ‘0’.
Then at the next positive clock edge occur 2 process simultaneous:

1. The shift register sends '0' to the correct SAR logic register, which set '1' in his
output.
2. The SAR logic register, which awake firm the shift register, on the clock if the
previous register. That leads to the comparator value set at the register.

In the next positive clock edge this process are repeats.

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Waveform:

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4. Unit-Length DAC Layout Technique
4.1 Theory from Article:
We are present 2 approach for implementing binary scaled capacitor base DAC.
we are target to small as possible chip area, accurate and power consumption DAC ,
therefore those approaches will design to this purpose and we will understand the trade-off
considerations that achieve those Characteristics.

4.1.1 Unit Element Capacitor

The conventional and common approach to implement an N-bit capacitive DAC for an SAR
ADC is to implement 2N-1 unit capacitors and to group these in binary-scaled sets to create
the DAC. To minimize power consumption and chip area, ideally, one would like to minimize
the size of the unit capacitor toward the fundamental noise limit. In order to get closer to
the fundamental limit, there are several challenges to deal with:
first of all, a custom capacitor layout should be developed to reach this small value in the
first place.
Second, the capacitor mismatch needs to be improved; otherwise, such a small unit will not
achieve sufficient linearity.
Finally, as already shown in figure above, once the capacitor size is small, the interconnect
starts to become important for the overall area and also increases power losses.
Overall, the binary-scaled array based on the unit elements is not able to reach the capacitor
noise limit in an area-efficient and power efficient manner.

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4.1.2 Unit Length Capacitors

To overcome the conventional approach limitation, not only the capacitor value but also the
amount of interconnect should be minimized. This is done by using a unit-length rather than
a unit-element approach. It is known that changing the length of a metal strip will change its
capacitance, and it is also known that this relation is not accurate, since edge effects do not
scale with the length. To solve this, the length difference between two strips rather than the
absolute length of a single strip is used to define the capacitances. In this way, edge effects
are compensated thanks to subtraction, and accurate scaling of the effective capacitance
proportional to the length difference can be achieved.

Six relevant capacitors are formed, each from an input node to the shared output node of
the DAC. Each DAC bit 𝑖 drives two capacitors (𝐶𝑖 and 𝐶𝑖 ′ ) that are both coupled to the DAC
output but with opposite control polarity. However, by making the metal of 𝐶0 an amount ∆
longer and the metal of 𝐶0 ′ an amount ∆ shorter than their average, the effective
capacitance is determined by the total length difference 2∆. A binary-scaled array can now
be made by scaling ∆ in binary steps as shown in the figure above.

Note that systematic capacitance errors, such as caused by the vias or the metal strip ends
are, compensated by the oppositely switched element. Therefore, accurate binary scaling
can be achieved. Moreover, the regular layout pattern with constant metal density is less
likely to suffer from systematic mismatches. Since ∆ can be set with fine granularity (for
instance 5-nm steps in 65-nm CMOS), very small effective capacitors can be designed.
A further advantage is that it is now possible to design matched capacitors that are
noninteger multiples of each other. This is different from the unit element approach, where
only integer multiples of the unit can be implemented accurately, as fractional units
introduce systematic mismatch.

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4.1.3 Segmented DAC

In practice, it is not convenient to scale all N bits by means of ∆, as this would result in long
metal strips of 2 ∙ 2𝑁 ∙ ∆.
Moreover, this would also result in a large percentage of “negative” capacitance (𝐶𝑖 ′), which
is disadvantageous in terms of mismatch, noise, power, and area.

As a solution, the DAC can be segmented, where the LSBs are scaled using ∆, and the MSBs
use the unit-element approach. An example sketch of a segmented DAC (with 3-b binary and
2-b unary) is shown
in Fig. 3. Within the 3-b binary segment, good matching is achieved thanks to length scaling
(∆, 2∆, and 4∆). Within the 2-b unary segment, good matching is achieved thanks to the unit
elements (either one element or two elements of 8∆). Matching between the binary and
unary segments is also assured, as the unit element of the MSB array (8∆) is length-scaled by
2× compared with the largest LSB element of 4∆.

All in all, the proposed layout technique from figure above has three benefits that help to
minimize the chip area:
First, very small LSBs can be made thanks to using the length difference. This can reduce the
total capacitance and thus reduces the area for the MSB capacitors.
Second, fewer components are needed as opposed to a binary-weighted array with unit
elements, which also results in area savings.
Third, the interconnect is more simple thanks to the lower component count and can be
placed under the capacitors, such that it does not take extra area.

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4.2 Custom DAC Specification

Based on the Segmented DAC scheme, a 10-b DAC was manual implemented with six binary
bits and four unary bits.

Process [nm] 65 [nm]

Area [𝑢𝑚 2 ] 354.1776
Supply 1V
Resolution [bits] 10
𝑀𝑆
𝐹𝑠𝑎𝑚𝑝𝑙𝑒 [ ]
𝑠
Power [uW]
INL [LSB] 0.25
DNL [LSB] 0.28
Offset [LSB] 0.0026
Gain error [LSB] 759

Layout dimention:

Bit Unit ∆ [𝝁𝒎] 𝑪 [𝒇𝑭] 𝑪′ [𝒇𝑭] 𝑪𝒆𝒇𝒇 [𝒇𝑭]

9 8 12.76 69.317 5.101 64.216
8 4 12.76 35.666 2.632 33.034
7 2 12.76 17.86 1.336 16.524
6 1 12.76 8.918 0.655 8.263
5 1 6.4 6.846 2.725 4.121
4 1 3.2 5.819 3.759 2.06
3 1 1.6 5.303 4.275 1.028
2 1 0.8 5.043 4.533 0.51
1 1 0.4 4.914 4.663 0.251
0 1 0.2 4.849 4.727 0.122
Calibrition P1 1 0.2 4.84 3.506 1.334
Calibrition P0 1 0.2 5.995 4.915 1.08

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Parsitics capacitances:

Pin 𝑪 [𝒇𝑭] 𝑪′ [𝒇𝑭]

Out - VSS 7.334 [fF]
P0 - VSS 0.259 0.25
P1 - VSS 0.234 0.231
B0 - VSS 0.178 0.176
B1 - VSS 0.177 0.155
B2 - VSS 0.181 0.154
B3 - VSS 0.189 0.145
B4 - VSS 0.204 0.128
B5 - VSS 0.239 0.096
B6 - VSS 0.285 0.053
B7 - VSS 0.594 0.121
B6 - VSS 1.085 0.263
B7 - VSS 2.37 0.548

4.3 DAC Implementation

For the unit length we use separated symbols and layout cell for each bit, for example we
display B0:

In our case cells from B7 design at unary method that is B7 is built from units of B6,
consequently if we want to do change in B6 (which relevant for the all up bits), it will change
at all together.

The reference size for the first from the article:

25
The unit length from the custom layout example B0:

Our layout size properties we defined that don’t

mention in the article:

 The distance between the frame and the finger

horizontal is 0.52um.
 The middle of the instance is 15.24 from the out
frame.
 The delta that mentioned into the article is the
distance from the center of the instance to the middle
of the space between the two fingers.
 The distance between the two fingers is 0.2um.

26
4.4 Documentation Setbacks Along the Way

We made performed several attempts to get the precise capacitor size reach binary scale:

Different metals for the frame and the finger. In the first we think that the article means
that the frame and the finger should be in different metals. So, we do the finger in metal 6
and the frame in metal 7. The logic behind it, the capacitance between the 2 layers
diagonally should be small. That was good to the article goal, small capacity. The problem
with that application that we got in some bits DNL larger than 1 LSB, which cannot allow
reliable results for the DAC as well as we don’t get the capacitor size we wanted.
To overcame this we built the frame and the fingers in M6 & M7 stack parallel to increase
the capacitor density.

Capacitance to Substrate. At first DAC measuring we had noticed the voltage DAC's range
didn’t come to VDD (1V). we are expecting that our manual capacitor respond to step input
with the same step in the output (capacitor is non sensitive to high frequency).
To our disappointment we get step output but with amplitude of 40 [mV].
The reason was the significant parasitic capacitance of the metal to the ground. Because the
ratio: DAC's capacitance and parasitic capacitors was bed at the beginning , it had big effect
on the DAC's output voltage and efficiency.
To overcame this we built shield layer at M5 and connect her to ground.
at this solution we reduce the majority of the parasitic and got now output step 600 [mV].
this is very good efficiency result because in the total we save a big area and in relation to
the voltage we lose.

CM fingers. After many failures with the length unit methodology, we try to stick up with the
unary idea instead of the delta increasing. Also replace the two inputs to the capacitance by
one input. The results were 3.38fF for the fundamental unit that is very large capacitors and
very large area. Another problem comes out with the DAC was the edges (up and down).
To fix it we adding two dummies CM fingers connecting to the ground. This way gets great
results for capacitance, however bad for the size. We abandoned this methodology and
made a concerted effort to solve the unit length method.

27
4.5 Capacitance Measuring

There are several ways we tried to measure the capacitance of the units:

 Connect an ideal cap to instance output, then increase the capacitance until the
voltage fall by factor of two.
 Run a DC simulation with insert current to the capacitor. The slope of the VT curve
1 𝐼𝑑𝑡
should be the inverse of the capacitance ( = ).
𝐶 𝑉
 For measure the effective capacitance which makes by the delta we develop the
following equation. First the final charge of the capacitor with the definition of
capacitance is 𝑄𝑓 = 𝑉𝑓 (𝐶 + 𝐶 ′ ) = 2𝐶𝐶𝑀 , second the charge is superposition of all
initial charge of the instance
𝑄𝑓 = 𝑄𝑖 + 𝑄𝑖′ = 𝑉𝑑𝑑(𝐶𝐶𝑀 + 𝑑) − 𝑉𝑑𝑑(𝐶𝐶𝑀 − 𝑑 ) = 2𝑉𝑑𝑑 ∙ 𝑑 .
𝑉𝑓
That all leads to the equation 𝑑 = ∙ 𝐶𝐶𝑀 . All the parameters we can measure.
𝑉𝑑𝑑
 Extraction. Run av_extracted on the capacitor layout and see the results from the
simulator.

The final measuring was the most accurate, because we can separate between the
capacitance between the input to output without consider the capacitance to subtract (VSS).

28
4.6 Accurate the manual layout capacitor size to reach binary scale

The problem we have that the MSB bit (B9) has large jump which can skip over a code
symbol and we get DNL > 0.5 LSB at B6.
To solve this, we did two things:
1) Change B6's delta and metal length
2) Add calibration

4.6.1 DNL problem

After we create the DAC according to article, we found gaps between the bits that bigger
than 1 LSB. For be more specific we measured the delta between 2 bits and calculate relative
to LSB.

To see this, we make graph of the voltage steps, in LSB:

The LSB for this section consider in the rail to rail voltage range we got form the DAC, which
is 0 to 631.252mV, that means (for 10bits resolution) 9.77 ∙ 10−4 𝑚𝑉 for LSB. So, we got that

29
chart:

LSB for symbol

2.8

2.3
LSB

1.8

1.3

0.8
0 200 400 600 800 1000
symbols

Because we see periodicity phenomena, that can be caused by specific capacitor in the
layout that are not accurate in his capacitance size that fit our binary DAC logic. We can see
the difference at the voltage steps especially at MSB bit B9. Moreover, most the bits with
the large error are the unary bits which are constructed by B6 units. To improve that we try
changing at capacitor B6 delta location and metal length to make change at capacitance.

After we change the B6 metal length to be 12.76 um, we got improve the DNL:

LSB for symbol

2.5

1.5
LSB

0.5

0
0 200 400 600 800 1000
symbols

We can see that except B9 we success to reduce the DNL error to be less than 0.5 LSB as we
want to achieve in theory (2.1.3).

In our iteration, we got to minimum point of improve the results.

30
 LSB for symbol
2.4
2.2
2
1.8
LSB

1.6 12.77
1.4 12.76
1.2 12.75
1
0.8
0 200 400 600 800 1000
symbols

As we can see, the best result for better voltage step was around 12.76um. Indeed, we
achieve the DNL code step less than 0.5 LSB.

4.6.2 Missing Code Problem

when B9 switched his logic level, we turn on the additional cap that design as B0 sizes, but in
the opposite inputs. Its purpose to subtract 1 LSB value (B0) from B9. The results:

LSB for symbol

1.4

1.3

1.2
LSB

1.1

0.9

0.8
0 200 400 600 800 1000
symbols

31
4.6.3 Additional Attempts to Improve DNL and Accurate DAC Step Output:

To improve the result, we implement the calibration for all the LSB there are above 1.2LSB in
the same method with insert negative LSB to the DAC. In this case we try to insert negative
0.25LSB. so, we have to do 2 additions: first, making a logic equation to the specific
combination of bits we want that the calibration works (in our case the bits between B0 to
B5 should be on so it makes more easer). Second, a level shifter that convert the logic
equation output to the wanted voltage value to make 0.25LSB.

The equation = (B7′ + 𝐵7 ∙ 𝐵6′ + 𝐵7 ∙ 𝐵9′ ∙ 𝐵8) ∙ 𝐴𝑁𝐷(𝐵0, . . , 𝐵5)

The results were bad:

LSB for symbol

10.8
9.8
8.8
7.8
6.8
LSB

5.8
4.8
3.8
2.8
1.8
0.8
0 200 400 600 800 1000
symbols

The changes with the calibration make big voltage steps which out the circuit from balance.
So, we tried to change the LSB coefficient to get better result, so best change we get at
0.04LSB:

32
 LSB for symbol
2.6
2.4
2.2
2
1.8
LSB

1.6
1.4
1.2
1
0.8
0 200 400 600 800 1000
symbols

We don’t succeed to improve DAC DNL in this attempts.

4.7 Layout Metal Layer

The final layout looks:

M3:

Inter connect to ADC SAR circuit.

M4:

33
VSS shield

M6:

M7:

34
4.8 DAC Performance and Characteristics Graphs

Size: height 11.62 um, width 30.48 um.

Results:

DNLmax = 0.28LSB
1
0.8
0.6
0.4
DNL [LSB]

0.2
0
-177 -0.2 23 223 423 623 823 1023
-0.4
-0.6
-0.8
-1
Code

35
 INLmax = 0.25LSB
1.00
0.80
0.60
0.40
0.20
INL [LSB]

0.00
-177 -0.20 23 223 423 623 823 1023
-0.40
-0.60
-0.80
-1.00
Code

Gain linearity

0.5

0.4
Voltage [V]

0.3

0.2

0.1

0
0 200 400 Code 600 800 1000

36
 5. Comparator Transistor Level

5.1 Strong Arm Latch Scheme

For our ADC project we design strong arm latch PMOS configuration that will be used as
comparator. we design in a different way than appears at the article.

37
5.2 Strong Arm Latch Operation

The SAL operation has four stages (in one clock cycle):

1. Clock is on VDD so the voltage is initialized to VSS at nodes P, Q, X, Y. At this stage all
the operation transistors are closed.
2. Clock goes down to VSS, it makes P and Q node to be charged to VDD. The charge
rate of the nodes depends on the entrance voltage at the transistors above. Which
more open means the entrance voltage more low (bigger 𝑉𝑔𝑠 ) has faster charge.
3. At the beginning of this phase, 𝑉𝑔𝑠 of the middle transistors are VSS. When nodes P
and Q started being charged, the first transistor that will be opened, |𝑉𝑔𝑠 | > 𝑉𝑡ℎ , will
flow current and increase the voltage at his drain.
4. The nodes X and Y had been charged, the faster charge made another transistor
been more closed, until all the current threw one branch.

38
5.3 Circuit Performance Reliability

The initial setup is:

All nch_mac, regular Vth, 𝑊 = 200𝑛𝑚, 𝐿 = 240𝑛𝑚, VDD=1V, clock period=2ns,
vin1=ramp from 1V to 0, vin2 = 0.4V.
We sampled the results at the end of the cycle:

Here we notice two major flaws to improve:

1. Gain when vin1 is higher than vin2.

2. Comparator decision for close values.

5.3.1 Gain Improvement:

For the nodes Q and P voltage's we can derives from the scheme:
𝑔𝑚𝑖𝑛1,2|𝑉𝑖𝑛1 −𝑉𝑖𝑛2|
|𝑉𝑄 − 𝑉𝑃 | ≈ ( )𝑡 , where 𝐶𝑃 = 𝐶𝑄 = 𝐶𝑃,𝑄 .
𝐶𝑃,𝑄

The next stage (3) will begin when the middle transistors arrive to |𝑉𝑔𝑠| = 𝑉𝑡ℎ,
𝐶𝑃,𝑄
approximation of transient time: 𝑡 = 𝑉𝑡ℎ , where 𝐼𝐶𝑀 is the common mode current.
𝐼𝐶𝑀
|𝑉𝑄 −𝑉𝑃 | 𝑔𝑚𝑖𝑛1,2𝑉𝑡ℎ
The gain is |𝑉𝑖𝑛1−𝑉𝑖𝑛2|
= 𝐴𝑣 ≈ 𝐼𝐶𝑀
.

To improve the gain, we change 𝑊𝑖𝑛1,2 = 200 ∙ 4𝑛𝑚 for get larger 𝑔𝑚:

39
5.3.2 Comparator decision improvement

In our DAC custom layout we defined that 𝐿𝑆𝐵 ≈ 561𝑢𝑉, hence we run simulation with
entrance delta voltage of 0.5𝑚𝑉. The results on high values gives bad results
For example: Vin1 = 400mV Vin2 = 399.5mV CLK = 2ns.

The reason for the wrong output is the clock high frequency. We increased the clock to 10ns.
That leads to correct output for all values.

40
The final results for 10ns:

41
5.4 Comparator Integration in Circuit

The are 3 significant challenges we faced where we replace the ideal comparator with
the SAL:

1. Initial condition in DAC Output voltage and Sample&Hold output voltage where
comparator iteration beginning was unknown.
2. The SAL finish his operation during the negative clock pulse width, therefore we
sampled the comparator result there and the result reset when the clock rise again.
While the same time the next component (SAR logic) start his operation at positive
clock and the comparator result lost.
3. Capacity coordination

5.4.1 Initial condition

We are initial DAC output voltage and Sample&Hold output voltage by connect them to
ground through NMOS that control by reset signal.

42
 5.4.2 Timing Matching between Comparator to SAR Logic

We put DFF between the comparator to the SAR login that sample the comparator results
when positive clock pulse width that mean for our first trying we hope that DFF will sampled
before the SAL reset mechanism complete his work. Following that we had small timing
overlap and the operation success sample the correct value.
After we meet David we decided that it is risky mechanism and can easily break down
because noise and jitter.

The Second trying was design delay for the comparator clock, that make the comparator
operation start in delay after positive clock pulse width.

The delay we made with buffers, delay of 1.1ns.

To make sure, we did simulation with ideal voltage source for the clock and defined ideal
delay. For insert of 200mV and delay 1.1ns:

Ideal delay:

43
Real delay:

First line – comparator output and DFF output.

Second line – global clock, delay clock.
Third line – Vsample and Vdac.

We can see the glitch at the real clock, that may cause the difference between the two
operations.

The final trying, we using SR Latch between the comparator to the SAR login that save the
comparator result until the next SAL comparator decision

44
The operation of the SR Latch:

The SR Latch integrate at the ADC SAR operation:

It gave better result with small offset: 1.3mV.

45
5.4.3 SAL Parasitic Capacitance
For our first iteration we design ideal Sample&Hold component that save the SAR ADC input
by 1pF capacitance, integrated the DAC custom layout and SAL comparator. Major problem
we deal with was the comparator receive input ability.

As we can see, the voltage has steps according to the clock phase. This cause problem when
we required high resolution. Moreover, Sample&Hold output voltage and DAC output
voltage respond different to clock phase: 0.962 mV, 4.24 mV respectfully. That can cause
problem of missing code by LSB or more.
The reasons for this phenomenon is parasitic capacitance between MOSFET gate to his
drain/source that have significant effect because Sample&Hold and DAC, the components
who connect to the comparator input, have large different on them output.

To solve this problems, we made capacity matching and dummy devices:

5.4.3.1 Capacity matching.

The voltages step size determines by Sample&Hold and DAC output capacitance. When
comparator current transistor clock toggling, high frequency voltage (step input) pass the
parasitic capacitor and have influence on voltage that save at Sample&Hold and DAC output
capacitor.

Therefore, to match the steps, the device's capacitance need be to matched. As we

measured above at section 4.2, DAC total capacitance is around 226fF. So, we set
Sample&Hold output capacitor be in same value.

46
This graph present Sample&Hold and DAC output voltages respond to clock phase after we
set Sample&Hold output capacitor be 0.226pF
To our pleasure we success and receive good result :
Sample&Hold and DAC output voltages respond to clock phase is 4.25 mV, 4.24 mV
respectfully.

5.4.3.2 Dummy Devices:

For canceling input respond to clock toggling, we design opposite parasitic capacitor by
PMOS and connect his source to drain, connect them to the comparator entrance and insert
throw the same clock toggling. As we can see at the below comparator schematic.

The dummy devices size where need to be equal to all the transistor parasitic path that
connect to clock toggling. The size we set is W = 10.3*200n, L = 240n.

The results of the comparator input voltage for the Vin = 0, 200mV:

47
The biggest offset of this configuration is 785uV.

48
 6. Sample and hold Transistor Level
Now, we replace the ideal Sample&Hold component by transistor level component.
For switch we choose single NMOS transistor. The reason that we don’t use the
PMOS is the range of the ADC is near to 580mV, so NMOS can pass low voltage
pretty well. The new Sample&Hold scheme:

As we define in the previous section 5.4.3.1 , Sample&Hold output capacitor size is

226fF and the NMOS has size of L = 60nm W = 200n.
The results for insert max voltage 580mV:

At this graph we can see the sample voltage reach only to 447mV. It seems that it
needs more time for the capacitor load but if we do so we reduce SAR frequency. So,

49
we increase the tunnel's width to get more current, faster loading. We increase by 20:

50
We got to 578mV, closer to our input. Now, we set another input 200mV:

We are notice that after the sample was carried out, the sample output voltage
decreases 5 mV. We are assuming that Counter glitch have influence and we trying
cancel it.
The reason for this glitch is overlap timing in the Counter component. As we know,
the output of the Counter is AND gate with the following inputs: shift register and the
clock. So, the delay of the DFF's fall signal and the clock timing overlap each other,
hence this overlap cause glitch:

Adding four buffering to AND clock signal fix it:

51
However, it doesn’t success to prevent decrease in sampled voltage.

As we do in the previous section when we integrated the comparator transistor level

component we design dummy device to canceling parasitic capacitor and clock
toggling influence:

The result of L=60nm, W = 200∙7nm, Vin = 200mV:

52
The dummy device canceling parasitic capacitor and clock toggling influence and
success to prevent decrease in sampled voltage.

53
7 Appendix: Setup for custom layout and explanation of running
layout simulation.

At following appendix, we show the setup we use to build the DAC's layout.

7.1High lights
Setup for running extracted simulation:

Integrity check

1. Calibre -> Run nmDRC

2. Unboxing all box in Customization Setting window.
3. Click on "Run DRC", you should get only one error ("Check DRM.R.1").
4. Add an instance from a library to the scheme (like sc9 or analoglib) and source it to
the layout.
5. Do DRC with the new instance (step 1-3).
6. Calibre -> Run nmLVS.
7. Unboxing all box in Customization Setting window.
8. LVS Options -> LVS Box.
9. Unbox "Use LVS Box…" and add the instance that no runed LVS.
10. Click on "Run LVS", you should get all match.

Making av_extracted

11. Assura -> Run LVS.

12. Click "Ok".
13. Quantus -> Run Assura – Quantus.
14. At Quantus window -> tab Extraction -> Ref Node, insert the name of the ground in
your schematic.

Run simulation in the av_extracted

15. Library Manager -> file -> new -> cell view -> Type: config. (choose the testbench
cell)
16. New Configuration Window -> Top cell,View: schematic.
17. Click on "Use Tamplate": spectre.
18. At the config, choose the new instance "View Found" to av_extracted, and save
19. At the assembler ADE right click on the test, choose Design -> View Name -> config -
> Ok.
20. Run the simulation.

7.2 Extension
First, when we built the unit length cells according to the article details, we run on in only
Calibre DRC and not LVS.

54
We except to get only one DRC warning

The reason for that is the LVS can work only if there is an instance from some library in the
layout and not all custom. So, if we want to make an av_extracted for one of the cells, we
need to an instance to the scheme and the layout to run LVS.

When we did LVS we use the Caliber LVS:

55
If there are some instances in the layout which didn’t threw LVS (like unit length bits), we
used LVS box to threw the LVS check, for example 3-unit length:

Then you get a massage that all match.

56
For run simulation on the layout you need to do av_extracted. For making extraction we
need netlist of the layout which make the LVS, and after use Quantus for extraction. In our
server we use Quantus-Assura so we need Assura LVS (we used in first the LVS of Calibre
because it has more details and more friendly to fix problems).

We didn’t change
anything
We only change the Ref Node
to our ground name in the
scheme

After the extraction to run simulation, we need to do config to the scheme with the custom
instance. Library Manager -> file -> new -> cell view -> Type: config.

When you open new configuration view -> schematic.

57
Then click on Use Template and select spectre

In the config. Choose the new instance to be "View Found" as av_extracted and save.

58
Then in the ADE, right click on the test and select design:

In the design choose the cell and View Name: config

Run the simulation.

59