Ppi
Ppi
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Introduction
• PPI – Programmable Peripheral Interface
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Block Diagram
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Pin Description
• PA7-PA0 : These are eight port A lines that acts as either latched
output or buffered input lines depending upon the
control word loaded into the control word register.
• PC3-PC0 : These are the lower port C lines, other details are the
same as PC7-PC4 lines.
• PB0-PB7 : These are the eight port B lines which are used as
latched output lines or buffered input lines in the same
way as port A.
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Pin Description
• RD : This is the input line driven by the microprocessor and
should be low to indicate read operation to 8255.
• A1-A0 : These are the address input lines and are driven by the
microprocessor.
• RESET : The 8255 is placed into its reset state if this input line is
a logical 1. All peripheral ports are set to the input
mode.
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8255 Operations
• The lines A1-A0 with RD, WR and CS form the following
operations for 8255.
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Mode 0 - Simple Input or Output
• In this mode, ports A, B are used as two simple 8-bit I/O
ports & port C as two independent 4-bit ports.
• Each port can be programmed to function as simply an
input port or an output port.
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Mode 1 - Input or Output with Handshake
• In this mode, handshake signals are exchanged between
the MPU and peripherals prior to data transfer.
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Mode 1 - Input or Output with Handshake
Mode 1 - Input or Output with Handshake
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Mode 2 - Bidirectional Data Transfer
• This mode is used primarily in applications such as data
transfer between two computers.
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Mode 2 - Bidirectional Data Transfer
8255 Modes Summary
• Port A can work in Mode 0, Mode 1, or Mode 2
• Port B can work in Mode 0, or Mode 1
• Port C can work in Mode 0 only, if at all
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