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Presentation on Power Amplifier Design using

ADS

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Power Amplifier Design using ADS

PA Workshop

Wilfredo Rivas-Torres
Technical Support Application Engineer
October 12, 2004

Page 1
Outline

• Introduction
• DC and Loadline analysis
• Bias and Stability
• LoadPull
• Matching using Smith Chart Utility
• SourcePull
• PA Characterization – Did we meet the specification?
• Optimize/Fine Tune the design
• Test Design with real world modulated signals
• Layout

Page 2
ADS Power Amp Design
Why do we need a Power Amplifier?

Power Amplifiers (PA) are in the transmitting chain of a

wireless system. They are the final amplification stage before
the signal is transmitted, and therefore must produce enough
output power to overcome channel losses between the
transmitter and the receiver.
Basic Transmitter

Baseband MOD Driver PA

OSC

Page 3
ADS Power Amp Design
PA requirements

• The PA is typically the primary consumer of power in a

transmitter. A major design requirement is how efficiently the
PA can convert DC power to RF output power.
• The design engineer has to often concern himself with the
Efficiency of the Power Amplifier. Notice that efficiency
translates into either lower operation cost (e.g. cellular
basestation) or longer battery life (e.g. wireless handheld).
• PA linearity is another important requirement, the input/ output
relationship must be linear to preserve the signal integrity.
• The design of PAs often involves the tradeoff of efficiency and
linearity.

Page 4
ADS Power Amp Design
PA Design Requirement

• RF Output Power: 50 W PEP

• Input Drive Level : 1 W
• Output Load (RL): 50 Ω
• Efficiency (η) > 50%
• Bias Voltage: 28 V
• Device: MRF9045M

Page 5
ADS Power Amp Design
DC Curves
FET Curve Tracer

I_Probe
V_DC IDS
SRC1
Vdc=VDS FSL_MRF_MET_MODEL
VJ MRF1
Var
Eqn
VAR MODEL=MRF9045M
VAR1 V_DC
VDS =0 V SRC2
VGS =0 V Vdc=VGS

PARAMETER SWEEP DC
ParamSweep DC
Sweep1 DC1
SweepPlan="SwpPlan1" SweepVar="VDS"
Start=2.5 Start=0
Stop=5.0 Stop=28*2
Step=0.1 Step=0.1
Set drain and gate voltage FSL_TECH_INCLUDE
sweep limits as needed.
FSL_TECH_INCLUDE
Disp
T emp
DisplayTemplate
FTI
disptemp1
"FET_curve_tracer"

Page 6
ADS Power Amp Design
DC Curves
5

4
Load_Line

3
IDS.i, A

VDsat
1
IQ
m3
0
0 5 10 15 20 25 30 35 40 45 50 55 60
VDS

VDsat IQ m3
VDS=0.600 VDS=28.000 VDS=33.400
IDS.i=0.562 IDS.i=0.717 IDS.i=0.004
VGS=3.800000 VGS=3.800000 VGS=2.500000

Page 7
ADS Power Amp Design
Bias and Stability
MLIN MLIN
T L20 TL21
Subst="MSub1" Subst="MSub1"
W=63.668898 mil W=63.668898 mil
L=100 mil L=100 mil

Port
sc_mrt_MC_GRM40C0G050_J_19960828
P3 sc_spr_293D_A025_X9_19960828 sc_mrt_MC_GRM40C0G050_D_19960828
C25
Num=3 C19 C20
PART _NUM=GRM40C0G330J050 33pF
PART _NUM=293D474X9025A2 0.47uF PART_NUM=GRM40C0G100D050 10pF
MLIN MRF9045M_AMP
T L1
Subst="MSub1" X2
W=63.670079 mil
L=2194.444882 mil

sc_mrt_MC_GRM40C0G050_J_19960828 Port
C8 P2
PART_NUM=GRM40C0G330J050 33pF Num=2
sr_avx_CR_10_K_19960828 VD
R13
PART _NUM=CR10-150K 15 Ohm

FSL_MRF_MET_MODEL
MRF1
VG VJ MODEL=MRF9045M
T SNK=25
Port sc_mrt_MC_GRM40C0G050_J_19960828 sc_mrt_MC_GRM40C0G050_J_19960828 RTH=-1
P1 C7 C3
CTH=-1
Num=1 PART _NUM=GRM40C0G330J050 33pF PART_NUM=GRM40C0G330J050 33pF sr_avx_CR_10_K_19960828
R12
PART_NUM=CR10-680K 68 Ohm

MSub
sl_tok_LL2012-F_J_19960828
L2 MSUB
MLIN MLIN PART_NUM=LL2012-F82NJ 82 nH MSub1
T L22 TL23 H=33.6 mil
Subst="MSub1" Subst="MSub1" Er=4.2
W=63.668898 mil W=63.668898 mil Mur=1
L=100 mil L=100 mil Cond=5.8E+08
Hu=3.9e+034 mil
T =2.8 mil
Port T anD=0.002
P4 sc_spr_293D_A025_X9_19960828 sc_mrt_MC_GRM40C0G050_D_19960828 sc_mrt_MC_GRM40C0G050_J_19960828 Rough=0 mil
Num=4 C24 C23 C17
PART_NUM=293D474X9025A2 0.47uF PART_NUM=GRM40C0G100D050 10pF PART _NUM=GRM40C0G330J050 33pF

Page 8
ADS Power Amp Design
 Stability Analysis
VDD

P_1Tone VGG
PORT1 Term
Num=1 MRF9045M_AMP R3
Z=50 Ohm X1 Num=2
Z=50 Ohm
P=polar(dbmtow (-60),0)
Freq=fss

S-PARAMETERS FSL_TECH_INCLUDE

S_Param FSL_TECH_INCLUDE
SP2 FTI VDD VGG
Start=1 MHz
I_Probe I_Probe
Stop=3000 MHz
Step=1.0 MHz IDD IGG

Var VAR
Eqn
VAR3
V_DC V_DC
VDS =28 V
SRC1 SRC2 VGS =3.8 V
StabFact StabMeas Mu MuPrime
Vdc=VDS Vdc=VGS
StabFact StabMeas Mu MuPrime
StabFact1 StabMeas1 Mu1 MuPrime1
StabFact1=stab_fact(S) StabMeas1=stab_meas(S) Mu1=mu(S) MuPrime1=mu_prime(S)

Page 9
ADS Power Amp Design
Stability Analysis

3E4
1E4
StabFact1

1E3

1E2

1E1

1
0.0 0.5 1.0 1.5 2.0 2.5 3.0

freq, GHz
Page 10
ADS Power Amp Design
Impedance Matching

• The need for matching circuits is because amplifiers, in order to

perform in a certain way(e.g. maximize output power), must be
presented with a certain impedance at both the load and the
source ports.
• For example in order to deliver maximum power to the load RL the
transistor must have termination Zs and ZL.
• The input matching network is designed to transform the
generator impedance Rs to the optimum source impedance Zs.
• The output matching network transform the load termination RL
(50 Ω) to the optimum load impedance ZL.
• A LoadPull measurement will help the designer determine the
optimum load impedance ZL.

Page 11
ADS Power Amp Design
LoadPull Setup I_Probe
Is_high

Vs_high
PARAMETER SWEEP
ParamSw eep V_DC
Sw eep2 SRC1
Vdc=Vhigh

HARMONIC BALANCE
HarmonicBalance
HB1 I_Probe
Freq[1]=RFfreq Iloadv load
Order[1]=15
P_1Tone S1P_Eqn
MRF9045M_AMP
PORT1 S1
X2
Num=1 S[1,1]=LoadTuner
Set Load and Source Z=Z_s
I_Probe
FSL_TECH_INCLUDE Z[1]=Z0
impedances at P=dbmtow (Pavs)
Is_low FSL_TECH_INCLUDE
harmonic frequencies Freq=RFfreq
Vs_low FTI
Var VAR
Eqn
VAR2
Z_l_2 =Z0 + j*0
Z_l_3 = Z0 + j*0 V_DC
Var VAR
SRC2 Eqn
Z_l_4 = Z0 + j*0 Set these values: Sw eepEquations
Z_l_5 = Z0 + j*0 Vdc=Vlow
Var VAR s11_rho =0.75
Z_s_fund =1.0 + j*0 Eqn
STIMULUS s11_center =-0.6 +j*0.1
Z_s_2 = Z0 + j*0 Pavs=30 _dBm pts=100 Examples
Z_s_3 = Z0 + j*0 Z0=50
Z_s_4 = Z0 + j*0
RFfreq=760 MHz Search
Vhigh=28.0
Z_s_5 =Z0 + j*0 Vlow =3.8

Page 12
ADS Power Amp Design
LoadPull Contours

m2
indep(m2)=6
Pdel_contours_p=0.914 / 171.170
level=44.195857, number=1
impedance = 2.265 + j3.852
PAE_contours_p
Pdel_contours_p

m1
indep(m1)=6
PAE_contours_p=0.914 / 171.180
level=47.552308, number=1
impedance = 2.265 + j3.848

indep(Pdel_contours_p) (0.000 to 46.000)

indep(PAE_contours_p) (0.000 to 18.000)

Page 13
ADS Power Amp Design
Matching using Smith Chart Utility

Page 14
ADS Power Amp Design
Matching using Smith Chart Utility

Page 15
ADS Power Amp Design
Output Match

C
C1
C=12.975203 pF

Port TLIN TLIN TLIN Port

P1 TL1 TL2 TL3 P2
Num=1 Z=50 Ohm Z=50 Ohm Z=22.85 Ohm Num=2
E=8.891 C E=32.25 E=25.92
F=760 MHz C2 F=760 MHz C F=760 MHz
C3
C=2.307137 pF
C=27.689016 pF

DA_SmithChartMatch1_output_match_design
DA_SmithChartMatch1
F=760 MHz
Zs=50 Ohm
Zl=(2.300-j*3.800) Ohm
Z0=50 Ohm

Page 16
ADS Power Amp Design
SourcePull Contours

m2
indep(m2)=4
Pdel_contours_p=0.960 / 174.023
level=46.038749, number=1
Pdel_contours_p
PAE_contours_p

impedance = 1.016 + j2.609

m1
indep(m1)=4
PAE_contours_p=-0.952 + j0.100
level=58.130703, number=1
impedance = 1.096 + j2.618

indep(PAE_contours_p) (0.000 to 77.000)

indep(Pdel_contours_p) (0.000 to 66.000)

Page 17
ADS Power Amp Design
Matching Circuits

MLIN MLIN MLIN

TL9 TL8 TL7
Subst="MSub1" Subst="MSub1" Subst="MSub1"
Output Match W=63.670079 mil
L=216.786614 mil
W=63.670079 mil
L=786.342520 mil
W=199.971654 mil
L=596.716535 mil

Port sc_mrt_MC_GRM40C0G050_D_19960828 Port

P2 C28 sc_mrt_MC_GRM40C0G050_C_19960828 sc_mrt_MC_GRM40C0G050_J_19960828 P1
Num=2 PART_NUM=GRM40C0G090D050 9pF C21 C22 Num=1
PART_NUM=GRM40C0G020C050 2pF PART_NUM=GRM40C0G150J050 15pF

MLIN MLIN MLIN

TL16 TL18 TL17

Input Match Subst="MSub1"

W=63.670079 mil
L=205.546063 mil
Subst="MSub1"
W=63.670079 mil
L=802.433071 mil
Subst="MSub1"
W=199.971654 mil
L=414.385827 mil

Port Port
sc_mrt_MC_GRM40C0G050_D_19960828
P1 P2
C24 sc_mrt_MC_GRM40C0G050_C_19960828 sc_mrt_MC_GRM40C0G050_J_19960828
Num=1 Num=2
PART_NUM=GRM40C0G090D050 9pF C25 C26
PART_NUM=GRM40C0G020C050 2pF PART_NUM=GRM40C0G220J050 22pF

Page 18
ADS Power Amp Design
Complete Design Power Sweep

V_DC
SRC1
Vdc=VDS

Vin
I_Probe I_Probe
Iin input_match output_match Iload Vload
P_1Tone X5 MRF9045M_AMP X3
PORT1 X4
Num=1 R
Z=50.0 Ohm R1
Var VAR Var VAR R=50 Ohm
P=dbmtow(Pin) Eqn Eqn V_DC
VAR2 VAR1 SRC2
Freq=fo
fo=760.0 MHz VDS =28 V Vdc=VGS
Vdc=
VGS =3.8 V
Pin=30

HARMONIC BALANCE
FSL_TECH_INCLUDE
HarmonicBalance
FSL_TECH_INCLUDE HB1
FTI Freq[1]=fo
Order[1]=15
SweepVar="Pin"
Start=-30
Stop=40
Step=1

Page 19
ADS Power Amp Design
Power Compression Curve

Output
Pin=30.000
Pdel_dBm=45.570
60
Output
40
Pdel_dBm

20

-20
-30 -20 -10 0 10 20 30 40
Pin

Page 20
ADS Power Amp Design
Gain Compression Curve
LinearGain GainComp
Pin=-30.000 ind Delta=60.00
Gp=17.341 dep Delta=-1.771
LinearGain delta mode ON
18

16 GainComp
14
Gp

12

10

6
-30 -20 -10 0 10 20 30 40

Pin
Page 21
ADS Power Amp Design
Power Added Efficiency

60
m1 m1
50 Pin=30.000
PAE=49.618
40
PAE

30

20

10

0
-30 -20 -10 0 10 20 30 40

Pin

Page 22
ADS Power Amp Design
Getting ready to Optimize the PA
• The next step is to optimize the design to meet the requirements.
• The Designer can take the opportunity to see if other requirements, such
as layout will require any changes before proceeding to optimize.
• Example: we notice that the transistor pads are rather wide and the Tlines
leading up to it are not the same width.
• Since the Tlines are much narrower, we could add a taper so we have a
nice transition.
• We included a MTAPER at the input and output side

MTAPER
Taper2
Subst="MSub1"
W1=199.971654 mil
dBm(Vload[1])
W2=63.670079 mil
L=100.0 mil 41.549

Page 23
ADS Power Amp Design
Optimization Setup

OPTIM GOAL GOAL

Optim Goal Goal

Optim1 Goal1 Goal2
OptimType=Gradient Expr="dBm(Vload[1])" Expr="dBm(Vload[2])-dBm(Vload[1])"
MaxIters=25 SimInstanceName="HB1" SimInstanceName="HB1"
DesiredError=0.0 Min=47.0 Min=
FinalAnalysis="None" Max= Max=-40
NormalizeGoals=no Weight= Weight=
SetBestValues=yes RangeVar[1]= RangeVar[1]=
SaveSolns=yes RangeMin[1]= RangeMin[1]=
SaveGoals=yes RangeMax[1]= RangeMax[1]=
SaveOptimVars=no
UpdateDataset=yes
SaveNominal=no
SaveAllIterations=no
UseAllOptVars=yes
UseAllGoals=yes
SaveCurrentEF=no

Page 24
ADS Power Amp Design
Optimization Results

InitialEF FinalEF
67.187 0.000

optIter Goal1 Goal2

10 47.003 -40.017

M L IN
MLIN
TL39
Before T L39
After
Subst="MSub1" S u b s t= "M S u b 1 "
W=63.670079 mil W = 6 3 .6 7 0 0 7 9 m il
L=2194.444882 mil opt{ 250 mil to 3500 mil } L = 5 5 1 .5 9 1 m il o p t{ 2 5 0 m il to 3 5 0 0 m il }

Page 25
ADS Power Amp Design
Optimization Values

TL39.L*1e5/2.54 TL15.L*1e5/2.54 TL7.L*1e5/2.54

551.591 247.144 320.449

TL30.L*1e5/2.54 TL8.L*1e5/2.54

814.900 622.341

TL31.L*1e5/2.54 TL9.L*1e5/2.54

202.643 248.635

TL32.L*1e5/2.54 TL10.L*1e5/2.54
184.709 244.711

Page 26
ADS Power Amp Design
 PA Results

60
m1 m1
Pin=30.000
40
Pdel_dBm=47.003
Pdel_dBm

20

-20
-30 -20 -10 0 10 20 30 40

Pin

Page 27
ADS Power Amp Design
Power Added Efficiency

80
m3
m3 Pin=30.000
60 PAE=56.736
PAE

40

20

0
-30 -20 -10 0 10 20 30 40

Pin

Page 28
ADS Power Amp Design
Gain Compression Curve

0
m4
m4
-2 Pin=30.000
Gp-Gp[0]=-0.728
Gp-Gp[0]

-4

-6

-8

-10
-30 -20 -10 0 10 20 30 40

Pin

Page 29
ADS Power Amp Design
Complex Modulated Signal

40
16 QAM Spectrum (dBm)

20
0
-20
-40
-60
-80
-100
759.50 759.75 760.00 760.25 760.50
Frequency (MHz)

Page 30
ADS Power Amp Design
16 QAM Modulated Source
LPF_RaisedCosineTimed
L4
SymbolConverter Loss=0.0
S3 CornerFreq=bit_rate/8
SymbolTime=2/bit_rate ExcessBw =0.5
Delay=0 sec Type=Model w ith pulse equalization
CodeIn=nrzIn SquareRoot=Yes
CodeOut=pam4Out Delay=16/bit_rate

Data SymbolSplitter
D1 S1 QAM_Mod SpectrumAnalyzer
TStep=Tstep SymbolTime=1/bit_rate Q1 S9
FCarrier=Fc Plot=None
BitTime=1/bit_rate Delay=-1
UserPattern="" Pow er=Pc RLoad=DefaultRLoad
VRef=1.0 V Start=DefaultTimeStart
Type=Prbs
SequencePattern=23 SymbolConverter LPF_RaisedCosineTimed Phase=0 Stop=DefaultTimeStop
Repeat=Yes GainImbalance=0 Window =none
S4 L5
SymbolTime=2/bit_rate Loss=0.0 PhaseImbalance=0 Window Constant=0.0
Delay=0 sec CornerFreq=bit_rate/8
CodeIn=nrzIn ExcessBw =0.5
CodeOut=pam4Out Type=Model w ith pulse equalization
SquareRoot=Yes
Delay=16/bit_rate

Page 31
ADS Power Amp Design
DSP and Analog Circuits Setup

• Create a subcircuit with your analog design.

• You need to add either Circuit Envelope or Transient controller to the analog
circuit.
• We use Circuit Envelope specifically with our PA since we have a
Modulated Carrier.
• Circuit Envelope will also allow the use of Fast Cosim (Automatic
Verification Modeling – AVM). This will dramatically increase the
simulation speed.
• In the DSP schematic we will create the Modulated Carrier, feed it to the PA
and collect the signal samples and spectrum.
• The DSP schematic contains a Envelope Output Selector component used for
interfacing between circuit subnetwork output and the signal processing
components.

Page 32
ADS Power Amp Design
Ptolemy Cosim Schematic

SpectrumAnalyzer
S9
Plot=None
RLoad=DefaultRLoad
Start=DefaultT imeStart
Stop=DefaultT imeStop
Window=none
TimedSink
WindowConstant=0.0
Qout
Plot=Rectangular
Start=DefaultT imeStart
Stop=DefaultT imeStop
T imedSink ControlSimulation=YES
PA RF_in
Plot=Rectangular
Start=DefaultT imeStart
Stop=DefaultT imeStop
ControlSimulation=YES

QAM_src SplitterRF MRF9045M_AMP_CE2 PhaseShiftRF MatchedLoss QAM_Demod

EnvOutShort SplitterRF
X2 S10 X1 P1 M1 Q2
Pc=Pow O1 S7 PhaseShift=360-168 Loss=17.0 RefFreq=Fc
OutFreq=Fc Sensitivity=0.1*(10**((25-Pow)/20))
Phase=0.0 T imedSink
GainImbalance=0.0 Iout
PhaseImbalance=0.0 Plot=Rectangular
QAM Source Start=DefaultT imeStart
Stop=DefaultT imeStop
ControlSimulation=YES
TimedSink
RF_out
Plot=Rectangular
Start=DefaultT imeStart
Stop=DefaultT imeStop
ControlSimulation=YES

SpectrumAnalyzer
S8
Plot=None
RLoad=DefaultRLoad
Start=DefaultT imeStart
Stop=DefaultT imeStop
Window=none
WindowConstant=0.0

Page 33
ADS Power Amp Design
Fast Cosim Improvements

Simulation Time Benchmark:

Total bits: 1024 bits
AVM disabled : 410 sec
AVM enabled: 13 sec
AVM data reuse: 5.5 sec
--------------
AVM data reuse (16 Kbits): 17.5 sec

Page 34
ADS Power Amp Design
 Cosimulation Results - Spectrum
Carrier Power Carrier Power
25 dBm 30 dBm
20 20

0 0

-20 -20

-40 -40

-60 -60

-80 -80

-100 -100
759.0 759.5 760.0 760.5 761.0
759.0 759.5 760.0 760.5 761.0
freq, MHz
freq, MHz

Page 35
ADS Power Amp Design
 Cosimulation Results - Constellation

Carrier Power Carrier Power

25 dBm 30 dBm
1.5 1.5

1.0 1.0

0.5 0.5

0.0 0.0

-0.5 -0.5

-1.0 -1.0

-1.5 -1.5
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Page 36
ADS Power Amp Design
 Cosimulation Results
Carrier Power peakP_in peak_avg_in avgPin
30 dBm 32.163 4.951 27.212

peakP_out peak_avg_out avgPout

47.969 3.516 44.453

Carrier Power peakP_in peak_avg_in avgPin

25 dBm 30.000 7.788 22.212

peakP_out peak_avg_out avgPout

44.715 4.832 39.883

Page 37
ADS Power Amp Design
 Cosimulation Results – CCDF

Carrier Power Carrier Power

25 dBm 30 dBm
9E-1 9E-1

1E-1 1E-1

1E-2 1E-2

1E-3 1E-3

1E-4 1E-4

1E-5 1E-5
-8 -6 -4 -2 0 2 4 6 -8 -6 -4 -2 0 2 4 6
dB dB

Page 38
ADS Power Amp Design
EVM vs. Power Measurement

Var
Eqn VAR Var
Eqn VAR
VAR3 VAR2 RES
Tstep=1/(bit_rate*oversample) bit_rate=1.0 MHz R2
Tstop=num_bits/bit_rate oversample=4 R=50 Ohm
Fc=760 MHz num_bits=4096*4
Pow=30 _dBm

Ref

tes t EVM
Ref

EVM_WithRef
E2
QAM_src SplitterRF MRF9045M_AMP_CE2 StartSym=10
EnvOutShort
X2 S7 X1 SymBurstLen=1024
O1
Pc=Pow SampPerSym=16
OutFreq=Fc
SymDelayBound=-1
NumBursts=2
MeasType=EVM_rms
PARAMETER SWEEP
SymbolRate=0.25 MHz
ParamSweep DF RES
Sweep1 DF1 R1
SweepVar="Pow" DefaultNumericStart=0 R=50 Ohm
SimInstanceName[1]="DF1" DefaultNumericStop=100
SimInstanceName[2]= DefaultTimeStart=0
SimInstanceName[3]= DefaultTimeStop=Tstop
SimInstanceName[4]= SavedEquationName[1]="Tstep"
SimInstanceName[5]=
SimInstanceName[6]=
Start=18
Stop=30
Step=1

Page 39
ADS Power Amp Design
EVM vs. Power Results

EVM vs. Carrier Power

5

4
EVM (%)

0
18 20 22 24 26 28 30

Power (dBm)

Page 40
ADS Power Amp Design
ADS to VSA link
VSA

MRF9045M_AMP_CE2
QAM_src Env OutShort RES VSA_89600_1_Sink
X1
X2 O1 R1 V1
Pc=Pow OutFreq=Fc R=50 Ohm VSATitle="Simulation output"
TStep=Tstep
SamplesPerSy mbol=16
SetupFile="C:\Program Files\Agilent\89600
RestoreHW=NO
FSL_TECH_INCLUDE
SetFreqProp=Y ES

FSL_TECH_INCLUDE Var
Eqn
VAR
FTI VAR3
Tstep=1/(bit_rate*oversample)
Tstop=num_bits/bit_rate
Fc=760 MHz
Pow=30 _dBm
DF
DF1 Var
Eqn VAR
DefaultNumericStart=0 VAR2
DefaultNumericStop=100 bit_rate=1.0 MHz
DefaultTimeStart=0 oversample=4
DefaultTimeStop=Tstop num_bits=1024*16
SavedEquationName[1]="Tstep"

Page 41
ADS Power Amp Design
VSA Spectrum from ADS Cosim

Page 42
ADS Power Amp Design
VSA Constellation from ADS Cosim
Carrier Power
30 dBm

Page 43
ADS Power Amp Design
VSA Constellation from ADS Cosim
Carrier Power
30 dBm

Page 44
ADS Power Amp Design
VSA EVM from ADS Cosim

Carrier Power
30 dBm

Page 45
ADS Power Amp Design
 PA Layout

M CURVE2

M LI N M LI N Cur ve2
TL20 TL21 Subst =" M Sub1"
Subst =" M Sub1" Subst =" M Sub1" W=63. 668898 m li

W=63. 668898 m li W=63. 668898 m li Angle=90

Radius=100. 0 m li
L=225 m li L=200 m li
Nm ode=2

Por t M LI N sc_spr _293D_A025_X9_19960828 sc_m r t _M C_G RM 40C0G 050_D_19960828

P3 TL42 C19 C20
Num =3 Subst =" M Sub1" PART_NUM =293D474X9025A2 0. 47uF PART_NUM =G RM 40C0G 100D050 10pF
W=63. 668898 m li
L=440 m li

M LI N
TL41

Subst =" M SUB1"

W=63. 6689 m li
L=253. 4234 m li

sc_m r t _M C_G RM 40C0G 050_J_19960828

C17
M TAPER
M LI N PART_NUM =G RM 40C0G 330J050 33pF
TL39 M LI N Taper 2 M LI N M LI N M LI N
Subst =" M Sub1" TL7 Subst =" M Sub1" TL8 TL9 TL10
W1=199. 971654 m li
W=63. 670079 m li Subst =" M Sub1" W2=63. 670079 m li Subst =" M Sub1" Subst =" M Sub1" Subst =" M Sub1"
L=551. 591 m li opt { 250 m li t o 3500
W=199.
m li }971654 m li L=100. 0 m li W=63. 670079 m li W=63. 670079 m li W=63. 670079 m li
L=320. 449 m li opt { 75 m li t o 500 m li } L=622. 343 m li opt { 100 m li t o 750 m li } L=248. 635 m li opt { 75 m li t o 500 m li } L=244. 711 m li opt { 50 m li t o 500 m li }

M TEE_ADS sc_m r t _M C_G RM 40C0G 050_D_19960828 Por t

M TAPER sr _avx_CR_10_K_19960828 M TEE_ADS sc_m r t _M C_G RM 40C0G 050_C_19960828
Tee2 sc_m r t _M C_G RM 40C0G 050_J_19960828 C26 P2
M LI N M LI N M LI N Taper 1 M LI N R13 Tee1 C25
TL15 TL32 TL30 TL31 Subst =" M Sub1" C24 PART_NUM =G RM 40C0G 020C050 2pF PART_NUM =G RM 40C0G 090D050 9pF Num =2
Subst =" M Sub1" PART_NUM =CR10- 150K 15 O hm Subst =" M Sub1" W1=199. 971654 m li PART_NUM =G RM 40C0G 150J050 15pF
Subst =" M Sub1" Subst =" M Sub1" Subst =" M Sub1" Subst =" M Sub1"
W1=199. 971654 m li W1=199. 971654 m li W2=199. 971654 m li
W=63. 670079 m li W=63. 670079 m li W=63. 670079 m li W2=63. 670079 m li W=199. 971654 m li W2=199. 971654 m li W3=63. 670079 m li
L=247. 144 m li opt { 50 m li t o 500 m li } L=184. 709 m li opt { 100 m li t o 500 m li } L=814. 898 m li opt { 250 m li t o 1000 m li } L=100. 0 m li L=202. 643 m li opt { 75 m li t o 750 m li } W3=63. 668898 m li

Por t sc_m r t _M C_G RM 40C0G 050_D_19960828 sc_m r t _M C_G RM 40C0G 050_J_19960828 M RF9045_ar t
P1 C3 Q1
Num =1 C27 PART_NUM =G RM 40C0G 330J050 33pF sr _avx_CR_10_K_19960828
PART_NUM =G RM 40C0G 090D050 9pF sc_m r t _M C_G RM 40C0G 050_C_19960828
C28 sc_m r t _M C_G RM 40C0G 050_J_19960828 R12
PART_NUM =G RM 40C0G 020C050 2pF C18 PART_NUM =CR10- 150K 15 O hm

PART_NUM =G RM 40C0G 220J050 22pF

M LI N
TL43
Subst =" M SUB1"
W=40 m li
L=90 m li

sl_t ok_LL2012- F_J_19960828

L2
PART_NUM =LL2012- F82NJ 82 nH

M Sub
M LI N
TL1
SM T_Pad SM T_Pa d
M SUB
Subst =" M SUB1" M Sub1
W=63. 668898 m li SM T_Pad SM T_Pad
Pad1 Pad2 H=33. 6 m li
L=100 m li
Er =4. 2
W=50. 0 m li W=70. 0 m li M ur =1
sc_m r t _M C_G RM 40C0G 050_J_19960828 L=40. 0 m li L=40. 0 m li Cond=5. 8E+08
M LI N C21 PadLayer =" cond" PadLayer =" cond" Hu=3. 9e+034 m li
TL44 PART_NUM =G RM 40C0G 330J050 33pF SM O =5. 0 m li SM O =5. 0 m li T=2. 8 m li
SM _Layer =" solder _m ask" SM _Layer =" solder _m ask"
Subst =" M SUB1" TanD=0. 002
M LI N W=63. 668898 m li PO =0 m li PO =0 m li
M LI N M LI N Rough=0 m li
TL40 L=315. 0248 m li
Subst =" M Sub1" TL23 TL22
Subst =" M Sub1" Subst =" M Sub1"
W=63. 668898 m li W=63. 668898 m li W=63. 668898 m li
L=200 m li
SM T_Pad
L=350 m li L=200 m li
SM T_Pad

Pad3
Por t M CURVE2 W=30. 0 m li
P4 Cur ve1 L=30. 0 m li
Num =4 sc_spr _293D_A025_X9_19960828 sc_m r t _M C_G RM 40C0G 050_D_19960828 Subst =" M Sub1" PadLayer =" cond"
C22 W=63. 668898 m li SM O =5. 0 m li
C23 PART_NUM =G RM 40C0G 100D050 10pF Angle=90
PART_NUM =293D474X9025A2 0. 47uF SM _Layer =" solder _m ask"
Radius=100. 0 m li PO =0 m li
Nm ode=2

Page 46
ADS Power Amp Design
PA Layout – Generated from Schematic

Page 47
ADS Power Amp Design
PA Layout – Ground Fill

Page 48
ADS Power Amp Design
Other Possibilities

• Run an EM Cosimulation – include layout effects in the simulation.

Optimize design if necessary.
• Run Loadpull for IP3 or ACPR. The optimum load would then be a
compromise between all the requirements.
• Use Connection Manager and real PA to validate design and compare
vs. simulated results.
• Create a behavioral data model that can be used to protect you IP yet
give access to your design results.

If there is any topic about PA Design and ADS you wish to

discuss email me: wilfredo_rivas-torres@agilent.com

Page 49
ADS Power Amp Design
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Revised: March 27, 2008

Product specifications and descriptions

in this document subject to change
without notice.

© Agilent Technologies, Inc. 2008

Printed in USA, October 12, 2004
5989-9594EN