Digital Design

FSM Optimization
A. Sahu
Dept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati
http://jatinga.iitg.ac.in/~asahu/cs221/
1
 Outline
• FSM Optimization: State Minimization
– Row Matching method
– Partitioning method
– Implication Chart
• FSM Optimization : State Encoding
– Binary/Sequential, Gray, One-hot
– Heuristic Based
Partitioning Methods

3
 State Minimization: Partitioning
• Form an initial partition (P1) : that includes all the states.
• Form a 2nd partition (P2)
– By separating the states into two blocks based upon their output
values.
• Form a third partition (P3)
– by separating the states into blocks corresponding to the next
state values.
• Continue partitioning until
– Two successive partitions are the same (i.e. PN-1 = PN).
• All states in any one block are equivalent
– Equivalent states can be combined into a single state.
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 State Minimization: Previous Example
• Sequence Detector for 010 or 110
• After is asserted after each 3 bit input sequence if it consist
of 110 or 010
S0
0/0 1/0

S1 S2
0/0 1/0 0/0 1/0
S3 S4 S5 S6
1/0 1/0 1/0 1/0
0/0 0/1 0/0 0/1
 State Minimization Example
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0 ( S0 S1 S2 S3 S4 S5 S6 )
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
 State Minimization Example
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0 ( S0 S1 S2 S3 S4 S5 S6 )
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
(S0 S1 S2 S3 S5) (S4 S6)
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
 State Minimization Example
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0 ( S0 S1 S2 S3 S4 S5 S6 )
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0 (S0 S1 S2 S3 S5) (S4 S6)
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
(S1 S2) (S0 S3 S5)
11 S6 S0 S0 1 0
(S0 S1 S2 S3 S5)
0 1
(S1 S3 S5 S0 S0) (S2 S4 S6 S0 S0)
 State Minimization Example
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
( S0 S1 S2 S3 S4 S5 S6 )
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0 (S0 S1 S2 S3 S5) (S4 S6)
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0 (S1 S2) (S0 S3 S5)
(S0 S3 S5)
0 1
(S1 S0 S0) (S2 S0 S0)
(S0) (S3 S5)
 State Minimization Example
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0 ( S0 S1 S2 S3 S4 S5 S6 )
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
(S0 S1 S2 S3 S5) (S4 S6)
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
(S1 S2) (S0 S3 S5)
11 S6 S0 S0 1 0

(S0) (S3 S5)

 State Minimization Example
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0 ( S0 S1 S2 S3 S4 S5 S6 )
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0 (S0) (S4 S6)
0 1
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0 (S0) (S0)
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0 (S1 S2) (S3 S5)
0 1 0 1

(S3 S5) (S4 S6) (S0) (S0)

 State Minimization Example
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0 ( S0 S1 S2 S3 S4 S5 S6 )
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0 (S0) (S4 S6)
0 1
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0 (S0) (S0)
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0 (S1 S2) (S3 S5)
0 1 0 1
No further
(S3 S5) (S4 S6) (S0) (S0)
partitions possible
 State Minimization Example
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0 ( S0 S1 S2 S3 S4 S5 S6 )
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
(S0) (S1 S2) (S3 S5) (S4 S6)
(S0) (S1‘) (S3’) (S4’)
 State Minimization Example
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1’ S1’ 0 0
0 S1’ S3 S4’ 0 0
1 S2 S5 S4’ 0 0
00 S3 S0 S0 0 0
01 S4’ S0 S0 1 0
10 S5 S0 S0 0 0
11 S4’ S0 S0 1 0

(S0) (S1 S2) (S3 S5) (S4 S6)

(S0) (S1‘) (S3’) (S4’)
 Minimized FSM
S0
X/0

0/0 S1’
1/0

S3’ S4’
X/0 0/1 1/0
 Row Matching Method : Fallacies
• Odd Parity Checker:
– Two alternative state diagrams
– Identical output behavior on all input strings
– FSMs are equivalent, but require different implementations
0 0
1 S0 [0]]
S0 [0] S1 [0] 0
1 1 1 1
Design state diagram
S1 [1] S2 [1] without concern for
# of states, Reduce
0 0 later 16
 Partitioning Method
(S0S1S2)
Next State
Present State X=0 X=1 Output Based on output
(S0S2) (S1)
S0 S0 S1 0
S1 S1 S2 1
S2 S2 S1 0
 Partitioning Methd
Next State
Present State X=0 X=1 Output
(S0S1S2)
S0 S0 S1 0
Based on output
S1 S1 S2 1
(S0S2) (S1)
S2 S2 S1 0

Was not possible with Row matching method

S0,S2 S0,S2 are same
0 1
S0,S2 S1 {S0 S2}, {S1} => {S0’}, {S1}
But possible with Partitioning method 18
 Some Definitions
• State Equivalence: S1 and S2 are equivalent if for
every input sequence applied to machine goes to
same NS and Output
– If S1(t+1)=S2(t+1) and Z1=Z2 then S1=S2

• Distinguishable States: Two states S1 and S2 are

Distinguishable if and only if there exist at least
one finite input sequence which produce
different outputs from S1 and S2
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Implication Chart
Methods

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 Sequence Detector Example
• Sequence Detector for 010 or 110
• After is asserted after each 3 bit input sequence if it consist of 110 or 010

S0
0/0 1/0

S1 S2
0/0 0/0
1/0 1/0

S3 S4 S5 S6
0/0 1/0 0/1 1/0 0/0 1/0 0/1 1/0
 FSM :Tabular Form
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0 22
 Implication Chart Method
Enumerate all possible combinations of states
taken two at a time
S0 S1
Next States
S1 S2
Under all S2 S3
Input S3 S4
Combinations S4 S5
S5 S6
S6 S0 S1 S2 S3 S4 S5
S0 S1 S2 S3 S4 S5 S6 Implication Chart

Naive Data Structure: Xij will be the same as Xji

Also, can eliminate the diagonal 23
 Implication Chart Method
Filling in the Implication Chart
• Entry Xij — Row is Si, Column is Sj
• Si is equivalent to Sj if outputs are the same and
next states are equivalent
• Xij contains the next states of Si, Sj which must
be equivalent if Si and Sj are equivalent
• If Si, Sj have different output behavior, then Xij is
crossed out 24
 Implication Chart Method
S1 If Si, Sj have different output
S2 behavior, then Xij is crossed out
S3
S4
Input PS NS OUTPUT
S5
X=0 X=1 X=0 X=1
S6 Reset S0 S1 S2 0 0
S0 S1 S2 S3 S4 S5
0 S1 S3 S4 0 0
Starting Implication Chart
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
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11 S6 S0 S0 1 0
 Implication Chart Method
S1
If Si, Sj have different output behavior, then
Xij is crossed out
S2 • S4 have different output behavior with S0,
S3 S1, S2, S3, S5
S4 • S6 have different output behavior with S0,
S1, S2, S3, S5 Input PS NS OUTPUT
S5
X=0 X=1 X=0 X=1
S6 Reset S0 S1 S2 0 0
S0 S1 S2 S3 S4 S5
Starting Implication Chart 0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
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11 S6 S0 S0 1 0
 Implication Chart Method
S1 S1-S3
S2-S4
Fill other Xij Based on Next State Transaction
S2 S0 : S1, S2 when X=0, 1
S3 S1 : S3, S4 when X=0,1
S4
Input PS NS OUTPUT
S5 X=0 X=1 X=0 X=1
S6 Reset S0 S1 S2 0 0
S0 S1 S2 S3 S4 S5 0 S1 S3 S4 0 0
Starting Implication Chart 1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
Fill others Xij Based on
S2 S2-S6 S4-S6 Next State Transaction
S1-S0 S3-S0 S5-S0
S3 S2-S0 S4-S0 S6-S0

S4 Input PS NS OUTPUT
S1-S0 S3-S0 S5-S0 S0-S0 X=0 X=1 X=0 X=1
S5 S2-S0 S4-S0 S6-S0 S0-S0
S0-S0 Reset S0 S1 S2 0 0
S6 S0-S0
0 S1 S3 S4 0 0
S0 S1 S2 S3 S4 S5
1 S2 S5 S6 0 0
Starting Implication Chart
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
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11 S6 S0 S0 1 0
 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
S2 and S4
S2 S2-S6 S4-S6 have
S3
S1-S0 S3-S0 S5-S0
S2-S0 S4-S0 S6-S0 different
I/O
S4
S1-S0 S3-S0 S5-S0 S0-S0
behavior
S5 S2-S0 S4-S0 S6-S0 S0-S0
S0-S0 This implies that
S6 S0-S0 S1 and S0 cannot
S0 S1 S2 S3 S4 S5 be combined

Marked with Cross

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 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
S2 and S4
S2 S2-S6 S4-S6 have
S3
S1-S0 S3-S0 S5-S0
S2-S0 S4-S0 S6-S0 different
I/O
S4
S1-S0 S3-S0 S5-S0 S0-S0
behavior
S5 S2-S0 S4-S0 S6-S0 S0-S0
S0-S0 This implies that
S6 S0-S0 S1 and S0 cannot
S0 S1 S2 S3 S4 S5 be combined

Marked with Cross

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 Implication Chart Method
S1-S3
S1 S2-S4
S2 and S6
S1-S5 S3-S5
S2 S2-S6 S4-S6
have different
S1-S0 S3-S0 S5-S0
I/O behavior
S3 S2-S0 S4-S0 S6-S0

S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0

S6
S0-S0
S0-S0
This implies that
S1 and S0 cannot
S0 S1 S2 S3 S4 S5
be combined

Marked with Cross

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 Implication Chart Method
S1-S3
S1 S2-S4
S2 and S6
S1-S5 S3-S5
S2 S2-S6 S4-S6
have different
S1-S0 S3-S0 S5-S0
I/O behavior
S3 S2-S0 S4-S0 S6-S0

S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0

S6
S0-S0
S0-S0
This implies that
S2 and S0 cannot
S0 S1 S2 S3 S4 S5
be combined

Marked with Cross

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 Implication Chart Method
S1-S3
S1 S2-S4
S4 and S6
S1-S5 S3-S5
S2 S2-S6 S4-S6 have Same
S1-S0 S3-S0 S5-S0
I/O behavior
S3 S2-S0 S4-S0 S6-S0

S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0
S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5

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 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
S2 S2-S6 S4-S6 S1 S0 is already crossed
S1-S0 S3-S0 S5-S0
S3 S2-S0 S4-S0 S6-S0
So S3 S0
S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0
S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5

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 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
S2 S2-S6 S4-S6 S4 S0 is already crossed
S1-S0 S3-S0 S5-S0
S3 S2-S0 S4-S0 S6-S0
So S3 S1
S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0
S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5

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 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
S2 S2-S6 S4-S6 S6 S0 is already crossed
S1-S0 S3-S0 S5-S0
S3 S2-S0 S4-S0 S6-S0
So S3 S2
S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0
S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5

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 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
S2 S2-S6 S4-S6 S2 S0 is already crossed
S1-S0 S3-S0 S5-S0
S3 S2-S0 S4-S0 S6-S0
So S5 S0
S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0
S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5

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 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
S2 S2-S6 S4-S6 Similarly..
S1-S0 S3-S0 S5-S0
S3 S2-S0 S4-S0 S6-S0

S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0

S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5

Second Pass Adds No New Information 38

 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
S2 S2-S6 S4-S6 Similarly..
S1-S0 S3-S0 S5-S0
S3 S2-S0 S4-S0 S6-S0

S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0

S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5
Second Pass Adds No New Information
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 Implication Chart Method
S1-S3
S1 S2-S4
S1-S5 S3-S5
S3 and S5 are equivalent
S2 S2-S6 S4-S6 S4 and S6 are equivalent
S3
S1-S0 S3-S0 S5-S0 S1 and S2 are equivalent
S2-S0 S4-S0 S6-S0

S4
S1-S0 S3-S0 S5-S0 S0-S0
S5 S2-S0 S4-S0 S6-S0 S0-S0

S0-S0
S6 S0-S0
S0 S1 S2 S3 S4 S5

Second Pass Adds No New Information

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 Final : Reduce State Table
Input PS NS OUTPUT
X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
Input PS NS Output
00 S3 S0 S0 0 0
X=0 X=1 X=0 X=1
01 S4 S0 S0 1 0
Reset S0 S1’ S1’ 0 0
10 S5 S0 S0 0 0
0 or 1 S1’ S3’ S4’ 0 0
11 S6 S0 S0 1 0
00 or 10 S3’ S0 S0 0 0
01 or 11 S4’ S0 S0 1 41 0
Minimized FSM
It can satisfy for
S0 both 110 and 010

X/0
S1’ 1/0
0/0
S3’ S4’
0/1 1/0
X/0
 Outline
• FSM Optimization: State Minimization
– Row Matching method
– Partitioning method
– Implication Chart
• FSM Optimization : State Encoding
– Binary/Sequential, Gray, One-hot
– Heuristic Based
State Encoding/Assignment

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 State assignment
• State encoding:
– Assigning unique binary value to each state
– So that we can implement FSM
• Since we don’t care about the actual flip-flop
values for each state
• We can assign each state to any binary number
we like as long as
– Each state is assigned a unique binary number
 Example of FSM: 3 cycle Laser
• Require 4 States
• Assigning unique binary value/code to each state
• Options available : 4!
Outputs: x
x=0 clk ^ x=1 clk ^ x=1 clk ^ x=1
Off On1 On2 On3

clk ^
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 State Encoding Example
• Four states SL S0 S1 S2 S3 SL S0 S1 S2 S3
1 00 01 10 11 13 10 01 00 11
S0, S1, S2, S3 2 00 01 11 10 14 10 01 11 00

• 4! options 3
4
00
00
10
10
01
11
11
01
15
16
10
10
00
00
01
11
11
01
5 00 11 01 10 17 10 11 01 00
6 00 11 10 01 18 10 11 00 01
7 01 00 11 10 19 11 00 01 10
8 01 00 10 11 20 11 00 10 01
9 01 10 11 00 21 11 10 01 00
10 01 10 00 11 22 11 10 00 01
11 01 11 10 00 23 11 01 10 00
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 State assignment
• Since we don’t care about the actual flip-flop values for each
state we can assign each state to any binary number we like as
long as each state is assigned a unique binary number
• Suppose a FSM have 6 states: Modulo 6 Counter
• If we use 3 bits to encode the 6 states, we have

8  8!

 6
  6!(8  6)!
 
possible choosing the 6 states from 8 total state
– Than encodings
 State Encoding
• The cost & delay of FSM implementation depends
on encoding of symbolic states.
– e.g., 4 states can be encoded in 4! = 24 different ways
• There are more than n! different encodings for n
states.
– Exploration of all encodings is impossible, therefore
heuristics are used
• Heuristics Used
– One-hot encoding, Minimum-bit change, Prioritized
adjacency
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 State assignment
state Encoding 1 Encoding 2 Encoding 3
(binary) (Gray)

a 000 000 000

b 001 001 100
c 010 011 010
d 011 010 101
e 100 110 011
 State Encoding
• Binary and Gray encoding use the minimum
number of bits for state register
• Gray and Johnson code: Two adjacent codes
differ by only one bit
– Reduce simultaneous switching
– Reduce crosstalk, Reduce glitch

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 One-hot encoding
• One flip-flop per state encoding
• Leads to greater number of flip-flops than
binary encoding but possibly to simpler
logic
 State Assignment Problem
 Some state assignments are better than others.
 The state assignment influences the complexity of the
state machine.
 The combinational logic required in the state machine
design is dependent on the state assignment.
 Types of state assignment
 Binary encoding: 2N states → N Flip-Flops
 Gray-code encoding: 2N states → N Flip-Flops
 One-hot encoding: N states → N Flip-Flops
53
 FSM: State Assignment
Example

Design a FSM that detects a sequence of two or

more consecutive ones on an input bit stream.

The FSM should output a 1 when the sequence is

detected, and a 0 otherwise.

54
 FSM: State Assignment

Input: 011101011011101…
Output: 001100001001100…

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 FSM: State Assignment
Reset w=1

w=0 S0/0 S1/0

w=0

w=0 w=1

S2/1
State Diagram
w=1
56
FSM: State Assignment
Present Next State Output
State
w=0 w=1
S0 S0 S1 0
S1 S0 S2 0
S2 S0 S2 1

State Table
57
 FSM: State Assignment #1
State Assigned Table
Present State Next State Output
w=0 w=1
QA QB QA+ QB+ Q A+ QB+ z
S0 0 0 S0 0 0 S1 0 1 0
S1 0 1 S0 0 0 S2 1 0 0
S2 1 0 S0 0 0 S2 1 0 1
1 1 d d d d d

DB=wQ’AQB’
Using Binary Encoding DA=w(QA+QB)
for the State Assignment 58
 FSM: State Assignment #2
State Assigned Table
Present State Next State Output
w=0 w=1
QA QB QA+ QB+ QA+ QB+ z
S0 0 0 S0 0 0 S1 0 1 0
S1 0 1 S0 0 0 S2 1 1 0
S2 1 1 S0 0 0 S2 1 1 1
1 0 d d d d d

DA=w.QB
Using Gray-code Encoding DB=W
for the State Assignment Z=QA 59
 FSM: State Assignment #3
State Assigned Table
Present State Next State
w=0 w=1
QA QB QC QA+ QB+ QC+ QA+ QB+ QC+

S0 0 0 1 S0 0 0 1 S1 0 1 0
S1 0 1 0 S0 0 0 1 S2 1 0 0
S2 1 0 0 S0 0 0 1 S2 1 0 0
Using One-hot Encoding DA=w.Qc’
for the State Assignment
For each state only one flip-flop is set to 1.
DB=w.QC
D =w’ 60
 State Encoding
# Binary Gray Johnson One-hot

0 000 000 0000 00000001

1 001 001 0001 00000010
2 010 011 0011 00000100
3 011 010 0111 00001000
4 100 110 1111 00010000
5 101 111 1110 00100000
6 110 101 1100 01000000
7 111 100 1000 10000000
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Johnson Counter

62
Thanks

63