Boolean Algebra and

logic gates
© Luis Entrena, Celia López, Mario García,
Enrique San Millán, Marta Portela, Almudena Lindoso

Universidad Carlos III de Madrid

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Outline
 Postulates and fundamental properties of Boolean
Algebra
 Boolean functions and expressions
 Logic gates. Digital technologies. Implementation of
logic functions
 Minimization of logic functions

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Boolean Algebra
 Mathematical foundations of digital circuits
 Called Boolean Algebra after its inventor, George
Boole
• “An Investigation of the Laws of Thought” (1854)
 An algebra is defined by a set of elements with some
operations. In our case:
• B = {0, 1}
•  = {+, }

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Postulates of Boolean Algebra
 Internal composition law
•  a, b  B  a + b  B, a  b  B
 Neutral elements
•  a  B   neutral elements (0 y 1 respectively)
a+0=a
a1=a
 Commutative property
•  a, b  B  a+b=b+a
ab=ba
 Distributive property
•  a, b, c  B  a + b  c = (a + b)  (a + c)
a  (b + c) = a  b + a  c

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Postulates of Boolean Algebra
 Inverse or complementary element
• aB B
a
aa 1
aa  0

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Fundamental properties of
Boolean Algebra
 Duality: Every valid law has its dual, which is
obtained by replacing 0 ↔ 1 and + ↔ 
 Idempotence
• aB a+a=a
aa=a
• Proof:
a  a  0  a  a a  (a  a)(a  a)  (a  a)  1  a  a
a  a  0  a  a a  (a  a)(a  a)  (a  a)  1  a  a
 Annihilation
• aB a+1=1
a0=0

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Fundamental properties of
Boolean Algebra
 The basic operations can be defined from the previous
properties

a b a+b a b ab a a
0 0 0 0 0 0 0 1
0 1 1 0 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1

 Truth table: provides the value of the function for all possible
combinations of input values

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Fundamental properties of
Boolean Algebra
 Involution
• aB aa

 Absorption
•  a, b  B  a + ab = a
a (a+b) = a
• Proof:
a  ab  a  1  ab  a(1  b)  a  1  a
 Associative property
•  a, b, c  B  (a + b) + c = a + (b + c)
(a  b)  c = a  (b  c)

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Fundamental properties of
Boolean Algebra
 De Morgan laws:
•  a, b B 

ab a b
ab  a b
• Proof:
(a  b)  a b  (a  b  a)(a  b  b)  1 1
(a  b)  a b  (aab)  (bab)  0  0

therefore (a+b) is the inverse of a b

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Boolean Functions and
Expressions

 Definitions:
• A logic or boolean variable is any element
x  B = {0, 1}
• A literal is a variable or its inverse
• Logic or Boolean Function:
f : Bn → B
(x1, x2, …, xn) → y

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Representation of logic functions
 Expression  Truth table
a b f(a,b)
0 0 0
f(a, b) = a + b 0 1 1
1 0 1
1 1 1

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Deriving the truth table from a
expression
 Evaluate the expression for every combination of
input values
a b c f
0 0 0 0
f (a, b, c )  a  b c
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

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Minterm function
 Expression: a product of all variables, either inverted or not
 Truth table: has a 1 for one combination and 0 elsewhere
 Example:
a b c f
f (a, b, c )  a b c  m2 0 0 0 0
0 0 1 0
0 1 0 1
 Rule to obtain the expression:
• 0 → inverted variable 0 1 1 0
• 1 → non-inverted variable 1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

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Maxterm function
 Expression: a sum of all variables, either inverted or not
 Truth table: has a 0 for one combination and 1 elsewhere
 Example:
a b c f
f (a, b, c )  (a  b  c )  M2 0 0 0 1
0 0 1 1
0 1 0 0
 Rule to obtain the expresion:
0 1 1 1
• 0 → inverted variable
• 1 → non-inverted variable 1 0 0 1
1 0 1 1
BEWARE: minterms use the opposite rule!
1 1 0 1
1 1 1 1

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Shannon’s Expansion Theorem
 Any boolean function can be decomposed in any of the
following forms
f ( x1, x 2,..., xn )  xi f ( x1,..., xi1,0, xi1,..., xn )  xi f ( x1,..., xi1,1, xi1,..., xn )
f ( x1, x 2,..., xn )  xi  f ( x1,..., xi1,1, xi1,..., xn )xi  f ( x1,..., xi1,0, xi1,..., xn )

 Proof:
xi  0  f ( x1, x 2,..., xn )  1  f ( x1,...,0,..., xn )  0  f ( x1,...,1,..., xn ) 
 f ( x1,...,0,..., xn )
xi  1  f ( x1, x 2,..., xn )  0  f ( x1,...,0,..., xn )  1  f ( x1,...,1,..., xn ) 
 f ( x1,...,1,..., xn )

• The proof of the other form is given by duality

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Corollary of Shannon’s Expansion
Theorem
 Apply the Theorem recursively:
f (a, b, c )  a f (0, b, c )  a f (1, b, c ) 
 a (b f ( 0,0, c )  b f ( 0,1, c ))  a (b f (1,0, c )  b f ( 0,1, c )) 
 a b f (0,0, c )  a b f ( 0,1, c ))  a b f (1,0, c )  a b f (0,1, c ) 
 a b c f ( 0,0,0)  a b c f ( 0,0,1)  a b c f (0,1,0)  a b c f (0,1,1) 
a b c f (1,0,0)  a b c f (1,0,1)  a b c f (1,1,0)  a b c f (1,1,1) 
  mik i
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 A function can be expressed as the sum of all minterms (mi)
multiplied by a coefficient (ki) equal to the value of the function
when each variable is substituted by 0, if the variable appears
as inverted in the minterm, or 1 otherwise.

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First canonical form
 A function can be expressed as the sum of all
minterms for which the function evaluates to 1
a b c f
0 0 0 1
0 0 1 0 f (a, b, c )   (0,2,5)   m(0,2,5) 
3 3
0 1 0 1
 abc  abc  abc
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0

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Second canonical form
 A function can be expressed as the product of all
maxterms for which the function evaluates to 0
a b c f
0 0 0 1
0 0 1 0 f (a, b, c )   (1,3,4,6,7 )   M(1,3,4,6,7 ) 
3 3
0 1 0 1
 (a  b  c )(a  b  c )(a  b  c )
0 1 1 0
(a  b  c )(a  b  c )
1 0 0 0
1 0 1 1
1 1 0 0
BEWARE: minterms use the opposite rule!
1 1 1 0

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Logic gates
 Logic gates are electronic circuits that implement the
basic functions of Boolean Algebra
 There is a symbol for each gate

 Identity  NOT gate or inverter

z=a za
a a a a
0 0 0 1
1 1 1 0

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AND and OR gates
 AND gate  OR gate
z=ab z=a+b

a b ab a b a+b
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

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NAND and NOR gates
 NAND gate  NOR gate
z  ab  a b z  ab  a b

a b ab a b ab
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

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XOR and XNOR gates
 XOR (Exclusive-OR) gate  XNOR (Exclusive-NOR) gate
z  a  b  ab  ab  (a  b )(a  b) z  a  b  ab  a b  (a  b )(a  b )

a b ab a b ab
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

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 Generalization to n inputs

Output value
Gate 0 1
AND Any input = 0 All inputs = 1
OR All inputs = 0 Any input = 1
NAND All inputs = 1 Any input = 0
NOR Any input = 1 All inputs = 0
XOR There is an even There is an odd number
number of inputs = 1 of inputs = 1
XNOR There is an odd There is an even
number of inputs = 1 number of inputs = 1

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Other symbols
 A circle at an input or output indicates inversion

a
b z  abc
c

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Implementation of a logic
function with logic gates
 Take the function expression and substitute logic
operations by logic gates
 Example:

a
f (a, b, c )  a  b c b
c

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Digital technologies
 Logic gates are electronic circuits
 Logic levels (0 or 1) are represented by means of a
voltage level
 “Positive logic” is generally used
• High voltage (5V, 3.3V, 2.5 V, etc.) → 1
• Low voltage (0V) → 0
 There are many technolgies, depending on the way
logic gates are implemented and the features
obtained by every implementation

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Features of digital technologies
 Main features:
• Operating temperature range
• Voltage supply
• Noise margin (voltage intervals associated to each logic
value)
• Switching delay
• Power
• Other
 Each technology or subfamily shows different values
for these features

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Delays
 Logic gates do not switch immediately
Ideal inverter Real inverter
V V

t t
tp

 Delay limits the operating speed of circuits

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Logic families
 The set of basic digital components, such as logic gates and
others that will be studied along the course, is commonly known
as 74 Series of Family
 There are many subfamilies:
• According to the operating temperature range:
• 74 Series : 0º a 70º
• 54 Series : -55º a 125º
• According to technology:
• LS
• ALS
• F
• HC
• AHC
• G
• ….

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Logic families
 Component denomination:
• <Series><Subfamily><Component>
 Example: 74HC00
• 74 Series: conventional temperature range
• HC subfamily (High speed CMOS)
• Component 00: 4 NAND gates, 2 inputs
 Important: members of different subfamilies are not
compatible
• Components of different subfamiles should not be
assembled together in a circuit

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Datasheets

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Integrated Circuits
 Nowadays, most digital circuits are integrated circuits:
• ASIC (ASIC (Application Specific Integrated Circuit)
• Programable: CPLD/FPGA

• Microprocessors and embedded systems (HW + SW)

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Minimization of logic functions
 A logic function has many equivalent expressions
• The simplest expression will lead to a better implementation
• The final implementation will depend on the selected
technology
 Optimization criteria:
• Area or size:
• Smaller logic gate count
• Logic gates with less inputs
• Speed or delay:
• Smaller number of logic gates from input to output

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Minimization of logic functions
 Manual optimization:
• Direct application of Boolean Algebra laws
• Very difficult, unsystematic
• Systematic algorithms:
• Karnaugh maps, Quine–McCluskey, etc.
• Limited to a few variables and only area optimization
• Restricted solutions (only 2 level forms, etc.)

 Logic synthesis
• Performed by a computer starting from a description of a
circuit in an HDL (Hardware Description Language)
• Optimization of the design and generation the logic gate
description for the selected technology is done automatically

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Hardware Descripton Languages
(HDLs)
 HDLs allow us to:
• Design at a higher abstraction level -> Increase productivity
• Simulate designs for operation validation
• Simulation is more efficient when performed at a higher
abstraction level
• Synthesize designs to obtain an optimal implementation,
depending on the target:
• Size
• Speed
• Increase portability and reuse
 Essential in modern design for:
• Complex designs(>10K gates)
• ASIC or CPLD/FPGA technologies

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Design Tools

 Simulator
• Functional descriptions (non-synthesizable)
• RTL descriptions (synthesizable)
• Logic gates netlist
• With or without delays (functional/timing)
 Synthesizer
• Transforms RTL descriptions into logic gates netlists
• Optimizes logic for size or delay
• Provides logic gates delays
 Place & Route /Implementation
• Places the gates and interconnects them
• Provides interconnection delays

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Design Flow with VHDL

VHDL Functional
description simulation

Automatic Post-synthesis
synthesis simulation

Place &
Route Post-layout
simulation

Field tests

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Advantages of HDLs
 Increase the abstraction level
• Focus on WHAT the circuit must do, instead of HOW to
implement the circuits
• The synthesis tool determines which components are needed
 Productivity
• This is the main reason why this methodology is adopted.
Productivity increases for several reasons:
• Designers do not need to solve the implementation of logic functions:
just describe them
• Tools make the “hard” work

 Capability to deal with complex designs, which would take

a much higher effort with former methodologies

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Advantages of HDLs
 Portability
• Schematic designs cannot be easily ported, they depend on
the libraries and formats in each specific tool.
• HDL designs are portable, they are usually standardized
(for instance IEEE Standard 1076 VHDL).
• There is a growing market of already designed circuits (IPs)
that can be integrated in our design
 Optimization of the same design for different
requirements
• Size
• Delay
• Power

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