EEP 598- Digital Systems

Design with FPGAS

Week 7
Registers
• Storage unit. Can hold an n-bit value D Q

• Composed of a group of n flip-flops

Dff
clk

• Each flip-flop stores 1 bit of information D Q

Dff
clk

D Q
Dff
clk

D Q
Dff
clk
Controlled Register D Q
Dff
Reset Load Action clk
0 0 Q = old Q
1 0 Q=0
0 1 Q=D
D Q
Dff
clk

D Q
Dff
clk

D Q
Dff
clk
Shift Register
• Register that shifts the binary values in one or both directions
In D Q D Q D Q D Q Out
Dff Dff Dff Dff
clk clk clk clk

Clock
Transfer of Data
• 2 modes of communication: Parallel vs. Serial
• Parallel: all bits transferred at the same time
• Serial: one bit transferred at a time
• Shift register can be used for serial transfer

D Q D Q
Dff Dff
clk clk
Shift Register w/Parallel Load
D Q
Dff
Shift Load Action clk
0 0 Q = old Q
1 0 Shift
X 1 Parallel Load
D Q
Dff
clk

D Q
Dff
clk

D Q
Dff
clk
Conversion between Parallel & Serial
D3 LSI Q3 D3 LSI Q3
4-bit 4-bit
D2 Q2 D2 Q2
Shift Shift
D1 Q1 D1 Q1
Reg. Reg.
D0 Q0 D0 Q0
Shift Load Clk Shift Load Clk

Cycle Op - Sender Q0 Q1 Q2 Q3 Op - Recvr Q0 Q1 Q2 Q3

0
1
2
3
4
5
6
7
8
9
10
Counters
• A reg. that goes through a specific state sequence
• n-bit Binary Counter: counts from 0 to 2N-1 in binary
• Up Counter: Binary value increases by 1
• Down Counter: Binary value decreases by 1
• 3-bit binary up counter state diagram:
Binary Up-Counter Imp.
Complex Binary Counter
Load Count Action
0 0 Q = old Q
0 1 Up Count
1 0 Reset
1 1 Load Parallel
Arbitrary Sequence Counters
• Design a 3-bit count that goes through the sequence
000->010->100->101->111->110->001->011->000->...
Counters in Verilog
module upcounter #(parameter WIDTH=8)
(out, incr, reset, clk);

output logic [WIDTH-1:0] out;

input logic incr, reset, clk;

endmodule
Memory
• Need method for storing large amounts of data
• Computer programs, data, pictures, etc.
Address Data 64x8 RAM
000000 00111110
000001 01101011
000010 01011101 A5 D7
000011 01100011 A4 D6
000100 00111110 A3 D5
000101 00000000 A2 D4
000110 11111111 A1 D3
000111 01010101 A0 D2
001000 10101010 D1
001001 00100001 Write D0
001010 11011010

• RAM: Random Access Memory, Read/Write

• ROM: Read-only Memory
RAM Cell
• Requirements:
• Store one bit of data
• Change data based on input when row is selected
Input D Q

Row Select en
8x4 RAM In3 In2 In1 In0
Write
000

001

010

3:8 011
Decoder
100

101
Enable
110

111
S2 S1 S0
A2
A1
A0 Out3 Out2 Out1 Out0
RAM example
• Use a memory to do a programmable 32-picture animation on a 7-
segment display
L0
L L
5 1
L6
L L
4 2
L3
Verilog Memories
module memory16x6 (data_out, data_in, addr, we, clk);
output logic [5:0] data_out;
input logic [5:0] data_in;
input logic [3:0] addr;
input logic we, clk;

logic [5:0] mem [15:0];

always_ff @(posedge clk) begin

data_out <= mem[addr];
if (we)
mem[addr] <= data_in;
end

endmodule
Memory
• ROM
• RAM
• Register File
• Small, fast, fixed-sized memory that holds CPU data state
• First in, first out (FIFO) buffers
Memory
The internal structure of an 8 x 4 static RAM:
Synchronous Single-Port RAM (SV)
• Synchronous Inputs:
• wren (1 = write, 0 = read)
• addr (𝐴-bit address)
• din (𝐷-bit data)
• Synchronous Output:
• dout (𝐷-bit data)

• Implementation hints:
• Will need an internal RAM array of what size?
• To synchronize, should update on clock triggers
• What should dout do when wren = 1?
Synchronous Single-Port RAM (SV)
Simplified Synchronous Dual-Port RAM
• 2 ports, with 1 dedicated to writing and the other dedicated to
reading
• Synchronous Inputs:
• wren (1 = write, 0 = read)
• addr_w (𝐴-bit address)
• addr_r (𝐴-bit address)
• din_w (𝐷-bit data)
• Synchronous Output:
• dout_r (𝐷-bit data)
Simplified Synchronous Dual-Port RAM
Synchronous Dual-Port RAM
• The most general configuration – each port can either read or write
• Synchronous Inputs:
• wren_a and wren_b
• addr_a and addr_b
• din_a and din_b
• Synchronous Output:
• dout_a and dout_b
• The SystemVerilog is very similar to single-port, just with two sets of
everything.
Memory Type #3: Register File
• Register File – a collection of registers
• 1 input data port – can only write to 1 register at a time
• 1+ output data ports – can read from 1+ register at a time
• Address inputs to specify read/write targets
• Write enable
• Frequently used in CPUs or as fast buffers
Memory Type #4: FIFO Buffer
• First-In First-Out (FIFO) Buffer
• Data storage such that elements that arrived earlier are accessed before
elements that arrived later

• Has a limited capacity, so there is a notion of fullness

• Useful for synchronization, especially in communication (e.g., UART,
disk, network)
FIFO Implementation
• A FIFO buffer is often implemented as a circular queue with two
pointers:
• rd_ptr indicates the location of the front/head (i.e., the first valid data) and
advances when rd is asserted
• wr_ptr indicates the location of the back/tail (i.e., the first empty element)
and advances when wr is asserted
• empty and full as buffer fullness status indicators
• These are tricky because both situations have rd_ptr == wr_ptr
Circular Queue Example Operation
Circular Queue Implementation
• A circular queue can be implemented using a RAM module and a FIFO
controller
• The controller handles the “arrangement” of the linear memory space into a
circular queue
FIFO Buffer (SV)